Author: Peter Forstner Date: 20.01.93 Rev.: This application repo
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208E Timing Measurements with Fast Logic Circuits
Author: Peter Forstner Date: 20.01.93 Rev.:
This application report describes problems which occur when making timing measurements with fast logic circuits. introduction methods impedance matching, determination impedance stripline, followed requirements efficient test set-up; report concludes with example realization such test set-up.
Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safe-guards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1995, Texas Instruments Incorporated
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Contents
Contents
Introduction. Error! Bookmark defined. Theory. Methods Impedance Matching Theoretical Voltage Waveforms Impedance Striplines Test Set-Up. Inputs Outputs Bi-directional Connections Supply Voltage Example Test Set-Up 3.5.1 AC-TEST MOTHERBOARD 3.5.2 AC-TEST DUT-BOARD 3.5.3 Test Results with AC-TEST MOTHERBOARD Summary. Appendix. AC-Performance Board Documentation
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Introduction
Introduction
availability from semiconductor manufacturers ever-faster electronic components allows user design more effective efficient endequipment. These developments have however also increased problems which arise from line reflections. Signals having serious overshoot, undershoot steps pulse edges result. With circuits providing very steep edges their outputs, these problems arise even under laboratory conditions when measuring switching time behaviour individual circuits. appropriate test set-up prerequisite reliable, repeatable comparable measurement results. Essential satisfactory test set-up are: stable power supply, which also shows voltage changes under conditions varying high-frequency current, undistorted signal input device under test, whereby there must overshoots, undershoots steps pulse edges, connection outputs device under test which does influence switching behaviour. addition attention must paid appropriate test equipment, influence such equipment test set-up.
This Report draws attention problems timing measurements individual devices, indicates possible solutions.
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Theory
Theory
rise- fall-times signal shorter than transit time from source line, then designer must take account resulting transient phenomena. These take form voltage current wave flowing forward back along line (Fig signal waveform will determined internal resistance source characteristic impedance line load resistance length line
Figure
Wave Propagation along Line
Methods Impedance Matching
Overshoots, undershoots steps pulse edges result from reflections signals along unterminated line. Various methods line matching shown internal resistance source characteristic impedance line exactly matched, then distortion waveform line takes place (see 2a). internal resistance source less than characteristic impedance line, then series resistor used impedance matching. This method limits drive capability source, advantage that bi-directional channels realized without loading output device under test, when source high impedance state.
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Theory
Figure
Methods Line Matching
value chosen load resistor line which accordance with characteristic impedance, then line reflections will also eliminated (Fig 2b). signal source must however this case have adequate drive capability, order able drive relatively resistance load. Many generators available market already drive particular terminating resistance, mostly such case this method line matching must used, because otherwise voltage level preset generator applied device under test. channel should operated bi-directionally during measurement, then this method usable, since terminating impedance test device represents unacceptable load. current load resistance line (and also power consumption) need reduced, then terminating resistance alternatively connected voltage other than example (Fig 2c). However, with this method voltage level input device under test will determined only voltage level source, also greater extent voltage source line termination. such case precise test set-up longer possible. additional option matching line resistors, which first connected second (Fig 2d). This method however good practice test set-up, since advantage current 208E
Theory power consumption this case insignificant, resulting voltage level also depends only source, also supply voltage VCC. Another matching line combination resistor capacitor (Fig 2e). power consumption will this case reduced, since component eliminated. value capacitor estimated with following formula:
where:
Equation
value terminating resistor value terminating capacitor signal propagation time from beginning line
choice capacitor needs made more "trial error", whereby type line termination question precise test set-up. Signal generators commonly available provided with output resistor that methods line matching Figs chosen. setting output voltage level usually calibrated load resistor that with laboratory set-ups termination resistor usual (Fig 2b). variant mainly applicable production testing, since with bi-directional channels realized. other three methods used precise measurements laboratory.
Theoretical Voltage Waveforms
With assistance Bergeron method possible determine waveforms lines theoretically. Bergeron method will explained here, details found Application Report EB162 from TEXAS INSTRUMENTS
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Theory
Figure
Voltage Waveforms with Incorrect Termination. Terminating Resistor.
Figure
Voltage Waveforms with Incorrect Terminating Resistor
Termination.
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Theory
Figure
Voltage Waveforms with Impedance Matching. Terminating Resistor.
Figure
Voltage Waveforms with Impedance Terminating Resistor
Matching.
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Theory
Figure
Voltage Waveforms with Incorrect Termination. Terminating Resistor.
Figure
Voltage Waveforms with Incorrect Terminating Resistor
Termination.
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Theory above examples show voltage waveforms rising pulse beginning, middle, line. Falling pulses show similar behaviour, though obviously with opposite polarities. time interval transit time signal from beginning line, calculated with equation Matching with series resistors (Figs also with terminating resistors line (Figs have been shown. Also, voltage waveforms with correctly terminated lines (Figs with incorrect termination (Figs shown. easily seen that incorrect termination causes steps pulse edges overshoot signal. line which correctly matched with series resistor delivers undistorted waveform only line; along line, step pulse edge will seen. termination line with load resistor ensures clean pulses along whole length line.
Impedance Striplines
characteristic dimension line impedance (ZL). resistive part neglected, calculated follows:
where:
Equation
Impedance line Inductance unit line length
Capacitance unit line length
transit time from beginning line calculated from speed signal:
Equation
Equation
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Theory
Figure
Micro-Striplines
basic dimensions micro-stripline, inductance unit line length capacitance unit line length depend solely cross-sectional geometry relative permittivity (Fig this following expression deduced characteristic impedance microstripline:
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Theory where: r.eff
weff
.eff
Equation
characteristic impedance free space effective relative permittivity effective width micro-stripline
height dielectric
0.05, then effective relative permittivity determined
with margin error follows: r.eff whereby following applies:
Equation
where:
relative permittivity dielectric width micro-stripline height dielectric
ratio effective width micro-stripline width dielectric approximates closely following: Equation ln(8 0.25
where:
width micro-stripline height dielectric
characteristic impedance micro-stripline calculated good approximation from cross-sectional geometry relative permittivity circuit-board material, using formulas curves were drawn using these calculations, show characteristic impedance micro-stripline function parameters mentioned above. Typical figures cross-sectional geometry dielectric constant line with characteristic impedance given Table
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Theory
Figure Characteristic Impedance Micro-Stripline
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Theory 412µm 515µm 618µm 376µm 470µm 565µm 346µm 433µm 520µm
Table
200µm 250µm 300µm 200µm 250µm 300µm 200µm 250µm 300µm
50.0 50.0 50.0 50.0 50.0 50.0 50.0 50.0 50.0
Typical cross-sectional Geometry Dielectric Constant Line with Characteristic Impedance
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Test Set-Up
Test Set-Up
timing behaviour fast logic circuit needs evaluated, great care must taken with set-up procedures which used. Undistorted signals must provided generators inputs devices under test, apart from intended capacitive resistive loads outputs must subjected outside interference. Bi-directional channels particularly critical this respect, since direction which signal flows must reversed during testing. most cases impedance matching possible, that bidirectional channels should avoided tests. measurement each direction, they should configured pure inputs outputs.
Inputs
When evaluating timing behaviour, inputs device under test must provided with undistorted pulse edges. Most signal generators which generally available provided with output resistor such cases, either series matching (Fig 2a), matching with terminating resistor (Fig used.
important that input resistance device under test should considerably greater than characteristic impedance. This will however case will currently available digital circuits line. Series matching characteristic impedance usual method with automatic testers. Here must noted that, although signal waveform line undistorted, along line there will steps pulse edges. such cases, oscilloscope used, should connected directly input device under test. lab, matching with terminating resistor most commonly used method. waveform signal along line will change, although position time signal pulse edge will vary with signal delay time. voltage level device under test will half that signal source; signal generators currently available market however take account this. further important aspect when dimensioning lines differences signal delay times. lines need same length signals have same delay times. they different length, positions pulse edges will longer conform those generator. This will then entail adjusting generator accordance with length line.
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Test Set-Up
Outputs
outputs device under test usually provided with defined output resistance. addition, there often considerable difference between output resistances High levels. example, SN74F245 digital with bipolar output, whose output resistance changes from about High level, between level; such case, line matching difficult. shows theoretically calculated waveforms beginning line unterminated line, when this driven SN74F245. usually necessary that device being tested should drive line, this therefore completely dispensed with. Outputs should usually provided with defined loads, these should sited close possible device under test. Since oscilloscope with high resistance probe usually used precise measurement timing behaviour, input resistance measuring instrument ignored. However, capacitive loading output probe need taken into account. these requirements lead conclusion that, output, load circuit, probe head, should positioned close possible device under test, further that stub line should connected output (Fig 11).
often case when evaluating timing behavior IC's that load 50pF specified. this then shows solution problem, when measuring instrument with input resistance must used. input resistance measuring instrument behaves hand terminating resistance line; other hand, part load resistance. This means that 10:1 potential divider been created, made series resistor input resistance measuring equipment. When evaluating test results, 10:1 potential divider also signal transit time along line test equipment must taken into account. Again, load capacitance 50pF should possible placed close output device under test.
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Test Set-Up
Figure Theoretically Calculated Waveform Beginning Unterminated Line, driven SN74F245.
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Test Set-Up
Figure Decoupling Signal using Load 50pF GND, using Test Equipment with Input Resistance
Bi-directional Connections
line termination both signal directions only seldom possible with bidirectional channels. measurements made such points, then each measurement they should connected pure inputs outputs.
Supply Voltage
voltage supplying device under test must show changes, even with high-frequency current variations. This ensured attention paid following points: There must resistance connection from voltage source device under test. Preferably, each circuit board should have extra layer supply voltage. supply voltage must decoupled with capacitor directly device under test. This capacitor must have very good characteristics high frequencies i.e. inductance. Ceramic capacitors about 100nF have been found suitable this purpose.
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Test Set-Up
Example Test Set-Up
test set-up laboratory evaluations been developed TEXAS INSTRUMENTS, which required meet following requirements: Connections from signal generator input device under test have characteristic impedance Connections from generator input device same length. Load connected directly device under test. stub lines outputs. resistance connections supply voltage. flexible layout, allowing set-up used variety different measurements.
order achieve this flexibility, test circuitry built separate circuit boards follows: AC-TEST MOTHERBOARD, AC-TEST DUT-BOARD (DEVICE UNDER TEST) each type measurement.
Thanks this division circuitry boards, high degree flexibility various measurements which needed done achieved, with outstanding electrical performance lowest possible cost. signal connections both circuit boards have characteristic impedance result materials used, distances between layers resulting from manufacturing process, cross-sectional line geometries shown Table resulted. 418µm
Table
300µm
4.35
50.0
Sectional Geometries Circuit Boards used
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Test Set-Up
3.5.1 AC-TEST MOTHERBOARD
AC-TEST MOTHERBOARD five internal layers. Each used three voltage sources DPS1, DPS2 DPS3, ground connection made with separate layers. These layers brought with banana sockets. board provided with sockets maximum channels order provide connections word pulse generators. These sockets arranged circle, order ensure same line length from socket test device. lines used connect these sockets interconnection area. This area provided with jumpers allow flexible configuration each channel individually (Fig 13). this point choice made which signal applied device under test: signal from generator plug, supply voltage DPS1, supply voltage DPS2, supply voltage DPS3 ground connection.
Figure Interconnection Area Configuration each Channel signal taken from this area 'Pogo pins' arranged circle, which pass signal AC-TEST DUT-BOARD.
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Test Set-Up
Figure AC-TEST MOTHERBOARD
3.5.2 AC-TEST DUT-BOARD
example DUT-BOARD (DEVICE UNDER TEST), circuit board 1024 FIFO (First First Out) SN74ACT7801FN with 68-Pin Plastic Chip Carrier package will used. This inputs outputs, together with connections. track circuit board found which could used equally well inputs outputs. signal from AC-TEST MOTHERBOARD taken input with jumper, i.e. with resistor. circuit input (Figure includes terminating resistor between line GND.
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Test Set-Up
Figure Circuit Input SN74ACT7801FN DUT-BOARD jumper mentioned above removed when making timing measurements output pins. this there unterminated stub lines output, reflections avoided. addition there possibility soldering load circuits (Figure 16). layout circuit board however also allows connection measuring instruments with input resistance (see Figure 17).
Figure Circuit Output SN74ACT7801FN DUT-BOARD
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Test Set-Up
Figure Circuit Output SN74ACT7801FN DUT-BOARD, with load circuit 50pF GND, assuming signal analyzer with input resistance
Figure Cross-Section SN74ACT7801FN DUT-BOARD, with printed line position passive components input output. jumpers, terminating resistors load circuit should sited close possible DUT. These passive components therefore spacesaving (SURFACE MOUNT DEVICE) packages. jumper should soldered topside board; terminating resistor load circuit should however underside (Fig 18). complete layout topside underside DUT-BOARD SN74ACT7801FN shown Figs
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Test Set-Up
Figure Topside AC-TEST DUT-BOARD FIFO SN74ACT7801FN 68-Pin PLCC Package.
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Test Set-Up
Figure Underside AC-TEST DUT-BOARD SN74ACT7801FN 68-Pin PLCC Package.
FIFO
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Test Set-Up
3.5.3 Test Results with AC-TEST MOTHERBOARD
test set-up described previous section been fully evaluated. this purpose AC-TEST MOTHERBOARD used together with AC-TEST DUT-BOARD FIFO SN74ACT7801FN. tests included jumper connections, 'Pogo pins' jumper field. attenuation function frequency measured with help Network Analyzer HP8505A S-Parameter Test HP8503. results measurements seen only frequency there attenuation 3dB.
AC-BOARD: Rev. DUT-BOARD: 7801 Channel:
1000
Figure Transmission Loss measured Channel AC-TEST MOTHERBOARD connected AC-TEST DUT-BOARD FIFO SN74ACT7801FN. Measurements with various DUT-BOARDs some cases considerably lower limiting frequencies: this demonstrates that DUT-BOARD must also constructed with great care, precise measurement results desired.
208E
Summary
Summary
timing behaviour circuits having very steep pulse edges evaluated, appropriate test set-up absolutely essential achieve reliable, repeatable comparable test results. good test set-up should take into account following points: Each supply voltage ground connection should have separate layer circuit board. This ensures stable voltage supply which will change even when there high frequency current fluctuations. wiring test boards must have defined characteristic impedance, normally terminated with series load resistor. This provides input device under test with undistorted signals which free from overshoot, undershoot without steps pulse edges. There must stub lines output, since otherwise reflections will generated. this reason, load circuit must close possible device under test. Lastly, consideration must paid suitability test equipment influence have complete test set-up.
attention paid above points, then there should nothing prevent accurate orderly measurements.
208E
Appendix
Appendix Application Report 208E AC-Performance Board Documentation
Author: Claus Kuch Date: 15.08.92 Rev.:
208E
Appendix
Contents
Introduction. Specifications. 2.1. Mechanical dimensions 2.2. Electrical characteristics 2.3. Temperature range Description Operation 3.1. Performance Board 3.2. Jumper Matrix 3.3. Board Rev. SO-Package 3.4. Board Rev. SSO-Package 3.5. Board Rev. SQF-Package Description Applications. 4.1. Measuring Transit Time Description Signals. 5.1. Signal Waveforms 5.2. Description Transmission Loss measurement 5.3. Results Transmission Loss measurement 5.4. Description measurement 5.5. Result measurement Part List.
208E
Appendix
Introduction
This Appendix Application Report 208E ("Time Measurements with Fast logic Circuits") concerned with construction, operation typical applications Performance Board. Performance Board following features contacts (Device Under Test) compatible industrial standards Boards. possible switch input Three separate voltage connection options available. Suitable measuring characteristic curves. Suitable simultaneous switching applications. Suitable common measurements.
208E
Appendix
Specifications
2.1. Mechanical dimensions
Performance Board: Length:. Width: Thickness: Board: Diameter: Thickness:
2.2. Electrical characteristics
Performance Board: Capacitance between signal ground level: Impedance signal line: Difference delay times between signal lines without Board: Board: Impedance signal line:
2.3. Temperature range
Temperature Range:
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Appendix
Description Operation
3.1. Performance Board
1a&1b Separate voltage connections (DPS1, DPS2, DPS3) 2a&2b Three ground connection options Signal connectors (SMB) Jumper matrix (detailed information next page) Screw grounding connection DUT-Board Signal connections DUT-Boards Pogo-Pins holes spacers
208E
Appendix
3.2. Jumper Matrix
jumper matrix provides possibility connecting various voltages (DSP1, DSP2, DSP3) Ground gold bridges each signal pin. connection between contact Pogo made with gold bridge signal path.
208E
Appendix
3.3. Board Rev. SO-Package
Connection Pogo contact ground, connection Pogo (56) contact input bridges Connection cable contact area Optional point isolate from connection Pogo (55) contact series resistor from connector cable contact ground connection Pogo (56)
208E
Appendix
contact series resistor from connector cable contact ground connection Pogo (56)
208E
Appendix
3.4. Board Rev. SSO-Package
side
chan
Connection Pogo contact input bridge Connection cable contact area contact series resistor from connector cable contact ground connection Pogo (56)
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Appendix
contact series resistor from connector cable contact ground connection Pogo (56)
208E
Appendix
3.5. Board Rev. SQF-Package
Connection Pogo contact input bridge Connection cable contact area contact series resistor from connector contact ground connection Pogo (56)
208E
Appendix
contact series resistor from connector cable contact ground connection Pogo (56)
208E
Appendix
Description Applications
4.1. Measuring Transit Time
oscilloscope inputs have impedance effective load capacitance made specific load capacitance output plus board capacitance (see book). connections from generator board oscilloscope, connections from oscilloscope board, made with cable.
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Appendix
Description Signals
5.1. Signal Waveforms
Waveform Performance Board Board Rev.
Driver Input
Driver Output
-1.00E-08
-5.00E-09
0.00E+00
5.00E-09
1.00E-08
1.50E-08
2.00E-08
2.50E-08
3.00E-08
3.50E-08
4.00E-08
above curves have been measured with test setup shown page (4.1. Measuring Transit Time device under test ABT32501, soldered board Rev. ABT32501 been configured measure propagation delay time (Tphl/Tplh) driver (1A1 1B1).
208E
Appendix
5.2. Description Transmission Loss measurement
Principle test setup Transmission Loss measurement With help Network Analyzer HP8505A S-Parameter Test HP8503, measured values have been determined. test setup shows, measurement been made using channel Performance Board conjunction with board Rev. well combination channels. Here important include complete lines board each channel. following page shows results Transmission Loss measurement graphically.
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Appendix
5.3. Results Transmission Loss measurement
Frequency dependency Transmission Loss, using channel Performance Board conjunction with board Rev.
Frequency dependency Transmission Loss, using channel 82-57 Performance Board conjunction with board Rev.
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Appendix
5.4. Description measurement
Principle test setup measurement measurement been made using Tektronix Communication Signal Analyzer with special Sampling Head (SD-24, GHz). make this measurement voltage slope with defined amplitude must applied test line. Analyzing waveform signal source leads impedance delay time line. makes necessary calculation itself shows impedance delay time directly. signal generator with defined resistance integrated sampling head. generates amplitude 500mV with rise time about 25ps. Besides this generator second internal generator available sampling head. Because both generators driven push-pull basic line dimension ZLodd symmetrical cross coupled lines determined. following page shows first figure time dependency Rho() single line. result symmetrical cross coupled lines presents second figure.
formula calculation impedance
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Appendix
5.5. Result measurement
Time dependency using channel AC-Performance board with board Rev.
Time dependency using channel with symmetrical cross coupled channel push-pull) AC-Performance board with board Rev.
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Appendix
Part List
Description Board Rev.2.0 Inset Nuts Sockets, black Sockets, Posts Nuts Washers Plug Plug Mini Sockets Pogo Pins Sleeves Addresses Suppliers: Hans Schillerstr. D-80336 Suhner Elektronik GmbH Mehlbeerenstr. D-82024 Taufkirchen Infratron Schnepfenweg D-80995 Feinmetall Zeppelinstr. D-71083 Herrenberg Supplier Texas Instruments Suhner Infratron Feinmetall Feinmetall Part Number AC-Board 16H600 25F220 25F230 18H236 16H7906 16H864 77F210 82SMC-50-0-1 H3153-05 FM670/15 FM6010-10 S003 Quantity
208E
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