Author: Peter Forstner Date: 10.12.91 Rev.: This report takes det

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Author: Peter Forstner Date: 10.12.91 Rev.: This report takes det

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201E FIFOs Architecture, Functions, Application
Author: Peter Forstner Date: 10.12.91 Rev.:
This report takes detailed look FIFO devices from TEXAS INSTRUMENTS first part presents different functions FIFOs resulting types that found. second part deals with current FIFO architectures different ways which they work. Finally some application examples given illustrate FIFOs from TEXAS INSTRUMENTS range.
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Contents
Contents
Introduction. FIFO TYPES. Synchronous FIFOs Asynchronous FIFOs 2.2.1 Metastability Synchronizing Circuits 2.2.2 Strobed FIFOs 2.2.3 Clocked FIFOs FIFO Architectures. Fall-Through FIFOs 3.1.1 Architecture 3.1.2 Advantages Drawbacks FIFOs with Static Memory 3.2.1 Architecture 3.2.2 Advantages Drawbacks FIFOs from TEXAS INSTRUMENTS. Features 4.1.1 Data Outputs with Latches 4.1.2 Synchronization Flags 4.1.3 Edges Outputs Extending Word Width Extending Memory Depth Application Examples. Asynchronous Operation Synchronous FIFOs Connection Peripherals Processors Block Transfer Data Programmable Delay Collecting Data before Event Collecting Data before after Event Summary.
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Introduction
Introduction
every item digital equipment find exchange data between different boards. Intermediate storage buffering will always necessary when data arrive receiving board fast batches processed slowly irregularly. Buffers this kind also observed everyday life, e.g. queue customers cashpoint supermarket cars backed traffic lights. cashpoint supermarket works slowly constantly, while number customers coming very irregular. customers want same time, queue forms, which works principle first come, first served. backup traffic lights caused sporadic arrival cars, traffic lights only allowing them pass through batches. electronic systems buffers this kind also advisable interfaces between components that work different speeds irregularly. Otherwise slowest component will determine operating speed other components involved data transfer. compact-disk player instance, speed rotation disk determines data rate. make reproduced sound fluctuations independent speed, data rate converter controlled quartz crystal. different data rates compensated buffering. this sound fluctuations largely independent speed which disks rotate. FIFO special type buffer. name FIFO stands First First means that data which written into buffer first will also come first. There other kinds buffers like LIFO (Last First Out), often called stack memory, shared memory. choice buffer architecture will depend application solved. FIFOs implemented with software hardware. choice between software hardware solution will depend your application features aiming When requirements change, software FIFO easily adapted them modifying program, while hardware FIFO demand board layout. software more flexible than hardware. advantage hardware FIFOs shows their speed. data rate MWords second guaranteed TEXAS INSTRUMENTS SN74ABT7819 FIFO instance.
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FIFO TYPES
FIFO TYPES
Every memory which data word that written first also comes first when memory read first-in-first-out memory. Fig. illustrates data flow FIFO. There following kinds FIFO: FIFO with invariable number stored data words thus necessary synchronism between read write operation, since data word read every time written: shift register. FIFO with variable number stored data words and, because internal structure, necessary synchronism between read write operation: synchronous FIFO. FIFO with variable number stored data words possible asynchronism between read write operation: asynchronous FIFO.
Fig.
First-In-First-Out Data Flow
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FIFO TYPES shift register usually referred FIFO, although first-in-first-out nature. This application report will consequently focus exclusively FIFOs that variable length their data. There always electronic systems connected input output FIFO, that writes that reads. certain timing conditions have maintained between writing reading system, speak synchronous FIFOs, because systems have synchronized. there timing restrictions systems driven, meaning that writing system reading system work synchronism, FIFO called asynchronous. first FIFO designs appear market were synchronous because these were easier implement. present FIFOs nearly asynchronous because many applications call asynchronous versions. Asynchronous FIFOs can, course, also used synchronous systems without difficulty.
Synchronous FIFOs
synchronous FIFOs writing data independent they read. There timing relationships between write clock read clock. Overlapping read write clock could prohibited instance. permit such FIFOs between systems that work asynchronously another, external circuit required synchronization. this sync circuit will usually reduce data rate considerably.
Asynchronous FIFOs
asynchronous FIFOs there kind dependence between writing reading data. Writing reading possible simultaneously, overlapping fashion successively. This means that systems with different frequencies connected FIFO. designer does have worry about synchronizing systems because this taken care FIFO. Asynchronous FIFOs, depending control signals writing reading, fall into groups: Strobed FIFOs Clocked FIFOs
2.2.1 Metastability Synchronizing Circuits
digital engineering there constantly recurring problem synchronizing systems that work different frequencies. Asynchronous FIFOs also handle data exchange between systems different frequencies,
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FIFO TYPES internal synchronizing circuits called for. This chapter brief introduction problems that involved synchronization. problem synchronizing external signal with local clock generator normally solved means flip-flop (Fig. this means violation setup hold times that stated data sheets circuits. result flip-flop into metastable state.
Fig.
Synchronization external Signal
With flip-flop setup hold time maintained. This means that short time before clock edge (setup time) short time afterwards (hold time) level input must alter ensure that function flipflop executed correctly. these conditions maintained, flip-flop become metastable. flip-flop metastable states possible reset inputs change from active inactive state same time. both cases flip-flop adopts undefined unstable metastable state. defined state guaranteed outputs course. After time flipflop goes into stable states, possible predict which.
Fig.
Timing Diagram Metastab State
These operating conditions flip-flops easily maintained synchronous circuits. with asynchronous circuits synchronizing circuits above violations operating conditions flip-flops unavoidable. Asynchronous FIFOs that driven systems working asynchronously
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FIFO TYPES another must perform internal synchronization asynchronous external signals. physical reasons there ideal flip-flops with setup hold time there synchronizing circuit that works absolutely faultlessly. quality synchronizing circuit given MTBF, i.e. Mean Time Between Failures. This calculated from frequency asynchronous signal (fin), clock frequency synchronizing circuit (fclk) length critical time window MTBF (eq.
clock frequency fclk MHz, input frequency critical time window MTBF 33.3s
flip-flop used synchronize signals, longer expect maximum delays stated data sheets. reliable operation system therefore, must know long necessary wait after clock pulse until data evaluated.
Fig.
Block Diagram Two-Level Synchronization
MTBF figure improved appreciably multi-level synchronization. Fig. illustrates two-level synchronizing circuit timing signals shown Fig. second flip-flop only into metastable state first flip-flop already metastable. This metastability increase delay first flip-flop quite considerably. period clock signal longer than increased delay plus setup time second flip-flop, second flip-flop never into metastable state.
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FIFO TYPES
Fig.
Timing Diagram Two-Level Synchronization
Fig.
Signals FIFO with Single-Level Synchronization, Recorded Hours under Worst-Case Conditions
measure metastability, conventional asynchronous FIFOs were operated metastable region READ CLOCK input signal EMPTY output signal were recorded period using storage oscilloscope.
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FIFO TYPES signal patterns single-level synchronization shown Fig. easy that synchronizing flip-flop sometimes decides sometimes level first clock edge. some cases decision obviously difficult flip-flop, because takes much more time than normally. After second clock edge output stable again every case. measurement that illustrated Fig. performed SN74ACT7807 FIFO from TEXAS INSTRUMENTS This FIFO features three-level synchronization. Here decision High level EMPTY output sometimes comes clock cycle later, metastable response with much longer time decide longer observed.
Fig.
Signals SN74ACT7807 FIFO from TEXAS INSTRUMENTS with ThreeLevel Synchronization, Recorded Hours under Worst-Case Conditions
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FIFO TYPES
2.2.2 Strobed FIFOs
control signals Strobed FIFO correspond most closely human intuition were therefore, past, only kind FIFO driving. block diagram Fig. shows control lines Strobed FIFO Fig. illustrates typical timing these lines read write operation. control lines WRITE CLOCK FULL
used write data. When data word written into Strobed FIFO, first necessary check whether there space available FIFO. This done querying FULL status line. free space indicated, data word applied data inputs written into FIFO clock edge WRITE CLOCK input. analogous fashion, control lines READ CLOCK EMPTY
used read data. this case EMPTY status output queried before reading, because data only read there stored FIFO. Then clock edge applied READ CLOCK input, causing first word data queue appear data output.
Fig.
Connections Strobed FIFO
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FIFO TYPES timing Fig. shows resetting FIFO that always necessary beginning. Then three data words written data words through appear after other INPUT DATA inputs clock edges applied WRITE CLOCK transfer data. Once first data word been written into FIFO, EMPTY signal changes from high level. Another data words written into FIFO before first read cycle. subsequent reading first data word with clock edge READ CLOCK does alter status signals. With writing another data words FIFO full. This indicated FULL signal. Finally four data words through remaining FIFO read out. Thus FIFO empty again, EMPTY status line shows this level.
Fig.
Timing Diagram Strobed FIFO Length
drawback FIFO this kind that status signals cannot fully synchronized with read write clock. example this illustrated Fig.
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FIFO TYPES
Fig.
Asynchronism when Resetting FULL Signal
there only space FIFO data word, next write cycle will FULL signal. Then writing system queries FULL signal with flip-flop waits until there again space FIFO. When data word read, READ CLOCK resets FULL status line. This reset synchronous with reading system asynchronous writing system. worst case setup hold time flip-flop writing system violated. This flip-flop therefore goes into metastable state, results which were already looked Chapter 2.2.1. problem described above also occurs with EMPTY status signal. EMPTY should synchronous with reading system, reset writing system. resetting EMPTY inevitably asynchronous reading system. This asynchronism result system synchronization possible within Strobed FIFO. synchronization should necessary, designer provide externally. there nevertheless wide-ranging application possibilities Strobed FIFOs.
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FIFO TYPES
2.2.3 Clocked FIFOs
which Clocked FIFOs controlled based methods control proven processor systems. Every digital processor system works synchronized with system-wide clock signal. This system timing continues even actions being executed. ENABLE signals, also often called CHIP SELECT signals, start synchronous execution write read operations various devices like memories ports.
Fig.
Connections Clocked FIFO
block diagram Fig. shows signal lines Clocked FIFO. requires free-running clock from writing system another from reading system. Writing controlled WRITE ENABLE input synchronous with WRITE CLOCK. FULL status line synchronized entirely with WRITE CLOCK free-running clock. analogous manner data words read level READ ENABLE input synchronous with READ CLOCK. Here free-running clock permits 100% synchronization EMPTY signal with READ CLOCK. This means that Clocked FIFOs easily integrated into common processor architectures, offering complete synchronism FULL EMPTY status signals with particular free-running clock.
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FIFO TYPES
Fig.
Timing Diagram Clocked FIFO Length
Fig. shows typical wave form Clocked FIFO. WRITE CLOCK READ CLOCK free-running. writing data into FIFO initialized level WRITE ENABLE line. data written into FIFO with next rising edge WRITE CLOCK. analogous fashion READ ENABLE line controls reading data synchronous with READ CLOCK. status lines within FIFO synchronized free-running clock signals. FULL line only changes level synchronously with WRITE CLOCK, even change produced reading data word. Likewise, EMPTY signal synchronized with READ CLOCK. Clocked FIFO only asynchronous FIFO which status signals synchronized with driving logic. Clocked FIFOs from TEXAS INSTRUMENTS feature multi-level synchronization status lines described Chapter 2.2.1.
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FIFO Architectures
FIFO Architectures
kinds FIFO described chapter implemented different hardware architectures. past architecture conventional FIFOs constantly been further developed. begin with, FIFOs worked fallthrough principle. Today FIFOs nearly always based S-RAM. This meant considerable increase number data words stored, despite faster speed. possible hardware architectures also found software FIFOs.
Fall-Through FIFOs
Fall-through FIFOs were first FIFO generation. customers queuing cashpoint supermarket could easily have been model this variant. first customer goes right cashpoint while others queue behind. Once first customer paid left front queue, other customers move place.
3.1.1 Architecture
Fig.
Circuitry Fall-Through FIFO
Fig. shows possible design this kind FIFO, implemented example SN74S225. half illustration there 201E
FIFO Architectures latches storing data words. clock generator bottom half controls data transfer, shifting data data output chain latches. When word written into FIFO, "falls through" entire latches stored last free location. reading word causes remaining words shifted position direction output. fall-through FIFO, like other FIFO, reset before used that clock generator defined initial state. internal states produced this clock generator when shifting word shown Fig. clock pulses generated entirely internal gate propagation delays.
Fig.
Timing Diagram Fall-Through FIFO Fig.
Fig. possible clock generator, when writing word, produces clock pulse turn. With these clock pulses data word shifted through latches last that free. clock generator also produces necessary status information each data word, specifying whether data latch already contains valid data word still empty. time required data word shifted from input through output called fall-through time.
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FIFO Architectures
3.1.2 Advantages Drawbacks
There must status flip-flop each data word, effort involved controlling data latches only justifiable very short FIFOs. With long FIFOs there also enormous increase fall-through time. 16X5 fallthrough FIFO SN74S225 maximum delay guaranteed from READ CLOCK FULL signal. 1024X18 FIFO like SN74ACT7811 would require multiple this time with fall-through architecture. existence fallthrough architecture historical reasons. developments longer this principle.
FIFOs with Static Memory
counter drawback long fall-through time long FIFOs, architecture should longer shift data words through memory locations. problem solved circular memory with pointers. circular FIFO concept memory address incoming data write pointer. address first data word FIFO that read read pointer. After reset both pointers indicate same memory location. After each write operation write pointer next memory location. reading data word sets read pointer next data word that read out. read pointer constantly follows write pointer. When read pointer reaches write pointer, FIFO empty. write pointer catches with read pointer, FIFO full. Fig. outlines principle circular FIFO with pointers.
Fig.
Circular FIFO with Pointers 201E
FIFO Architectures
3.2.1 Architecture
hardware implementation circular memory dual-port SRAM used data storage. pointers take form binary counters, which generate memory addresses SRAM. advantage number memory locations because then pointer implemented n-bit binary counter whose carry ignored. Fig. shows block diagram FIFO with static memory. Read addresses generated READ POINTER write addresses WRITE POINTER. write-control read-control blocks control operation during write read access. FULL EMPTY status signals generated separate flag logic. Some FIFOs also offer status signals HALF FULL, ALMOST FULL ALMOST EMPTY. FIFO with static memory also initialized before used pointers status logic defined initial states.
Fig.
Block Diagram FIFO with Static Memory
3.2.2 Advantages Drawbacks
Unlike fall-through FIFO, fall-through time FIFO with static memory independent length. This means that possible create fast FIFOs with length several thousand words. effort that goes into circuitry control logic does increase significant degree with length, because only pointers parts flag logic have expanded. Today's developments only architecture FIFO with static memory.
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FIFOs from Texas Instruments
FIFOs from TEXAS INSTRUMENTS
TEXAS INSTRUMENTS range there both Strobed FIFOs (e.g. ACT2235) Clocked FIFOs (e.g. ACT7801). circuits offered asynchronous FIFOs with static memory.
Features
4.1.1 Data Outputs with Latches
data outputs FIFOs from TEXAS INSTRUMENTS buffered latch (Fig. 17), output signal always valid. outputs sent highimpedance with separate input signal
Fig.
Wave forms FIFO Outputs
4.1.2 Synchronization Flags
FIFOs from TEXAS INSTRUMENTS flags ALMOST EMPTY, HALF FULL ALMOST FULL often implemented addition FULL EMPTY status outputs. conditions ALMOST EMPTY ALMOST FULL usually programmable. flags Clocked FIFOs from TEXAS INSTRUMENTS bear following designations: EMPTY FULL (OUTPUT READY) (INPUT READY)
shown Chapter 2.2.2, status outputs Strobed FIFOs cannot synchronized entirely because factors system. resetting status outputs always triggered signals that asynchronous status signal:
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FIFOs from Texas Instruments WRITE CLOCK signal resets EMPTY status output, EMPTY should synchronous with READ CLOCK. READ CLOCK signal resets FULL status output, FULL should synchronous with WRITE CLOCK. status outputs Clocked FIFOs from TEXAS INSTRUMENTS through multi-level synchronization when flags reset, described Chapter 2.2.1. This means that resetting status outputs delayed clock cycles. Fig. shows this taking (OUTPUT READY) flag SN74ACT7801 example. most cases this delay insignificant however, because does affect data rate either writing reading. status outputs without delay because this triggered synchronous signal.
Fig.
Signals Clocked FIFO SN74ACT7801 Synchronization Status Outputs
with
Multi-Level
4.1.3 Edges Outputs
patented OEC(Output Edge Control) circuit simultaneously limits current across VCC, outputs. This reduces noise caused switching operations. This offers best possible protection against noise wave forms against alteration memory contents.
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FIFOs from Texas Instruments
Extending Word Width
Fig. Extending Word Width Strobed FIFOs
Fig. Extending Word Width Clocked FIFOs
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FIFOs from Texas Instruments types FIFOs very easy cascade their word width, shown Fig. control inputs FIFOs used connected parallel. status outputs sufficient, theory, look just FIFO because parallel connected FIFOs must always show same internal state. safer consider status lines FIFOs that differences delay between FIFOs lead malfunctions. This taken care simply with gates.
Extending Memory Depth
memory depth Clocked FIFOs easily extended. Fig. that individual FIFOs configured fall-through principle. extra clock signal required transfer data from first FIFO second. This clock signal WRITE CLOCK, READ CLOCK another free-running clock signal, frequency this clock signal determines fall-through time. higher frequency clock signal, faster fall-through time overall system. This fall-through time does degrade data rate when reading writing however.
Fig. Extending Memory Depth Clocked FIFOs
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Application Examples
Application Examples
this chapter number application examples will looked illustrate versatility performance FIFOs from TEXAS INSTRUMENTS
Asynchronous Operation Synchronous FIFOs
synchronous FIFOs SN74LS222A, SN74LS224A, SN74LS227 SN74LS228 timing conditions write (WRITE CLOCK) read (READ CLOCK) inputs have maintained ensure proper functioning devices. Asynchronous FIFOs also offered market which, their empty full state, require timing conditions between write read inputs that will ensure errorfree working FULL EMPTY flags. Fig. shows timing conditions signals WRITE READ CLOCK abovementioned types FIFO. Besides minimum pulse widths signals (WRITE CLOCKmin READ CLOCKmin ns), necessary ensure that alternating write read instructions separated time window least
Fig.
Timing Conditions WRITE READ CLOCK
write read signals originate from sources that work asynchronously another, synchronizing circuit should used shown Fig. This will ensure correct operation even signals appear same time.
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Application Examples
Fig.
Synchronizing Circuit Generating WRITE CLOCK READ CLOCK Signals
positive edge WRITE signal first sets flip-flop FF1. Flip-flop next edge signal. clock signal goes again, READ CLOCK signal appears output gate length determined long clock signal level. circuit generating WRITE CLOCK signal works same way. avoid conflicts WRITE READ signals appear same time, READ function higher priority. produce this, output flip-flop disables gate when READ CLOCK signal being generated, WRITE CLOCK signal delayed clock period. There also WRDY RRDY outputs, which level during write read cycle.
Fig. Timing Signals Synchronizing Circuit Fig. shows timing circuit. this case WRITE READ signals appear simultaneously. mentioned above, READ function higher priority first READ CLOCK signal generated then, next clock period, WRITE CLOCK signal. 201E
Application Examples Finally maximum possible frequency signal determined. WRITE CLOCK signal, according data sheet, should least length. Thus minimum time defined during which clock signal must low. According Fig. there must time window least between WRITE CLOCK READ CLOCK signals. This corresponds minimum time that clock signal must high. READ WRITE signals asynchronous signal, setup hold timing conditions flip-flops maintained. flip-flops SN74ALS series used, time sufficient prevent metastable states occur with these flip-flops (MTBF 1000 years). therefore, take being each, maximum clock frequency becomes 1/(twL twH) MHz. This turn means that maximum write frequency maximum read frequency MHz.
Connection Peripherals Processors
Modern processors often considerably faster than those peripherals connected them. FIFOs used that processing speed processor does have reduced when exchanges data with peripheral. peripheral sometimes faster than processor, FIFO again used resolve problem. Different variations circuitry possible, depending particular problem. some cases processor will read input data over unidirectional peripheral, e.g. from converter (see Fig. 25). FIFO buffer certain amount input data then interrupt that processor reads data. This interrupt triggered HALF FULL, ALMOST FULL FULL flag.
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Application Examples
Fig.
Connection unidirectional peripheral with FIFO SN74ACT7801
Fig.
Connection bidirectional peripheral with FIFO SN74ACT2235
Often connected peripherals bidirectional, like parallel port, serial port, hard-disk controller interface with magnetic-tape drive. these cases there possibility using bidirectional FIFO like SN74ACT2235. independent FIFOs implemented this device, each with word width
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Application Examples bits memory depth 1024 words. Fig. shows block diagram such application. above circuit also combined with controller. Without FIFO controller will normally request from processor control entire duration data transfer. processor must wait transfer cannot work meantime. FIFO, shown Fig. permits block transfer data. FIFO collects incoming data. When stored enough data, FIFO uses HALF FULL, ALMOST FULL FULL flag request data transfer controller. latter only requires control during data transfer from FIFO RAM, after which control returned processor. data transferred block block from FIFO into RAM.
Fig.
Connection SN74ACT2235
Bidirectional
Peripheral
with
FIFO
FIFO used same optimize data transfer from processor peripheral. practical example connection fast peripheral processor, will look compression digitized video signal with TMS320C30 signal processor. video signal digitized converter (ADC) then picture information contained video signal compressed signal processor. Besides picture information video signal (Fig. includes pulses horizontal vertical synchronization well porch. only pure picture information interest further processing TMS320C30 signal processor
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Application Examples
Fig.
Video Signal with Picture Information Porch
data rate digitized picture information high direct acceptance TMS320C30. But, because picture information only accounts part video signal, time scanning line quite sufficient receiving data. FIFO used buffer data, computing time that gained even made compress data.
Fig.
Digitizing Compressing Video Signal with TMS320C30 Signal Processor
circuit shown Fig. first digitizes video signal with ADC. clock generator produces timing from video signal. cycle generator only transfers clock signal FIFO digitized picture data, data originating from porch synchronization. Once there enough data buffered FIFO, HALF FULL flag starts data transfer means (Direct Memory Access) controller.
Block Transfer Data
Data often split into blocks transmitted data lines. Computer networks digital telephone switching installations examples this kind application. such conversion into blocks made very high speed, will only possible with appropriate hardware, through software. very simple solution this hardware problem FIFOs, illustrated circuit Fig. FIFO should selected that HALF FULL flag. 201E
Application Examples Furthermore, memory depth should correspond twice size block. soon HALF FULL flag set, send controller starts sending data block. send controller consists this case counter some gates very easy implement with just PAL. writing data into FIFO carried continuously quite independent transfer data blocks.
Fig.
Block Transfer Data with Clocked FIFO SN74ACT7801
Programmable Delay
With FIFOs possible implement programmable, digital delay line with minimum effort. Because programmable AF/AE (ALMOST FULL/ALMOST EMPTY) flag SN74ACT7801, only inverter necessary addition FIFO (Fig. 31).
Fig.
Programmable Digital Delay with SN74ACT7801 201E
Application Examples First program AF/AE flag according required delay clock cycles value n-2. obtain 64-bit delay line, instance, programming AF/AE When write data words into FIFO, constantly fills. When number stored data words corresponds programmed value, AF/AE flag changes clock cycles later level. delay clock cycles results from integrated, multi-level synchronization AF/AE flag. This flag then starts, with inverter, reading data words output FIFO. From here FIFO works like shift register fixed length. timing signals this programmable, digital delay illustrated Fig.
Fig.
Timing Signals Programmable Digital Delay with SN74ACT7801
Collecting Data before Event
Some applications require data collected that appear before event. This solved with circular memory whose data intake stopped event. FIFO makes excellent basis circuit fulfill this function. circuit shown Fig. extension programmable delay Fig. timing signals circuit illustrated Fig.
Fig.
Collecting Data before Event with SN74ACT7801
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Application Examples
Fig. Timing Circuit Fig. After circuit been reset, AF/AE flag programmed with input signal. programmed value corresponds number data words stored before event. When TRIGGER WINDOW input signal changes high level, FIFO starts store data. Because integrated, multi-level synchronization AF/AE flag takes effect clock cycles after value. From here FIFO begins read excess data words. Thus there always data words stored FIFO. When event occurs TRIGGER WINDOW input signal changes level, another data word read thus AF/AE signal reset. This terminates data output. READ ENABLE input signal enables reading required data that data word appears OUTPUT DATA outputs with each rising clock edge.
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Application Examples
Collecting Data before after Event
extension circuit Fig. data words collected both before after occurrence event (Fig. 35). 1024 data words always collected. With programmable AF/AE (ALMOST FULL/ALMOST EMPTY) flag possible specify number data words that collected before after event.
Fig.
Collecting Data before after Event with SN74ACT7801
Until appearance event, circuit works like that Fig. Here flip-flop used drive WRTEN input. TRIGGER WINDOW sets this flip-flop thus permits data capture. When event occurs TRIGGER WINDOW signal goes level, data still captured until (Input Ready) flag level flip-flop reset. There also gate signal path from AF/AE output RDEN1/RDEN2 input. This prevents continued reading data after event. Once data have been captured, collected data words read out. Fig. show timing signals this circuit with AF/AE flag programmed such case, (n+2) data words collected before event (1022-n) 1016 data words after event.
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Application Examples
Fig.
Timing signals circuit Fig. during initialization start data capture
Fig.
Timing signals circuit fig. data capture start readout
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Summary
Summary
Because their versatile possibilities use, FIFOs present solutions very many different applications. There different kinds FIFO according their function, especially attractive features being offered asynchronous Strobed FIFOs asynchronous Clocked FIFOs. choice between these will depend application they intended for. With asynchronous Strobed FIFOs flags cannot entirely synchronized however. Wherever possible, asynchronous Clocked FIFO should given preference because only FIFO that offers entirely synchronized flags. FIFOs designed with different architectures. FIFO architecture that established itself firmly today FIFO with static memory. Fall-through FIFOs present advantages some serious drawbacks compared FIFOs with static memory. TEXAS INSTRUMENTS offers solely asynchronous FIFOs with static memory. FIFO range from TEXAS INSTRUMENTS includes both Strobed Clocked FIFOs virtually every kind application every speed requirement.
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Author: Peter Forstner Date: 10.12.91 Rev.: This report takes det

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