SPSU006B October 1998 Copyright 1998, Texas Instruments Incorpora
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MSP50x3x Mixed-Signal Processor User's Guide
SPSU006B October 1998
Copyright 1998, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This manual describes MSP50x3x family speech synthesizing devices. When necessary, differences between family members shown separate consecutive sections. object this user's guide provide information needed implement speech synthesizer design using MSP50x3x devices.
This Manual
This document contains following chapters: Chapter Introduction MSP50x3x Family This chapter describes MSP50x3x family features, options, assignments descriptions, gives brief introduction linear predictive coding. MSP50x3x Family Architecture This chapter describes architecture MSP50x3x family with separate sections speech synthesis, interrupts, power control, initialization, clocks. MSP50x37, there separate sections analog-to-digital converter power amplifier. MSP50x3x Assembler This chapter contains detailed description MSP50x3x assembler. MSP50x3x Instruction This chapter provides instruction MSP50x3x. MSP50x3x Applications This chapter describes various hints useful advice designing applications MSP50x3x.
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Chapter
Chapter
Chapter
Chapter
Running Title-Attribute Reference
Chapter
Customer Information This chapter describes customer information including development cycles structure, speech development/production sequence, mechanical information, ordering information. Script Preparation Speech Development Tools This appendix describes script preparation development tools MSP50x3x. MSP50C3x Versus TSP50C1x This appendix contains information about switching from TSP50C1x family device MSP50C3x family device MSP50x3x Sample Dual Synthesis Program This appendix contains sample dual synthesis program that uses both channels speak echo. Sample Synthesis Program This appendix contains sample synthesis program that counts numbers from five channel only. MSP50C3x Data Sheet This appendix contains data sheet MSP50C3x family devices. This data sheet lists absolute maximum operating condition, recommended operation conditions, electrical characteristics MSP50C3x devices.
Appendix
Appendix
Appendix
Appendix
Appendix
Notational Conventions
Notational Conventions
This document uses following conventions.
Program listings, program examples, interactive displays shown special typeface similar typewriter's. Here sample program listing:
0349 0059 0350 005A 005B SPEAK2 LUAA ANEC StopWord -Get word -End phase?
syntax descriptions following notational conventions used this guide:
reserved keyword instruction, command directive) shown bold capital letters should entered shown. optional field indicated brackets italics describes type information that should entered: [label User-supplied contents indicated angle brackets italics describe type information that should entered: <num required blank indicated caret (^).
following syntax example demonstrates notational conventions used this guide. [<label >]^ABAAC^.[<comment lower case numeric value indicates that value hexadecimal (e.g., 01FAh, 032Bh, 0FFh). addresses this manual hexadecimal format unless otherwise noted. other numbers decimal format unless otherwise noted. Abbreviations:
'04: MSP50C04 '06: MSP50C06 '10: MSP50C10 '11: MSP50C11 '12: MSP50C12 '13: MSP50C13 '14: MSP50C14 '19: MSP50C19 LSB, MSB: Least significant most significant bits LSbyte, MSbyte: Least significant most significant bytes
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Information About Cautions
Port refers pins operating together. Port refers pins operating together. Individual bits register indicated with register abbreviation followed decimal point number (e.g., register mode register MR.2). contents location pointed address stored register. indicates contents register
Information About Cautions
This book contain cautions.
This example caution statement. caution statement describes situation that could potentially damage your software equipment.
information caution provided your protection. Please read each caution carefully.
Need Assistance
Need Assistance
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Notes:
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Trademarks
IBM, PC/XT, PC/AT trademarks Corporation. trademark Texas Instrument Incorporated.
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viii
Contents
Contents
Introduction MSP50x3x Family MSP50x3x Device Family Applications Description Features 1.4.1 MSP50x32/33/34 Additional Features 1.4.2 MSP50x37 Additional Features Options 1.5.1 Two-Pin Push Pull (Option Accurate part 1024 1.5.2 Single-Pin Double-Ended (Option Accurate part 1024 1-12 Terminal Assignments Signal Descriptions 1-15 1.6.1 MSP50x32/33/34 Terminal Assignments Signal Descriptions (16-Terminal Package) 1-15 1.6.2 MSP50C34/P34 Terminal Assignments Signal Descriptions 1-18 1.6.3 MSP50x37 28-Pin Package Terminal Assignments Signal Descriptions 1-21 Introduction Linear Predictive Coding (LPC) 1-23 1.7.1 Vocal Tract 1-23 1.7.2 Model 1-23 1.7.3 Data Compression 1-24 MSP50x3x Mask Options 1-25 1.8.1 Clock Select Option 1-25 1.8.2 Option 1-26 1.8.3 Power Amplifier Options (MSP50C37 Only) 1-27 MSP50x3x Family Architecture MSP50C3x Family Architecture 2.1.1 Read-Only Memory (ROM) 2.1.2 Program Counter 2.1.3 Program Counter Stack 2.1.4 MSP50C3x Random Access Memory (RAM) 2.1.5 MSP50C3x Memory-Mapped Registers 2.1.6 Arithmetic Logic Unit (ALU) 2-11 2.1.7 Register 2-11 2.1.8 Register 2-12 2.1.9 Register 2-12
Contents
2.1.10 Status Flag 2.1.11 Integer Mode Flag 2.1.12 Timer Register 2.1.13 Timer Prescale Register 2.1.14 Pitch Register Pitch Period Counter (PPC) 2.1.15 Speech Address Register (SAR) 2.1.16 Parallel-to-Serial Register 2.1.17 Input/Output Ports 2.1.18 Mode Registers Speech Synthesis 2.2.1 Synthesizer Mode 2.2.2 Synthesizer Mode 2.2.3 Synthesizer Mode 2.2.4 Synthesizer Mode excited 2.2.5 Synthesizer 2.2.6 Pass Filter 2.2.7 Channel Scaling (C3) 2.2.8 Frame Length Control 2.2.9 Digital-to-Analog Converter Interrupts MSP50C3x Power Control Initialization MSP50C3x Clocks 2.5.1 Internal Oscillator 2.5.2 External Oscillator 2.5.3 External Clock 2.5.4 Long Interval Monitor Timer Timer-2 (MSP50x37 Only) Analog-to-Digital Converter (MSP50x37 Only) Power Amplifier (MSP50x37 Only)
2-12 2-13 2-13 2-14 2-14 2-16 2-16 2-17 2-19 2-22 2-22 2-22 2-23 2-23 2-23 2-25 2-25 2-26 2-26 2-27 2-29 2-30 2-30 2-30 2-30 2-31 2-32 2-33
MSP50C3x Assembler Description Notation Used Invoking Assembler Command-Line Options 3.3.1 BYTE Unlist Option 3.3.2 DATA Unlist Option 3.3.3 XREF Unlist Option 3.3.4 TEXT Unlist Option 3.3.5 WARNING Unlist Option 3.3.6 Complete XREF Switch 3.3.7 Object Module Switch 3.3.8 Listing File Switch 3.3.9 Page-Eject Disable Switch 3.3.10 Error-to-Screen Switch 3.3.11 Instruction Count Switch
Contents
3.10 3.11
3.3.12 Show Usage Switch 3.3.13 Macro Switch 3.3.14 Symbolic Debugging Switch Assembler Input Output Files 3.4.1 Assembler Source File 3.4.2 Assembler Binary Object File 3.4.3 Assembler Listing File Source Statement Format 3.5.1 Label Field 3.5.2 Command Field 3.5.3 Operand Field 3.5.4 Comment Field 3.5.5 Constants Symbols 3-11 Character Strings 3-12 Expressions 3-13 3.8.1 Arithmetic Operators Expressions 3-13 3.8.2 Parentheses Expressions 3-13 Assembler Directives 3-14 3.9.1 AORG Directive 3-16 3.9.2 BYTE Directive 3-16 3.9.3 COPY Directive 3-16 3.9.4 DATA Directive 3-17 3.9.5 Directive 3-17 3.9.6 Directive 3-17 3.9.7 Directive 3-18 3.9.8 LIST Directive 3-18 3.9.9 NARROW Directive 3-19 3.9.10 OPTION Directive 3-19 3.9.11 PAGE Directive 3-21 3.9.12 RBYTE Directive 3-21 3.9.13 RDATA Directive 3-22 3.9.14 RTEXT Directive 3-22 3.9.15 TEXT Directive 3-23 3.9.16 TITL Directive 3-23 3.9.17 Directive 3-24 3.9.18 WIDE Directive 3-24 3.9.19 MACRO/ENDM Directive 3-25 3.9.20 TABSIZE Directive 3-26 Listing Formats 3-27 Placing Binary Data Above #FFFF 3-28
Contents
Contents
MSP50x3x Instruction Instruction Syntax MSP50x3x Assembly Instructions Applications Synthesizer Control 5.1.1 Speech Coding Decoding 5.1.2 Usage 5.1.3 Usage Program Overview 5.2.1 Initialization 5.2.2 Phrase Selection 5.2.3 Speech Initialization 5.2.4 Interpolation Routine 5-10 5.2.5 Frame-Update Routine 5-11 Dual Synthesis Program Walk-Through 5-12 Arithmetic Modes 5-45 Operation Multiply Instruction 5-48 Power-Saving Modes 5-49 5.6.1 Standby Mode 5-49 5.6.2 Sleep Mode 5-49 Slave Mode 5-50 5.7.1 Slave-Mode Write Operation 5-51 5.7.2 Slave-Mode Read Operation 5-52 Instruction 5-54 5.8.1 From Internal 5-55 5.8.2 From Internal 5-56 Generating Tones Using 5-58 5.9.1 Operation TASYN Instruction Mode 5-58 5.10 5-60 Customer Information Development Cycle Summary Speech Development/Production Sequence Mechanical Information 6.3.1 Plastic Dual-In-Line Packages 6.3.2 DW016 DW028 Plastic Small-Outline Wide-Body (SOWB) Packages Ordering Information 6-10 Product Release Forms (MSP50C3x) 6-11 6.5.1 Product Release Form MSP50C32 6-12 6.5.1 Product Release Form MSP50C33 6-15 6.5.1 Product Release Form MSP50C34 6-17 6.5.2 Product Release Form MSP50C37 6-20
Contents
Script Preparation Speech Development Tools Script Generation A.1.1 Speaker Selection A.1.2 Speech Collection A.1.3 Editing A.1.4 Pitfalls Speech Development Tools A.2.1 WINSDS Features A.2.2 EMU50C3x Features A.2.3 MSD50C3x Features A.2.4 OTP-PROG2 Features MSP50C3x Versus TSP50C1x Summary Changes from TSP50C1x Family Upgrading TSP50C1x Program MSP50C3x Program B.2.1 Normal Operation B.2.2 B.2.3
MSP50C3x Sample Dual Synthesis Program MSP50C3x Sample Dual Synthesis Program Sample Synthesis Program Sample Synthesis Program MSP50C3x Family Data Sheet MSP50C3x Family Data Sheet
Contents
xiii
Figures
Figures
1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-17 5-10
MSP50x3x Functional Block Diagram MSP50x37 Functional Block Diagram Output Waveforms Two-Pin Push Pull (Option Four-Transistor Amplifier Circuit 1-10 Operational Amplifier Interface Circuit 1-10 Power Amplifier Interface Circuit 1-11 Figure 1-7. Output Waveforms Single-Pin Double-Ended (Option 1-12 Operational Amplifier Interface Circuit 1-13 Two-Pin Push Pull Power Amplifier Output Circuit with External 1-14 One-Pin Analog Power Amplifier Output Circuit with External 1-14 MSP50x32/33/34 16-Pin Package Terminal Assignments 1-15 Power-Up Initialization Circuit 1-17 MSP50P34 40-Pin Package Terminal Assignments 1-18 MSP50x37 28-Pin Package Terminal Assignments 1-21 LPC-12 Vocal Tract Model 1-24 Oscillator Circuit 1-26 External Clock Interface 1-26 MSP50C3x System Block Diagram MSP50x37 System Block Diagram MSP50x32/33/34 MSP50x37 During Speech Generation 2-24 Oversampling Output Filter 2-25 Oversampling Output Filter Circuit 2-33 Frame Decoding Speech Parameter Unpacking Decoding ACAAC Extended-Sign Mode 5-47 ACAAC Integer Mode 5-47 Slave-Mode Write Operation 5-52 Slave-Mode Read-Then-Write Operation 5-53 Register Connections Instruction 5-54 Parallel-to-Serial Operation Instruction 5-55 Operation TASYN Mode 5-58 Format Data Register before TASYN 5-58 Speech Development Cycle MSP50C32/33/34 16-Pin Package
Figures
MSP50C32/33/34 28-Pin Package MSP50P34 40-Pin Package MSP50C32/33/34 MSP50P34/37 Package WINSDS EMU50C3x MSD50C3x OTP-PROG
Contents
Tables
Tables
2-10 MSP50x3x Device Family MSP50x3x Options MSP50C32/33/34 16-Pin Package Terminal Functions 1-16 Location MSP50C32/C33 Form 1-17 MSP50P34 40-Pin Package Terminal Functions 1-19 Location MSP50C34/P34 Form 1-20 MSP50x37 28-Pin Package Terminal Functions 1-22 Reserved Locations Memory-Mapped Registers 2-10 Registers 2-17 Terminal Functions 2-17 Mode Register 2-20 Mode Register 2-21 Level-1 Interrupt Vectors 2-27 Level-2 Interrupt Vectors 2-27 Memory Assignment Additional Timer 2-31 Port Terminal input 2-32 Switches Options Summary Assembler Directives 3-15 MSP50x3x Instruction MSP50x3x Instruction Table Parameter Size Hardware-Fixed Locations Other Locations Used Sample Program FLAGS Descriptions Sample Program FLAGS_1 FLAGS_2 Descriptions Sample Program Usage Operation 5-46 Mode Register Control Data Source 5-55 Relative Weights Magnitude Bits 5-59 Interrupt Vectors TSP50C1x MSP50C3x Ports TSP50C1x MSP50C3x
Examples
Examples
XREF Unlist Option
Contents
xvii
Notes, Cautions, Warnings
Notes Cautions
MSP50C34I/O Lines 1-15 Unused Terminals 2-18 Pins 2-18 Using ORCM Instruction 2-19 TSP50C1x Device Family 2-29 Additional Precautions 2-29 Long Interval Timer 2-31 Transferring Data Register 2-31 MSP50x37 Timer Registers Development Tools 2-31 AORG# 10000 Statement Restriction 3-28 Extended-Sign Mode 4-32 Extended-Sign Mode 4-33 RETI Executed With Interrupts Enabled 4-36 Instruction 5-55 Using Prototype Devices Production Systems Required Recommended Equipment TSP50C19
xviii
Chapter
Introduction MSP50x3x Family
MSP50x3x family uses revolutionary architecture combine 8-bit microprocessor, speech synthesizers, ROM, RAM, low-cost single-chip system. architecture uses same arithmetic logic unit (ALU) synthesizers microprocessor, thus reducing chip area cost enabling microprocessor multiply operation MSP50x3x family features semi-independent channels linear predictive coding (LPC), which synthesize high-quality speech data rate. Pulsecode modulation (PCM) produce music sound effects. added together produce composite result.
Topic
Page
MSP50x3x Device Family Applications Description Features Options
1.6.1 Terminal Assignments Signal Descriptions 1-15 1.6.3 MSP50x37 Terminal Assignments Signal Descriptions 1-21 Introduction Linear Predictive Coding (LPC) 1-23 Mask Options 1-25
MSP50x3x Device Family
MSP50x3x Device Family
MSP50x3x family speech synthesizers consists family members differentiated size type hard storage incorporated device. Table gives list members with amount PROM each device.
Table 1-1. MSP50x3x Device Family
Device MSP50C32 MSP50C33 MSP50C34 MSP50P34 MSP50C37 MSP50P37 Amount ROM/PROM bytes mask bytes mask bytes mask bytes PROM bytes mask bytes PROM Features 9/10 lines 9/10 lines 9/10 lines package, lines form 9/10 lines lines, converter/analog amplifier lines, converter/analog amplifier
Applications
Applications
MSP50x3x highly flexible programmable, making suitable wide variety applications. system cost opens applications solid-state speech. These include:
Talking clocks Toys Games Telephone answering machines Home monitors Navigation aids Laboratory instruments Personal computers Inspection controls Inventory controls Machine controls Warehouse systems Warning systems Appliances Voice mailboxes Equipment handicapped Learning aids Computer-aided instruction Magazine direct-mail advertisements Point-of-sale displays Talking books
MSP50x37 basically designed warning systems such warning system (GWS), smoke detector systems, other similar applications. device flexible enough used other applications that require converters such motor control toys, etc.
Introduction MSP50x3x Family
Description
Description
MSP50x3x divided into several functional blocks (see Figure Figure 1-2). shared speech synthesizers microcomputer. MSP50x3x implements LPC-12 speech-synthesis algorithm using 12-pole lattice filters. internal microprocessor fetches speech data from internal ROM, decodes speech data, sends decoded data synthesizer. microprocessor also interpolates (smoothes) speech data between fetches. microprocessor calculate waveform, which added output lattice filters create composite waveforms. general purpose microprocessor MSP50x3x, which capable variety logical, arithmetic, control functions, used nonsynthesis tasks application well. MSP50x3x family parts incorporates built-in oscillator capability directly driving speaker.
Figure 1-1. MSP50x3x Functional Block Diagram
Microcomputer Port Port
Dual Speech Synthesizers
Microprocessor
DAC+
Timing Oscillator
MSP50x37 contains features contained other members MSP50x3x family such integrated 8-bit successive approximation (SAR) analog-to-digital converter (ADC) with analog multiplexer ports, power amplifier that capability directly drive speaker,a long interval timer four ports with sufficient drive capability directly drive LED.
Description
Figure 1-2. MSP50x37 Functional Block Diagram
Microcomputer
Microprocessor
Dual Speech Synthesizers
Port Port Port
Timing Oscillator
PW1/PW2
Power Amplifier
Introduction MSP50x3x Family
Features
Features
features entire MSP50x3x family following list.
1.4.1
Dual programmable LPC-12 speech synthesizers Simultaneous 8-bit microprocessor with instructions Thirty-two 12-bit words bytes 3.3V 6.5V CMOS technology power dissipation Direct speaker drive capability Mask-selectable internal external Clock Internal clock generator that requires external components software-selectable clock speeds 10-kHz 8-kHz speech sample rate Seven levels stack Internal timer Externally-controlled interrupt Single-cycle multiply instruction Executes 1,200,000 instructions second Built-in slave mode microprocessor peripheral Software-configurable wakeup function from Port line
MSP50x32/33/34 Additional Features
MSP50x32/33/34 features present other family members include:
software configurable terminals (nine terminals with external clock selected) digital-to-analog (D/A) configurations-mask selectable Several ROM/PROM configurations
bytes MSP50C32 bytes MSP50C33 bytes MSP50C34 MSP50P34
Features
1.4.2
MSP50x37 Additional Features
MSP50x37 features present other family members include:
Incorporated 8-bit analog-to-digital converter multiplexed ports Ports) software configurable terminals Power amplifier direct speaker drive 20-mA sink current direct drive Additional long interval timer/counter Single-pin double-ended output 16K-bytes PROM
Introduction MSP50x3x Family
Options
Options
MSP50x3x family offers (digital-to-analog) output options match different applications. Option directly drive speaker. Note: MSP50x37 incorporates analog power amplifier that drive speaker. Table gives list devices options available each.
Table 1-2. MSP50x3x Options
Device MSP50C32 MSP50C33 MSP50C34 MSP50P34 MSP50C37 MSP50P37 Options Available Option Option Option Option Option Option Option Option Option Option Speaker Drive direct drive Drives operational amplifier direct drive Drives operational amplifier direct drive Drives operational amplifier direct drive Drives operational amplifier direct drive direct drive
1.5.1
Two-Pin Push Pull (Option Accurate part 1024
Option two-pin push pull. direct speaker drive desired, works well with very efficient inexpensive four-transistor amplifier. When idle output value both pins low. When output value positive, DAC+ pulses high with pulse density proportional output value, while stays low. When output value negative, goes high with pulse density proportional output value, while DAC+ stays low. This option respond values ranging from -512 +512. Figure shows examples output waveforms with different output values. Each sample period divided into segments. positive output value, 512, DAC+ goes high segments while stays low. When idle output value both DAC+ low. negative value -512, goes high segments while DAC+ stays low.
Options
Figure 1-3. Output Waveforms Two-Pin Push Pull (Option
High DAC+ High
Output Value
High DAC+ High
Output Value
Output Value
Output Value
High DAC+ High
Output Value
Output Value
Output Value
Output Value
Output Value
Figure 1-4, Figure 1-5, Figure show examples circuits that used with this option.
Introduction MSP50x3x Family
Options
Figure 1-4. Four-Transistor Amplifier Circuit
DAC+ Speaker
Figure 1-5. Operational Amplifier Interface Circuit
VDD/
DAC+
1-10
Options
Figure 1-6. Power Amplifier Interface Circuit
DAC+ 0.01 0.01 Note Note: components each dotted optional. They provide stages low-pass filters. remainder circuit minimum configuration recommended. application does need volume control, 100-k potentiometer replaced with fixed-value resistor. 0.001 0.05 0.001 Audio Taper
Introduction MSP50x3x Family
1-11
Options
1.5.2
Single-Pin Double-Ended (Option Accurate part 1024
Option with operational power amplifiers. When output value zero, output biased approximately VDD. When output value positive, output pulses approximately with pulse density proportional output value. When output value negative, output pulses with pulse density proportional output value. Figure shows examples output waveforms with different output values. Each pulse divided into segments sample period. positive output value 512, DAC+ goes high 3/4VDD segments. When idle output value DAC+ stays 1/2VDD. negative value 512, DAC+ goes 1/4VDD segments.
Figure 1-7. Figure 1-7. Output Waveforms Single-Pin Double-Ended (Option
DAC+
Output Value
Output Value
Output Value
DAC+
Output Value
Output Value
Output Value
DAC+
Output Value
Output Value
Output Value
1-12
Options
Figure gives example circuit that demonstrates interface with this output option.
Figure 1-8. Operational Amplifier Interface Circuit
VO(PP)
DAC+
MSP50x37 incorporates power amplifier that consists terminal either two-pin differential output one-pin analog output. This amplifier capability drive speaker with 0.5-W typical power. one-pin analog output typically one-half power two-pin differential output. amplifier have times voltage gain. Therefore, input voltage range should limited within 0.28V prevent output power from exceeding Figure shows two-pin push pull power amplifier output option with external filter circuit. Figure 1-10 shows one-pin analog power amplifier output option with external filter circuit. recommended that analog signal that filtered externally applied. When applying signal centered VDD, coupling condenser required between filter output
Introduction MSP50x3x Family
1-13
Options
Figure 1-9. Two-Pin Push Pull Power Amplifier Output Circuit with External
MSP50x37 Speaker
2SC1815
6800 6800
C(cup)
Figure 1-10. One-Pin Analog Power Amplifier Output Circuit with External
MSP50x37 2SC1815 Speaker
6800 6800
C(cup)
1-14
Terminal Assignments Signal Descriptions
Terminal Assignments Signal Descriptions
following sections give terminal assignment signal description information MSP50x3x family. MSP50x32/33/34 available 16-pin package form. MSP50P34 also available 40-pin package, which used engineering evaluation. MSP50x37 available 28-pin package.
1.6.1
MSP50x32/33/34 Terminal Assignments Signal Descriptions (16-Terminal Package)
MSP50x32/33/34 available 16-pin package form. Figure 1-11 shows terminal assignments MSP50x32/33/34 16-pin package. Table provides terminal function descriptions. Table gives locations MSP50C32/C33 form. Note: MSP50C34I/O Lines
form, more lines available MSP50C34 than packaged version. Figure 1-12 illustrates recommended power-up initialization circuit. Refer Chapter more information configuration. Refer section 6.3, Mechanical Information, detailed package dimensions.
Figure 1-11. MSP50x32/33/34 16-Pin Package Terminal Assignments
PACKAGE (TOP VIEW)
PB1/OSC
INIT
Introduction MSP50x3x Family
1-15
Terminal Assignments Signal Descriptions
Table 1-3. MSP50C32/33/34 16-Pin Package Terminal Functions
Terminal Name Terminal Number Signal Description output. When Option selected, DAC+ pulses high positive output values. remains when negative values output. output. When Options selected, pulses high negative output values. remains when positive values output. When Option selected, this terminal driven low. Initialize input. When INIT goes low, clock stops, MSP50x3x goes into low-power mode, program counter contents retained. INIT pulse sufficient reset processor. Clock input. When use, should tied VSS. Clock return. When internal clock option selected, This terminal terminal. 8-bit bidirectional port 2-bit bidirectional port. When external clock option selected, available, since terminal used function. supply voltage
INIT
14,6-
Ground Option selected, terminal asserted low.
1-16
Terminal Assignments Signal Descriptions
Table 1-4. Location MSP50C32/C33 Form
Lower Left Name PB1/ INIT DAC- DAC+ (microns) 902.25 571.50 185.00 28.75 28.75 261.00 647.50 979.00 3153.50 3450.50 3783.75 4007.75 4007.75 4031.00 3721.00 3334.50 (microns) 4321.00 4321.75 4321.75 1719.75 1333.25 31.00 31.00 31.00 36.50 36.25 36.25 1749.75 2759.25 4043.25 4321.75 4321.75 Upper Right (microns) 1053.75 721.50 335.00 178.75 178.75 411.00 797.50 1129.00 3303.50 3600.50 3933.75 4157.75 4157.75 4181.00 3871.00 3484.50 (microns) 4772.50 4471.75 4471.75 1869.75 1483.25 181.00 181.00 181.00 186.50 186.25 186.25 1899.75 2909.25 4193.25 4471.75 4471.75 Description Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Clock input (see Table 1-3) Initialize input (see Table 1-3) Ground supply voltage output (see Table 1-3) output (see Table 1-3) Port I/O, terminal Port I/O, terminal Port I/O, terminal
Coordinates respect specific corner device.
Figure 1-12. Power-Up Initialization Circuit
Optional Reset Switch
INIT
Introduction MSP50x3x Family
1-17
Terminal Assignments Signal Descriptions
1.6.2
MSP50C34/P34 Terminal Assignments Signal Descriptions
MSP50C34 MSP50P34 available form allowing additional capability. MSP50P34 also available 40-pin package engineering evaluation purposes. Figure 1-13 shows terminal assignments MSP50P34 40-pin package. Table provides terminal function descriptions. Table gives location MSP50C34 form. Figure 1-12 illustrates recommended power initialization circuit. Refer Chapter more information configuration. Refer section 6.3, Mechanical Information, detailed package dimensions.
Figure 1-13. MSP50P34 40-Pin Package Terminal Assignments
PACKAGE (TOP VIEW)
PB1/OSC
DAC+ INIT
internal connection
1-18
Terminal Assignments Signal Descriptions
Table 1-5. MSP50P34 40-Pin Package Terminal Functions
Terminal Name Terminal Number Signal Description output. When Option selected, DAC+ pulses high positive output values. remains when negative values output. output. When Options selected, pulses high negative output values. remains when positive values output. When Option selected, this terminal driven low. Initialize input. When INIT goes low, clock stops, MSP50x3x goes into low-power mode, program counter contents retained. INIT pulse sufficient reset processor. Clock input. When use, should tied VSS. Clock return. When internal clock option selected, this terminal terminal. 8-bit bidirectional port 8-bit bidirectional port. When external clock option selected, available, since terminal used function. 8-bit bidirectional port. supply voltage
INIT
Ground Option selected, terminal asserted low.
Introduction MSP50x3x Family
1-19
Terminal Assignments Signal Descriptions
Table 1-6. Location MSP50C34/P34 Form
Lower Left Name PB1/ INIT DAC- DAC+ (microns) 982.50 538.00 245.50 25.50 25.50 25.50 25.50 25.50 25.50 25.50 25.50 25.50 257.00 614.50 926.25 3200.50 3497.50 3830.75 4053.25 4053.25 4079.50 4079.50 4079.50 4079.50 3751.25 3440.25 2941.50 2565.25 1944.75 1502.00 (microns) 6375.25 6376.25 6376.25 5903.25 5488.75 4963.25 4232.75 3799.25 3124.25 2709.25 2034.25 1283.75 22.50 22.50 22.50 30.00 29.75 29.75 1744.50 4018.25 4461.50 5136.50 5551.50 6198.50 6376.25 6376.25 6376.25 6376.25 6376.25 6376.25 Upper Right (microns) 1132.50 688.00 395.50 175.50 175.50 175.50 175.50 175.50 175.50 175.50 175.50 175.50 407.00 764.50 1076.25 3350.50 3647.50 3980.75 4203.25 4203.25 4229.50 4229.50 4229.50 4229.50 3901.25 3590.25 3091.50 2715.25 2094.75 1652.00 (microns) 6525.25 6526.25 6526.25 6053.25 5638.25 5113.25 4832.75 3949.25 3274.25 2859.25 2184.25 1433.75 172.50 172.50 172.50 180.00 179.75 179.75 1894.50 4168.25 4611.50 5286.50 5701.50 6348.50 6526.25 6526.25 6526.25 6526.25 6526.25 6526.25 Description Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Clock input (see Table 1-5) Initialize input (see Table 1-5) Ground supply voltage output (see Table 1-5) output (see Table 1-5) Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal Port I/O, terminal
Coordinates respect specific corner device.
1-20
Terminal Assignments Signal Descriptions
1.6.3
MSP50x37 28-Pin Package Terminal Assignments Signal Descriptions
Figure 1-14 shows terminal assignments MSP50C37 28-pin package. Table provides terminal functional descriptions. device packaged 28-pin Package. Refer Section 6.3, Mechanical Information, detailed package dimensions.
Figure 1-14. MSP50x37 28-Pin Package Terminal Assignments
PACKAGE (TOP VIEW)
ADVDD INIT ADVSS OUT/PB1
PW2/AMPVDD AMPIN
Introduction MSP50x3x Family
1-21
Terminal Assignments Signal Descriptions
Table 1-7. MSP50x37 28-Pin Package Terminal Functions
Terminal Name ADVDD ADVSS AMPIN AMPVDD Terminal Number Signal Description Power supply ADC. reference voltage connected ADVDD internally. Ground level ADC. reference voltage connected ADVSS internally. Power amplifier input. Amplifier input power. When one-pin analog power amplifier output option selected, AMPVDD acts amplifier power supply. signal description when two-pin push pull power amplifier output option selected. Digital-to-analog output. Single-pin double-ended mode. Initialize input. When INIT goes low, clock stops, MSP50x3x goes into low-power mode, program counter contents retained. INIT pulse sufficient reset processor. Clock input. When use, should tied VSS. Clock return. When internal clock option selected, this terminal terminal. 8-bit bidirectional port have large sink current (20ma) ort. 2-bit bidirectional port. When external clock option selected, available, since this terminal used function. 8-bit bidirectional port analog signal input terminal ADC. terminal configuration software. Power amplifier output. Power amplifier output. When two-pin push pull power amplifier output option selected, power amplifier outputs. AMPVDD signal description when one-pin analog power amplifier output option selected. supply voltage Ground
INIT
1-22
Introduction Linear Predictive Coding (LPC)
Introduction Linear Predictive Coding (LPC)
LPC-12 system uses mathematical model human vocal tract enable efficient digital storage recreation realistic speech. understand LPC, essential understand vocal tract works. This introduction, therefore, begins with short description vocal tract, after which model data compression techniques addressed.
1.7.1
Vocal Tract
Speech result interaction among three elements vocal tract; from lungs, restriction that converts airflow sound, vocal cavities that positioned resonate properly. from lungs expelled through vocal tract when muscles chest diaphragm compressed. Pressure used volume control, with higher pressure louder speech. flows through vocal tract, makes little sound there restriction. vocal cords type restriction. They tightened across vocal tract stop flow air. Pressure builds behind them forces them open. This happens over over, generating series pulses. tension vocal cords varied change frequency pulses. Many speech sounds, such sound, produced this type restriction, which called "voiced" speech. different type restriction mouth causes hissing sound called white noise. sound good example. White noise occurs when tongue some part mouth close contact when lips pursed. This restriction causes high flow velocities that cause turbulence producing white noise, which called "unvoiced" speech. pulses from vocal cords noise from turbulence have fairly broad, flat spectral characteristics. other words, they noise, speech. shape oral cavity changes noise into recognizable speech. positions tongue, lips, jaws change resonance vocal tract, shaping noise restricted airflow into understandable sounds.
1.7.2
Model
model incorporates elements analogous each elements vocal tract described above. excitation function generator that models both types restriction, gain multiplication stage model possible levels pressure from lungs, digital filter model resonance oral nasal cavities.
Introduction MSP50x3x Family
1-23
Introduction Linear Predictive Coding (LPC)
Figure 1-15 shows LPC-12 vocal tract model schematic form. excitation function generator accepts coded pitch information input generate series pulses similar vocal cord pulses. also generate white noise. waveform then multiplied energy factor that corresponds pressure from lungs. Finally, signal passed through digital filter that models shape oral cavity. MSP50x3x, this filter poles, synthesis referred LPC-12.
Figure 1-15. LPC-12 Vocal Tract Model
Pitch
Periodic Sound
LPC-12 Digital Filter
White Noise Energy Filter Coefficients
1.7.3
Data Compression
data compression LPC-12 takes advantage other characteristics speech. Speech changes fairly slowly, oral nasal cavities tend fall into certain areas resonance more that others. speech analyzed into frames generally from long. inputs model calculated average entire frame. synthesizer smooths interpolates data during frame that there abrupt transition each frame. Often speech changes even more slowly than frame. Texas Instruments model allows repeat frame which only values changed pitch energy. filter coefficients kept constant from previous frame. take advantage recurrent nature resonance oral cavity, coefficients encoded, with anywhere from bits bits encoding each coefficient. coding table designed that more coverage given coefficient values that occur more frequently.
1-24
MSP50x3x Mask Options
MSP50x3x Mask Options
MSP50x3x configured suit different applications with variety mask options.
1.8.1
Clock Select Option
MSP50x3x family three mask-selectable clock options: internal oscillator; external oscillator; input driven external clock. internal oscillator recommended when lowest-cost solution required absolute accuracy oscillator secondary consideration. internal clock trimmed probe standard frequencies 15.36 19.2 MHz. frequency internal clock switched between these values software setting clearing SPEED mode register When using internal-clock option external-clock option, terminal available Port external oscillator mask option recommended when accurate frequency standard important. When external oscillator mask option selected, Port available because terminal used oscillator return line. Either ceramic resonator quartz crystal connected between lines with appropriate capacitors provide desired frequency clock. Alternatively, terminal driven with externally derived clock signal. When external oscillator option used, SPEED mode register function. SETOFF instruction INIT terminal disable operation clock circuit. Figure 1-16 suggested oscillator circuit. external clock mask option recommended when externally derived clock available drive device. 15.36-MHz 19.2-MHz clock should Figure 1-17 recommended circuit this mask option. When external clock option used, SPEED mode register function. When using external clock option, terminal available Port
Introduction MSP50x3x Family
1-25
MSP50x3x Mask Options
Figure 1-16. Oscillator Circuit
MSP50x3x
INIT
Crystal Ceramic Resonator
Figure 1-17. External Clock Interface
MSP50x3x
INIT
Clock
1.8.2
Option
MSP50C32/33/34 selected either two-pin push pull one-pin analog. MSP50C37 only output option, onepin analog power amplifier output option. Section 1.5, Options, more information.
1-26
MSP50x3x Mask Options
1.8.3
Power Amplifier Options (MSP50C37 Only)
MSP50C37 mask-selectable power amplifier output options: one-pin analog two-pin push pull differential. When one-pin analog option selected, terminal power amplifier output PW2/AMPVDD power amplifier current supply. When two-pin pushpull option selected, PW2/AMPVDD power amplifier differential outputs. both options, amplifier voltage gain
Introduction MSP50x3x Family
1-27
1-28
Chapter
MSP50x3x Family Architecture
This chapter describes architecture function MSP50x3x family speech synthesizers including RAM, ROM, registers, flags, DAC.
Topic
Page
MSP50C3x Family Architecture Speech Synthesis Interrupts MSP50C3x Power Control Initialization MSP50C3x Clocks Analog-to-Digital Converter (MSP50x37 Only) Power Amplifier (MSP50x37 Only) 2-22 2-27 2-29 2-30 2-32 2-33
MSP50C3x Family Architecture
MSP50C3x Family Architecture
shown block diagram Figure 2-1, major components MSP50C3x speech synthesizer; 8-bit microprocessor; internal byte (MSP50C32), byte (MSP50C33), byte (MSP50C34) ROM; input/output ports. system clock internally generated driven externally. When internal clock used, clock operates under software control programmed frequencies, 19.2 (used when operating 10,000 samples second) 15.36 (for 8,000 samples second). internally generated frequencies sufficiently accurate, device configured with mask option provide custom frequency operation using external clock signal, external ceramic resonator, quartz crystal (with appropriate capacitors). When synthesis disabled, instructions fetched microprocessor 1/16 clock frequency. These instructions control actions MSP50C3x. placing different instruction patterns ROM, MSP50C3x programmed accomplish wide variety tasks. generate speech, processor accesses speech data from internal internal RAM, some external source. Once data been read, processor must unpack decode individual speech parameters store results dedicated section RAM. synthesizer shares access addresses individual parameter locations needed when generating speech. Each synthesizer uses approximately quarter available instruction cycles when enabled. instruction execution rate slows when synthesizer enabled when both synthesizers enabled.
MSP50C3x Family Architecture
Figure 2-1. MSP50C3x System Block Diagram
Integer Flag Timer Prescaler Mode Register Mode Register Buffer Random Number 12-Bit 8-Bit 8-Bit Port) 2-Bit Port) Program Counter 16-Bit Data Port Port Register Integer Flag' Status Flag Register Stack Register Stack Register Stack Status Flag'
7-Level Stack Speech Address
16384-Byte (MSP50C32) 32768-Byte (MSP50C33) 65536-Byte (MSP50C34) 384-Byte Excitation Pitch Counter
Pitch Register Pitch Counter
Pitch Register Register Excitation Synthesizer Stack Output
MSP50C3x Family Architecture
MSP50C3x Family Architecture
block diagram Figure shows that MSP50x37 consists MSP50C3x core, several ports 16K-byte (MSP50C37) PROM (MSP50P37), 8-bit converter with analog multiplexer that connected Port power amplifier. Since device structured based MSP50C3x core, most features associated with performance core, such clock speed, instruction cycle, structure, speech synthesizer operations, etc., same those MSP50x32/33/34.
Figure 2-2. MSP50x37 System Block Diagram
MSP50C3x Core Power Amplifier P-AMP (PW1, PW2) 16-Bit Data 8-Bit Port) 2-Bit Port) 8-Bit Port) Port Port Port
16K-Byte (MSP50C37) 16K-Byte PROM (MSP50P37)
8-Bit Presaler Register 16-Bit Timer
2.1.1
Read-Only Memory (ROM)
MSP50C32 16K-bytes ROM. MSP50C33 32K-byte ROM. MSP50C34 64K-byte MSP50P34 64K-bytes PROM. MSP50C37 16K-bytes ROM, MSP50P37 16K-bytes PROM. MSP50C3x program instructions speech data required application. Certain locations ROM, described Table 2-1, reserved specific purposes.
MSP50C3x Family Architecture
Table 2-1. Reserved Locations
Address 0000h 0002h 0010h 001Fh 3FDBh 3FFFh 7FDBh 7FFFh FFDBh FFFFh Function Execution start location after INIT rising edge Execution start location after wakeup falling edge Interrupt start locations (see Section 2.3, Interrupts) Texas Instruments test code (MSP50C32/37) Texas Instruments test code (MSP50C33) Texas Instruments test code (MSP50C34)
accessed following four ways:
2.1.2
program counter addresses processor instructions (see Chapter instruction definitions). instruction transfers bits from register. counter initialized LUAPS instruction. (speech address register) points location used. LUAA instruction transfers byte from into register. value register when LUAA executed points address used. LUAB instruction transfers byte from into register. value register when LUAB executed points address used.
Program Counter
MSP50C3x 16-bit program counter that points next instruction executed. After instruction executed, program counter normally incremented point next instruction. When interrupt occurs, program counter loaded with interrupt vector address; where execution resumes. Section 2.3, Interrupts, more information. following instructions modify program counter:
RETN RETI CALL
Branch Branch address register Short branch Return from subroutine Return from interrupt Subroutine Call
MSP50C3x Family Architecture
MSP50C3x Family Architecture
2.1.3
Program Counter Stack
program counter stack seven levels. When subroutine called interrupt occurs, contents program counter pushed onto stack. When RETN (return from subroutine) RETI (return from interrupt) executed, contents stack location popped into program counter.
2.1.4
MSP50C3x Random Access Memory (RAM)
MSP50C3x locations general purpose (Figure Figure 2-4). first locations, which bits wide, used first synthesizer when enabled. next locations, which also bits wide, used second synthesizer when enabled. block associated with synthesizer released general when synthesizer enabled. remaining locations bits wide. When synthesizing, entire used algorithm data storage. control registers mapped into address space from 0F0h 0FFh (depending which part used) when mode register low. When high, mapped into 0F0h through 0FFh. more information, subsection 2.1.17, Input/Output Ports. mode registers also mapped into address space FFEh FFFh. more information, subsection 2.1.18, Mode Registers.
MSP50C3x Family Architecture
Figure 2-3. MSP50x32/33/34
Address 000h 001h Synthesizer
00Eh 00Fh 010h 011h 01Fh 020h Synthesizer Synthesizer Synthesizer
07Eh 07Fh 0F4h 0F5h 0F6h 0F7h 0F8h 0F9h 0FAh 0FBh 0FCh 0FDh 0FEh 0FFh FEFh FF0h Port Port Port Port Port Port Port Port Port Port Port Port High Bits Bits Bits Bits
Wakeup Control Register Speech Synthesis Register
FF4h FF7h Speech Synthesis Register
FFEh FFFh
Mode Register Mode Register
Port only included MSP50C34 form MSP50P34 package.
MSP50C3x Family Architecture
MSP50C3x Family Architecture
Figure 2-4. MSP50x37
Address 000h 001h 00Eh 00Fh 010h 011h 01Fh 020h Synthesizer Synthesizer Synthesizer
Synthesizer
07Eh 07Fh Port Port 0F1h Port 0F2h 0F3h Port 0F0h High
0F8h 0F9h 0FAh 0FBh 0FCh 0FDh 0FEh 0FFh
Port Port Port Port Port Port Port Port
Bits Bits Bits Bits
MSP50C3x Family Architecture
Figure 2-4. MSP50x37 (Continued)
FEBh FECh FEDh FEEh FEFh FF0h Power Amplifier Register Timer Register Long Time Measurement
Wakeup Control Register Speech Synthesis Registers
FF7h
Speech Synthesis Registers
FFCh FFDh FFEh FFFh
Control Register Control Register Mode Register Mode Register
2.1.5
MSP50C3x Memory-Mapped Registers
Several internal registers mapped into address space. Table shows memory-mapped register allocations devices combined.
MSP50C3x Family Architecture
MSP50C3x Family Architecture
Table 2-2. Memory-Mapped Registers
Address FEBh FECh FEDh FEEh FEFh FF0h FF1h FF2h FF3h FF4h FF5h FF6h FF7h FFCh FFDh FFEh FFFh Port Input Register Port Pullup Enable Register Port Data Direction Register Port Data Output Register Port Input Register Port Pullup Enable Register Port Data Direction Register Port Data Output Register Port Input Register Port Pullup Enable Register Port Data Direction Register Port Data Output Register Port Input Register Port Pullup Enable Register Port Data Direction Register Port Data Output Register Power Amplifier Register Timer Register Timer Register Timer Register Wakeup Select Register bit) PITCH2 bits) bits) PITCH bits) TEMP bits) TEMP bits) TEMP bits) TEMP bits) Register Register Mode Register Mode Register (synthesizer control register) (synthesizer control register) (synthesizer control register) (synthesizer control register) (synthesizer control register) (synthesizer control register) (synthesizer control register) (synthesizer control register) (MSP50x37 only) (MSP50x37 only) (see subsection 2.1.18) (see subsection 2.1.18) Function (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (see subsection 2.1.17) (MSP50x37 only) (MSP50x37 only) (MSP50x37 only) (MSP50x37 only)
2-10
MSP50C3x Family Architecture
2.1.6
Arithmetic Logic Unit (ALU)
performs arithmetic logic functions microprocessor synthesizer. bits wide, providing resolution needed speech synthesis. When 8-bit 12-bit data transferred ALU, they right justified. input upper bits either zeros (integer mode) equal 8-bit data 12-bit (extended sign mode) depending arithmetic mode selected using EXTSG INTGR instructions. description each instruction specific information Chapter comparison operations performed lower bits. capable doing 8-bit 16-bit multiply with 16-bit scaled result single instruction cycle.
2.1.7
Register
register, accumulator, primary 16-bit register used arithmetic logical operations. loaded with contents ROM, RAM, most other registers. register contents written most registers. contents saved dedicated storage register during level-1 interrupts restored RETI instruction. When leaving level-1 interrupt routine using RETI instruction, contents register prior execution RETI instruction lost. (Branch address contained register) branch between pages.
Register
MSP50C3x Family Architecture
2-11
MSP50C3x Family Architecture
2.1.8
Register
register 12-bit register used index register. access instructions (except direct addressing instructions TAMD, TMAD, TMXD) register point specific location. register also used general purpose counter. contents register saved during level-1 interrupts restored RETI instruction. When leaving level-1 interrupt routine using RETI instruction, contents register prior execution RETI instruction lost. Sign extension does affect data transferred register.
Register
2.1.9
Register
16-bit register used temporary storage. helpful storing address because exchanged with register using instruction. register added subtracted from, exchanged with register, making useful data storage after calculations. contents register saved during level-1 interrupts restored RETI instruction. When leaving level-1 interrupt routine using RETI instruction, contents register prior execution RETI instruction lost.
Register
2.1.10 Status Flag
1-bit status flag cleared various instructions depending result instruction. Refer individual description instructions Chapter determine effect instruction value status flag. SBR, CALL instructions conditional, modifying program counter only when status flag set. value status flag initialized upon powerup, initialization, wakeup. status flag interrupt.
Status Flag
2-12
MSP50C3x Family Architecture
2.1.11 Integer Mode Flag
1-bit integer mode flag INTGR instruction cleared EXTSG instruction. When integer mode flag (integer mode), upper bits data less than bits length zero filled when being transferred added subtracted from registers. upper bits data less than bits length zero filled when being transferred register. When integer mode flag cleared (extended sign mode), upper bits data less than bits length sign extended when being transferred added subtracted from registers. upper bits data less than bits length sign extended when being transferred register. value integer mode flag saved during interrupts restored RETI instruction.
Integer Mode Flag
2.1.12 Timer Register
8-bit timer register generates interrupts also counts events. decrements once each time timer prescale register goes from FFh. loaded using TAinstruction examined with TTMA instruction. When decrements from FFh, level-2 interrupt request generated. When interrupts enabled interrupt been processed already, immediate interrupt occurs; not, interrupt remains pending until interrupts enabled. timer continues count whether reloaded. timer does decrement before loaded with initial value using TAinstruction. However, evaluation module unit (EMU), timer decrements after STOP/RUN.
Timer Register
MSP50C3x Family Architecture
2-13
MSP50C3x Family Architecture
2.1.13 Timer Prescale Register
8-bit timer prescale register programmable divider between processor clock timer register. When decrements from FFh, timer register also decremented. timer prescale register then reloaded with value preset latch, counting starts again. When value loaded preset latch, prescale register counts through states. timer prescale register clock comes from internal clock. internal clock runs 1/32 clock frequency chip; thus, timer prescale register decrements once every instruction cycles when mode. TAPSC instruction loads timer prescale register preset latch. timer been initialized with TAinstruction, TAPSC instruction also loads timer prescale register.
Timer Prescale Register
2.1.14 Pitch Register Pitch Period Counter (PPC)
MSP50C3X family contains pitch registers pitch period counters (PPC). used each synthesizer. following discussion presented synthesizer. Although 16-bit pitch register pitch period counter part synthesizer, they affect microprocessor many ways. pitch period counter controls timing periodic impulse (excitation function) that simulates vocal cords. MSP50C3x, pitch period counter also controls interpolation synthesis parameters during each frame. This pitch-synchronous interpolation helps minimize inevitable noise from interpolation making occur lowest energy part synthesis making harmonic fundamental frequency. pitch register used when speech being synthesized. following discussion presumes that mode active. pitch register loaded with TASYN instruction. channel mode register controls which pitch register loaded with TASYN instruction. pitch period counter decremented each sample, with synthesis samples occurring 8-kHz 10-kHz rate. When pitch period counter decrements past zero, pitch register added When pitch period counter goes below 200h when pitch register added with result less than 200h, that synthesis channel high. This polled
2-14
MSP50C3x Family Architecture
microprocessor determine when interpolation should performed. excitation function loaded input filter while pitch period counter between 140h 000h. further information, Chapter
Pitch Register
voiced unvoiced frames, register must both when data transferred from register pitch register with TASYN instruction (see following illustration). this done, problems with MSP50C3x chip occur. Also, these problems apparent when using MSE50C3x chip.
Register
Pitch Register
voiced frames, pitch register must loaded with value higher than 7FFEh. addition, there three recommendations minimum pitch register value voiced frames. First, required that pitch register value higher. Second, strongly recommended that pitch register loaded with value 142h higher. This permits complete excitation pulse used synthesis. Third, best results with recommended software algorithms, pitch register value 202h higher recommended. requirement that pitch register value less than equal 7FFEh recommendation value greater than equal 142h results pitch range when operating with 10-kHz sample rate. unvoiced frames, pitch register required loaded with value between 3FEh. this done, problems with MSP50C3x chip occur that apparent MSE50C3x.
MSP50C3x Family Architecture
2-15
MSP50C3x Family Architecture
2.1.15 Speech Address Register (SAR)
speech address register (SAR) 16-bit register that points data internal ROM. LUAPS instruction transfers value register speech address register loads parallel-to-serial register (see subsection 2.1.16, Parallel-to-Serial Register) with internal value pointed SAR. instruction then bring bits time from parallel-to-serial register into accumulator. Whenever parallelto-serial register becomes empty, loaded with internal value pointed SAR, incremented.
Speech Address Register
2.1.16 Parallel-to-Serial Register
8-bit parallel-to-serial register used primarily unpack speech data. loaded with bits data from internal pointed speech address register internal pointed register. LUAPS instruction initializes parallel-to-serial register zeroes counter. instructions then transfer bits from parallel-to-serial register accumulator. When parallel-to-serial register empty, automatically reloaded. When from RAM, however, register automatically incremented. RAMROM mode register controls source parallel-to-serial register. speech address register description subsection 2.1.15, Speech Address Register (SAR), more information.
Parallel-to-Serial Register
2-16
MSP50C3x Family Architecture
2.1.17 Input/Output Ports
MSP50x32/33/34 devices, bidirectional lines 8-bit Port 2-bit Port available interfacing with external devices. MSP50C34 form bidirectional lines 8-bit Port 8-bit Port 8-bit Port MSP50x37 bidirectional lines 8-bit Port, 2-bit Port, 8-bit Port, external interface. Each individually programmable input output under control respective data direction register. addition, each output individually programmed using pullup enable register output modes push-pull open-drain pullup). Each input programmed same register resistive pullup high impedance. four registers associated with each ports memory mapped. Only bits Port available outside chip, states upper bits registers undetermined. MSP50C34 eight bits available when form. Transfers from port registers register leave upper bits (bits undetermined. MSP50x37, Port input converter. 8-bit ports selected control register analog input signal multiplexed 8-bit converter. Details registers shown Table Table 2-4.
Table 2-3. Registers
Location Register Data Input Register (DIR) Pullup Enable Register (PER) Data Direction Register (DDR) Data Output Register (DOR) Type Read Only Read/Write Read/Write Read/Write Port Port Port ('50C34 Only) Port ('50x37 Only) FFCh FFDh
terminal select conversion start Read Only (MSP50x37 only)
Table 2-4. Terminal Functions
Terminal Function Input, high impedance Input, internal pullup Output, active pullup Output, active pullup Output, open drain Output, open drain Terminal State High impedance Passive pullup High impedance
read DDR, PER, registers indicates last value written them.
MSP50C3x Family Architecture
2-17
MSP50C3x Family Architecture
read always indicates actual signal level terminal, which true even when output. This allows true bidirectional data flow without having switch port between input output. avoid high current conditions, this should only attempted terminals open drain with written data register. Unused Terminals unused terminals should tied high low. Floating terminals cause leakage current.
Pins MSP50P34 pins. Only them wired pins when 16-pin package used. remaining bits (Port bits Port should programmed either totem-pole output pins input pins with passive pullups avoid these pins being left floating. this done, leakage current result. Leaving high-impedance terminal unconnected could cause power consumption rise while processor mode. power consumption between with increase current through input. This should cause problem with device functionality. When part sleep mode, unconnected high-impedance terminals have effect either power consumption device functionality. terminal also slave mode, making MSP50C3x usable peripheral host microprocessor. Port connected 8-bit data controlled R/W_ (Port chip enable (Port B0). read (R/W_ high chip enable low) puts Port output latch values Port write (R/W_ chip enable low) latches value data into Port input latch. addition, output latch cleared. This makes possible write handshake line. lines used data this mode must configured inputs. When external clock option selected, available because used function. PCM1 LPC1 mode register bits both cleared, high-to-low transition causes level-1 interrupt. pulse must have minimum width This generate interrupt with external event.
2-18
MSP50C3x Family Architecture
2.1.18 Mode Registers
There 8-bit mode registers that memory mapped. contents both mode register cleared upon power-up reset, wakeup, when INIT line pulses low. contents mode register initialized (PPC bits both high) upon INIT. contents mode registers saved during subroutine call interrupt. Mode register memory mapped address FFEh mode register memory mapped address FFFh. contents either mode register copied register using instruction. Individual bits either mode register tested using TSTCM instruction modified using ANDCM ORCM instructions. TAMODE instruction transfers bottom bits register mode register
2.1.18.1 Mode Register
usage mode register bits given Table 2-5. Mode register controls first synthesizer channel, interrupt mode, slave mode, mode. ENA1 ENA2 bits mode register enable disable level-1 level-2 interrupts respectively. interrupt condition occurs while corresponding ENA1 ENA2 mode register cleared interrupt pending latch set, execution interrupt delayed until interrupt enabled. LPC1, PCM1, UNVOICE1 bits control activity first synthesis channel. Section 2.2, Speech Synthesis, more information. LPC1 PCM1 bits control interrupt vectors. Note: Using ORCM Instruction
When using ORCM instruction UNVOICE1 bit, LPC1 should also reset avoid glitch (i.e., ORCM LPC1). SLAVE enables special mode designed enable MSP50C3x operate slave processor under control external master microprocessor. Chapter Applications, more information. RAMROM selects data source instructions. When RAMROM low, instruction accesses internal ROM. When RAMROM high, instruction accesses location selected register.
MSP50C3x Family Architecture
2-19
MSP50C3x Family Architecture
Table 2-5. Mode Register
Name ENA1 LPC1 Disables level-1 interrupt High Enables level-1 interrupt
Disables channel processor Enables channel processor instruction cycles used microprocessor instruction cycles dedicated service this channel. locations dedicated synthesis. Disables mode Disables level-2 interrupt Leave this Enables mode channel Enables level-2 interrupt this
PCM1 ENA2 Reserved RAMROM SLAVE
Enables data source instructions Enables data source either internal instructions internal Enables master operation. available Enables slave operation. Terminal terminals controlled internal becomes hardware chip enable strobe, microprocessor becomes R/W_, Port controlled Enables pitch-controlled excitation Enables random excitation sequence sequence when mode (PCM1 low, when mode (PCM1 low, voiced) voiced) channel channel
UNVOICE1
2.1.18.2 Mode Register
usage mode register bits given Table 2-6. Mode register controls second synthesizer channel, map, channel selected, internal oscillator speed, reports status pitch period counters. LPC2, PCM2, UNVOICE2 bits control activity second synthesis channel. Section 2.2, Speech Synthesis, more information. PPC1 PPC2 bits report status pitch period counters used synthesis. They both initialized upon power INIT, wakeup. PPC1 when pitch period counter channel decrements below 200h. PPC2 high when pitch period counter channel decrements below 200h. They only cleared explicit write register using either instruction ANDCM instruction. Both bits upon INIT subsequently need software before starting synthesis. CHANNEL selects which channel TASYN addresses. When CHANNEL TASYN loads pitch register channel When CHANNEL TASYN instruction loads pitch register channel
2-20
MSP50C3x Family Architecture
SPEED controls speed internal oscillator. When this cleared internal oscillator generates 15.36-MHz clock synthesis operates 8000 samples/second sample rate. When this internal oscillator generates 19.2-MHz clock synthesis operates samples/second rate. When external oscillator mask option effect, SPEED affect. I/O_MAP controls address spaces located 0xF8h through 0xFFh. When this cleared (the default condition), ports (port port mapped into these locations. When this ports hidden mapped into these addresses. ports maintain separate storage locations that different data maintained location port latch while using same address.
Table 2-6. Mode Register
Name PPC1 Cleared using software High high when decrements below 200h channel program init wakeup Enables mode channel instruction cycles dedicated service this channel. locations dedicated synthesis. Enables mode channel high when decrements below 200h channel program init wakeup
LPC2
Disables mode
PCM2 PPC2
Disables mode Cleared using software
CHANNEL
Synthesizer channel selected. TASYN Synthesizer channel selected. instruction addresses first channel. TASYN instruction addresses second channel. Selects internal clock speed 15.36 Selects internal clock speed 19.2 (8,000 samples/second sample rate) (10,000 samples/second sample rate) ports (ports mapped into ports hidden mapped 0xF0h through 0xFFh. into 0xF0h through 0xFFh. Enables pitch-controlled excitation Enables random excitation sequence sequence when mode (PCM1 low, when mode (PCM1 low, voiced) voiced) channel channel
SPEED UNVOICE2
MSP50C3x Family Architecture
2-21
Speech Synthesis
Speech Synthesis
MSP50C3x family incorporates synthesis channels. Each synthesis channel controlled separately setting clearing bits mode registers, loading both pitch registers using TASYN instruction, properly loading values synthesis RAM. output each channel added together input oversampling output filter. Each synthesis channel operate four modes based upon setting LPCx PCMx bits mode register. following discussion, LPCx refers either LPC1 LPC2 mode register depending upon which synthesis channel active. similar manner, PCMx UNVOICEx, PPCx refer PCM1, PCM2, UNVOICE1, UNVOICE2, PPC1, PPC2 depending upon context.
2.2.1
Synthesizer Mode
When PCMx LPCx bits both cleared, synthesizer channel disabled. microprocessor cycles needed service channel this mode. TASYN instruction transfers contents register pitch register selected CHANNEL mode register making easy preload pitch register prior starting synthesizer. LPC1 PCM1 bits mode register both cleared level-1 interrupt triggered high-to-low transition terminal disabled.
2.2.2
Synthesizer Mode
Synthesizer mode normal speaking mode. selected setting LPCx clearing PCMx this mode, TASYN instruction transfers contents register pitch register selected CHANNEL mode register synthesis channel this mode, level-1 interrupt occurs synchronously with filter speech sample rate. Approximately percent instruction cycles used each synthesis channel using this mode. PPCx mode register when pitch period counter that channel decrements below 200h when pitch register added pitch period counter with result less than 200h. PPCx mode register remains until reset software. microprocessor controls speech synthesis unpacking decoding parameters, setting update interval (frame rate), interpolating parameters during frame. speech synthesizer acts 12-pole digital lattice filter, pitch-controlled white-noise excitation generator, 2-pole digital low-pass filter, digital-to-analog converter (DAC). Speech parameter
2-22
Speech Synthesis
input received from dedicated space RAM, speech samples generated kHz. Communication between microprocessor speech synthesizer takes place shared memory space microprocessor. Refer Chapter Applications, more information. When UNVOICEx cleared excitation filter periodic pulse with pulse period determined value loaded pitch register using TASYN instruction. When UNVOICEx excitation filter pseudo-random white noise sequence. When synthesis channel operating synthesizer mode locations dedicated synthesis. When synthesis channel operating this mode, locations dedicated synthesis.
2.2.3
Synthesizer Mode
When LPCx zero PCMx synthesizer placed mode. synthesizer mode synthesizer filter channel disabled does microprocessor cycles, TASYN transfers contents register directly input output filter. When synthesizer channel this mode, level-1 interrupt occurs speech sample rate, which gives access unfiltered output.
2.2.4
Synthesizer Mode excited
When both PCMx LPCx bits synthesizer runs normally with excitation function being provided software. level-1 interrupt occurs speech sample rate, TASYN instruction transfers register excitation function input synthesizer selected CHANNEL mode register Each channel this synthesizer mode uses approximately microprocessor instruction cycles.
2.2.5
Synthesizer
synthesizer uses locations RAM. When synthesis taking place, parameters synthesizer come directly from locations 1Eh. addresses shown Figure 2-5.
MSP50C3x Family Architecture
2-23
Speech Synthesis
Figure 2-5. During Speech Generation
Address 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh Energy (Channel2) (Channel2) (Channel2) (Channel2) (Channel2) (Channel2) (Channel2) (Channel2) (Channel2) (Channel2) (Channel2) (Channel2) (Channel2) (Channel Scaling) Energy (Channel (Channel1) (Channel1) (Channel1) (Channel1) (Channel1) (Channel1) (Channel1) (Channel1) (Channel1) (Channel1) (Channel1) (Channel1) (Low-Pass Filter) Description
2-24
Speech Synthesis
2.2.6
Pass Filter
MSP50C3x synthesizer incorporates oversampling output filter. flow diagram shown Figure 2-6. output filter (appropriately delayed) alternately switched with output filter shown rate double speech sample rate. With appropriate choice parameters C2), this filter interpolates data points improves sound quality. Recommended values F61h B67h E00h A00h.
Figure 2-6. Oversampling Output Filter
LPC-12 Lattice Filter
FIRn
2.2.7
Channel Scaling (C3)
When both channels operating, channel output scaled relative channel output value loaded location 1Eh. When desired that both channels operate with same scaling, load location with value 7FFh. Loading values smaller than this linearly scale output channel with respect channel
MSP50C3x Family Architecture
2-25
Speech Synthesis
2.2.8
Frame Length Control
frame length controlled value into prescale register range over which timer allowed vary. Typical synthesis interpolation routines timer decrement through range fixed size. Consequently, prescale value should selected give proper frame duration based timer range.
2.2.9
Digital-to-Analog Converter
MSP50C3x contains internal digital-to-analog converter (DAC) connected output synthesizer. available pulse-density-modulated forms. Section 1.5, Options, more information. output produces samples rate given fosc/1920. 19.2-MHz clock frequency, this formula results output sample rate KHz. 15.36-MHz clock frequency, this results output sample rate KHz. output rate twice speech sample rate with digital low-pass filter modes except mode. When synthesizer (mode goes state. state same zero state.
2-26
Interrupts
Interrupts
MSP50C3x interrupts: level-1 interrupt level-2 interrupt. Both enabled disabled bits mode register level-1 interrupt higher priority more hardware support. When level-1 interrupt occurs, program counter placed program counter stack, status flag, integer mode flag, register, register, register saved dedicated storage registers. Then program counter loaded with interrupt start location execution interrupt routine begins. When interrupt routine returns, these registers restored, program counter popped from stack. level-1 interrupt caused four conditions depending state mode-register bits PCM1 LPC1. These conditions, well interrupt routine start address each case, shown Table 2-7.
Table 2-7. Level-1 Interrupt Vectors
Address 0018h 001Ah 001Ch 001Eh PCM1 LPC1 Interrupt Trigger Terminal goes from high (see Section 2.1.17) fclock/1920 (see subsection 2.1.14) fclock/1920 (see subsection 2.2.3) fclock/1920 (see subsection 2.2.4)
level-2 interrupt lower priority cannot interrupt level-1 interrupt routine. Although, level-2 interrupt interrupted level-1 interrupt. During level-2 interrupt, program counter, status bit, integer mode flag only registers saved. register, register, register must saved program they used both routine being interrupted. mode register saved. level-2 interrupt always caused timer underflow-the timer going from FFh-but starts different addresses depending state mode-register bits. Table shows level-2 interrupt vectors.
Table 2-8. Level-2 Interrupt Vectors
Address 0010h 0012h 0014h 0016h PCM1 LPC1 level-2 interrupts caused timer underflow interru underflow. Interrupt Trigger
MSP50C3x Family Architecture
2-27
Interrupts
interrupting conditions level-1 level-2 interrupt interruptpending latches. When interrupt enabled (and level-2 interrupt case, overridden level-1 interrupt pending condition), interrupt taken immediately. however, interrupt enabled, interrupt pending latch causes interrupt occur soon respective interrupt enabled mode register Interrupts taken middle double-byte instructions, during branch call instructions, during subroutine interrupt returns (RETN RETI). single instruction software loop (instruction BRA, CALL, itself) should avoided since interrupt never taken. Consecutively executed branches calls delay interrupts until after execution instruction eventual destination string branches calls). consecutive branches calls) avoided, worst-case interrupt delay main level four instruction cycles. worst-case delay occurs when interrupt occurs during first execution cycle branch first instruction branch destination address double-cycle instruction. When interrupt occurs, execution begins interrupt address. state status known when interrupt occurs, CALL instruction should used first instruction. SBRs used, since them always taken, possible some other instruction that sets status bit, followed SBR. mode register saved restored during interrupts. changes made mode register during interrupts remain effect after return, including enabling disabling interrupts.
2-28
MSP50C3x Power Control Initialization
MSP50C3x Power Control Initialization
Upon initial powerup, status sign extension integer mode, contents unknown, cleared forcing terminals high-impedance input state. Mode Register initialized Mode Register initialized 09h. software program begins operating location 0000. device subsequently placed several power saving modes:
STANDBY Executing SETOFF instruction places device standby mode. When this occurs, internal clock shut down, program stops executing, device placed low-power state. lines retain their last programmed state. This mode terminated either taking INIT waking device with negative transition designated wakeup line. Port line software selected wakeup line. This done setting corresponding Wakeup Control Register (FEFh). When device restarted using wakeup line, program begins executing location 0002. When device restarted, retained, mode registers cleared lines unchanged, status random number counter unchanged. device otherwise completely initialized.
TSP50C1x Device Family TSP50C1x device family high impedance input state after SETOFF command. This true MSP50x3x family. left last programmed state.
Additional Precautions MSP50P34 requires additional precautions when placing device into standby condition which required other MSP50C3x device family. programmed input, than should driven either high low. addition, ports B2.B7 C0.C7 exist MSP50P34 will bonded 16-pin package. Software should program these ports output state. these precautions taken, some leakage current result.
MSP50C3x Family Architecture
2-29
MSP50C3x Clocks
SLEEP Taking INIT line reinitializes MSP50C3x places device sleep mode. program counter cleared 0000, random number counter reinitialized, lines high-impedance state, state device completely initialized. When INIT signal returns high, program begins executing location 0000 with status
MSP50C3x Clocks
MSP50C3x operate either internal clock requiring external components external clock requiring external components. Either internal clock external clock selected mask option when device code released. internal clock used when economy more important than absolute frequency accuracy. external clock used when frequency accuracy requirements clock justify added cost necessary external components, when preset frequencies available with internal clock applicable application, when synchronization with other processors important.
2.5.1
Internal Oscillator
internal clock provides either 15.36 19.2 selectable setting clearing SPEED mode register Both frequencies trimmed during manufacturing process. When using internal clock, should tied VSS. internal clock disabled when either INIT taken when SETOFF instruction executed. enabled when INIT returns high when device wakeup occurs.
2.5.2
External Oscillator
external oscillator provides capability providing either nonstandard more accurate clock frequencies. Using on-chip oscillator, either ceramic resonator quartz crystal connected between provide custom frequency. Alternatively, driven with externally derived clock signal. on-chip oscillator circuit disabled when MSP50C3x placed low-power mode. When external oscillator mask option selected, Port available since extra terminal required provide oscillator output line (OSC OUT). Figure 1-16 suggested external oscillator circuit.
2.5.3
External Clock
external clock mask option allows externally derived clock used device without loosing Port terminal. identical external oscillator except that terminal used Port oscillator return line provided.
2-30
MSP50C3x Clocks
2.5.4
Long Interval Monitor Timer Timer-2 (MSP50x37 Only)
MSP50x37 implements timers addition timers incorporated CPU. Since this timer designed long interval time count, such that required external host processor communication, this timer does initiate interrupt. Table shows memory this timer. Note: Long Interval Timer
long interval timer does decrement before loaded with initial value from upper 8-bit timer (FEEh).
Table 2-9. Memory Assignment Additional Timer
Address FECh FEDh FEEh Prescaler (Write only) Lower 8-bit timer (Read/Write) Upper 8-bit timer (Read/Write) Function
prevent count error, recommended load entire data when presetting data. Note: Transferring Data Register
These additional timing registers 8-bit registers. When transferring data from these registers register, upper bits register arbitrary values. user should careful depend upon value upper bits
Note:
MSP50x37 Timer Registers Development Tools
ANDCM, ORCM, TSTCM, SMAAN AMAAC instructions work properly these additional timing registers development tools. lack development tool support, recommended that only operations performed these registers transfers from memory using TAM, TAMIX, TMA, TMAIX, instructions.
MSP50C3x Family Architecture
2-31
Analog-to-Digital Converter (MSP50x37 Only)
Analog-to-Digital Converter (MSP50x37 Only)
MSP50C37 MSP50P37 incorporate analog-to-digital converter (ADC). This circuit disabled draws current when device SLEEP STANDBY mode. D-Port terminals multiplexed input ADC. Writing value through either location 0xFFCh 0xFFDh selects which port terminals through provides input. Subsequent reads either 0xFFCh OxFFDh read output ADC. Reading either 0xFFCh 0xFFDh initiates next conversion. This conversion available instruction cycles later. Attempts read sooner than that result being reset conversion being initiated without results current conversion being either completed written buffer. does convert continuously, only response reading previous data. converter output bits wide with accuracy bits. clock rate results maximum conversion rate 31.25K samples/second.
Table 2-10.D Port Terminal Input
Port Terminal Selected 0xFFCh 0xFFDh Bits
2-32
Power Amplifier (MSP50x37 Only)
Power Amplifier (MSP50x37 Only)
MSP50x37 integrates power amplifier that either one-pin analog option two-pin differential output. This amplifier drive speaker directly 0.5-W driving power (typical). voltage gain this amplifier input signal should kept within 0.28 prevent exceeding When set, AMP_ENA (bit power amplifier register (FEBh) activates power amplifier. contents power amplifier register cleared upon power reset, wake when INIT terminal asserted low. Figure example application circuit.
Figure 2-7. Oversampling Output Filter Circuit
2SC1815
C(cup)
NOTE 6800
p1RC)
Output gain modified with and/or
MSP50C3x Family Architecture
2-33
2-34
Chapter
MSP50C3x Assembler
MSP50C3x assembler chapter describes invoke assembler, assembler command-line options, source-statement format, assembler symbols characters, assembler directives.
Topic
Page
Description Notation Used Invoking Assembler Command-Line Options Assembler Input Output Files Source-Statement Format Symbols 3-11 Character Strings 3-12 Expressions 3-13 Assembler Directives 3-14
3.10 Listing Formats 3-27 3.11 Placing Binary Data Above #FFFF 3-28
Description Notation Used
Description Notation Used
notation used this document follows:
optional field indicated brackets; example,
[LABEL]
User-supplied contents indicated braces; example,
<num>
reserved word shown capital letters. required blank indicated caret (^).
following syntax example demonstrates notational conventions used this guide.
Involking Assembler
Invoking Assembler
assembler invoked from command line from within software. assembler invoked from command line typing:
ASMX^[<options>]^<source[.ext]>
where:
Options represents list assembler options (see Section 3.3, Command-Line Options). Source name source file with extension optional. extension given, then default extension .asm assumed. example:
ASMX PROGRAM
runs assembler using source file program.asm generates output object file program.bin. list file generated. assembler invoked within selecting Assemble from Assembler menu. window appears allowing user select file assemble. Assembler options selected from Options Assembler Options menu.
MSP50C3x Assembler
Command-Line Options
Command-Line Options
Several options invoked from command line (Table 3-1). They invoked listing their abbreviation prefixed minus sign. following example:
ASMX PROGRAM.ASM
assembles program file program.asm does generate either listing file object file; however, errors written console. available options detailed Table 3-1. subsection 3.9.10, OPTION Directive, information invoking options within source code.
Table 3-1. Switches Options
Character Action Lists only first data byte BYTE RBYTE Lists only first data byte DATA RDATA Displays usage information Counts number times valid instruction been used Displays error messages without generating list Expands macros listing Disables object file output Prints listing without page breaks Produces reduced cross-reference list Writes errors screen unless listing file generated Lists only first data byte TEXT RTEXT Produces symbolic debugging information Suppresses warning message Adds cross-reference list
3.3.1
BYTE Unlist Option
Placing command-line option field causes assembler list only first opcode BYTE RBYTE statement. Normally, BYTE RBYTE statement arguments, they listed column running down page opcode column listing, taking lines completely list resulting opcodes. When BYTE unlist switch set, then only first line (which also contains source line listing) written listing file.
Command-Line Options
3.3.2
DATA Unlist Option
Placing command-line option field causes assembler list only first opcode DATA RDATA statement. Normally, DATA RDATA statement arguments, they listed column running down page opcode column listing, taking lines completely list resulting opcodes. When DATA unlist switch set, then only first line (which also contains source line listing) written listing file.
3.3.3
XREF Unlist Option
Placing command-line option field causes assembler cross-reference listing listing file (see Example 3-1). cross reference listing condenses output printing multiple line numbers line. line that contains symbol name shows where symbol defined. second following lines show where symbol used.
Example 3-1.XREF Unlist Option
Cross Reference Symbol -------- ---- ERR_CODE 0040 Filename --------------- big.asm big.asm big.asm PAGE 0063 Line ------------------------------
3.3.4
TEXT Unlist Option
Placing command-line option field causes assembler list only first opcode TEXT RTEXT statement. Normally, TEXT RTEXT statement argument string containing characters, ASCII representation these characters written column opcode column program listing. When TEXT unlist switch set, then only first line (which also contains source line listing) written listing file.
3.3.5
WARNING Unlist Option
Placing command-line option field causes assembler suppress WARNING messages. Warnings still counted error messages still generated.
3.3.6
Complete XREF Switch
Placing command-line option field causes assembler produce reduced XREF listing produced. Normally, symbols (whether
MSP50C3x Assembler
Command-Line Options
used not) listed XREF listing. option causes assembler omit from XREF listing symbols from copy files that were never used.
3.3.7
Object Module Switch
Placing command-line option field causes assembler generate object output modules.
3.3.8
Listing File Switch
Placing command-line option field causes assembler generate listing file display error messages screen.
3.3.9
Page-Eject Disable Switch
Placing command-line option field causes assembler print listing continual manner without division into separate pages. When desired, form feed still forced using PAGE command.
3.3.10 Error-to-Screen Switch
Placing command-line option field causes assembler write errors screen unless listing file being generated.
3.3.11 Instruction Count Switch
Placing command-line option field causes assembler generate table containing number times each valid instruction used program.
3.3.12 Show Usage Switch
Placing command line option field causes assembler display proper command line usage table command line switches that used.
3.3.13 Macro Switch
Placing command-line option field causes assembler expand macros listing file.
3.3.14 Symbolic Debugging Switch
Placing command-line option field causes assembler produce symbolic debugging information.
Assembler Input Output Files
Assembler Input Output Files
assembler takes input file containing assembler source produces output listing file object file binary format.
3.4.1
Assembler Source File
assembly source file specified command line. When filename command line extension, then file name used given. extension specified, then extension .asm assumed. example:
ASMX PROGRAM.SRC
uses file program.src assembly source file.
ASMX PROGRAM
uses file program.asm assembly source file.
3.4.2
Assembler Binary Object File
assembly process produces object file binary format. object output placed into file with same filename assembly source except that extension .bin. When binary file desired, disabled either command-line option with OPTION statement. example:
ASMX PROGRAM.SRC
uses file program.src assembly source file file program.bin binary object output file.
ASMX PROGRAM.SRC
uses file program.src assembly source file produces object output.
3.4.3
Assembler Listing File
assembly process produces listing file that contains source instructions, assembled code, (optionally) cross-reference table. listing file placed file with same file name assembly source except that extension .lst. example:
ASMX PROGRAM.SRC
uses file program.src assembly source file file program.lst assembly listing file.
MSP50C3x Assembler
Source Statement Format
Source Statement Format
assembly-language source program consists source statements contained assembly source file(s) that contain assembler directives, machine instructions, comments. Source statements contain four ordered fields separated more blanks. These fields (label, command, operand, comment) discussed following paragraphs. source statement long characters. When form width characters (the default), assembler truncates source line characters. user should ensure that nothing other than comments extend past column source line starting with asterisk first character position anything following semicolon treated comment entirety. ignored assembler affect assembly process. syntax source statements
source statement have optional label that defined user. more blanks separate label from COMMAND mnemonic. more blanks separate mnemonic from operand required command). more blanks separate operand from comment field. Comments ignored assembler.
3.5.1
Label Field
label field begins character position source line. When position character other than blank asterisk, assembler assumes that symbol label. When label omitted, then first character position must blank. label contain characters consisting alphabetic characters (a-z, A-Z), numbers (0-9), some other characters (@,$,_). first character should alphabetic character, remaining nine character positions legal characters listed above.
3.5.2
Command Field
command field begins after blank that terminates label field first nonblank character past first character position (which must blank when label omitted). command field terminated more blanks extend past sixtieth character position. command field contain either assembler mnemonic (e.g. TAX) assem-
Source Statement Format
bler directive (e.g. OPTION). assembler does distinguish between capital small letters command name; example, TAX, Tax, identical names assembler.
3.5.3
Operand Field
operand field begins following blank that terminates command field extend past sixtieth column position. operand contain more constants expressions described subsection 3.5.5, Constants, through subsection 3.5.5.5, Assembly-Time Constants. Terms operand field separated commas. operand field terminated first blank encountered.
3.5.4
Comment Field
comment field begins either after blank that terminates operand field after blank that terminates command field operand required. comment field must begin with semicolon. assembler generates errors there comments without leading semicolon. comment field extend source record contain ASCII character including blanks.
3.5.5
Constants
assembler recognizes following five types constants:
3.5.5.1
Decimal integer constants Binary integer constants Hexadecimal integer constants Character constants Assembly-time constants
Decimal Integer Constants
decimal integer constant written string decimal digits. range values decimal integers -32,768 65,535. Positive decimal integer constants greater than 32,767 considered negative when interpreted two's complement values. following valid decimal constants:
1000 Constant equal 1000 03E8h -32768 Constant equal -32,768 8000h Constant equal 0019h
MSP50C3x Assembler
Source Statement Format
3.5.5.2
Binary Integer Constants
binary integer constant written string binary digits (0/1) preceded question mark (?). When less than digits specified, assembler right-justifies given bits resulting constant. following valid binary constants:
3.5.5.3
?0000000000010011 ?0111111111111111 ?11110
Constant equal 0013h Constant equal 32,767 7FFFh Constant equal 001Eh
Hexadecimal Integer Constants
hexadecimal integer constant written string four hexadecimal digits preceded number sign greater than sign (>). When less than four hexadecimal digits specified, assembler right-justifies bits that specified resulting constant. Hexadecimal digits include decimal values through letters through following valid hexadecimal constants:
3.5.5.4
#07F >07f #307A
Constant equal 07Fh Constant equal 07Fh Constant equal 12,410 307Ah
Character Constants
character constant written string alphabetic characters enclosed single quotes. single quote represented within character constant successive quotes. When less than characters specified, assembler right-justifies given bits resulting constant. characters represented internally 8-bit ASCII characters. character constant consisting only single quotes character) valid assigned value 0000h. following valid character constants:
3.5.5.5
`AB' `''D'
Constant equal 4142h Constant equal 0043h Constant equal 2744h
Assembly-Time Constants
assembly-time constant symbol given value directive (see subsection 3.9.5, Directive). value symbol determined assembly time assigned values with expressions using constant types.
3-10
Symbols
Symbols
Symbols used label field operand field. symbol string fewer alphanumeric characters (a-z, A-Z,0-9, characters Upper-case lower-case characters distinguished from another; example, treated identically assembler. character blank. When more than characters used symbol, assembler prints characters issues warning message that symbol been truncated uses only first characters processing. Symbols used label field become symbolic addresses. They associated with locations program must used label field other statements. Mnemonic operation codes assembler directives also used valid user-defined symbols when placed label field. Symbols used operand field must defined assembly, usually appearing label field statement operand field directive. following examples valid symbols:
START Start Strt_1
Predefined Symbol
dollar sign predefined symbol given value current location within program. used operand field indicate relative program offsets. example:
results branch address bytes beyond current location.
MSP50C3x Assembler
3-11
Character Strings
Character Strings
Several assembler directives require character strings operand field. character string written string characters enclosed single quotes. quote represented string successive quotes. maximum length string defined each directive that requires character string. characters represented internally 8-bit ASCII. following valid character strings:
`SAMPLE PROGRAM' `Plan `C'''
3-12
Expressions
Expressions
Expressions used operand fields assembler instructions directives. expression constant symbol, series constants symbols, series constants symbols separated arithmetic operators. Each constant symbol preceded minus sign (unary minus) plus sign (unary plus). Unary minus same taking two's complement value. expression must contain embedded blanks. valid range values expression -32,768 65,535. value terms expression must known assembly time.
3.8.1
Arithmetic Operators Expressions
following arithmetic operators used expression:
inversion addition subtraction multiplication division (remainder truncated) modulo (remainder after division) bitwise bitwise bitwise EXCLUSIVE-OR
evaluating expression, assembler first negates constant symbol preceded unary minus then performs arithmetic operations from left right. assembler does assign arithmetic operation precedence operation other than unary plus unary minus that expression 4+4*2 evaluated 12).
3.8.2
Parentheses Expressions
assembler supports parentheses expressions alter order evaluating expression. Nesting parentheses within expressions also supported. When parentheses used, portion expression within innermost parentheses evaluated first, then portion expression within next innermost pair evaluated. When evaluation portions expression within parentheses been completed, evaluation completed from left right. Evaluation portions expression within parentheses same nesting level considered simultaneous. Parenthetical expressions nested more than eight deep.
MSP50C3x Family Architecture
3-13
Assembler Directives
Assembler Directives
Assembler directives (Table 3-2) instructions that modify assembler operation. They invoked placing directive mnemonic command field modifying operands operand field. valid directives described following paragraphs.
3-14
Assembler Directives
Table 3-2. Summary Assembler Directives
Directives That Affect Location Counter Mnemonic AORG Directive Absolute origin Syntax Directives That Affect Assembler Output LIST NARROW OPTION PAGE TABSIZE TITL WIDE Program identifier Restart source listing 80-column form width Output options Page eject stops Page title Stop source listing 130-column form width [<label>]^LIST^[<comment>] [<label>]^NARROW^[<comment>] [<label>]^OPTION^<option list>^[<comment>] [<label>]^PAGE^[<comment>] [<label>]^UNL^[<comment>] [<label>]^WIDE^[<comment>]
Directives That Initialize Constants BYTE RBYTE DATA RDATA TEXT RTEXT Initialize byte Reverse initialization byte Initialize word Reverse initialization word Define assembly time constant Initialize text <expr-n>]^[<comment>] <expr-n>]^[<comment>] <expr-n>]^[<comment>] <expr-n>]^[<comment>]
Reverse byte initialization text Miscellaneous Directives
COPY MACRO/ ENDM
Copy source file Program Macro definition
[<label>]^END^[<comment>] MACRO^'<name>` <statements> ENDM
MSP50C3x Assembler
3-15
Assembler Directives
3.9.1
AORG Directive
AORG directive places value found expression operand field into location counter. Subsequent instructions have addresses starting this value. label field optional, when label used, assigned value found operand field. syntax AORG directive follows: following statement:
AORG #1000+offset
offset value AORG sets location counter #1008. label included, also assigned value #1008. symbol offset must previously defined.
3.9.2
BYTE Directive
BYTE directive places value more expressions into successive bytes program memory. range each term 255. command field contains BYTE. operand field contains series more terms separated commas terminated blank that represents values placed successive bytes program memory. syntax BYTE directive follows: following statement:
BYTE #E0,5,data+5
places numbers 224, result arithmetic operation data into next three bytes program memory. value symbol data must defined assembly process.
3.9.3
COPY Directive
COPY directive causes assembler read source statements from different file. assembler gets subsequent statements from copy file until either end-of-file marker found directive found copy file. copy file cannot contain another COPY directive. command field contains COPY. operand field contains name file from which source files read.
3-16
Assembler Directives
syntax COPY directive follows: directive following example:
COPY `copy.fil'
causes assembler take source statements from file called copy.fil. end-of-file copy.fil when directive encountered copy.fil, assembler resumes processing source statements from original source file. single quotes around filename required assembler.
3.9.4
DATA Directive
DATA directive places value more expressions into successive words program memory. range each term 65,535. command field contains DATA. operand field contains series more terms separated commas terminated blank that represents values placed successive words program memory. syntax DATA directive follows: following statement:
DATA #E000,'AB'
places following bytes into successive locations program memory: E0h, 00h, 41h,
3.9.5
Directive
directive assigns value symbol. label field contains name symbol which value assigned. command field contains EQU. operand field contains value assigned symbol. syntax directive follows: following statement:
Offset #100
assigns numeric value (100h) symbol Offset.
3.9.6
Directive
directive signals source copy file. treated program end-of-file marker. When found copy file, copy file
MSP50C3x Assembler
3-17
Assembler Directives
closed subsequent statements taken from source file. When found source file, assembly process terminates that point file. syntax directive follows: [<label>]^END^<comment>] following statement:
ACAAC
ACAAC instruction assembled, subsequent instructions ignored.
3.9.7
Directive
assigns name object module produced. label field optional. When used, label assumes current value location counter. command field contains IDT. operand field contains module name <string>, character string eight characters within single quotes. When character string more than eight characters entered, assembler prints truncation warning message retains first eight characters program name. syntax directive follows: following example:
AORG `Example'
assigns value symbol assigns name `Example' module being assembled. module name then printed source listing operand directive appears page heading source listing.
3.9.8
LIST Directive
LIST directive restores printing source listing. This directive required only when no-source-listing (UNL) directive effect causes assembler resume listing. This directive printed source listing, line counter increments. syntax LIST directive follows:
3-18
Assembler Directives
[<label>]^LIST^[<comment>] following statement:
AORG LIST ;Turn source listing
label assigned value listing resumed. line printed that although label entered into symbol table appears cross-reference listing, line which assigned value does appear listing file.
3.9.9
NARROW Directive
NARROW directive causes assembler assume 80-column form width listing file. default columns (See subsection 3.9.18, Wide Directive). syntax NARROW directive follows: [<label>]^NARROW^[<comment>] following example uses NARROW directive:
AORG NARROW ;Switch 80-column listing format.
3.9.10 OPTION Directive
OPTION directive selects several options that affect assembler operation. <option list> operand list keywords separated commas; each keyword selects assembly feature. Only first character keyword significant. label field optional. When used, label assumes current value location counter. syntax OPTION directive follows: following examples OPTION directive:
OPTION OPTION XREF,SCRNOF
examples above have identical effects. cross-reference listing produced error messages sent screen (unless source listing file being produced). Section 3.3, Command-Line Options, information invoking options from command line. available options listed following paragraphs.
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Assembler Directives
3.9.10.1 BUNLST Byte Unlist Option
Placing valid symbol starting with option list enables byte unlist option. This option limits listing BYTE RBYTE directives line. Normally, BYTE RBYTE directive more than operand, resulting object code listed column opcode column source listing. BUNLST used avoid this.
3.9.10.2 DUNLST Data Unlist Option
Placing valid symbol starting with option list enables data unlist option. This option limits listing DATA RDATA directives line. Normally, DATA RDATA directive more than operand, resulting object code listed column opcode column source listing. DUNLST used avoid this.
3.9.10.3 FUNLST Byte, Data Text Unlist Option
Placing valid symbol starting with option limits listing BYTE, RBYTE, DATA, RDATA, TEXT, RTEXT directives line. effect, equivalent calling DUNLST, BUNLST, TUNLST directives same time.
3.9.10.4 LSTUNL Listing Unlist Option
Placing valid symbol starting with option list inhibits listing file from being produced. takes precedence over LIST directive.
3.9.10.5 OBJUNL Object File Unlist Option
Placing valid symbol starting with option enables object file unlist option. This option inhibits generation object file.
3.9.10.6 PAGEOF Page Break Inhibit Option
Placing valid symbol starting with option enables page break inhibit option. This option causes listing file printed continuous stream without page breaks.
3.9.10.7 RXREF Reduced XREF Option
Placing valid symbol starting with option enables reduced XREF option. This option causes symbols that were found copy files never used omitted from cross-reference listing produced).
3.9.10.8 SCRNOF Screen Error Message Unlist Option
Placing valid symbol starting with option enables screen error message unlist option. This option causes error messages listed screen unless listing file being produced.
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Assembler Directives
3.9.10.9 TUNLST Text Unlist Option
Placing valid symbol starting with option list enables text unlist option. This option limits listing TEXT RTEXT directives line. TEXT RTEXT directive normally takes many lines list there characters operand. TUNLST causes only first line directive listing produced.
3.9.10.10 WARNOFF Warning Message Unlist Option
Placing valid symbol starting with option list inhibits listing warning diagnostics. Warnings still counted total still printed source listing.
3.9.10.11 XREF Cross-Reference Listing Enable
Placing valid symbol starting with option list causes crossreference listing produced source listing. When used, should placed start program.
3.9.11 PAGE Directive
PAGE directive forces assembler continue source program listing page. PAGE directive printed source listing, line counter increments. label field optional. When used, label assumes current value location counter. command field contains PAGE. operand field used. syntax PAGE directive follows: [<label>]^PAGE^[<comment>] following statement:
AORG PAGE ;Force page eject
label assigned value listing resumed next page. line printed that although label entered into symbol table appears cross-reference listing, line which assigned value does appear listing file.
3.9.12 RBYTE Directive
RBYTE directive places value more expressions into successive bytes program memory bit-reversed form. range each term
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Assembler Directives
255. command field contains RBYTE. operand field contains series more terms separated commas terminated blank that represents values placed successive bytes program memory. syntax RBYTE directive follows: following statement:
RBYTE #E0,5,data+5
places numbers (07h), (A0h), reversed result arithmetic operation data+5 into next three bytes program memory. value symbol data must defined assembly process.
3.9.13 RDATA Directive
RDATA directive places value more expressions into successive words program memory bit-reversed form. range each term 65,535. command field contains RDATA. operand field contains series more terms separated commas terminated blank that represents values placed successive words program memory. syntax RDATA directive follows: following statement:
RDATA #E000,'AB'
places following bytes into successive locations program memory: 00h, 07h, 42h,
3.9.14 RTEXT Directive
RTEXT directive writes ASCII string object file reverse order. When string preceded minus sign, last character string written (which first character string given) written with most significant label field optional. When used, label assumes current value location counter. command field contains RTEXT. operand field contains character string characters long enclosed single quotes (optionally preceded minus sign).
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Assembler Directives
syntax RTEXT directive follows: following examples:
RTEXT -'This test' RTEXT `This test'
both write string "tset sihT" output file. first example writes first word "This", which last character written with most significant (that instead 54h).
3.9.15 TEXT Directive
TEXT directive writes ASCII string object file. When string preceded minus sign, last character string written with most significant label field optional. When used, label assumes current value location counter. command field contains TEXT. operand field contains character string characters long enclosed single quotes (optionally preceded minus sign). syntax TEXT directive follows: following examples:
RTEXT -'This test' RTEXT `This test'
both write string This test output file. first example writes final word "test" with most significant (that instead 74h).
3.9.16 TITL Directive
TITL directive inserts title printed heading each page source listing. When title desired heading listing page, TITL directive must first source statement submitted assembler. Unlike directive, TITL directive printed source listing. assembler does print comment because TITL directive printed, line counter does increment. label field optional. When used, label field assumes current value location counter. command field contains TITL. operand field contains title (string)-a character string characters length enclosed single quotes. When more than characters entered, assembler retains first
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Assembler Directives
characters title prints syntax error message. comment field optional. syntax TITL directive follows: following example:
TITL 'Sample Program' This sample line
causes title, Sample Program, printed page heading source listing. When TITL directive first source statement program, title printed pages until another TITL directive processed. Otherwise, title printed page after directive processed subsequent pages until another TITL directive processed. None this line printed listing file.
3.9.17 Directive
directive inhibits printing source listing output until occurrence LIST directive. printed source listing, source line counter incremented. label field assumes value location counter. command field contains symbol UNL. operand field used. syntax directive follows: [<label>]^UNL^[<comment>] following statement:
AORG Turn source listing<
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