Volume Enhanced Peripherals Literature Number: SPRU302 June 1999
|
|
|
Top Searches for this datasheet
TMS320C54x Reference
Volume Enhanced Peripherals
Literature Number: SPRU302 June 1999
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Preface
Read This First
About This Manual
TMS320C54x fixed-point digital signal processor (DSP) Texas Instruments (TITM) TMS320 family. These devices characterized lowpower, enhanced architecture core. This book, fifth volume 5-volume set, provides information about enhanced peripherals available some these devices. Many device references shown with apostrophe replacing usual alphanumeric prefix (ex. '5420 instead TMS320VC5420). Unless otherwise specified, references '54x this book apply TMS320VC54x. This user's guide describes enhanced peripherals available '5402, '5410, '5420 devices, explains their operations. main topics discussed are: Host port interface (HPI) Multi-channel buffered serial ports (McBSPs) Programmable clock generator with multiple phase-locked loop (PLL) controller (DMA) Enhanced external input/output interface (EnhXIO) Interprocessor FIFO non-enhanced peripheral information related '54x devices, TMS320C54x DSP, Peripherals, Volume referenced section titled Related Documents from Texas Instruments.
Notational Conventions Information About Cautions Notational Conventions Information About Cautions
Notational Conventions
This book uses following conventions.
TMS320C54x either forms instruction set:
mnemonic form algebraic form. This book uses mnemonic form instruction set. information about mnemonic form instruction set, TMS320C54x Reference Set, Volume Mnemonic Instruction Set. information about algebraic form instruction set, TMS320C54x Reference Set, Volume Algebraic Instruction Set.
Program listings program examples shown special type-
face. Here segment program listing:
RSBX A,*AR1+ INMAIN_PG ;Int_RAM(I)=0 ;Globally enable interrupts ;Return foreground program
Square brackets, identify optional parameter.
tional parameter, specify information within brackets; type brackets themselves.
Information About Cautions
This book contains cautions.
This example caution statement. caution statement describes situation that could potentially damage your software equipment.
information caution provided your protection. Please read each caution carefully.
Related Documentation From Texas Instruments
Related Documentation from Texas Instruments
following books provide related documentation TM320C54x. obtain copy these documents, call Texas Instruments Literature Response Center (800) 477-8924. When ordering, please identify book title literature number. Many these documents located internet http://www.ti.com.
TMS320C54x Reference Set, Volume Peripherals (literature number SPRU131) describes TMS320C54x 16-bit fixed-point general-purpose digital signal processors. Covered architecture, internal register structure, data program addressing, instruction pipeline, on-chip peripherals. Also includes development support information, parts lists, design considerations using XDS510 emulator. TMS320C54x Reference Set, Volume Mnemonic Instruction (literature number SPRU172) describes TMS320C54x digital signal processor mnemonic instructions individually. Also includes summary instruction classes cycles. TMS320C54x Reference Set, Volume Algebraic Instruction (literature number SPRU179) describes TMS320C54x digital signal processor algebraic instructions individually. Also includes summary instruction classes cycles. TMS320C54x Reference Set, Volume Applications Guide (literature number SPRU173) describes software hardware applications TMS320C54x digital signal processor. Also includes development support information, parts lists, design considerations using XDS510 emulator. TMS320C54x Reference Set, Volume Enhanced Peripherals (literature number SPRU302) describes enhanced peripherals available TMS320C54x digital signal processors. Includes multichannel buffered serial ports (McBSPs), direct memory access (DMA) controller, HPI-8 HPI-16 host port interfaces, interprocessor. TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital Signal Processors (literature number SPRS039) data sheet contains electrical timing specifications these devices, well signal descriptions pinouts available packages.
Read This First
Related Documents From Texas Instruments
TMS320C54x DSKplus User's Guide (literature number SPRU191) describes TMS320C54x digital signal processor starter (DSK), which allows execute custom 'C54x code real time debug line line. Covered installation procedures, description debugger assembler, customized applications, initialization routines. TMS320C54x Assembly Language Tools User's Guide (literature number SPRU102) describes assembly language tools (assembler, linker, other tools used develop assembly language code), assembler directives, macros, common object file format, symbolic debugging directives 'C54x generation devices. TMS320C5xx Source Debugger User's Guide (literature number SPRU099) tells invoke 'C54x emulator, evaluation module, simulator versions source debugger interface. This book discusses various aspects debugger interface, including window management, command entry, code execution, data management, breakpoints. also includes tutorial that introduces basic debugger functionality. TMS320C54x Code Generation Tools Getting Started Guide (literature number SPRU147) describes install TMS320C54x assembly language tools compiler 'C54x devices. installation MS-DOSTM, OS/2TM, SunOSTM, SolarisTM, HP-UX9.0x systems covered. TMS320C54x Evaluation Module Technical Reference (literature number SPRU135) describes 'C54x evaluation module, features, design details external interfaces. TMS320C54x Optimizing Compiler User's Guide (literature number SPRU103) describes 'C54x compiler. This compiler accepts ANSI standard source code produces TMS320 assembly language source code 'C54x generation devices. TMS320C54x Simulator Getting Started (literature number SPRU137) describes install TMS320C54x simulator source debugger 'C54x. installation MS-DOSTM, PC-DOSTM, SunOSTM, SolarisTM, HP-UXsystems covered. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over third parties that provide various products that serve family TMS320 digital signal processors. myriad products applications offered-software hardware development tools, speech recognition, image processing, noise cancellation, modems, etc.
Technical Articles Related Documentation from Texas Instruments Technical Articles
TMS320C548/C549 Bootloader Technical Reference (literature number SPRU288) describes process bootloader uses transfer user code from external source program memory power (Presently available only internet.) TMS320 Development Support Reference Guide (literature number SPRU011) describes TMS320 family digital signal processors tools that support these devices. Included code-generation tools (compilers, assemblers, linkers, etc.) system integration debug tools (simulators, emulators, evaluation modules, etc.). Also covered available documentation, seminars, university program, factory repair exchange.
Technical Articles
wide variety related documentation available digital signal processing. These references fall into following application categories:
General-Purpose Graphics/Imagery Speech/Voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development Support
following list, references appear alphabetical order according author. documents contain beneficial information regarding designs, operations, applications signal-processing systems; documents provide additional references. Texas Instruments strongly suggests that refer these publications.
General-Purpose DSP:
Chassaing, Horning, D.W., "Digital Signal Processing with Fixed Floating-Point Processors" CoED, USA, Volume Number pages 1-4, March 1991. Defatta, David Joseph Lucas, William Hodgkiss, Digital Signal Processing: System Design Approach, York: John Wiley, 1988.
Read This First
Technical Articles
Erskine, Magar, "Architecture Applications SecondGeneration Digital Signal Processor," Proceedings IEEE International Conference Acoustics, Speech, Signal Processing, USA, 1985. Essig, Erskine, Caudel, Magar, Second-Generation Digital Signal Processor," IEEE Journal Solid-State Circuits, USA, Volume SC-21, Number pages 86-91, February 1986. Frantz, Lin, Reimer, Bradley, "The Texas Instruments TMS320C25 Digital Signal Microcomputer," IEEE Microelectronics, USA, Volume Number pages 10-28, December 1986. Gass, Tarrant, Richard, Pawate, Gammel, Rajasekaran, Wiggins, Covington, "Multiple Digital Signal Processor Environment Intelligent Signal Processing," Proceedings IEEE, USA, Volume Number pages 1246-1259, September 1987. Jackson, Leland Digital Filters Signal Processing, Hingham, Kluwer Academic Publishers, 1986. Jones, D.L., T.W. Parks, Digital Signal Processing Laboratory Using TMS32010, Englewood Cliffs, Prentice-Hall, Inc., 1987. Lim, Jae, Alan Oppenheim, Advanced Topics Signal Processing, Englewood Cliffs, Prentice- Hall, Inc., 1988. Lin, Frantz, Simar, Jr., "The TMS320 Family Digital Signal Processors," Proceedings IEEE, USA, Volume Number pages 1143-1159, September 1987. Lovrich, Reimer, Advanced Audio Signal Processor" Digest Technical Papers 1991 International Conference Consumer Electronics, June 1991. Magar, Essig, Caudel, Marshall Peters, NMOS Digital Signal Processor with Multiprocessing Capability," Digest IEEE International Solid-State Circuits Conference, USA, February 1985. Oppenheim, Alan R.W. Schafer, Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975 1988. Papamichalis, P.E., C.S. Burrus, "Conversion Digit-Reversed BitReversed Order Algorithms," Proceedings ICASSP USA, pages 984-987, 1989. Papamichalis, Simar, Jr., "The TMS320C30 Floating-Point Digital Signal Processor," IEEE Micro Magazine, USA, pages 13-29, December 1988.
viii
Technical Articles
Papamichalis, P.E., "FFT Implementation TMS320C30," Proceedings ICASSP USA, Volume page 1399, April 1988. Parks, T.W., C.S. Burrus, Digital Filter Design, York, John Wiley Sons, Inc., 1987. Peterson, Zervakis, Shehadeh, "Adaptive Filter Design Implementation Using TMS320C25 Microprocessor" Computers Education Journal, USA, Volume Number pages 12-16, July-September 1993. Prado, Alcantara, Fast Square-Rooting Algorithm Using Digital Signal Processor," Proceedings IEEE, USA, Volume Number pages 262-264, February 1987. Rabiner, L.R. Gold, Theory Applications Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors," Proceedings ICASSP USA, Volume page 1678, April 1988. Simar, Jr., Leigh, Koeppen, Leach, Potts, Blalock, MFLOPS Digital Signal Processor: First Supercomputer Chip," Proceedings ICASSP USA, Catalog Number 87CH2396-0, Volume pages 535-538, April 1987. Simar, Jr., Reimer, "The TMS320C25: CMOS VLSI Digital Signal Processor," 1986 Workshop Applications Signal Processing Audio Acoustics, September 1986. Texas Instruments, Digital Signal Processing Applications with TMS320 Family, 1986; Englewood Cliffs, Prentice-Hall, Inc., 1987. Treichler, J.R., C.R. Johnson, Jr., M.G. Larimore, Practical Guide Adaptive Filter Design, York, John Wiley Sons, Inc., 1987.
Graphics/Imagery:
Reimer, Lovrich, "Graphics with TMS32020," WESCON/85 Conference Record, USA, 1985.
Read This First
Technical Articles
Speech/Voice:
DellaMorte, Papamichalis, "Full-Duplex Real-Time Implementation FED-STD-1015 LPC-10e Standard V.52 TMS320C25," Proceedings SPEECH TECH pages 218-221, 1989. Gray, A.H., J.D. Markel, Linear Prediction Speech, York, Springer-Verlag, 1976. Frantz, G.A., K.S. Lin, Low-Cost Speech System Using TMS320C17," Proceedings SPEECH TECH '87, pages 25-29, April 1987. Papamichalis, Lively, "Implementation Standard LPC-10/52E TMS320C25," Proceedings SPEECH TECH '87, pages 201-204, April 1987. Papamichalis, Panos, Practical Approaches Speech Coding, Englewood Cliffs, Prentice-Hall, Inc., 1987. Pawate, B.I., G.R. Doddington, "Implementation Hidden Markov Model-Based Layered Grammar Recognizer," Proceedings ICASSP USA, pages 801- 804, 1989. Rabiner, L.R., R.W. Schafer, Digital Processing Speech Signals, Englewood Cliffs, Prentice-Hall, Inc., 1978. Reimer, J.B. K.S. Lin, "TMS320 Digital Signal Processors Speech Applications," Proceedings SPEECH TECH '88, April 1988. Reimer, J.B., M.L. McMahan, W.W. Anderson, "Speech Recognition Low-Cost System Using DSP," Digest Technical Papers 1987 International Conference Consumer Electronics, June 1987.
Control:
Ahmed, "16-Bit Microcontroller Fits Motion Control System Application," PCIM, October 1988. Ahmed, "Implementation Self Tuning Regulators with TMS320 Family Digital Signal Processors," MOTORCON '88, pages 248-262, September 1988. Ahmed, Lindquist, "Digital Signal Processors: Simplifying HighPerformance Control," Machine Design, September 1987. Ahmed, Meshkat, "Using DSPs Control," Control Engineering, February 1988.
Technical Articles
Allen, Pillay, "TMS320 Design Vector Current Control Motor Drives" Electronics Letters, Volume Number pages 2188-2190, November 1992. Bose, B.K., P.M. Szczesny, Microcomputer-Based Control Simulation Advanced Synchronous Machine Drive System Electric Vehicle Propulsion," Proceedings IECON '87, Volume pages 454-463, November 1987. Hanselman, "LQG-Control Highly Resonant Disc Drive Head Positioning Actuator," IEEE Transactions Industrial Electronics, USA, Volume Number pages 100-104, February 1988. Lovrich, Troullinos, Chirayil, All-Digital Automatic Gain Control," Proceedings ICASSP USA, Volume page 1734, April 1988. Matsui, Shigyo, "Brushless Motor Control Without Position Speed Sensors" IEEE Transactions Industry Applications, USA, Volume Number Part pages 120-127, January-February 1992. Meshkat, Ahmed, "Using DSPs Induction Motor Drives," Control Engineering, February 1988. Panahi, Restle, "DSPs Redefine Motion Control" Motion Control Magazine, December 1993.
Multimedia:
Reimer, "DSP-Based Multimedia Solutions Lead Enhancing Audio Compression Performance" Dobbs Journal, December 1993. Reimer, Benbassat, Bonneau Jr., "Application Processors: Making Multimedia Happen" Silicon Valley Design Conference, July 1991.
Military:
Papamichalis, Reimer, "Implementation Data Encryption Standard Using TMS32010," Digital Signal Processing Applications, 1986.
Read This First
Technical Articles
Telecommunications:
Ahmed, Lovrich, "Adaptive Line Enhancer Using TMS320C25," Conference Records Northcon/86, USA, 14/3/1-10, September/October 1986. Casale, Russo, Bellina, "Optimal Architectural Solution Using Processors Implementation ADPCM Transcoder," Proceedings GLOBECOM '89, pages 1267-1273, November 1989. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller SINGLE TMS32020," Proceedings ICASSP USA, Catalog Number 86CH2243-4, Volume pages 429-432, April 1986. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller Single TMS32020," Proceedings IEEE International Conference Acoustics, Speech Signal Processing, USA, 1986. Lovrich, Reimer, Multi-Rate Transcoder," Transactions Consumer Electronics, USA, November 1989. Lovrich, Reimer, Multi-Rate Transcoder" Digest Technical Papers 1989 International Conference Consumer Electronics, June 7-9, 1989. Hedberg, Fraenkel, "Implementation High-Speed Voiceband Data Modems Using TMS320C25," Proceedings ICASSP USA, Catalog Number 87CH2396-0, Volume pages 1915-1918, April 1987. Mock, "Add DTMF Generation Decoding DSP- Designs," Electronic Design, USA, Volume Number pages 205-213, March 1985. Reimer, McMahan, Arjmand, "ADPCM TMS320 Chip," Proceedings SPEECH TECH pages 246-249, April 1985. Troullinos, Bradley, "Split-Band Modem Implementation Using TMS32010 Digital Signal Processor," Conference Records Electro/86 Mini/Micro Northeast, USA, 14/1/1-21, 1986.
Automotive:
Lin, "Trends Digital Signal Processing Automotive," International Congress Transportation Electronic (CONVERGENCE '88), October 1988.
Technical Articles
Consumer:
Frantz, G.A., J.B. Reimer, R.A. Wotiz, "Julie, Application Product," Speech Tech Magazine, USA, September 1988. Reimer, J.B., G.A. Frantz, "Customization Integrated Circuit Customer Product," Transactions Consumer Electronics, USA, August 1988. Reimer, J.B., P.E. Nixon, E.B. Boles, G.A. Frantz, "Audio Customization IC," Digest Technical Papers 1988 International Conference Consumer Electronics, June 8-10 1988.
Medical:
Knapp Townshend, Real-Time Digital Signal Processing System Auditory Prosthesis," Proceedings ICASSP USA, Volume page 2493, April 1988. Morris, L.R., P.B. Barszczewski, "Design Evolution PocketSized Speech Processing System Cochlear Implant Other Hearing Prosthesis Applications," Proceedings ICASSP USA, Volume page 2516, April 1988.
Development Support:
Mersereau, Schafer, Barnwell, Smith, Digital Filter Design Package TMS320," MIDCON/84 Electronic Show Convention, USA, 1984. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors," Proceedings ICASSP USA, Volume pages 1678-1681, April 1988.
Read This First
xiii
Trademarks
Trademarks
HP-UX trademark Hewlett-Packard Company. MS-DOS registered trademark Microsoft Corporation. OS/2 PC-DOS trademarks International Business Machines Corporation. PAL® registered trademark Advanced Micro Devices, Inc. Solaris SunOS trademarks Microsystems, Inc. SPARC trademark SPARC International, Inc., licensed exclusively Microsystems, Inc. Windows registered trademark Microsoft Corporation. Hotline On-line, XDS510, XDS510WS trademarks Texas Instruments Incorporated. Micro Star trademark Texas Instruments Incorporated. trademark Motorola Corporation.
Contents
Contents
Introduction Provides overview enhanced peripherals available '5402, '5410, '5420 devices. Overview '54x Enhanced Peripherals 1.1.1 Multi-channel Buffered Serial Ports (McBSPs) 1.1.2 Direct Memory Access (DMA) Controller 1.1.3 Host Port Interfaces (HPI-8 HPI-16)
Multichannel Buffered Serial Port (McBSP) Describes features operation multichannel buffered serial ports (McBSPs). McBSP Features McBSP General Description 2.2.1 Serial Port Configuration 2.2.2 Receive Transmit Control Registers: RCR[1,2] XCR[1,2] 2-15 Data Transmission Reception Flow 2-22 2.3.1 Resetting Serial Port: (R/X)RST, RESET 2-22 2.3.2 Determining Ready Status 2-26 2.3.3 Interrupts: (R/X)INT 2-27 2.3.4 Frame Clock Configuration 2-27 2.3.5 McBSP Standard Operation 2-38 2.3.6 Frame-Synchronization Ignore 2-40 2.3.7 Serial Port Exception Conditions 2-43 2.3.8 Receive Data Justification Sign-Extension: RJUST 2-52 µ-LAW/A-LAW Companding Hardware Operation: (R/X)COMPAND 2-53 2.4.1 Companding Internal Data 2-55 Programmable Clock Framing 2-57 2.5.1 Sample Rate Generator Clocking Framing 2-58 2.5.2 Data Clock Generation 2-62 2.5.3 Frame-Sync Signal Generation 2-66 2.5.4 Clocking Examples 2-69 Multichannel Selection Operation 2-72 2.6.1 Multichannel Operation Control Registers 2-73 2.6.2 Enabling Multichannel Selection 2-76 2.6.3 Enabling Masking Channels 2-76 2.6.4 A-bis interface functionality (available '5410 only) 2-83
Contents
2.10 2.11
Protocol: McBSP Clock Stop Mode 2.7.1 Clock Stop Mode Configuration Signal Descriptions 2.7.2 McBSP Operation Master 2.7.3 McBSP Operation Slave 2.7.4 McBSP Initialization Mode Emulation FREE SOFT Bits McBSP Pins General Purpose McBSP Operation Power-Down Mode McBSP Programming Example Code
2-86 2-88 2-90 2-92 2-93 2-95 2-96 2-98 2-99
Direct Memory Access (DMA) Controller Describes direct memory access (DMA) controller, channels, registers. Overview Operation Configuration 3.2.1 Register subaddressing 3.2.2 Channel Priority Enable Control Register 3.2.3 Channel-Context Registers 3-11 Extended Addressing 3-33 Memory Maps 3-34 3.4.1 '5402 Memory 3-34 3.4.2 '5410 Memory 3-35 3.4.3 '5420 Memory 3-36 Transfer Latency 3-39 Enhanced Host Port Interface Access through Controller 3-42 Interprocessor FIFO Communication '5420 3-43 Operation Power-Down Mode 3-43 Programming Examples 3-44
Enhanced 8-Bit Host Port Interface (HPI-8) Describes operation function enhanced 8-bit host port interface (HPI-8). Introduction Enhanced 8-Bit Host Port Interface (HPI-8) HPI-8 Basic Functional Description Details HPI-8 Operation 4.3.1 HPI-8 Address Register Memory 4.3.2 Extended HPI-8 Addressing 4-10 4.3.3 Address Autoincrement 4-11 4.3.4 HPI-8 Control Register Bits Functions 4-12 Host Read/Write Access HPI-8 4-14 4.4.1 Latency HPI-8 Accesses 4-16 4.4.2 Access Sequence Examples 4-19 DSPINT HINT Operation 4-23 4.5.1 Host Device Using DSPINT Interrupt '54x 4-23 4.5.2 '54x Using HINT Interrupt Host Device 4-23 Considerations HPI-8 Transfers While Changing Clock Modes 4-24
Contents
Considerations IDLE 4.7.1 HPI-8 Accesses During IDLE1 IDLE2 4.7.2 HPI-8 Accesses During IDLE3 Effects Reset HPI-8 Operation 4.8.1 Accesses HPI-8 After Reset 4.8.2 Access HPI-8 During Reset ('5410 Only) HPI-8 Data Pins General Purpose Pins (Not Available '5410) 4.9.1 Using GPIO feature
4-26 4-26 4-26 4-28 4-28 4-28 4-30 4-36
Enhanced 16-Bit Host Port Interface (HPI-16) Describes operation function enhanced 16-bit host port interface (HPI-16). HPI-16 Operational Overview Multiplexed Mode 5.2.1 Host Accesses With 5-10 5.2.2 Host Accesses Without 5-11 5.2.3 Autoincrement Operation 5-12 Non-Multiplexed Mode 5-15 HPI-16 Memory 5-18 HPI-16 Interaction 5-19 HPI-16 Operation During Reset 5-21 HPI-16 Operation During IDLEn 5-21 Changes Clock Modes That Affect HPI-16 5-22
Interprocessor Communications Describes multi-core communications, including core-to-core FIFO communications external memory interface- to-host port interface (EMIF-to-HPI) communications. Communication Within Multi-Core DSPs Bi-Directional FIFO Accessing HPI-16 From External Memory Space Subsystem Communication Using McBSP 6-10 Interprocessor Interrupts 6-11
Enhanced External Interface (EnhXIO) Describes improved functionality enhanced external parallel interface. Introduction Enhanced External Parallel Interface (XIO2) 7.1.1 Additional Features Sequences
Glossary
Contents
xvii
Figures
Figures
2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 2-33 2-34 2-35 2-36
xviii
McBSP Internal Block Diagram Serial Port Control Register (SPCR1) Serial Port Control Register (SPCR2) 2-10 Control Register (PCR) 2-12 Receive Control Register (RCR1) 2-16 Receive Control Register (RCR2) 2-17 Transmit Control Register (XCR1) 2-19 Transmit Control Register (XCR2) 2-20 Frame Clock Operation 2-28 Receive Data Clocking 2-30 Dual-Phase Frame Example 2-30 Single-Phase Frame Four 8-Bit Words 2-33 Single-Phase Frame 32-Bit Word 2-34 Data Delay 2-34 Two-bit Data Delay Used Discard Framing 2-35 AC97 Dual-Phase Frame Format 2-36 AC97 Timing Near Frame-Synchronization Example 2-36 Enabler Normal Mode 2-37 Enabler A-bis mode 2-37 McBSP Standard Operation 2-38 Receive Operation 2-39 Transmit Operation 2-39 Maximum Frame Frequency Receive/Transmit (R/X)DATDLY 2-40 Maximum Packet Frequency Operation with 8-bit Data 2-41 Data Packing Maximum Packet Frequency With (R/X)FIG=1 2-42 Unexpected Frame Synchronization With (R/X)FIG=0 2-43 Unexpected Frame Synchronization With (R/X)FIG 2-43 Serial Port Receive Overrun 2-45 Serial Port Receive Overrun Avoided 2-46 Response Receive Frame-Synchronization Pulse 2-47 Unexpected Receive Synchronization Pulse 2-48 Transmit With Data Overwrite 2-48 Transmit Empty 2-49 Transmit Empty Avoided 2-50 Response Transmit Frame Synchronization 2-51 Unexpected Transmit Frame-Synchronization Pulse 2-52
Figures
2-37 2-38 2-39 2-40 2-41 2-42 2-43 2-44 2-45 2-46 2-47 2-48 2-49 2-50 2-51 2-52 2-53 2-54 2-55 2-56 2-57 2-58 2-59 2-60 2-61 2-62 2-63 2-64 2-65 2-66 2-67
Companding Flow 2-54 µ-Law Transmit Data Companding Format 2-54 A-Law Transmit Data Companding Format 2-54 Companding Internal Data 2-55 Clock Frame Generation 2-57 Sample Rate Generator 2-58 Sample Rate Generator Register (SRGR1) 2-59 Sample Rate Generator Register (SRGR2) 2-60 CLKG Synchronization generation when GSYNC CLKGDV 2-63 CLKG Synchronization generation when GSYNC CLKGDV 2-64 Programmable Frame Period Width 2-67 ST-BUS MVIP Example 2-69 Single-Rate Clock Example 2-70 Double-Rate Clock Example 2-71 Multichannel Control Register (MCR1) 2-73 Multichannel Control Register (MCR2) 2-75 Channel Enabling Blocks Partition 2-77 XMCM Operation 2-79 Receive Channel Enable Register Partition (RCERA) 2-80 Receive Channel Enable Register Partition (RCERB) 2-81 Transmit Channel Enable Register Partition (XCERA) 2-81 Transmit Channel Enable Register Partition (XCERB) 2-82 A-bis Mode Receive Operation 2-84 A-bis Mode Transmit Operation Indicates High-Impedance) 2-84 Typical Interface 2-86 Configuration: McBSP Master 2-87 Configuration: McBSP Slave 2-87 Transfer with CLKSTP 10b, CLKXP 2-88 Transfer with CLKSTP 11b, CLKXP 2-89 Transfer with CLKSTP 10b, CLKXP 2-89 Transfer with CLKSTP 11b, CLKXP 2-89 Register Subaddressing Channel Priority Enable Control (DMPREC) Register Sync Event Frame Count (DMSFCn) Register 3-13 Transfer Mode Control (DMMCRn) Register 3-17 Data Sorting Example 3-23 Source Program Page Address Register (DMSRCP) 3-33 Destination Program Page Address Register (DMDSTP) 3-33 Host Port Interface Block Diagram Generic System Block Diagram Strobe Select Logic HPI-8 Memory Maps
Contents
Figures
4-10 4-11 5-10 5-11 5-12 5-13
HPIC Diagram Host '54x Accesses 4-13 HPI-8 Timing Diagram 4-15 HPI-8 Transfers While Switching Clock Modes 4-24 HPI-8 Transfers While '54x IDLE3 Mode 4-27 General Purpose Control Register (GPIOCR) Address 003Ch 4-30 General Purpose Status Register (GPIOSR) address 003Dh 4-32 GPIO Code Example 4-36 Strobe Select Logic Interfacing HPI-16 Multiplexed Mode ('VC5420) HPIC Register HPIA Write Using 5-10 HPIC Read Without Using 5-11 HPID Read using Autoincrement 5-12 HPID Write Using Autoincrement 5-13 Interfacing HPI-16 Non-Multiplexed Mode ('VC5420) 5-15 HPID Read Non-Multiplexed Mode 5-16 HPID Write Non-Multiplexed Mode 5-17 'VC5420 Memory Relative 5-18 Interaction 5-19 HPI-16 Operation During Clock Mode Change 5-22 'VC5420 2-Subsystem 'VC5420 FIFO Configuration Configuration FIFO Operation HPI-16 External Memory Interface Connection ('VC5420) McBSP-to-McBSP Connection 6-10 Non-Consecutive Memory Read Read Sequence Consecutive Memory Read Sequence reads) Memory Write Write Sequence
Tables
Tables
2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 2-33 2-34 McBSP Interface Signals McBSP Registers McBSP Interrupts Event Synchronization Serial Port Control Register (SPCR1) Bit-Field Descriptions Serial Port Control Register (SPCR2) Bit-Field Descriptions 2-10 Control Register (PCR) Bit-Field Descriptions 2-12 Receive Control Register (RCR1) Bit-Field Descriptions 2-16 Receive Control Register (RCR2) Bit-Field Descriptions 2-17 Transmit Control Register (XCR1) Bit-Field Descriptions 2-19 Transmit Control Register (XCR2) Bit-Field Descriptions 2-20 Reset State McBSP Pins 2-23 RCR[1,2]/XCR[1,2] Bit-Fields Controlling Words Frame Bits Word 2-31 McBSP Receive/Transmit Frame Length (1,2) Configuration 2-31 McBSP Receive/Transmit Word Length Configuration 2-32 RJUST Field With 12-Bit Example Data 0xABC 2-52 RJUST Field With 20-Bit Example Data 0xABCDE 2-52 Sample Rate Generator Register (SRGR1) Bit-Field Descriptions 2-59 Sample Rate Generator Register (SRGR2) Bit-Field Descriptions 2-60 Receive Clock Selection 2-65 Transmit Clock Selection 2-65 Receive Frame-Synchronization Selection 2-67 Transmit Frame-Synchronization Selection 2-68 Multichannel Control Register (MCR1) Bit-Field Descriptions 2-73 Multichannel Control Register (MCR2) Bit-Field Descriptions 2-75 Receive Channel Enable Register Partition (RCERA) Bit-Field Descriptions 2-80 Receive Channel Enable Register Partition (RCERB) Bit-Field Descriptions 2-81 Transmit Channel Enable Register Partition (XCERA) Bit-Field Descriptions 2-81 Transmit Channel Enable Register Partition (XCERB) Bit-Field Descriptions 2-82 Clock Stop Mode Configurations 2-88 Register Values Mode Configuration 2-90 Register Values Master Operation 2-91 Register Values Slave Operation 2-92 McBSP Clock Configuration 2-95 Configuration Pins General Purpose 2-97 Registers Channel Priority Enable Control (DMPREC) Register Bit/Field Descriptions
Contents
Tables
3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 4-10 4-11 4-12 4-13 4-14
Multiplexed Interrupt Assignments '5402 3-10 Multiplexed Interrupt Assignments '5410 3-10 Multiplexed Interrupt Assignments '5420 (each subsystem) 3-10 Sync Event Frame Count (DMSFCn) Register Bit/Field Descriptions 3-13 Sync Event Options '5402 3-14 Sync Event Options '5410 3-15 Sync Event Options '5420 (each subsystem) 3-16 Transfer Mode Control (DMMCRn) Register Bit/Field Descriptions 3-17 Buffer Examples 3-24 Address Indexing Modes 3-25 Block Transfer Interrupt Generation Modes 3-28 '5402 Memory 3-34 '5410 Memory 3-35 '5420 Memory 3-37 Transfer Cycle Times 3-39 Main Differences Between Enhanced 8-Bit Standard 8-Bit HPI-8 Register Description HPI-8 Signal Names Functions HPI-8 Input Control Signals Function Selection Control Register (HPIC) Descriptions 4-12 HPIC Host '54x Read/Write Characteristics 4-13 HPI-8 Internal Delays Access Type 4-17 Wait-State Generation Conditions 4-18 Initialization HPIA 4-20 Read Access HPI-8 With Autoincrement 4-21 Write Access With Autoincrement 4-22 HPI-8 Operation During RESET ('5410 only) 4-29 General Purpose Control Register (GPIOCR) Functions 4-30 General Purpose Status Register (GPIOSR) Functions 4-32 HPI-16 Descriptions HCNTL0/1 Modes HPIC Descriptions Configuration Support FIFO Transfers EMIF/HPI-16 Modes MP/MC Levels Reset
xxii
Examples
Examples
3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 Resetting Configuring Transmitter While Receiver Running 2-26 Using Register Subaddressing Without Autoincrement Using Register Subaddressing With Autoincrement Data Sorting Address Modification 3-22 Buffer Size Examples 3-25 Wrap Address Calculation Single-Word Transfer With Indexed Addressing 3-26 Wrap Address Calculation Double-Word Transfer With Indexed Addressing 3-26 '5402/'5420 Interrupt Example Even Size Buffer With Index 3-29 '5402/'5420 Interrupt Example Size Buffer With Index 3-29 '5402/'5420 Interrupt Example Even Size Buffer With Index 3-30 '5402/'5420 Interrupt Example Size Buffer With Index 3-30 '5410 Interrupt Example Even Size Buffer With Index 3-31 '5410 Interrupt Example Size Buffer With Index 3-31 '5410 Interrupt Example Even Size Buffer With Index 3-32 '5410 Interrupt Example Size Buffer With Index 3-32 Channel Transfer Rate Example 3-40 Program Memory Data Memory Transfer Without Autoincremented Subaddressing 3-46 Program Memory Data Memory Transfer Using Autoincremented Subaddressing 3-48 Program Memory Data Memory Transfer With Autoinitialization 3-50 McBSP Data Transfer Mode 3-52 McBSP Data Transfer Double-Word Mode 3-54 McBSP Data Memory Transfer With Data Sorting 3-56 Channels Configured FIFO Transmit Receive
Contents
xxiii
Running Title-Attribute Reference
xxiv
Chapter
Introduction
'54x device fixed-point digital signal processor (DSP) TMS320 family. central processing unit (CPU), with modified Harvard architecture, minimizes power consumption adds high degree parallelism. System performance further enhanced versatile addressing modes instruction sets. These other characteristics allow '54x meet specific needs real-time embedded applications such telecommunications. '54x devices have general-purpose pins BIO), timer (two '5402), clock generator, software-programmable wait-state generator, programmable bank-switching module. Different types quantities serial ports, host-port interfaces, clock generators specific various '54x devices. This chapter discusses enhanced peripherals available '5402, '5410, '5420 devices.
Topic
Page
Overview '54x Enhanced Peripherals
Overview '54x Enhanced Peripherals
sections that follow provide overview enhanced peripherals available '54x.
1.1.1
Multi-channel Buffered Serial Ports (McBSPs)
The'54x family provides high-speed, full-duplex multi-channel buffered serial ports (McBSPs) that allow direct interface other '54x devices, codecs, other devices system. MCBSPs enhanced version standard serial port interface found other '54x devices. Some features McBSP include:
Double-buffered transmit triple-buffered receive operation allow
continuous data stream.
Independent framing clocking receive transmit. Multi-channel transmit receive channels. Data sizes including bits. µ-law A-law companding. Programmable polarity both frame synchronization clocks. Programmable internal clocks frame synchronization.
more information McBSPs, Chapter
1.1.2
Direct Memory Access (DMA) Controller
6-channel '54x direct memory access (DMA) controller transfers data between points memory without intervention CPU. allows following movements data occur background operation: data from internal program/data memory; internal peripherals such McBSP's; external memory devices. independent programmable channels allowing different contexts operation. more information DMA, Chapter
1.1.3
Host Port Interfaces (HPI-8 HPI-16)
There enhanced host port interfaces '54x, HPI-8 HPI-16. These 8-bit 16-bit parallel ports that provide interface host processor. Information exchanged between '54x host processor through '54x on-chip memory that accessible both host processor '54x. more details about operation HPI-8 HPI-16, Chapters respectively.
Chapter
Multichannel Buffered Serial Port (McBSP)
Depending specific device, digital signal processor provides multiple high-speed, full-duplex, multichannel buffered serial ports (McBSPs) that allow direct interface other '54x devices, codecs, other devices system. '5402 provides two, '5410 three, '5420 McBSPs. They based standard serial port interface found other '54x devices. This chapter describes operation McBSPs, includes register definitions timing diagrams.
Topic
Page
McBSP Features McBSP General Description Data Transmission Reception Flow 2-22 µ-LAW/A-LAW Companding Hardware Operation: (R/X) COMPAND 2-53 Programmable Clock Framing 2-57 Multichannel Selection Operation 2-72 Protocol: McBSP Clock Stop Mode 2-86 Emulation FREE SOFT Bits 2-95 McBSP Pins General-Purpose 2-96
2.10 McBSP Operation Power-Down Mode 2-98 2.11 McBSP Programming Example Code 2-99
McBSP Features
McBSP Features
McBSP based standard serial port interface found TMS320C2x, 'C20x, 'C5x, 'C54x devices. McBSP provides:
Full-duplex communication Double-buffered transmit triple-buffered receive data registers, which
allow continuous data stream
Independent framing clocking receive transmit Direct interface industry-standard codecs, analog interface chips (AICs),
other serially connected devices
External shift clock generation, internal, programmable-frequency
shift clock addition, McBSP following capabilities:
Direct interface
T1/E1 framers MVIP switching compatible ST-BUS compliant devices including: MVIP framers H.100 framers SCSA framers
IOM-2 compliant devices AC97 compliant devices (The necessary multi-phase frame-synchronization capability provided.) compliant devices SPIt devices
Multichannel transmit receive channels wide selection data sizes including bits
Note: Data sizes referred word serial word throughout this document bits, contrast true definition word which bits.
µ-Law A-Law companding 8-bit data transfers with option first Programmable polarity both frame synchronization data clocks Highly programmable internal clock frame generation
McBSP General Description
McBSP General Description
McBSP consists data path control path connected external devices seven pins shown Figure 2-1.
Figure 2-1. McBSP Internal Block Diagram
McBSP Compand
CLKX CLKR CLKS
Expand Compress SPCR Clock frame-sync generation control SRGR Multichannel selection RCER XCER RINT XINT REVT XEVT REVTA XEVTA
16-bit peripheral
Interrupts
Synchronization events
Multichannel Buffered Serial Port (McBSP)
McBSP General Description
Data communicated devices interfacing McBSP data transmit (DX) transmit data receive (DR) receive. Control information form clocking frame synchronization communicated CLKX, CLKR, FSX, FSR. '54x communicates with McBSP through 16-bit-wide control registers accessible internal peripheral bus. controller reads received data from data receive register (DRR[1,2]) writes data transmitted data transmit register (DXR[1,2]). Data written DXR[1,2] shifted transmit shift register (XSR[1,2]). Similarly, receive data shifted into receive shift register (RSR[1,2]) copied into receive buffer register (RBR[1,2]). RBR[1,2] then copied DRR[1,2], which read controller. This allows simultaneous movement internal external data communications. DRR2, RBR2, RSR2, DXR2, XSR2 registers utilized (written, read, shifted) receive/transmit word length, R/XWDLEN[1,2], specified 12-, 16-bit mode. remaining registers accessible configure control mechanism McBSP. These registers listed Table 2-2, McBSP Registers, page 2-5. control block consists internal clock generation, frame-synchronization signal generation, their control multichannel selection. This control block sends notification important events controller interrupt four event signals shown Table 2-3, McBSP Interrupts Event Synchronization, page 2-6.
Table 2-1. McBSP Interface Signals
CLKR CLKX CLKS I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Description Receive clock Transmit clock External clock Received serial data Transmitted serial data Receive frame synchronization Transmit frame synchronization
Input, Output, High-impedance
McBSP General Description
Table 2-2. McBSP Registers
Address McBSP 0020 0021 0022 0023 0038 0039 0039 0039 0039 0039 0039 0039 0039 0039 0039 0039 0039 McBSP 0040 0041 0042 0043 0048 0049 0049 0049 0049 0049 0049 0049 0049 0049 0049 0049 0049 McBSP 0030 0031 0032 0033 0034 0035 0035 0035 0035 0035 0035 0035 0035 0035 0035 0035 0035 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B SubS bAddress Acronym Register Name{ RBR[1,2] RSR[1,2] XSR[1,2] DRR2x DRR1x DXR2x DXR1x SPSAx SPCR1x SPCR2x RCR1x RCR2x XCR1x XCR2x SRGR1x SRGR2x MCR1x MCR2x RCERAx RCERBx McBSP receive buffer register McBSP receive shift register McBSP transmit shift register McBSP data receive register McBSP data receive register McBSP data transmit register McBSP data transmit register McBSP sub-address register McBSP serial port control register McBSP serial port control register McBSP receive control register McBSP receive control register McBSP transmit control register McBSP transmit control register McBSP sample rate generator register McBSP sample rate generator register McBSP multichannel register McBSP multichannel register McBSP receive channel enable register partition McBSP receive channel enable register partition 2.2.1 2.2.1 2.2.2 2.2.2 2.2.2 2.2.2 2.5.1.1 2.5.1.1 2.6.1 2.6.1 2.6.3.1 2.6.3.1
Section
RBR[1,2], RSR[1,2], XSR[1,2] directly accessible DMA.
Multichannel Buffered Serial Port (McBSP)
McBSP General Description
Table 2-2. McBSP Registers (Continued)
Address McBSP 0039 0039 0039 McBSP 0049 0049 0049 McBSP 0035 0035 0035 SubAddress 0x000C 0x000D 0x000E Acronym Register Name{ XCERAx XCERBx PCRx McBSP transmit channel enable register partition McBSP transmit channel enable register partition McBSP control register
Section 2.6.3.1 2.6.3.1 2.2.1
RBR[1,2], RSR[1,2], XSR[1,2] directly accessible DMA.
Table 2-3. McBSP Interrupts Event Synchronization
Interrupt Name RINT XINT REVT XEVT REVTA XEVTA Description Receive interrupt Transmit interrupt Receive synchronization event Transmit synchronization event Receive synchronization eventA Transmit synchronization eventA Section 2.3.3 2.3.3 2.3.2.1 2.3.2.2 2.6.4 2.6.4
2.2.1
Serial Port Configuration
serial port configured 16-bit serial port control registers (SPCR[1,2]) Control Register (PCR). These registers shown Figure 2-2, Figure Figure 2-4, respectively. SPCR[1, contain McBSP status information also bits that configured desired operation. operation each bit-field discussed sections listed Table 2-4, Serial Port Control Register (SPCR1) Bit-Field Description, page 2-7; Table 2-5, Serial Port Control Register (SPCR2) BitField Description, page 2-10; Table 2-6, Control Register (PCR) Bit-field Description, page 2-12.
McBSP General Description
addition being used configure McBSP pins inputs outputs during normal serial port operation, used configure serial port pins general purpose inputs outputs during receiver and/or transmitter reset. This described section 2.9, McBSP Pins General Purpose I/O, page 2-96.
Figure 2-2. Serial Port Control Register (SPCR1)
RW,+0 DXENA RW,+0
Note:
RJUST RW,+0 ABIS RW,+0
CLKSTP RW,+0 RINRW,+0
reserved R,+0
RW,+0
RSYNCERR RW,+0
RFULL R,+0
RRDY R,+0
RRST RW,+0{
Read, Write, Value reset
means read-only, reset value means read write allowed, reset value
Table 2-4. Serial Port Control Register (SPCR1) Bit-Field Descriptions
Name Function Digital Loop Back Mode 14-13 RJUST Digital loop back mode disabled Digital loop back mode enabled 2.3.8 Section 2.5.2.5
Receive Sign-Extension Justification Mode RJUST RJUST RJUST RJUST Right-justify zero-fill MSBs DRR[1,2] Right-justify sign-extend MSBs DRR[1,2] Left-justify zero-fill LSBs DRR[1,2] Reserved
Multichannel Buffered Serial Port (McBSP)
McBSP General Description
Table 2-4. Serial Port Control Register (SPCR1) Bit-Field Descriptions (Continued)
12-11 Name CLKSTP Function Clock Stop Mode CLKSTP Clock stop mode disabled. Normal clocking non-SPI mode. Section
Various modes when: CLKSTP CLKXP CLKSTP CLKXP CLKSTP CLKXP CLKSTP CLKXP 10-8 reserved DXENA Reserved Enabler. DXENA DXENA ABIS ABIS Mode ABIS ABIS RINA-bis mode disabled A-bis mode enabled 2.3.3 enabler enabler 2.6.4 2.3.4.8 Clock starts with rising edge without delay Clock starts with falling edge without delay Clock starts with rising edge with delay Clock starts with falling edge with delay
Receive Interrupt Mode RIN= RIN= RIN= RINTM=11 RINT driven RRDY (i.e. word) frame A-bis mode. RINT generated end-of-block end-of-frame multichannel operation RINT generated frame synchronization RINT generated RSYNCERR
RSYNCERR
Receive Synchronization Error RSYNCERR RSYNCERR synchronization error Synchronization error detected McBSP.
2.3.7.2
McBSP General Description
Table 2-4. Serial Port Control Register (SPCR1) Bit-Field Descriptions (Continued)
Name RFULL Function Receive Shift Register (RSR[1,2]) Full RFULL RFULL RRDY Receiver Ready RRDY RRDY RRST Receiver ready. Receiver ready with data read from DRR[1,2]. 2.3.1 RBR[1,2] overrun condition DRR[1,2] read, RBR[1,2] full RSR[1,2] also full with word 2.3.2 Section 2.3.7.1
Receiver reset. This resets enables receiver. RRST RRST serial port receiver disabled reset state. serial port receiver enabled.
Multichannel Buffered Serial Port (McBSP)
McBSP General Description
Figure 2-3. Serial Port Control Register (SPCR2)
reserved{ R,+0 FREE RW,+0 SOFT RW,+0
FRST RW,+0
Note:
GRST RW,+0
XINRW,+0
XSYNCERR} RW,+0
XEMPTY R,+0
XRDY R,+0
XRST RW,+0
Read, Write, Value reset
Note: This reserved bit-fields have storage associated with them; however, they always read CAUTION: Writing this sets error condition; thus, mainly used testing purposes this operation desired.
Table 2-5. Serial Port Control Register (SPCR2) Bit-Field Descriptions
15-10 Name rsvd FREE Function Reserved Free Running Mode FREE FREE SOFT Soft SOFT SOFT FRST SOFT mode disabled SOFT mode enabled 2.3.1 Free running mode disabled Free running mode enabled Section
Frame-Sync Generator Reset FRST Frame-synchronization logic reset. Frame-sync signal generated sample-rate generator. Frame-sync signal generated after (FPER+1) number CLKG clocks; i.e., frame counters loaded with their programmed values.
FRST
GRST
Sample-Rate Generator Reset GRST GRST Sample rate generator reset Sample rate generator pulled reset. CLKG driven programmed value sample rate generator registers (SRGR[1,2]).
2.3.1
2-10
McBSP General Description
Table 2-5. Serial Port Control Register (SPCR2) Bit-Field Descriptions (Continued)
Name XINFunction Transmit Interrupt Mode XIN= XIN= XIN= XINTM=11 XSYNCERR XINT driven XRDY (i.e., word) frame A-bis mode. XINT generated end-of-block end-of-frame multichannel operation XINT generated frame synchronization XINT generated XSYNCERR 2.3.7.2 Section 2.3.3
Transmit Synchronization Error XSYNCERR XSYNCERR synchronization error Synchronization error detected McBSP.
XEMPTY
Transmit Shift Register (XSR[1,2]) Empty XEMPTY XEMPTY XSR[1,2] empty XSR[1,2] empty
2.3.7.4
XRDY
Transmitter Ready XRDY XRDY Transmitter ready. Transmitter ready data DXR[1,2]. This resets enables transmitter. serial port transmitter disabled reset state. serial port transmitter enabled.
2.3.2
XRST
Transmitter reset. XRST XRST
2.3.1
Multichannel Buffered Serial Port (McBSP)
2-11
McBSP General Description
Figure 2-4. Control Register (PCR)
reserved R,+0 reserved R,+0
Note:
XIOEN RW,+0
RIOEN RW,+0 DR_STAT R,+0
FSXM RW,+0 FSXP RW,+0
FSRM RW,+0 FSRP RW,+0
CLKXM RW,+0 CLKXP RW,+0
CLKRM RW,+0 CLKRP RW,+0
CLKS_STAT R,+0
DX_STAT R,+0
Read, Write, Value reset
Table 2-6. Control Register (PCR) Bit-Field Descriptions
15-14 Name reserved XIOEN Function Reserved Transmit general purpose mode only when XRST SPCR[1,2] XIOEN XIOEN CLKX configured serial port pins function general-purpose I/Os. general purpose output. CLKX general purpose I/Os. These serial port pins perform serial port operation. Section
RIOEN
Receive general purpose mode only when RRST SPCR[1,2] RIOEN RIOEN FSR, CLKR CLKS configured serial port pins function general-purpose I/Os. CLKS pins general purpose inputs; CLKR general purpose I/Os. These serial port pins perform serial port operation. CLKS affected combination RRST RIOEN signals receiver.
2-12
McBSP General Description
Table 2-6. Control Register (PCR) Bit-Field Descriptions (Continued)
Name FSXM Function Transmit Frame-Synchronization Mode FSXM FSXM Frame-synchronization signal derived from external source Frame synchronization determined sample rate generator frame-synchronization mode FSGM SRGR2. 2.5.3.2 Section 2.5.3.3
FSRM
Receive Frame-Synchronization Mode FSRM FSRM Frame-synchronization pulses generated external device. input Frame synchronization generated internally sample rate generator. output except when GSYNC=1 SRGR (see section 2.5.1.1).
CLKXM
Transmitter Clock Mode CLKXM CLKXM Transmitter clock driven external clock with CLKX input pin. CLKX output driven internal sample rate generator.
2.5.2.7
During mode (when CLKSTP non-zero value): CLKXM CLKXM McBSP slave clock (CLKX) driven master system. CLKR internally driven CLKX. McBSP master generates clock (CLKX) drive receive clock (CLKR) shift clock SPI-compliant slaves system.
Multichannel Buffered Serial Port (McBSP)
2-13
McBSP General Description
Table 2-6. Control Register (PCR) Bit-Field Descriptions (Continued)
Name CLKRM Function Receiver Clock Mode Case Digital loop back mode (DLB SPCR1 CLKRM CLKRM Receive clock (CLKR) input driven external clock. CLKR output driven internal sample rate generator. Section 2.5.2.6
Case Digital loop back mode (DLB=1) SPCR1 CLKRM Receive clock (not CLKR pin) driven transmit clock (CLKX) which based CLKXM PCR. CLKR high-impedance. CLKR output driven transmit clock. transmit clock derived based CLKXM PCR.
CLKRM
rsvd CLKS_ STAT DX_STAT DR_STAT FSXP
Reserved CLKS status. Reflects value CLKS when selected general purpose input. status. Reflects value driven when selected general purpose output. status. Reflects value when selected general purpose input. Transmit Frame-Synchronization Polarity 2.3.4.1
FSXP FSXP FSRP
Frame-synchronization pulse active high Frame-synchronization pulse active 2.3.4.1
Receive Frame-Synchronization Polarity
FSRP FSRP
Frame-synchronization pulse active high Frame-synchronization pulse active
2-14
McBSP General Description
Table 2-6. Control Register (PCR) Bit-Field Descriptions (Continued)
Name CLKXP Function Transmit Clock Polarity CLKXP CLKXP CLKRP Transmit data sampled rising edge CLKX Transmit data sampled falling edge CLKX 2.3.4.1 Section 2.3.4.1
Receive Clock Polarity CLKRP CLKRP Receive data sampled falling edge CLKR Receive data sampled rising edge CLKR
2.2.2
Receive Transmit Control Registers: RCR[1,2] XCR[1,2]
receive transmit control registers (RCR[1,2] XCR[1,2]) configure various parameters receive transmit operations, respectively. They shown Figure 2-5, Receive Control Register (RCR1), page 2-16; Figure 2-6, Receive Control Register (RCR2), page 2-17; Figure 2-7, Transmit Control Register (XCR1), page 2-19; Figure 2-8, Transmit Control Register (XCR2), page 2-20. operation each bit-field discussed sections listed Table 2-7, Receive Control Register (RCR1) Bit-Field Description, page 2-16; Table 2-8, Receive Control Register (RCR2) Bit-Field Description, page 2-17; Table 2-9, Transmit Control Register (XCR1) Bit-Field Description, page 2-19; Table 2-10, Transmit Control Register (XCR2) Bit-Field Description, page 2-20.
Multichannel Buffered Serial Port (McBSP)
2-15
McBSP General Description
Figure 2-5. Receive Control Register (RCR1)
rsvd R,+0
Note:
RFRLEN1 RW,+0
Read, Write, Value reset
RWDLEN1 RW,+0
reserved R,+0
Table 2-7. Receive Control Register (RCR1) Bit-Field Descriptions
14-8 Name rsvd RFRLEN1 Function Reserved Receive Frame Length RFRLEN1 0000 RFRLEN1 0001 word frame words frame RFRLEN1 1111 RWDLEN1 Receive Word Length RWDLEN1 RWDLEN1 RWDLEN1 RWDLEN1 RWDLEN1 RWDLEN1 RWDLEN1 rsvd Reserved bits bits bits bits bits bits Reserved words frame 2.3.4.4 2.3.4.3 Section
2-16
McBSP General Description
Figure 2-6. Receive Control Register (RCR2)
RPHASE RW,+0
Note:
RFRLEN2 RW,+0
RFIG RW,+0
RWDLEN2 RW,+0
RCOMPAND RW,+0
RDATDLY RW,+0
Read, Write, Value reset
Table 2-8. Receive Control Register (RCR2) Bit-Field Descriptions
Name RPHASE Function Receive Phases RPHASE RPHASE 14-8 RFRLEN2 Receive Frame Length RFRLEN2 0000 RFRLEN2 0001 word frame words frame RFRLEN1 1111 RWDLEN2 Receive Word Length RWDLEN2 RWDLEN2 RWDLEN2 RWDLEN2 RWDLEN2 RWDLEN2 RWDLEN2 bits bits bits bits bits bits Reserved words frame 2.3.4.4 Single-phase frame Dual-phase frame 2.3.4.3 Section 2.3.4.2
Multichannel Buffered Serial Port (McBSP)
2-17
McBSP General Description
Table 2-8. Receive Control Register (RCR2) Bit-Field Descriptions (Continued)
Name RCOMPAND Function Receive companding mode. Modes other than only enabled when appropriate RWDLEN 000b, indicating 8-bit data. RCOMPAND RCOMPAND RCOMPAND RCOMPAND RFIG Receive Frame Ignore RFIG RFIG RDATDLY Receive data delay RDATDLY RDATDLY RDATDLY RDATDLY 0-bit data delay 1-bit data delay 2-bit data delay Reserved Receive frame-synchronization after first restarts transfer. Receive frame-synchronization after first ignored. pulses pulses 2.3.4.6 companding, data transfer starts with first. companding, 8-bit data, transfer starts with first. Compand using µ-law receive data. Compand using A-law receive data. 2.3.6.2 Section
2-18
McBSP General Description
Figure 2-7. Transmit Control Register (XCR1)
rsvd R,+0
Note:
XFRLEN1 RW,+0
Read, Write, Value reset
XWDLEN1 RW,+0
rsvd R,+0
Table 2-9. Transmit Control Register (XCR1) Bit-Field Descriptions
14-8 Name rsvd XFRLEN1 Function Reserved Transmit Frame Length XFRLEN1 0000 XFRLEN1 0001 word frame words frame RFRLEN1 1111 XWDLEN1 Transmit Word Length XWDLEN1 XWDLEN1 XWDLEN1 XWDLEN1 XWDLEN1 XWDLEN1 XWDLEN1 rsvd Reserved bits bits bits bits bits bits Reserved words frame 2.3.4.4 2.3.4.3 Section
Multichannel Buffered Serial Port (McBSP)
2-19
McBSP General Description
Figure 2-8. Transmit Control Register (XCR2)
XPHASE RW,+0
Note:
XFRLEN2 RW,+0
XFIG RW,+0
XWDLEN2 RW,+0
XCOMPAND RW,+0
XDATDLY RW,+0
Read, Write, Value reset
Table 2-10. Transmit Control Register (XCR2) Bit-Field Descriptions
Name XPHASE Function Transmit Phases Section 2.3.4.2
XPHASE XPHASE 14-8 XFRLEN2 Transmit Frame Length XFRLEN2 0000 XFRLEN2 0001
Single-phase frame Dual-phase frame 2.3.4.3 word frame words frame
XFRLEN1 1111 XWDLEN2 Transmit Word Length XWDLEN2 XWDLEN2 XWDLEN2 XWDLEN2 XWDLEN2 XWDLEN2 XWDLEN2
words frame 2.3.4.4 bits bits bits bits bits bits Reserved
2-20
McBSP General Description
Table 2-10. Transmit Control Register (XCR2) Bit-Field Descriptions (Continued)
Name XCOMPAND Function Transmit companding mode. Modes other than only enabled when appropriate XWDLEN 000b, indicating 8-bit data. XCOMPAND XCOMPAND XCOMPAND XCOMPAND XFIG Transmit Frame Ignore XFIG XFIG XDATDLY Transmit Data Delay XDATDLY XDATDLY XDATDLY XDATDLY 0-bit data delay 1-bit data delay 2-bit data delay Reserved Transmit frame-synchronization pulses after first restarts transfer. Transmit frame-synchronization pulses after first ignored. 2.3.4.6 companding, data transfer starts with first. companding, 8-bit data, transfer starts with first. Compand using µ-law transmit data. Compand using A-law transmit data. 2.3.6.2 Section
Multichannel Buffered Serial Port (McBSP)
2-21
Data Transmission Reception Flow
Data Transmission Reception Flow
shown Figure 2-1, McBSP Internal Block Diagram, page 2-3, receive operation triple buffered transmit operation double buffered. Receive data arrives shifted into RSR[1,2]. Once full word (8-, 12-, 16-, 20-, 24-, 32-bit) received, RSR[1,2] copied receive buffer register, RBR[1,2], only RBR[1,2] full. RBR[1,2] then copied DRR[1,2], unless DRR[1,2] read DMA. Transmit data written DXR[1,2]. there data XSR[1,2], value DXR[1,2] copied XSR[1,2]; otherwise, DXR[1,2] copied XSR[1,2] when last data shifted from After transmit frame synchronization, XSR[1,2] begins shifting transmit data from
2.3.1
Resetting Serial Port: (R/X)RST, RESET
serial port reset following ways: Device reset places receiver, transmitter sample rate generator reset. When device reset removed GRST FRST RRST XRST keeping entire serial port reset state. serial port transmitter receiver independently reset RRST XRST bits serial port control registers. sample rate generator reset GRST SPCR2. Table 2-11, Reset State McBSP Pins, page 2-23 shows state McBSP pins when serial port reset device reset receiver/ transmitter reset (XRST RRST FRST
2-22
Data Transmission Reception Flow
Table 2-11. Reset State McBSP Pins
McBSP Pins Direction Device Reset (RESET McBSP Reset Receiver Reset (RRST GRST CLKR CLKS I/O/Z I/O/Z I/O/Z Input Input Input Input Input Known state Input; CLKR running output Known state Input; FSRP inactive state output Input Transmitter Reset (XRST GRST CLKX CLKS I/O/Z I/O/Z Hi-Impedance Input Input Input Hi-Impedance Known state Input; CLKX running output Known state Input; FSXP inactive state output Input
Device reset McBSP reset: When McBSP reset
above ways, state machine reset initial state. This initial state includes resetting counters status bits. receive status bits include RFULL, RRDY, RSYNCERR. transmit status bits include XEMPTY, XRDY, XSYNCERR.
Device reset: When McBSP reset device reset (device
entire serial port including transmitter, receiver, sample rate generator reset. input-only pins three-state pins should known state. output-only pin, high-impedance state. Since sample rate generator also reset (GRST sample rate generator clock, CLKG, driven divide-by-2 clock, whereas frame-sync signal, FSG, generated. more information sample rate generator reset, section 2.5.1.2, Sample Rate Generator Reset Procedure, page 2-61. When device pulled reset, serial port remains reset condition ([R/X]RST FRST this condition pins used general purpose described section 2.9, McBSP Pins General Purpose I/O, page 2-96.
McBSP reset: When receive transmitter reset bits, RRST
XRST, written with zero, respective portions McBSP reset activity corresponding section serial port stops. input-only pins, such CLKS, other pins that
Multichannel Buffered Serial Port (McBSP)
2-23
Data Transmission Reception Flow
configured inputs, known state. FS(R/X) driven inactive state (same polarity FS[R/X]) output. CLK(R/X) programmed output, will driven CLKG, provided that GRST Lastly, will high-impedance state when transmitter and/or device reset. During normal operation, sample rate generator reset writing zero GRST. GRST should only when neither transmitter receiver using sample rate generator. this case, internal sample rate generator clock (CLKG) frame-sync signal (FSG) driven inactive low. When sample rate generator reset state (GRST pins inactive state when RRST XRST respectively, even they outputs driven FSG. This ensures that when only portion McBSP reset, other portion continue operation when FRST frame sync driven FSG. more information sample rate generator reset, section 2.5.1.2, Sample Rate Generator Reset Procedure, page 2-61.
Sample rate generator reset: noted earlier, sample rate generator
reset when device reset bit, GRST, written with zero. case device reset, sample rate generator clock, CLKG, driven divide-by-2 clock, whereas frame-sync pulse, FSG, driven inactive low. want reset sample rate generator when neither transmitter receiver CLKG FSG, program GRST SRGR2 zero. Here, CLKG driven inactive-low. When GRST CLKG comes running programmed SRGR1. Later, FRST driven active-high after programmed frame period (FPER number CLKG cycles elapsed. After device reset complete serial port initialization procedure follows: XRST RRST FRST SPCR[1,2]. coming device reset, this step required. Program only McBSP configuration registers (and data registers) listed Table 2-2, McBSP Registers, page 2-5, required when serial port reset state (XRST RRST FRST Wait clocks. This ensure proper synchronization internally. data acquisition required such writing DXR. XRST RRST= enable serial port. Note that value written SPCR[1,2] this time should have only reset bits changed remaining bit-fields should have same value step above.
2-24
Data Transmission Reception Flow
FRST internally generated frame sync required. Wait clocks receiver transmitter become active. Alternatively, either write (steps transmitter receiver placed taken reset individually modifying desired bit. Note that necessary duration active-low period XRST RRST least bit-clocks (CLKR/CLKX) wide. above procedure reset initialization applied general when receiver transmitter reset during normal operation, also when sample rate generator used either operation. Notes: appropriate bit-fields serial port configuration registers, SPCR[1,2], PCR, RCR[1,2], XCR[1,2], SRGR[1,2], should only modified user when affected portion serial port reset. Data Transmit Register, DXR[1,2], should loaded only when transmitter reset (XRST exception this rule during digital loop back mode described section 2.4.1, Companding Internal Data, page 2-55. multichannel selection registers, MCR, XCER[A/B], RCER[A/B], modified time long they being used current block multichannel selection. section 2.6.3.2 page 2-82 further details this case.
Example shows values control registers that reset configure transmitter while receiver running.
Multichannel Buffered Serial Port (McBSP)
2-25
Data Transmission Reception Flow
Example 2-1. Resetting Configuring Transmitter While Receiver Running
SPCR1 0x0001 SPCR2 0x0030 0x0A00 Transmitter reset, transmit interrupt (XINT CPU) generated XSYNCERR; receiver running with RINT driven RRDY. determined FSGM SRGR, transmit clock driven external source, receive clock continues driven sample rate generator. clock drives sample rate generator clock (CLKG) after divide-by-2. DXR[1,2]-to-XSR[1,2] copy generates transmit frame-sync signal. Dual-phase frame; phase eight 16-bit words; phase four 12-bit words, 1-bit data delay Transmitter taken reset
SRGR1 0x0001 SRGR2 0x2000 XCR1 0x0840 XCR2= 0x8421 SPCR2 0x0031
2.3.2
Determining Ready Status
RRDY XRDY indicate ready state McBSP receiver transmitter, respectively. Serial port writes reads synchronized polling RRDY XRDY, using events (REVT XEVT normal mode, REVTA XEVTA A-bis mode), interrupts (RINT XINT), which events generate. Note that reading DRR[1,2] writing DXR[1,2] affects RRDY XRDY.
2.3.2.1
Receive Ready Status: REVT, RINT, RRDY
RRDY indicates that RBR[1,2] contents have been copied DRR[1,2] that data read DMA. Once that data been read either DMA, RRDY cleared Also, device reset serial port receiver reset (RRST RRDY cleared indicate data been received loaded into DRR[1,2]. RRDY directly drives McBSP receive event (REVT). Also, McBSP receive interrupt (RINT) driven RRDY, RIN= SPCR1.
2.3.2.2
Transmit Ready Status: XEVT, XINT, XRDY
XRDY indicates that DXR[1,2] contents have been copied XSR[1,2] that DXR[1,2] ready loaded with data word. When transmitter transitions from reset non-reset (XRST transitions from XRDY also transitions from indicating that DXR[1,2] ready data. Once data loaded DMA, XRDY cleared However, once this data copied from DXR[1,2] XSR[1,2], XRDY transitions again from once again, write DXR[1,2] although
2-26
Data Transmission Reception Flow
XSR[1,2] been shifted yet. XRDY directly drives transmit synchronization event (XEVT XEVTA). addition, transmit interrupt (XINT) also driven XRDY, XIN= SPCR2.
2.3.3
Interrupts: (R/X)INT
receive interrupt (RINT) transmit interrupt (XINT) signals changes serial port status. Four options exist configuring these interrupts. options receive/transmit interrupt mode bit-field, (R/X)INTM, SPCR[1,2]. (R/X)INTM=00b. Interrupt every serial word tracking (R/X)RDY bits SPCR[1,2]. Sections 2.3.2.1 2.3.2.2 describe RRDY XRDY bits. (R/X)INTM=01b. Interrupt after every 16-channel block boundary multichannel selection mode) been crossed within frame. other serial transfer case, this setting applicable; therefore, interrupts generated. details, section 2.6.3.3, Update Interrupt, page 2-83. (R/X)INTM=10b. Interrupt detection frame-synchronization pulses. This generates interrupt even when transmitter/receiver reset. This done synchronizing incoming frame-sync pulse clock sending (R/X)INT. This described section 2.5.3.4, Frame Detection Initialization, page 2-68. (R/X)IN= 11b. Interrupt frame-synchronization error. Note that other interrupt modes selected, (R/X)SYNCERR read when servicing interrupts detect this condition. sections 2.3.7.2 2.3.7.5 more detail synchronization error. Note that last three options listed above applicable interrupts CPU, events DMA.
2.3.4
Frame Clock Configuration
Figure shows typical operation McBSP clock frame-sync signals. Serial clocks CLKR, CLKX define boundaries between bits receive transmit, respectively. Similarly, frame-sync signals define beginning serial word.
Multichannel Buffered Serial Port (McBSP)
2-27
Data Transmission Reception Flow
McBSP allows configuration various parameters data frame synchronization. This done independently receive transmit, which includes following items:
Polarities FSR, FSX, CLKX, CLKR choice single- dual-phase frames each phase, number words frame each phase, number bits word Subsequent frame synchronization restart serial data stream
ignored.
data delay from frame synchronization first data
2-bit delays.
Right- left-justification well sign-extension zero-filling
chosen receive data.
Figure 2-9. Frame Clock Operation
Internal CLK(R/X)
D(R/X)
2.3.4.1
Frame Clock Operation
Receive transmit frame-sync pulses generated either internally sample rate generator (see section 2.5.1, Sample Rate Generator Clocking Framing, page 2-58) driven external source. source frame sync selected programming mode bit, FS(R/X)M, PCR. also affected GSYNC SRGR2 (for details, section 2.5.3.2, Receive Frame-Sync Selection: DLB, FSRM, GSYNC, page 2-67). Similarly, receive transmit clocks selected inputs outputs programming mode bit, CLK(R/X)M, PCR. When inputs (FSXM=FSRM=0, external frame-sync pulses), McBSP detects them internal falling edge clock, internal CLKR, internal CLKX, respectively (see Figure 2-41, Clock Frame Generation, page 2-57). receive data arriving also sampled falling edge internal CLKR. Note that these internal clock signals either derived from external source CLK(R/X) pins driven sample rate generator clock (CLKG) internal McBSP.
2-28
Internal FS(R/X)
Data Transmission Reception Flow
When outputs, implying that they driven sample rate generator, they generated (transition their active state) rising edge internal clock, CLK(R/X). Similarly, data output rising edge internal CLKX. section 2.3.4.6, page 2-34, further details. FSRP, FSXP, CLKRP, CLKXP configure polarities FSR, FSX, CLKR, CLKX signals shown Table 2-6, Control Register (PCR) Bit-Field Description, page 2-12. frame-sync signals (internal FSR, internal FSX) that internal serial port active high. serial port configured external frame synchronization (FSR/FSX inputs McBSP), FSRP FSXP external active-low frame-sync signals inverted before being sent receiver (internal FSR) transmitter (internal FSX). Similarly, internal synchronization (FSR/FSX output pins GSYNC selected, internal active-high sync signals inverted, polarity FS(R/X)P before being sent FS(R/X) pin. Figure 2-41, page 2-57 shows this inversion using gates. transmit side, transmit clock polarity bit, CLKXP, sets edge used shift clock transmit data. Note that data always transmitted rising edge internal CLKX. CLKXP=1, external clocking selected (CLKXM CLKX input), external falling-edge triggered input clock CLKX inverted rising-edge triggered clock before being sent transmitter. CLKXP internal clocking selected (CLKXM CLKX output pin), internal (rising-edge triggered) clock, internal CLKX, inverted before being sent CLKX pin. Similarly, receiver reliably sample data that clocked with rising edge clock transmitter). receive clock polarity bit, CLKRP, sets edge used sample received data. Note that receive data always sampled falling edge internal CLKR. Therefore, CLKRP external clocking selected (CLKRM CLKR input pin), external rising edge triggered input clock CLKR inverted falling-edge before being sent receiver. CLKRP internal clocking selected (CLKRM internal falling edge triggered clock inverted rising edge before being sent CLKR pin. Note that CLKRP CLKXP system where same clock (internal external) used clock receiver transmitter. receiver uses opposite edge transmitter ensure valid setup hold data around this edge. Figure 2-10 shows data, clocked external serial device using rising edge, sampled McBSP receiver with falling edge same clock.
Multichannel Buffered Serial Port (McBSP)
2-29
Data Transmission Reception Flow
Figure 2-10. Receive Data Clocking
Internal CLKR Data setup Data hold
2.3.4.2
Frame-Synchronization Phases
Frame synchronization indicates beginning transfer McBSP. data stream following frame synchronization have phases, phase phase number phases selected phase bit, (R/X)PHASE, RCR2 XCR2. number words frame bits word independently selected each phase (R/X)FRLEN[1,2] (R/X)WDLEN[1,2] respectively. Figure 2-11 shows example frame where first phase consists words bits each followed second phase three words bits each. Note that entire stream frame contiguous. There gaps either between words between phases. Table 2-12 shows bit-fields receive/transmit control register (RCR[1,2]/XCR[1,2]) that control number words frame bits word each phase, both receiver transmitter. maximum number words frame single-phase frame dualphase frame. number bits word bits.
Figure 2-11.Dual-Phase Frame Example
Phase word CLK(R/X) Phase word Phase word Phase word Phase word
FS(R/X) D(R/X)
2-30
Data Transmission Reception Flow
Table 2-12. RCR[1,2]/XCR[1,2] Bit-Fields Controlling Words Frame Bits Word
Serial Port McBSP0/1 Receive Receive Transmit Transmit Frame Phase RCR[1,2]/XCR[1,2] Bit-Field Control Words Frame RFRLEN1 RFRLEN2 XFRLEN1 XFRLEN2 Bits Word RWDLEN1 RWDLEN2 XWDLEN1 XWDLEN2
2.3.4.3
Frame Length: (R/X)FRLEN[1,2]
Frame length defined number serial words (8-, 12-, 16-, 20-, 24-, 32-bit) transferred frame. length corresponds number words logical time slots channels frame-synchronization signal. 7-bit (R/X)FRLEN[1,2] field (R/X)CR[1,2] supports words frame shown Table 2-13. (R/X)PHASE represents single-phase data frame (R/X)PHASE selects dual phase data stream. Note that single-phase frame, FRLEN2 don't care. user cautioned program frame length fields with minus where represents number words frame. example Figure 2-11, (R/X)FRLEN1 0000001b, (R/X)FRLEN2 0000010b.
Table 2-13. McBSP Receive/Transmit Frame Length (1,2) Configuration
(R/X) PHASE (R/X)FRLEN1 (R/X)FRLEN2 Frame Length Single-phase frame; (n+1) words frame Dual-phase frame; (n+1) plus (m+1) words frame
2.3.4.4
Word Length: (R/X)WDLEN[1,2]
3-bit (R/X)WDLEN[1,2] fields receive/transmit control register determine word length bits-per-word receiver transmitter each phase frame, shown Table 2-12. Table 2-14 shows value these fields selects particular word lengths bits. example Figure 2-11 page 2-30, (R/X)WDLEN1 001b, (R/X)WDLEN2 000b.
Multichannel Buffered Serial Port (McBSP)
2-31
Data Transmission Reception Flow
Notes: (R/X)PHASE indicating single-phase frame, (R/X)WDLEN2 used McBSP, value don't care. specified word length larger than bits, D(X/R)R2 must written read before D(X/R)R1.
Table 2-14. McBSP Receive/Transmit Word Length Configuration
(R/X)WDLEN[1,2] McBSP Word Length (bits) reserved reserved
2.3.4.5
Data Packing Using Frame Length Word Length
frame length word length manipulated effectively pack data. example, consider situation where four 8-bit words transferred single-phase frame shown Figure 2-12. this case:
(R/X)FRLEN1 0000011b, 4-word frame (R/X)PHASE single-phase frame (R/X)FRLEN2 (R/X)WDLEN1 000b, 8-bit word
this case, four 8-bit data elements transferred from McBSP DMA. Thus, four reads from DRR1 four writes DXR1 necessary each frame.
2-32
Data Transmission Reception Flow
Figure 2-12. Single-Phase Frame Four 8-Bit Words
Word CLKR Word Word Word
CLKX
RSR1 RBR1 copy RSR1 RBR1 copy RSR1 RBR1 copy RSR1 RBR1 copy DXR1 XSR1 copy DXR1 XSR1 copy DXR1 XSR1 copy DXR1 XSR1 copy
example Figure 2-12 also treated data stream singlephase frame consisting 32-bit data word, shown Figure 2-13. this case:
(R/X)FRLEN1 1-word frame (R/X)PHASE single-phase frame (R/X)FRLEN2 (R/X)WDLEN1 101b, 32-bit word
this case, 16-bit data words transferred from McBSP DMA. Thus, reads from DRR2 DRR1 writes DXR2 DXR1 necessary each frame. This results only one-half number transfers compared previous case. This manipulation reduces percentage time required serial port data movement. Note: this case, D(X/R)R2 must written read before D(X/R)R1.
Multichannel Buffered Serial Port (McBSP)
2-33
Data Transmission Reception Flow
Figure 2-13. Single-Phase Frame 32-Bit Word
Word CLKR
CLKX
2.3.4.6
Figure 2-14. Data Delay
CLK(R/X)
FS(R/X) 0-Bit Period 1-Bit Period D(R/X) Data Delay D(R/X) Data Delay D(R/X) Data Delay
2-34
RBR1 DRR1 copy RBR2 DRR2 copy DXR1 XSR1 copy DXR2 XSR2 copy
Data Delay: (R/X)DATDLY
start frame defined first clock cycle which frame synchronization found active. beginning actual data reception transmission with respect start frame delayed required. This delay called data delay. RDATDLY XDATDLY specify data delay reception transmission, respectively. range programmable data delay zero bit-clocks ([R/X]DATDLY -10b), described Table 2-7, Receive Control Register (RCR1) Bit-Field Description, page 2-16, Table 2-8, Receive Control Register (RCR2) Bit-Field Description, page 2-17, shown Figure 2-14, Data Delay. Typically 1-bit delay selected, since data often follows one-cycle active frame-sync pulse.
2-Bit Periods
Data Transmission Reception Flow
Normally, frame-sync pulse detected sampled with respect edge serial clock internal CLK(R/X) (see section 2.3.4.1, Frame Clock Operation, page 2-28). Thus, following cycle later (depending data delay value), data received transmitted. However, case zero-bit data delay, data must ready reception and/or transmission same serial clock cycle. reception, this problem solved, since receive data sampled first falling edge CLKR where active-high internal detected. However, data transmission must begin rising edge internal CLKX clock that generated frame synchronization. Therefore, first data assumed present XSR1, thus transmitter then asynchronously detects frame synchronization, FSX, going active high, immediately starts driving first transmitted pin. Another common mode data delay two. This configuration allows serial port interface different types framing devices where data stream preceded framing bit. During reception such stream with data delay bits (framing appears after one-bit delay data appears after 2-bit delay), serial port essentially discards framing from data stream shown Figure 2-15. transmission, delaying first transfer bit, serial port essentially inserts blank period (high-impedance period) place framing bit. Here, expected that framing device inserts framing that framing generated another device. Alternatively, pull pull down achieve desired value.
Figure 2-15. Two-Bit Data Delay Used Discard Framing
CLKR
2-bit periods
2.3.4.7
Multi-Phase Frame Example: AC97
Figure 2-16 shows example Audio Codec (AC97) standard which uses dual-phase frame feature. first phase consists single 16-bit word. second phase consists twelve 20-bit words. phases configured follows:
(R/X)PHASE dual-phase frame (R/X)FRLEN1 word frame phase
Framing
Multichannel Buffered Serial Port (McBSP)
2-35
Data Transmission Reception Flow
(R/X)WDLEN1 010b, bits word phase (R/X)FRLEN2 0001011b, words frame phase (R/X)WDLEN2 011b, bits word phase CLK(R/X)P receive data sampled falling edge internal CLKR; transmit data clocked rising edge internal CLKX. FS(R/X)P active-high frame-sync signals (R/X)DATDLY 01b, data delay bit-clock
Figure 2-16. AC97 Dual-Phase Frame Format
P1W1 P2W1 P2W2 P2W3 P2W4 P2W5 P2W6 P2W7 P2W8 P2W9 P2W10 P2W11 P2W12
FS(R/X) 1-bit data delay bits bits
D(R/X)
Figure 2-17. AC97 Timing Near Frame-Synchronization Example
CLKR
1-bit data delay
P2W12B1
2-36
PxWy Phase Word
Figure 2-16 shows timing AC97 near frame synchronization. First, notice that frame-sync pulse itself overlaps first word. McBSP operation, inactive active transition frame-synchronization signal actually indicates frame synchronization. this reason, frame synchronization high arbitrary number bit-clocks. Only after frame synchronization recognized have gone inactive, then active again, next frame synchronization recognized. Also, notice that there one-bit data delay Figure 2-17. Regardless data delay, transmission occur without gaps. last previous (last) word phase immediately followed first data first word phase next data frame.
P2W12B0
P1W1B15
P1W1B14
P1W1B13
P1W1B12
PxWyBz Phase Word
Data Transmission Reception Flow
2.3.4.8
Delay Enable/Disable
Figure 2-18 Figure 2-19 show timing when DXENA enable extra delay turn-on time. This controls high-impedance (hi-Z) enable pin, data itself; only first will delayed normal mode. A-bis mode, delayed since from hi-Z valid. This should avoid conflict when tying pins together.
Figure 2-18. Enabler Normal Mode
CLKX
Note:
extra delay turn time with DXENA
Figure 2-19. Enabler A-bis mode
CLKX
Note:
extra delay turn time with DXENA
Multichannel Buffered Serial Port (McBSP)
2-37
Data Transmission Reception Flow
2.3.5
McBSP Standard Operation
During serial transfer, there typically periods serial port inactivity between packets transfers. receive transmit frame-synchronization pulse occurs every serial transfer. When McBSP reset state been configured desired operation, serial transfer initiated programming (R/X)PHASE single-phase frame with required number words programmed (R/X)FRLEN1. number words range from ([R/X]FRLEN1 0x7F). required serial word length (R/X)WDLEN1 field (R/X)CR1. dual-phase required transfer, RPHASE (R/X)FRLEN[1,2] value between 0x7F, which represents words. Figure 2-20 shows example single-phase data frame comprising 8-bit word. Since transfer configured data delay, data pins available bit-clock after FS(R/X) goes active. This figure, well others this section, make following assumptions:
(R/X)FRLEN1 word frame (R/X)PHASE single-phase frame (R/X)FRLEN2 (R/X)WDLEN2 don't care (R/X)WDLEN1 000b, 8-bit word CLK(X/R)P receive data clocked falling edge; transmit data
clocked rising edge
FS(R/X)P active-high frame-sync signals (R/X)DATDLY 01b, one-bit data delay
Figure 2-20. McBSP Standard Operation
CLK(R/X) FS(R/X)
2.3.5.1
Receive Operation
Figure 2-21 shows example serial reception. Once receive frame-synchronization (FSR) transitions active state, detected first falling edge CLKR receiver. data then shifted into receive shift register (RSR[1,2]) after appropriate data delay RDATDLY. contents RSR[1,2] copied RBR[1,2] every
2-38
D(R/X)
Data Transmission Reception Flow
word rising edge clock, provided RBR[1,2] full with previous data. Then, RBR[1,2]-to-DRR[1,2] copy activates RRDY status following falling edge CLKR. This indicates that receive data register (DRR[1,2]) ready with data read DMA. RRDY deactivated when DRR[1,2] read DMA.
Figure 2-21. Receive Operation
CLKR RRDY
RBR1 DRR1 copy(A)
Read from DRR1(A) RBR1 DRR1 copy(B)
2.3.5.2
Transmit Operation
Once transmit frame synchronization occurs, value transmit shift register, XSR[1,2], shifted driven after appropriate data delay XDATDLY. XRDY activated every DXR[1,2]-toXSR[1,2] copy following falling edge CLKX, indicating that data transmit register (DXR[1,2]) written with next data transmitted. XRDY deactivated when DXR[1,2] written DMA. Figure 2-22 shows example serial transmission. section 2.3.7.4, Transmit Empty: XEMPTY, page 2-48, transmit operation when transmitter pulled reset (XRST
Figure 2-22. Transmit Operation
CLKX
XRDY
DXR1 XSR1 copy(B)
Write DXR1(C)
DXR1 XSR1 copy(C)
2.3.5.3
Maximum Frame Frequency
frame frequency determined period between frame-synchronization signals:
Frame Frequency
Bit-Clock Frequency Number Bit-Clocks Between Frame Sync Signals
Multichannel Buffered Serial Port (McBSP)
Read from DRR1(b)
Write DXR1
2-39
Data Transmission Reception Flow
frame frequency increased decreasing time between frame-synchronization signals clocks (limited only number bits frame). frame transmit frequency increased, inactivity period between data packets adjacent transfers decreases zero. minimum time between frame synchronization number bits transferred frame. maximum frame frequency defined follows:
Maximum Frame Frequency
Bit-Clock Frequency Number Bits Frame
Figure 2-23 shows McBSP operating maximum packet frequency. maximum packet frequency, data bits consecutive packets transmitted contiguously with inactivity between bits. there one-bit data delay shown, frame-synchronization pulse overlaps last transmitted previous frame.
Figure 2-23. Maximum Frame Frequency Receive/Transmit (R/X)DATDLY
CLK(R/X) FS(R/X) D(R/X)
Effectively, this permits continuous stream data; thus, frame-synchronization pulses essentially redundant. Theoretically, only initial frame-synchronization pulse required initiate multipacket transfer. McBSP supports operation serial port this fashion ignoring successive frame-sync pulses. Data clocked receiver, clocked transmitter, every clock{. frame ignore bit, (R/X)FIG, (R/X)CR programmed ignore successive frame-sync pulses until desired frame length number words reached. This explained section 2.3.6.1, Data Packing using Frame-Sync Ignore Bits, page 2-41
2.3.6
Frame-Synchronization Ignore
McBSP configured ignore transmit receive frame-synchronization pulses. (R/X)FIG (R/X)CR2 programmed zero recognize frame-sync pulses, ignore frame-sync pulses. user (R/X)FIG either pack data ignore unexpected frame-sync pulses. Section 2.3.6.1 explains data packing McBSP operation unexpected frame-sync pulses.
(R/X)DATDLY=0, first data transmitted asynchronous internal CLKX.
2-40
Data Transmission Reception Flow
2.3.6.1
Data Packing Using Frame-Sync Ignore Bits
Section 2.3.4.5, Data Packing using Frame Length Word Length, page 2-32, describes method changing word length frame length simulate 32-bit serial word transfers, thus requiring much less bandwidth. This example works when there multiple words frame. consider case McBSP operating maximum packet frequency shown Figure 2-24. Here, each frame only single 8-bit word. This stream takes read write transfer each 8-bit word. Figure 2-25 shows McBSP configured treat this stream continuous 32-bit word. this example, (R/X)FIG ignore subsequent frames after first. Only read- write-transfers needed every bits. This configuration effectively reduces required bandwidth one-half bandwidth needed transfer four 8-bit words.
Figure 2-24. Maximum Packet Frequency Operation With 8-bit Data
Word CLKR Word Word Word
CLKX
RBR1 DRR1 copy RBR1 DRR1 copy RBR1 DRR1 copy RBR1 DRR1 copy DXR1 XSR1 copy DXR1 XSR1 copy DXR1 XSR1 copy DXR1 XSR1 copy
Multichannel Buffered Serial Port (McBSP)
2-41
Data Transmission Reception Flow
Figure 2-25. Data Packing Maximum Packet Frequency With (R/X)FIG=1
Word CLKR
CLKX
2.3.6.2
2-42
Frame ignored Frame ignored Frame ignored RBR2 DRR2 copy RBR1 DRR1 copy Frame ignored Frame ignored Frame ignored DXR2 XSR2 copy DXR1 XSR1 copy
Frame-Sync Ignore Unexpected Frame-Sync Pulses
previous section explained frame ignore bits used pack data efficiently bandwidth. (R/X)FIG also used ignore unexpected frame-sync pulses. Thus, frame-sync pulse that occurs bit-clock earlier than programmed data delay ([R/X]DATDLY) considered unexpected. Setting frame ignore bits causes serial port ignore these unexpected frame-sync signals. reception, ignored (RFIG unexpected pulse will discard contents RSR[1,2] favor incoming data. Therefore, RFIG unexpected frame-synchronization pulse aborts current data transfer, sets RSYNCERR SPCR1 begins transfer data word. further details, section 2.3.7.2, Unexpected Receive Frame Synchronization: RSYNCERR, page 2-46. When RFIG reception continues, ignoring unexpected frame-sync pulses. transmission ignored [XFIG 0]), unexpected pulse aborts present transmission, sets XSYNCERR SPCR2 re-initiates transmission current word that aborted. further details, section 2.3.7.5, Unexpected Transmit Frame Synchronization: XSYNCERR, page 2-50. When XFIG normal transmission continues with unexpected frame-sync signals ignored.
Data Transmission Reception Flow
Figure 2-26. Unexpected Frame Synchronization With (R/X)FIG=0
CLK(R/X) FS(R/X) (R/X)SYNCERR Frame sync aborts current transfer data received Current data re-transmitted
Figure 2-26 shows example wherein word interrupted unexpected frame-sync pulse when (R/X)FIG case reception, reception aborted lost), data word this example) received after appropriate data delay. This condition receive synchronization error, thus sets RSYNCERR bit. However, transmission, transmission aborted, same data retransmitted after appropriate data delay. This condition transmit synchronization error thus sets XSYNCERR bit. Synchronization errors discussed sections 2.3.7.2 2.3.7.5. contrast, Figure 2-27 shows McBSP operation when unexpected frame-synchronization signals ignored setting (R/X)FIG Here, transfer word affected unexpected frame synchronization.
Figure 2-27. Unexpected Frame Synchronization With (R/X)FIG
CLK(R/X) FS(R/X) D(R/X) (R/X)SYNCERR Frame synchronization ignored
2.3.7
Serial Port Exception Conditions
There five serial port events that constitute system error: Receive Overrun (RFULL This occurs when DRR[1,2] been read since last RBR[1,2]-to-DRR[1,2] copy. Consequently, word RBR[1,2] will transferred DRR[1,2], RSR[1,2] full with another word shifted from Therefore, RFULL indicates error condition wherein data that arrive this time will replace contents RSR[1,2], thus, previous word lost. RSR[1,2] continues overwritten long data arrives DRR[1,2] read.
Multichannel Buffered Serial Port (McBSP)
2-43
Data Transmission Reception Flow
Unexpected Receive Frame Synchronization (RSYNCERR=1). This occur during reception when RFIG unexpected framesync pulse occurs. unexpected frame-sync pulse defined that which occurs RDATDLY minus bit-clock earlier than first next associated word. This causes current data reception abort restart. data been copied into RBR[1,2] from RSR[1,2] since last RBR[1,2]-to-DRR[1,2] copy, this data RBR[1,2] will lost. This because RBR[1,2]-to-DRR[1,2] copy occurs reception been restarted. Transmit Data Overwrite. Here user overwrites data DXR[1,2] before copied XSR[1,2]. data previously DXR[1,2] never transferred since never copied XSR[1,2]. Transmit Empty (XEMPTY frame-synchronization signal arrives before data loaded into DXR[1,2], data DXR[1,2] will sent again. This will continue every frame-sync signal that arrives until DXR[1,2] loaded with data. Unexpected Transmit Frame Synchronization (XSYNCERR This occur during transmission when XFIG unexpected framesync pulse occurs. Again, unexpected frame-sync pulse defined that which occurs XDATDLY minus bit-clock earlier than first next associated word. This causes current data transmission abort restart current transfer. data been written DXR[1,2] since last DXR[1,2]-to-XSR[1,2] copy, current value XSR[1,2] will lost. These events described more detail sections that follow.
2.3.7.1
Reception With Overrun: RFULL
RFULL SPCR1 indicates that receiver experienced overrun error condition. RFULL when following conditions met: DRR[1,2] been read since last RBR[1,2]-to-DRR[1,2] transfer (RRDY RBR[1,2] full RBR[1,2]-to-DRR[1,2] copy occurred. RSR[1,2] full RSR[1,2]-to-RBR[1,2] transfer occurred.
2-44
Data Transmission Reception Flow
Data arriving continuously shifted into RSR[1,2]. Once complete word shifted into RSR[1,2], RSR[1,2]-to-RBR[1,2] transfer occur only RBR[1,2]-to-DRR[1,2] copy complete. Therefore, DRR[1,2] been read since last RBR[1,2]-to-DRR[1,2] transfer (RRDY RBR[1,2]-to-DRR[1,2] copy will take place until RRDY this time, data arriving shifted into RSR[1,2] previous contents RSR[1,2] lost. This data loss occurs because completion serial-word reception triggers RBR[1,2]-to-DRR[1,2] transfer only when RRDY Note that after receive portion starts running from reset, minimum three words must received before RFULL set. data loss contents RSR[1,2] avoided DRR[1,2] read later than one-half cycles before third word RSR[1,2]. Either following events clears RFULL allows subsequent transfers read properly:
Reading DRR[1,2] Resetting receiver (RRST device
Another frame synchronization required restart receiver. Figure 2-28 shows receive overrun condition. Because serial word read before reception serial word complete, transferred DRR1 yet. Another word arrives RSR1 full with this data. DRR1 finally read, earlier than one-half cycles before word Therefore, data overwrites previous word RSR1. RFULL still after arrival next word overwrite read time.
Figure 2-28. Serial Port Receive Overrun
CLKR RRDY RFULL RSR1 RBR1 copy(C)
RBR1 DRR1 copy(A) read from DRR1(A)
RBR1 DRR1 copy(B)
read from DRR1(A)
Multichannel Buffered Serial Port (McBSP)
2-45
Data Transmission Reception Flow
Figure 2-29 shows case where RFULL set, overrun condition averted reading contents DRR1 least one-half cycles before next serial word completely shifted into RSR1. This ensures that RBR1-to-DRR1 copy data occurs before next serial word transferred from RSR1 RBR1.
Figure 2-29. Serial Port Receive Overrun Avoided
CLKR RRDY RFULL RBR1 DRR1(B) Read from DRR1(A)
RBR1 DRR1 copy(A) read from DRR1(A)
RBR1 DRR1 copy(B)
2.3.7.2
Unexpected Receive Frame Synchronization: RSYNCERR
Figure 2-30 shows decision tree that receiver uses handle incoming frame-synchronization pulses. diagram assumes that receiver been started, RRST Unexpected frame-sync pulses originate from external source from internal sample rate generator. unexpected frame-sync pulse defined sync pulse which occurs RDATDY bit-clocks earlier than last transmitted previous frame. four cases occur:
Case Unexpected internal pulses with RFIG This case dis-
cussed section 2.3.6.2 page 2-42 shown Figure 2-27 page 2-43. Case receive frame-sync pulses ignored reception continues.
Case Normal serial port reception. There three possible reasons
receive might progress: first after RRST first after DRR[1,2] read clearing RFULL condition. serial port interpacket intervals. programmed data delay (RDATDLY) reception start during these interpacket intervals first next word received. Thus, maximum frame frequency, frame synchronization still received RDATDLY bit-clocks before first associated word. Case reception continues normally since these unexpected frame-sync pulses.
2-46
Data Transmission Reception Flow
Case Unexpected receive frame synchronization with RFIG (unex-
pected frame ignored). This case shown Figure 2-26 page 2-43 maximum frame frequency. Figure 2-31 page 2-48 shows this case during normal operation serial port, with time intervals between packets. unexpected frame-sync pulse detected when occurs before RDATDLY minus bit-clock before last previous word received pin. both cases, RSYNCERR SPCR1 set. RSYNCERR{ cleared only receiver reset user writing this SPCR1. should note that RIN= SPCR1, RSYNCERR drives receive interrupt (RINT) CPU.
Figure 2-30. Response Receive Frame-Synchronization Pulse
Unexpected frame-sync pulse
RFIG=1
Case With Frame Ignore Ignore frame pulse Receiver continues running
RSYNCERR SPCR1 read/write bit. Therefore, writing sets error condition. Typically, writing expected.
Multichannel Buffered Serial Port (McBSP)
Case Normal Reception Start receiving data Case Without Frame Ignore Abort reception RSYNCERR Start next reception immediately Previous word lost 2-47
Receive frame-sync pulse occurs
Data Transmission Reception Flow
Figure 2-31. Unexpected Receive Synchronization Pulse
CLKR RRDY RSYNCERR Unexpected frame synchronization
RBR1 DRR1(B) Read from DRR1(A) RBR1 DRR1 copy(C) Read from DRR1(C)
RBR1 DRR1 copy(A)
2.3.7.3
Transmit with Data Overwrite
Figure 2-32 depicts what happens data DXR1 overwritten before being transmitted. Initially, programmer loaded DXR1 with data subsequent write DXR1 overwrites with before copied XSR1. Thus, never transmitted avoid data overwrite polling XRDY before writing DXR1 waiting XINT programmed triggered XRDY (XIN= 00b). avoid overwriting synchronizing data transfers with XEVT.
Figure 2-32. Transmit With Data Overwrite
CLKX XRDY
Write DXR1(C) Write DXR1(D)
DXR1 XSR1 copy(D)
2.3.7.4
Transmit Empty: XEMPTY
XEMPTY indicates when transmitter experienced underflow. following conditions causes XEMPTY become active (XEMPTY During transmission. DXR[1,2] been loaded since last DXR[1,2]-to-XSR[1,2] copy, bits data word XSR[1,2] have been shifted transmitter reset (XRST device reset) then restarted. During underflow condition, transmitter continues transmit data DXR[1,2] every frame-sync signal that arrives until word loaded into DXR[1,2] DMA. XEMPTY deactivated
2-48
Write DXR1(E)
Data Transmission Reception Flow
(XEMPTY when word DXR[1,2] transferred XSR[1,2]. case internal frame generation, transmitter regenerates single internal initiated DXR[1,2]-to-XSR[1,2] copy (FSXM FSGM=0 SRGR2). Otherwise, transmitter waits next frame synchronization. When transmitter taken reset (XRST transmit ready (XRDY=1) transmit empty (XEMPTY condition. DXR[1,2] loaded before internal goes active high, valid DXR[1,2]-toXSR[1,2] transfer occurs. This allows first word first frame valid even before transmit frame-sync pulse generated detected. Alternatively, transmit frame sync detected before loaded, zeros will output Figure 2-33 depicts transmit underflow condition. After transmitted, programmer fails reload DXR[1,2] before subsequent frame synchronization. Thus, again transmitted Figure 2-34 shows case writing DXR1 just before transmit underflow condition that would otherwise occur. After transmitted, written DXR1 before next transmit frame-sync pulse occurs that successfully transmitted thus averting transmit empty condition.
Figure 2-33. Transmit Empty
CLKX XRDY XEMPTY
DXR1 XSR1 copy(B)
Write DXR1(C)
Multichannel Buffered Serial Port (McBSP)
2-49
Data Transmission Reception Flow
Figure 2-34. Transmit Empty Avoided
CLKX XRDY
DXR1 XSR1 copy
Write DXR1(C)
DXR1 XSR1 copy(C)
XEMPTY
2.3.7.5
Unexpected Transmit Frame Synchronization: XSYNCERR
Figure 2-30 page 2-47 shows decision tree that transmitter uses handle incoming frame-synchronization signals. diagram assumes that transmitter been started (XRST unexpected transmit frame-sync pulse defined sync pulse which occurs XDATDLY bit-clocks earlier than last transmit previous frame. three cases occur:
Case Unexpected pulses with XFIG This case discussed
section 2.3.6.2 page 2-42 shown Figure 2-27 page 2-43.
Case Normal serial port transmission. This case discussed section
2.3.5.2 page 2-39. should note that there possible reasons transmit might progress:
This pulse first after XRST serial port interpacket intervals. programmed data delay (XDATDLY) start during these interpacket intervals before first previous word transmitted. Thus, operating maximum packet frequency, frame synchronization still received XDATDLY bit-clocks before first associated word.
2-50
Data Transmission Reception Flow
Figure 2-35. Response Transmit Frame Synchronization
Transmit frame-sync pulse occurs
Unexpected frame-sync pulse
Case Normal Transmission Start transmit
XFIG=1
Case Without Frame Ignore Abort transfer. XSYNCERR. Restart current transfer
Case With Frame Ignore Ignore frame pulse Transmit stays running Case Unexpected transmit frame synchronization with XFIG
case subsequent frame synchronization with XFIG maximum frame frequency shown Figure 2-26. Figure 2-36 shows case normal operation serial port with interpacket intervals. both cases, XSYNCERR SPCR2 set. XSYNCERR only cleared transmitter reset user writing this SPCR2. Note that XINTM=11b SPCR2, XSYNCERR drives receive interrupt (XINT) CPU. Note: XSYNCERR SPCR2 read/write bit. Therefore, writing sets error condition. Typically, writing expected.
Multichannel Buffered Serial Port (McBSP)
2-51
Data Transmission Reception Flow
Figure 2-36. Unexpected Transmit Frame-Synchronization Pulse
CLKX XRDY Unexpected frame synchronization
DXR1 XSR1 copy(B) XSYNCERR
Write DXR1(C)
DXR1 XSR1
2.3.8
Receive Data Justification Sign-Extension: RJUST
RJUST SPCR1 selects whether data RBR[1,2] right left justified (with respect MSB) DRR[1,2]. right-justification selected, RJUST further selects whether data sign-extended zero-filled. Table 2-15 shows effect various modes RJUST have example 12-bit receive-data value 0xABC. Table 2-16 shows effect various modes RJUST have example 20-bit receive-data value 0xABCDE.
Table 2-15. RJUST Field With 12-Bit Example Data 0xABC
RJUST Justification Right Right Left Reserved Extension Zero-fill MSBs Sign-extend MSBs Zero-fill LSBs Reserved Value DRR2 0x0000 0xFFFF 0x0000 Reserved Value DRR1 0x0ABC 0xFABC 0xABC0 Reserved
Table 2-16. RJUST Field With 20-Bit Example Data 0xABCDE
RJUST Justification Right Right Left Reserved Extension Zero-fill MSBs Sign-extend MSBs Zero-fill LSBs Reserved Value DRR2 0x000A 0xFFFA 0xABCD Reserved Value DRR1 0xBCDE 0xBCDE 0xE000 Reserved
2-52
Write DXR1(D)
µ-LAW/A-LAW Companding Hardware Operation: (R/X)COMPAND
µ-LAW/A-LAW Companding Hardware Operation: (R/X)COMPAND
Companding (COMpress exPAND) hardware allows compression expansion data either µ-law A-law format. companding standard employed United States Japan µ-law. European companding standard referred A-law. specification µ-law A-law part CCITT G.711 recommendation. A-law µ-law allows bits bits dynamic range, respectively. values outside this range will most positive most negative value. Thus, companding work best, data transferred from McBSP must least 16-bit wide data. µ-law A-law formats encode data into 8-bit code words. Companded data always 8-bits wide; therefore, appropriate (R/X)WDLEN[1,2] must indicating 8-bit wide serial data stream. companding enabled either phase frame does have 8-bit word length, then companding continues word length eight bits. When companding used, transmit data encoded according specified companding law, receive data decoded complement format. Companding enabled desired format selected appropriately setting (R/X)COMPAND (R/X)CR2 shown
Table 2-7, Receive Control Register (RCR1) Bit-Field Description,
page 2-16
Table 2-8, Receive Control Register (RCR2) Bit-Field Description,
page 2-17
Table 2-9, Transmit Control Register (XCR1) Bit-Field Description,
page 2-19
Table 2-10, Transmit Control Register (XCR2) Bit-Field Description,
page 2-20 Compression occurs during process copying data from DXR1-to-XSR1 from RBR1-to-DRR1, shown Figure 2-37.
Multichannel Buffered Serial Port (McBSP)
2-53
µ-LAW/A-LAW Companding Hardware Operation: (R/X)COMPAND
Figure 2-37. Companding Flow
Expand Compress RJUST DRR1 CPU/DMA
DXR1
From CPU/DMA
transmit data compressed properly, data should left-justified when written DXR1. When using µ-law, data bits left-justified register, with remaining low-order bits filled with zeros shown Figure 2-38.
Figure 2-38. µ-Law Transmit Data Companding Format
µ-law DXR1 Value
When using A-law, data bits left-justified register, with remaining three low-order bits filled with zeros shown Figure 2-39.
Figure 2-39. A-Law Transmit Data Companding Format
A-law DXR1 Value
reception, 8-bit compressed data RBR1 expanded left-justified 16-bit data DRR1. Note that RJUST ignored when companding used.
2-54
µ-LAW/A-LAW Companding Hardware Operation: (R/X)COMPAND
2.4.1
Companding Internal Data
McBSP otherwise unused (serial port sections reset), companding hardware compand internal data. This used
Convert linear appropriate µ-law A-law format. Convert µ-law A-law linear format. Observe quantization effects companding transmitting linear
data, compressing re-expanding this data. This only useful both XCOMPAND RCOMPAND enable same companding format. Figure 2-40 shows methods which McBSP compand internal data. Data paths these methods used indicate: When both transmit receive sections serial port reset, DRR1 DXR1 internally connected through companding logic. Values from DXR1 compressed, selected XCOMPAND, then expanded, selected RCOMPAND. Note that RRDY XRDY bits set. However, data available DRR1 within four clocks after being written DXR1. advantage this method speed. disadvantage that there synchronization available control flow. Note that DRR1 DXR1 internally connected (X/R)COMPAND bits 1xb, i.e., compand using Alaw µ-law. McBSP enabled digital loop back mode with companding appropriately enabled RCOMPAND XCOMPAND. Receive transmit interrupts (RINT when RIN= XINT when XIN= synchronization events (REVT XEVT) allow synchronization these conversions, respectively. Here, time this companding depends serial rate selected.
Figure 2-40. Companding Internal Data
RSR1 (DLB) XSR1 RBR1 Compress DXR1 From CPU/DMA Expand RJUST DRR1 CPU/DMA
Multichannel Buffered Serial Port (McBSP)
2-55
µ-LAW/A-LAW Companding Hardware Operation: (R/X)COMPAND
2.4.1.1
Ordering
Normally, transfers McBSP sent received with first. However, certain 8-bit data protocols (that companded data) require transferred first. setting (R/X)COMPAND (R/X)CR2, ordering 8-bit words reversed (LSB first) before being sent serial port. Similar companding, this feature only enabled appropriate (R/X)WDLEN[1,2] indicating 8-bit words transferred serially. either phase frame does have 8-bit word length, McBSP assumes word length eight bits, LSB-first ordering done.
2-56
Programmable Clock Framing
Programmable Clock Framing
McBSP several means selecting clocking framing both receiver transmitter. Clocking framing sent both portions sample rate generator. Each portion select external clocking and/or framing independently. Figure 2-41 shows block diagram clock frame selection circuitry. features that enabled this logic explained sections that follow.
Figure 2-41. Clock Frame Generation
Clock selection
CLKXM CLKXP
Frame selection
FSXP FSXM
CLKX
Inset CLKRM CLKRP CLKXM inset Internal CLKX Internal
Inset
CLKXP
Transmit
transfer
FSXP
CLKR
Internal CLKR Internal Receive Sample rate generator
FSXM FSGM Inset
FSRP
FSRM IGSYNC
CLKRP
FSRP Inset
CLKRM CLKS
CLKG
FSRM
clock FSRG
(R/X)RST Internal
Internal either internal CLKX, internal CLKR, internal FSR, Internal
Multichannel Buffered Serial Port (McBSP)
2-57
Programmable Clock Framing
2.5.1
Sample Rate Generator Clocking Framing
sample rate generator composed three-stage clock divider that allows programmable data clocks (CLKG) framing signals (FSG) shown Figure 2-42. CLKG McBSP internal signals that programmed drive receive and/or transmit clocking (CLKR/X) framing (FSR/X). sample rate generator programmed driven internal clock source internal clock derived from external clock source. three stages sample rate generator circuit compute following:
Clock divide down (CLKGDV): number input clocks data bit-
clock.
Frame period divide down (FPER): frame period data bit-clocks. Frame width count down (FWID): width active frame pulse
data bit-clocks. addition, frame pulse detection clock synchronization module allows synchronization clock divide down with incoming frame pulse. operation sample rate generator during device reset described section 2.3.1, Resetting Serial Port: (R/X)RST, RESET, page 2-22.
Figure 2-42. Sample Rate Generator
CLKGDV FPER FWID
clock CLKS CLKSP
CLKSRG
Frame Pulse
CLKSM
CLKG
GSYNC
Frame pulse detection clock synchronization
2-58
Programmable Clock Framing
2.5.1.1
Sample Rate Generator Register (SRGR [1,2])
Sample rate generator registers (SRGR[1,2]) control operation various features sample rate generator. These registers their bitfield descriptions shown Figure 2-43 Table 2-17, Figure 2-44 Table 2-18, respectively. sections that follow these figures tables describe configure operation SRGR using SRGR[1,2] bit-fields.
Figure 2-43. Sample Rate Generator Register (SRGR1)
FWID RW,+0
Note: Read, Write, Value reset
CLKGDV
Table 2-17. Sample Rate Generator Register (SRGR1) Bit-Field Descriptions
15-8 Name FWID Function Frame Width. This field plus determines width frame-sync pulse, FSG, during active period. Range: CLKG periods. CLKGDV Sample Rate Generator Clock Divider This value used divide-down number generate required sample rate generator clock frequency. Default value 2.5.2.2 Section 2.5.3.1
Multichannel Buffered Serial Port (McBSP)
2-59
Programmable Clock Framing
Figure 2-44. Sample Rate Generator Register (SRGR2)
GSYNC RW,+0
Note:
CLKSP RW,+0
CLKSM
FSGM RW,+0
FPER RW,+0
Read, Write, Value reset
Table 2-18. Sample Rate Generator Register (SRGR2) Bit-Field Descriptions
Name GSYNC Function Sample Rate Generator Clock Synchronization Only used when external clock (CLKS) drives sample rate generator clock (CLKSM=0). GSYNC GSYNC sample rate generator clock (CLKG) free running. sample rate generator clock (CLKG) running. CLKG resynchronized frame-sync signal (FSG) generated only after detecting receive frame-synchronization signal (FSR). Also, frame period, FPER, don't care because period dictated external frame-sync pulse. 2.5.2.3 Section 2.5.2.4
CLKSP
CLKS Polarity Clock Edge Select Only used when external clock CLKS drives sample rate generator clock (CLKSM CLKSP CLKSP Rising edge CLKS generates CLKG FSG. Falling edge CLKS generates CLKG FSG.
CLKSM
McBSP Sample Rate Generator Clock Mode CLKSM CLKSM Sample rate generator clock derived from CLKS pin. Sample rate generator clock derived from clock.
2.5.2.2
2-60
Programmable Clock Framing
Table 2-18. Sample Rate Generator Register (SRGR2) Bit-Field Descriptions (Continued)
Name FSGM Function Sample Rate Generator Transmit Frame-Synchronization Mode Used when FSXM=1 PCR. FSGM Transmit frame-sync signal (FSX) DXR[1,2]-to-XSR[1,2] copy. When FSGM FWID ignored. Transmit frame-sync signal driven sample rate generator frame-sync signal, FSG. 2.5.3.1 Section 2.5.3.3
FSGM 11-0 FPER
Frame Period. This field plus determines when next frame-sync signal becomes active. Range: 4096 CLKG periods.
2.5.1.2
Sample Rate Generator Reset Procedure
sample rate generator reset initialization procedure follows: During device reset, GRST Otherwise, during normal operation, sample rate generator reset with GR
Other recent searches
SP1590 - SP1590 SP1590 Datasheet
SN74ALVCH16270 - SN74ALVCH16270 SN74ALVCH16270 Datasheet
MM1381 - MM1381 MM1381 Datasheet
MAX1811 - MAX1811 MAX1811 Datasheet
ISL28194 - ISL28194 ISL28194 Datasheet
ISL28195 - ISL28195 ISL28195 Datasheet
APT64GA90B - APT64GA90B APT64GA90B Datasheet
APT64GA90S - APT64GA90S APT64GA90S Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
