Addendum TMS320C54x User's Guide User's Guide 1995 Digi
|
|
|
Top Searches for this datasheet
TMS320C54x Serial Ports
Addendum TMS320C54x User's Guide
User's Guide
1995
Digital Signal Processing Products
Printed U.S.A., December 1995 D425005-9741 revision
SPRU156
TMS320C54x Serial Ports User's Guide
Addendum TMS320C54x User's Guide
SPRU156 December 1995
Printed Recycled Paper
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1995, Texas Instruments Incorporated
Preface
Read This First
TMS320C54x fixed-point digital signal processor (DSP) TMS320 family. purpose this addendum TMS320C54x User's Guide serve reference TMS320C54x serial ports. Throughout this book, references 'C54x apply TMS320C54x, well TMS320LC54x TMS320VC54x, unless otherwise specified.
This User's Guide
following table summarizes 'C54x information contained this addendum:
looking information about: Buffered serial port 'C203 Serial Ports
Turn these sections: Section 1.2, Buffered Serial Port Section 1.2, Buffered Serial Port Section 1.3, Time-Division-Multiplexed (TDM) Serial Port
'C209 Serial Ports Synchronous serial port serial port
Section 1.1, Synchronous Serial Port Section 1.1, Synchronous Serial Port Section 1.3, Time-Division-Multiplexed (TDM) Serial Port
Read This First
Related Documentation
Related Documentation
following books describe 'C54x related support tools. obtain copy these documents, call Texas Instruments Literature Response Center (800) 477-8924. When ordering, please identify book title literature number.
TMS320C54x User's Guide (literature number SPRU131) describes TMS320C54x 16-bit, fixed-point, general-purpose digital signal processors. describes architecture, memory organization, program control, instruction set, pipeline, on-chip peripherals. Software hardware applications covered dedicated chapters. TMS320C54x Optimizing Compiler User's Guide (literature number SPRU103) describes 'C54x compiler. This compiler accepts ANSI standard source code produces TMS320 assembly language source code 'C54x generation devices. TMS320C5xx Source Debugger User's Guide (literature number SPRU099) tells invoke 'C54x emulator, EVM, simulator versions source debugger interface. This book discusses various aspects debugger interface, including window management, command entry, code execution, data management, breakpoints. also includes tutorial that introduces basic debugger functionality. TMS320C54x Assembly Language Tools User's Guide (literature number SPRU102) describes assembly language tools (assembler, linker, other tools used develop assembly language code), assembler directives, macros, common object file format, symbolic debugging directives 'C54x generation devices. TMS320 Third-Party Support Reference Guide (literature number SPRU052) alphabetically lists over third parties that provide various products that serve family '320 digital signal processors. myriad products applications offered-software hardware development tools, speech recognition, image processing, noise cancellation, modems, etc. TMS320 Family Development Support Reference Guide (literature number SPRU011) describes '320 family digital signal processors covers various products that support this product line. This includes code-generation tools (compilers, assemblers, linkers, etc.) system integration debug tools (simulators, emulators, evaluation modules, etc.). Also covered available documentation, seminars, university program, factory repair exchange.
Style Symbol Conventions
Style Symbol Conventions
This document uses following conventions.
Program listings program examples shown special typeface similar typewriter's typeface. Here segment program listing:
RSBX A,*AR1+ INMAIN_PG ;Int_RAM(I)=0 ;Globally enable interrupts ;Return foreground program
syntax descriptions, instruction bold typeface font parameters italic typeface. Portions syntax bold should entered shown; portions syntax italics describe type information that specify. Here example instruction syntax: [label] Xmem, Ymem instruction, which parameters indicated Xmem, Ymem. When LMS, parameters should actual dual datamemory operand values. comma space must separate values.
assembly language instructions, when word "or" capitalized, denotes boolean operation. When lowercased indicates selection. Here example instruction with (src)
[,dst]
This instruction value with contents src. Then, stores result depending syntax instruction.
Square brackets identify optional parameter. optional parameter, specify information within brackets; type brackets themselves. example above, instead typing [label], specify name label. When specify more than optional parameter from list, separate them with comma space.
Read This First
Technical Articles
Technical Articles
wide variety related documentation available digital signal processing. These references fall into following application categories:
General-Purpose Graphics/Imagery Speech/Voice Control Multimedia Military Telecommunications Automotive Consumer Medical Development Support
following list, references appear alphabetical order according author. documents contain beneficial information regarding designs, operations, applications signal-processing systems; documents provide additional references. Texas Instruments strongly suggests that refer these publications.
General-Purpose DSP:
Chassaing, Horning, D.W., "Digital Signal Processing with Fixed Floating-Point Processors" CoED, USA, Volume Number pages 1-4, March 1991. Defatta, David Joseph Lucas, William Hodgkiss, Digital Signal Processing: System Design Approach, York: John Wiley, 1988. Erskine, Magar, "Architecture Applications SecondGeneration Digital Signal Processor," Proceedings IEEE International Conference Acoustics, Speech, Signal Processing, USA, 1985. Essig, Erskine, Caudel, Magar, Second-Generation Digital Signal Processor," IEEE Journal Solid-State Circuits, USA, Volume SC-21, Number pages 86-91, February 1986. Frantz, Lin, Reimer, Bradley, "The Texas Instruments TMS320C25 Digital Signal Microcomputer," IEEE Microelectronics, USA, Volume Number pages 10-28, December 1986. Gass, Tarrant, Richard, Pawate, Gammel, Rajasekaran, Wiggins, Covington, "Multiple Digital Signal Processor Environment Intelligent Signal Processing," Proceedings IEEE, USA, Volume Number pages 1246-1259, September 1987.
Technical Articles
Jackson, Leland Digital Filters Signal Processing, Hingham, Kluwer Academic Publishers, 1986. Jones, D.L., T.W. Parks, Digital Signal Processing Laboratory Using TMS32010, Englewood Cliffs, Prentice-Hall, Inc., 1987. Lim, Jae, Alan Oppenheim, Advanced Topics Signal Processing, Englewood Cliffs, Prentice- Hall, Inc., 1988. Lin, Frantz, Simar, Jr., "The TMS320 Family Digital Signal Processors," Proceedings IEEE, USA, Volume Number pages 1143-1159, September 1987. Lovrich, Reimer, Advanced Audio Signal Processor" Digest Technical Papers 1991 International Conference Consumer Electronics, June 1991. Magar, Essig, Caudel, Marshall Peters, NMOS Digital Signal Processor with Multiprocessing Capability," Digest IEEE International Solid-State Circuits Conference, USA, February 1985. Oppenheim, Alan R.W. Schafer, Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975 1988. Papamichalis, P.E., C.S. Burrus, "Conversion Digit-Reversed BitReversed Order Algorithms," Proceedings ICASSP USA, pages 984-987, 1989. Papamichalis, Simar, Jr., "The TMS320C30 Floating-Point Digital Signal Processor," IEEE Micro Magazine, USA, pages 13-29, December 1988. Papamichalis, P.E., "FFT Implementation TMS320C30," Proceedings ICASSP USA, Volume page 1399, April 1988. Parks, T.W., C.S. Burrus, Digital Filter Design, York, John Wiley Sons, Inc., 1987. Peterson, Zervakis, Shehadeh, "Adaptive Filter Design Implementation Using TMS320C25 Microprocessor" Computers Education Journal, USA, Volume Number pages 12-16, July-September 1993. Prado, Alcantara, Fast Square-Rooting Algorithm Using Digital Signal Processor," Proceedings IEEE, USA, Volume Number pages 262-264, February 1987. Rabiner, L.R. Gold, Theory Applications Digital Signal Processing, Englewood Cliffs, Prentice-Hall, Inc., 1975.
Read This First
Technical Articles
Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors," Proceedings ICASSP USA, Volume page 1678, April 1988. Simar, Jr., Leigh, Koeppen, Leach, Potts, Blalock, MFLOPS Digital Signal Processor: First Supercomputer Chip," Proceedings ICASSP USA, Catalog Number 87CH2396 Volume pages 535-538, April 1987. Simar, Jr., Reimer, "The TMS320C25: CMOS VLSI Digital Signal Processor," 1986 Workshop Applications Signal Processing Audio Acoustics, September 1986. Texas Instruments, Digital Signal Processing Applications with TMS320 Family, 1986; Englewood Cliffs, Prentice-Hall, Inc., 1987. Treichler, J.R., C.R. Johnson, Jr., M.G. Larimore, Practical Guide Adaptive Filter Design, York, John Wiley Sons, Inc., 1987.
Graphics/Imagery:
Reimer, Lovrich, "Graphics with TMS32020," WESCON/85 Conference Record, USA, 1985.
Speech/Voice:
DellaMorte, Papamichalis, "Full-Duplex Real-Time Implementation FED-STD-1015 LPC-10e Standard V.52 TMS320C25," Proceedings SPEECH TECH pages 218-221, 1989. Gray, A.H., J.D. Markel, Linear Prediction Speech, York, Springer-Verlag, 1976. Frantz, G.A., K.S. Lin, Low-Cost Speech System Using TMS320C17," Proceedings SPEECH TECH '87, pages 25-29, April 1987. Papamichalis, Lively, "Implementation Standard LPC-10/52E TMS320C25," Proceedings SPEECH TECH '87, pages 201-204, April 1987. Papamichalis, Panos, Practical Approaches Speech Coding, Englewood Cliffs, Prentice-Hall, Inc., 1987. Pawate, B.I., G.R. Doddington, "Implementation Hidden Markov Model-Based Layered Grammar Recognizer," Proceedings ICASSP USA, pages 801- 804, 1989.
viii
Technical Articles
Rabiner, L.R., R.W. Schafer, Digital Processing Speech Signals, Englewood Cliffs, Prentice-Hall, Inc., 1978. Reimer, J.B. K.S. Lin, "TMS320 Digital Signal Processors Speech Applications," Proceedings SPEECH TECH '88, April 1988. Reimer, J.B., M.L. McMahan, W.W. Anderson, "Speech Recognition Low-Cost System Using DSP," Digest Technical Papers 1987 International Conference Consumer Electronics, June 1987.
Control:
Ahmed, "16-Bit Microcontroller Fits Motion Control System Application," PCIM, October 1988. Ahmed, "Implementation Self Tuning Regulators with TMS320 Family Digital Signal Processors," MOTORCON '88, pages 248-262, September 1988. Allen, Pillay, "TMS320 Design Vector Current Control Motor Drives" Electronics Letters, Volume Number pages 2188-2190, November 1992. Panahi, Restle, "DSPs Redefine Motion Control" Motion Control Magazine, December 1993. Lovrich, Troullinos, Chirayil, All-Digital Automatic Gain Control," Proceedings ICASSP USA, Volume page 1734, April 1988. Ahmed, Meshkat, "Using DSPs Control," Control Engineering, February 1988. Meshkat, Ahmed, "Using DSPs Induction Motor Drives," Control Engineering, February 1988. Matsui, Shigyo, "Brushless Motor Control Without Position Speed Sensors" IEEE Transactions Industry Applications, USA, Volume Number Part pages 120-127, January-February 1992. Hanselman, "LQG-Control Highly Resonant Disc Drive Head Positioning Actuator," IEEE Transactions Industrial Electronics, USA, Volume Number pages 100-104, February 1988. Bose, B.K., P.M. Szczesny, Microcomputer-Based Control Simulation Advanced Synchronous Machine Drive System Electric Vehicle Propulsion," Proceedings IECON '87, Volume pages 454-463, November 1987.
Read This First
Technical Articles
Ahmed, Lindquist, "Digital Signal Processors: Simplifying HighPerformance Control," Machine Design, September 1987.
Multimedia:
Reimer, "DSP-Based Multimedia Solutions Lead Enhancing Audio Compression Performance" Dobbs Journal, December 1993. Reimer, Benbassat, Bonneau Jr., "Application Processors: Making Multimedia Happen" Silicon Valley Design Conference, July 1991.
Military:
Papamichalis, Reimer, "Implementation Data Encryption Standard Using TMS32010," Digital Signal Processing Applications, 1986.
Telecommunications:
Ahmed, Lovrich, "Adaptive Line Enhancer Using TMS320C25," Conference Records Northcon/86, USA, 14/3/1-10, September/October 1986. Casale, Russo, Bellina, "Optimal Architectural Solution Using Processors Implementation ADPCM Transcoder," Proceedings GLOBECOM '89, pages 1267-1273, November 1989. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller SINGLE TMS32020," Proceedings ICASSP USA, Catalog Number 86CH2243-4, Volume pages 429-432, April 1986. Cole, Haoui, Winship, High-Performance Digital Voice Echo Canceller Single TMS32020," Proceedings IEEE International Conference Acoustics, Speech Signal Processing, USA, 1986. Lovrich, Reimer, Multi-Rate Transcoder," Transactions Consumer Electronics, USA, November 1989. Lovrich, Reimer, Multi-Rate Transcoder" Digest Technical Papers 1989 International Conference Consumer Electronics, June 7-9, 1989. Hedberg, Fraenkel, "Implementation High-Speed Voiceband Data Modems Using TMS320C25," Proceedings ICASSP USA, Catalog Number 87CH2396-0, Volume pages 1915-1918, April 1987.
Technical Articles
Mock, "Add DTMF Generation Decoding DSP- Designs," Electronic Design, USA, Volume Number pages 205-213, March 1985. Reimer, McMahan, Arjmand, "ADPCM TMS320 Chip," Proceedings SPEECH TECH pages 246-249, April 1985. Troullinos, Bradley, "Split-Band Modem Implementation Using TMS32010 Digital Signal Processor," Conference Records Electro/86 Mini/Micro Northeast, USA, 14/1/1-21, 1986.
Automotive:
Lin, "Trends Digital Signal Processing Automotive," International Congress Transportation Electronic (CONVERGENCE '88), October 1988.
Consumer:
Frantz, G.A., J.B. Reimer, R.A. Wotiz, "Julie, Application Product," Speech Tech Magazine, USA, September 1988. Reimer, J.B., G.A. Frantz, "Customization Integrated Circuit Customer Product," Transactions Consumer Electronics, USA, August 1988. Reimer, J.B., P.E. Nixon, E.B. Boles, G.A. Frantz, "Audio Customization IC," Digest Technical Papers 1988 International Conference Consumer Electronics, June 8-10 1988.
Medical:
Knapp Townshend, Real-Time Digital Signal Processing System Auditory Prosthesis," Proceedings ICASSP USA, Volume page 2493, April 1988. Morris, L.R., P.B. Barszczewski, "Design Evolution PocketSized Speech Processing System Cochlear Implant Other Hearing Prosthesis Applications," Proceedings ICASSP USA, Volume page 2516, April 1988.
Development Support:
Mersereau, Schafer, Barnwell, Smith, Digital Filter Design Package TMS320," MIDCON/84 Electronic Show Convention, USA, 1984. Simar, Jr., Davis, "The Application High-Level Languages Single-Chip Digital Signal Processors," Proceedings ICASSP USA, Volume pages 1678-1681, April 1988.
Read This First
Need Assistance
Need Assistance.
want Order Texas Instruments documentation Obtain technical support, report suspected problems this. Call Literature Response Center: (800) 477-8924 Call hotline: (713) 274-2320 send FAX: (713) 274-2324 +33-1-3070-1032 (Europe) send email 4389750@mcimail.com. Obtain product updates, application software Dial TMS320 Bulletin Board Service (BBS): (713) 274-2323 hrs.) +44-2-3422-3248 (Europe) your modem bits,1 stop bit, parity. Supported speeds from 14400 bps. Connect anonymous ftp.ti.com (192.94.94.5), subdirectory /pub/mirrors Fill return reader response card this book send your comments Texas Instruments Incorporated Technical Publications Manager, P.O. 1443 Houston, Texas 77251-1443 send email comments@books.sc.ti.com
Access TMS320 from Internet Report mistakes offer suggestions regarding this document other documentation
Running Title-Attribute Reference
Contents
Serial Ports Synchronous Serial Port 1.1.1 Serial Port Operation 1.1.2 Transmit Receive Operations (Burst Mode) 1.1.3 Transmit Receive Operations (Continuous Mode) 1-13 1.1.4 Error Conditions 1-15 1.1.5 Example 1-19 Buffered Serial Port (BSP) 1-21 1.2.1 Configuration 'C542 1-22 1.2.2 Serial Port Interface (SPI) Operation 1-24 1.2.3 Autobuffering Unit (ABU) 1-53 1.2.4 Initialization Operation 1-61 1.2.5 Operation During IDLE2 1-66 Time-Division-Multiplexed (TDM) Serial Port 1-70 1.3.1 Basic Operation 1-70 1.3.2 Serial Port Interface Operation 1-71 1.3.3 Mode Transmit Receive Operations 1-74 1.3.4 Serial Port Interface Error Conditions 1-76 1.3.5 Serial Port Interface Operation 1-77
xiii
Running Title-Attribute Reference
Figures
1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-17 1-18 1-19 1-20 1-21 1-22 1-23 1-24 1-25 1-26 1-27 1-28 1-29 1-30 1-31 1-32 1-33 1-34 One-Way Serial Port Transfer Serial Port Block Diagram Serial Port Control Register Receiver Signal MUXes Burst-Mode Serial Port Transmit Operation 1-10 Burst-Mode Serial Port Receive Operation 1-11 Burst-Mode Serial Port Transmit Maximum Packet Frequency 1-12 Burst-Mode Serial Port Receive Maximum Packet Frequency 1-12 Burst-Mode Serial Transmit Operation With Delayed Frame Sync 1-13 External Frame Sync Mode Serial Port Transmit Continuous Operation 1-14 Serial Port Receive Continuous Operation 1-15 Receive Error (Normal Burst Mode) 1-16 Transmit Error (Normal Burst Mode) 1-16 Receive Error (Continuous Mode) 1-18 Transmit Error (Continuous Mode) 1-18 Buffered Serial Port Block Diagram Registers 1-23 Half-Duplex Communication Between TMS320C54Xs 1-24 Module Block Diagram 1-24 Register 1-25 SPCE Register 1-28 Receiver Signal Multiplexers Digital Loop Back 1-29 Filling Process 1-30 Transmit Process Burst Mode With External Frame (FSM=1 TXM=0) 1-33 Short Pulse 1-34 Long Pulse 1-34 Transmit Burst Mode With External Frame Continuous Operation 1-35 Transmit Burst Mode With External Frame (Transmit Aborts-Format Bits) 1-35 Transmit Burst Mode With External Frame-XSREMPTY Activation 1-36 (Format Bits) Transmit Burst Mode With External Frame-XSREMPTY Deactivation 1-36 Transmit Process Burst Mode With Internal Frame (FSM=1 TXM=1) 1-37 Transmit Burst Mode Internal Frame(Format Bits) 1-38 Transmit Process Continuous Mode With External Frame 1-39 (FSM=0 TXM=0) Transmit Continuous Mode With External Frame (Format Bits) 1-40 Transmit Continuous Mode With External Frame Transmission Stop 1-40 (Format Bits)
Figures
1-35 1-36 1-37 1-38 1-39 1-40 1-41 1-42 1-43 1-44 1-45 1-46 1-47 1-48 1-49 1-50 1-51 1-52 1-53 1-54 1-55 1-56 1-57 1-58 1-59 1-60 1-61
Transmit Continuous Mode With External Frame (Format 16-bits) Transmit Continuous Mode With Internal Frame(FSM=0 TXM=1) Transmit Continuous Mode With Internal Frame (Format Bits) Emptying Process Receive Burst Mode (FSM=1 Short Pulse Long Pulse Receive Burst Mode-Continuous Reception (Format Bits) Receive Burst Mode With Reception Aborts Receive Burst Mode-RSRFULL Activation (Format Bits) Receive Burst Mode-RSRFULL Deactivation Receive Continuous Mode (FSM=0) Receive Continuous Mode (Format Bits) Receive Continuous Mode-Stop (Format Bits) Receive Continuous Mode With FIG=1 (Frame Ignore, Format 16-Bits) Block Diagram ABUC Register Circular Addressing Registers Transmit Buffer Receive Buffer Mapping Autobuffering Process Transmit Autobuffering Process Receive Pulse Occurs During Synchronization Window Pulse Occurs During Synchronization Window Time-Division Multiplexing Four-Wire Port Registers Serial Port Timing Mode
1-41 1-42 1-43 1-44 1-46 1-47 1-47 1-48 1-49 1-49 1-50 1-51 1-52 1-52 1-53 1-55 1-55 1-58 1-59 1-60 1-61 1-63 1-63 1-70 1-71 1-72 1-75
Contents
Running Title-Attribute Reference
Tables
Serial Port Registers Serial Port Control Register Bits Summary Register Bits Summary 1-26 SPCE Register Bits Summary 1-28 Transmit Flowcharts Signals Registers 1-31 Receive Flowcharts Signals Registers 1-44 ABUC Register 1-56 Interprocessor Communications Scenario 1-77 Register Contents 1-78
Examples
1-10 One-Way Transmit Operation From Device Device 1-Transmit Side One-Way Transmit Operation From Device Device 1-Receive Side Transmit Burst Mode With External Frame (External Clock Format bits; Polarities=0; Mode Off) Transmit Continuous Mode With Internal Frame (Internal Clock 1/16 CLKOUT Frequency; Polarities Format= Bits; Mode Off) Receive Burst Mode (Format= Bits; Polarities=1) Receive Continuous Mode (Polarities Format= Bits; Frame Ignore Set) Transmit Burst Mode With External Frame, External Clock Format=10 bits, Polarities=0, Mode Receive Continuous Mode Polarities Format= Bits, Frame Ignore Set, Receive Autobuffering Enabled One-Way Transmit Operation from Device Device 1-Transmit Side One-Way Transmit Operation from Device Device 1-Receive Side 1-19 1-20 1-64 1-65 1-65 1-65 1-66 1-66 1-79 1-80
Chapter
Serial Ports
This chapter describes serial port interfaces available 'C54x: synchronous serial port, buffered serial port (BSP), time-division-multiplexed (TDM) serial port. 'C54x devices contain combination serial port interfaces:
'C541 devices contain synchronous serial ports. 'C542 'C543 devices contain buffered serial port serial port.
Topic
Page
Synchronous Serial Port Buffered Serial Port (BSP) 1-21 Time-Division-Multiplexed (TDM) Serial Port 1-68
Synchronous Serial Port
Synchronous Serial Port
full duplex (bidirectional) on-chip serial port provides direct communication with serial devices such codecs, serial (analog-to-digital) converters, other serial systems. serial port also used intercommunication between processors multi-processor systems. Both receive transmit operations double-buffered 'C54x, thus allowing continuous communication stream (either 16-bit data packets). continuous mode provides operation that once initiated requires further frame synchronization pulses when transmitting maximum packet frequency. serial port fully static thus functions arbitrarily clocking frequencies. maximum operating frequency serial port while using internal clocks CLKOUT1/4 Mbps 50ns, 12.5 Mbps 20ns). When serial ports reset device configured shut serial port internal clocks, allowing device lower power mode operation.
1.1.1
Serial Port Operation
Three signals necessary connect devices data transmission. transmitting device, transmit data signal (DX) sends data, transmit frame synchronization signal (FSX) initiates transfer beginning packet, transmit clock signal (CLKX) clocks transfer. corresponding pins receiving device CLKR, respectively. Figure shows these pins 'C54x serial ports connected one-way transfer from device device reset, CLKX, CLKR, FSX, become inputs highimpedance.
Figure 1-1. One-Way Serial Port Transfer
'C54x CLKX
Legend: CLKX Transmit data Transmit frame synchronization Transmit clock CRKR
'C54x CLKR
Receive data Receive frame synchronization Receive clock
serial port operates through three memory-mapped registers: serial port control register (SPC), data transmit register (DXR), data receive register (DRR). Additionally, port uses unmapped registers that permit double-buffering capability: transmit shift register (XSR) receive shift register (RSR).
Synchronous Serial Port
Table 1-1. Serial Port Registers
Figure 1-2. Serial Port Block Diagram
Data (Load) Load Control Logic (16) (Load) Load Control Logic (16) (Clear) Byte/Word Counter (Clock) CLKR (Clear) (Clock) CLKX Byte/Word Counter (16) XINT DXR-XSR Transfer
(16) RINT RSR-DRR Transfer
Registers Description Serial port control register Data transmit register Data receive register Transmit shift register Receive shift register
Figure shows pins registers configured serial port double buffering implemented.
controls serial port operation; functions fields described Figure 1-2. Transmit data written DXR, while received data read from DRR. transmit executed writing data DXR, which copies data when empty (the last word been serially transmitted, that driven pin). manages shifting data pin, thus allowing another write soon DXR-to-XSR copy completed.
Serial Ports
Synchronous Serial Port
Upon completion DXR-to-XSR copy, 0-to-1 transition occurs transmit ready XRDY generates serial port transmit interrupt that signals that ready word. process similar receive side. Data from shifted into RSR, which copies data receive register (DRR) from which read. Upon completion RSR-to-DRR copy, 0-to-1 transition occurs receive ready (RRDY) generates serial port receive interrupt (RINT). Thus, serial port double-buffered because data transferred from while another transmit receive being performed. Note that transfer timing synchronized frame sync pulse burst mode discussed more detail subsection 1.1.2. Figure shows 16-bit memory-mapped register that configures serial port. Some bits read-only while others read/write.
Figure 1-3. Serial Port Control Register
FREE SOFT RSRFULL XSREMPTY XRDY RRDY RRST XRST
Table 1-2. Serial Port Control Register Bits Summary
Name Function Reserved Always read digital loopback mode used serial port digital loopback mode. When DLB=1, connected FSX, respectively, through multiplexers, shown Figure 1-4. Additionally, CLKR driven CLKX MCM=1. DLB=1 MCM=0, CLKR taken from CLKR device. This configuration allows CLKX CLKR tied together externally supplied common external clock source. DBL=0, FSR, CLKR taken from respective device pins. Note that must proper operation mode. Note also that signals appear device pins when DLB=1, not. format specifies word length serial port transmitter receiver. FO=0, data transmitted and/or received 16-bit words. FO=1, data transferred 8-bit bytes. data transferred with first. frame synch mode specifies whether frame synchronization pulses required serial port operation. FSM=1, frame sync pulse required FSX/FSR transmission/reception each word. When serial port operated continuous mode, FSM=0. Refer subsection 1.1.2 more details frame sync signals. clock mode specifies clock source CLKX. MCM=0, CLKX taken from CLKX pin. MCM=1, CLKX driven on-chip clock source having frequency equal one-fourth CLKOUT. Note that MCM=1 DLB=1, CLKR signal also supplied internal source.
Note:
R=Read, W=Write
Synchronous Serial Port
Table 1-2. Serial Port Control Register Bits Summary (Continued)
Name Function transmit mode configures input (TXM=0) output (TXM=1). When TXM=1, frame sync pulses generated internally when data transferred from initiate data transfers. internally generated framing signal synchronous with respect CLKX. When TXM=0, transmitter idles until frame synch pulse supplied pin. XRST RRST transmit reset receive reset signals reset transmitter receiver, respectively. modified reconfigure serial port, total writes should made SPC. first write should write XRST RRST desired configuration bits 1-5. second write should write XRST RRST, taking serial port reset. When written either these bits, activity corresponding section serial port halts. Note that when XRDY=0, writing XRST generates transmit interrupt. When XRST=0,RRST=0, MCM=0, internal clocks serial ports shut off, allowing device lower power mode operation. input input allow CLKR CLKX pins used inputs. reflect current levels CLKR CLKX pins, respectively, device. levels these pins read through SPC. They tested using BIT, BITF, BITT instruction. Note that there latency between CLKOUT cycles length from CLKR/CLKX switching CLKR/CLKX value being represented SPC. Receive ready transmit ready bits. transition from RRDY indicates that receive shift register (RSR) been copied that data read. receive interrupt generated upon transition. transition from XRDY indicates that contents have been copied that data ready loaded with data word. transmit interrupt generated upon transition. These bits polled software lieu using serial port interrupts. transmit shift register empty flag. This indicates whether transmitter experienced underflow. Underflow occurs when conditions satisfied: empties, been reloaded since last DXR-to-XSR transfer. Note that underflow does constitute error condition burst mode. another frame synch pulse occurs before writing DXR, while burst mode, previous data shifted pin. Writing inactivates XSREMPTY indicates underflow. RRDY XRDY XSREMPTY RSRFUL receive shift register full flag. This indicates whether receive experienced overrun. Overrun occurs when three conditions satisfied: full, been read since last RSR-to-DRR transfer, frame sync pulse appears FSR. Note that condition applies only when FSM=1. When FSM=0, only first conditions apply. When RSRFUL=1, receiver halts waits read. data preserved, data sent while receiver halted, lost. Reading DRR, device reset, serial port reset each clear RSRFUL bit. RSRFUL=1 indicates overflow.
Serial Ports
Synchronous Serial Port
Table 1-2. Serial Port Control Register Bits Summary (Continued)
Name SOFT Function soft bit. This enabled when FREE FREE=0, SOFT selects immediate stop, stop after word completion SOFT=0 upon reset. FREE free bit. FREE=1, free selected, regardless value SOFT bit. FREE=0, SOFT selects emulation mode described above. FREE=0 upon reset.
reserved read format SPC, specifies whether data transmitted 16-bit words (FO=0) 8-bit bytes (FO=1). Note that latter case, only lower byte whatever written transmitter transmitted lower byte whatever read from receiver received. transmit whole 16-bit word b-bit byte mode transmitter, writes necessary, with appropriate shifts value because upper bits written ignored. Similarly, receive whole 16-bit word 8-bit mode receiver, reads from necessary, with appropriate shifts value, because upper bits random values. source device clock serial port transfers (MCM) register. MCM=1 then CLKX configured output driven internal clock source with frequency equal CLKOUT. MCM=0, CLKX configured input thus accepts external clock. Note that CLKR always configured input. source device frame synchronization pulse with bit, (bit5). Like MCM, TXM=1, configured output drives pulse beginning every transmit. TXM=0, configured input accepts external frame sync signal. Note that always configured input. reset serial port both transmitter receiver done XRST RRST bit, respectively. These signals active low, that XRST= RRST= serial port reset. modify configure serial port, total writes necessary. first write should write zeros XRST RRST desired configuration bits 1-5. While maintaining desired configuration bits, second write should write ones XRST, RRST, bits, taking serial port reset. Note that these bits reset individually desired. When zero written either these bits, activity corresponding section serial port stops. When XRST=0 RRST=0, particular internal clocks serial port shut off. This minimizes switching allows device operate lower
Synchronous Serial Port
power consumption long CLKX configured input, that with MCM=0. (bit specifies whether frame syncs needed consecutive serial port transmits. FSM=1, frame sync required every transfer mode referred burst mode, because there periods inactivity serial port between transmits. frequency packet writes called packet frequency. packets bits long, depending packet frequency increases, reaches maximum that equivalent clock cycles, depending Note that this cycle count corresponds instruction cycles CPU, again depending internal 'C54x clocks used. Thus, transmitting maximum rate more than transmission, frame sync signal becomes extraneous. continuous mode operation (FSM=1) then mode that requires only initial frame sync pulse, long write transmit, read from receive, executed during each transmission. timing both modes discussed detail subsections 1.1.2 1.1.3. bit, (bit digital loop back mode that allows testing serial port code with just device. When DLB=1, connected FSX, respectively, through multiplexers, shown Figure 1-4.
Figure 1-4. Receiver Signal MUXes
(internal)
(internal)
CLKR
CLKR (internal)
CLKX
CLKR driven CLKX MCM=1. MCM=0 while DLB=1, then CLKR taken from CLKR pin. This allows external clock generation these signals during digital loopback mode. DLB=0, then normal operation occurs where FSR, CLKR taken from their respective pins.
Serial Ports
Synchronous Serial Port
Bits 10-13 read-only status bits that indicate various states serial port operation. Writes reads serial port synchronized polling RRDY XRDY, (bits respectively) using interrupts that they generate. transition from RRDY indicates that been copied that received data read. receive interrupt (RINT) generated upon this transition. transition from XRDY indicates that contents have been copied that ready loaded with data word. transmit interrupt (XINT) generated upon this transition. Polling these bits software either substitute complement serial port interrupts. other words, both polling interrupts used together, desired. XSREMPTY (bit indicates whether transmitter experienced underflow. (When active). following three situations cause flag become active:
been loaded since last DXR-XSR transfer empties. (The actual transition occurs after last been shifted XSR.) Serial port reset (XRST=0). Device reset.
When XSREMPTY active, transmit side serial port halts, thus driving value (the high-impedance state). exception occurs burst mode with external frame syncs, explained subsection 1.1.2. Note that underflow error condition burst mode, although continuous mode (error conditions further discussed subsection 1.1.4). XSREMPTY flag becomes inactive (XRSEMPTY=1) when:
write occurs. RSRFUL bit, (bit indicates whether receiver experienced overrun. (When RSRFULL=1, active.)
Overrun occurs when: been read since last RSR-to-DRR transfer. full. frame sync pulse appears FSR.
Note that continuous mode (FSM=0), only first conditions apply; therefore, RSRFULL transitions after last been shifted out. When RSRFULL=1, receiver halts waits read. data preserved, data driven while receiver halted lost.
Synchronous Serial Port
RSRFULL flag becomes inactive (RSRFULL=0) under following three conditions:
read. Serial port reset (RRST=0). Device reset.
(bit allow CLKR CLKX pins used inputs. reflect current levels CLKR CLKX pins. levels pins read reading SPC. they tested using BIT, BITF BITT instructions. Note that there latency between CLKOUT cycles length from CLKR/CLKX switching CLKR/CLKX value being represented SPC. Note that serial port into reset, used inputs general-purpose registers. SOFT FREE (bits respectively) special emulation bits that determine state serial port clock when breakpoint encountered high-level language debugger. FREE then, upon software breakpoint, clock continues (that free runs) data shifted out. this case, SOFT don't care. FREE then SOFT takes effect. SOFT=0, then clock immediately stops, thus aborting transmission. SOFT particular transmission continues until completion word, then clock halts. options follows:
receive side functions similar fashion. Note that option besides immediate stop chosen, receiver continues running overflow error possible. default value these bits immediate stop.
1.1.2
Transmit Receive Operations (Burst Mode)
burst mode operation, there periods serial port inactivity between packet transmits. data packet marked frame sync pulse FSX. transmit device, transmission initiated write DXR. value shifted XSR; upon frame sync pulse (generated internally externally depending TXM), value shifted driven pin. reloaded before contents have been transferred XSR, contents overwritten.
Serial Ports
FREE SOFT Free Immediate stop Stop after completion word
Synchronous Serial Port
copied only empty been loaded since last transfer. should written only XRDY=1, which guaranteed write made response transmit interrupt polling XRDY. timing serial port transmit shown Figure 1-5.
Figure 1-5. Burst-Mode Serial Port Transmit Operation
CLKX (TXM=1) (F0=1) XINT
Loaded
Loaded
Reloaded Reloaded
Note following discussion that timings slightly different internally (TMX=1, output) externally (TMX=0, input) generated frame syncs. This distinction made because former case, frame sync pulse generated transmitting device direct result write DXR. latter case, there such direct effect. Instead, transmitting device must write wait externally generated frame sync. frame sync pulse internally generated (TXM=1), then after write DXR, frame sync pulse generated next rising edge CLKX (For externally generated frame syncs following events will occur whenever frame sync pulse appears rising edge CLKX after write DXR). Then next falling edge CLKX, loaded with value from DXR, XRDY goes high, generating transmit interrupt (XINT). next rising edge CLKX cycle, first data (MSB first) driven pin. With fall frame sync pulse, rest bits will shifted out. (therefore, first could have variable length frame sync generated externally does fall within CLKX cycle. Internally generated frame syncs guaranteed 'C54x timings.) When bits transferred, enters high-impedance state. Note that been loaded when XINT generated, XSREMPTY flag would become active low), indicating underflow. Thus, there 2-CLKX cycle latency (approximately) after loaded, before
1-10
Synchronous Serial Port
data driven line, assuming that frame sync pulse generated internally (TXM=1). pulse externally generated, this latency does exist, timing specifications relaxed. With externally generated frame sync, XSREMPTY flag active frame sync pulse generated, data transmitted. This explained detail subsection 1.1.3.
Figure 1-6. Burst-Mode Serial Port Receive Operation
CLKR
(F0=1)
RINT Loaded From
shifting into begins falling edge CLKR cycle after frame sync gone low. After bits have been received, contents transferred falling edge CLKR RRDY goes high, generating receive interrupt (RINT), shown Figure 1-6. Note that from previous receive been read frame sync appears, RSRFULL flag would high. This condition actual error introduces questions serial port's behavior under various error situations: example, appearance frame sync during receive. Various error conditions discussed subsection 1.1.4. Note that packet frequency increased, inactivity period between data packets adjacent transfers decreases zero. This corresponds minimum period between frame sync pulses (equivalent CLKX/R cycles, depending that corresponds maximum packet frequency which serial port operate. maximum packet frequency (see Figure 1-7), timing looks like compressed version Figure 1-6.
Serial Ports
1-11
Synchronous Serial Port
Figure 1-7. Burst-Mode Serial Port Transmit Maximum Packet Frequency
CLKX (TXM=1) (F0=1) XINT
Loaded
Loaded
Reloaded
Reloaded
data bits consecutive packets transmitted continuously with inactivity between bits. frame sync pulse overlaps last transmitted previous packet. receive side Figure looks similar.
Figure 1-8. Burst-Mode Serial Port Receive Maximum Packet Frequency
CLKR
(F0=1)
RINT Loaded From Loaded From
maximum packet frequency transfer looks like compressed version burst mode with periods inactivity. frame sync pulse overlaps first transmitted. Figure Figure show transfer multiple data packets maximum packet frequency; frame sync appears extraneous information. Since data packets transmitted constant rate, provides enough timing information transfer permits continuous stream data. Theoretically, only initial frame sync signal needed initiate multipacket transfer. This continuous mode supported 'C54x serial port discussed subsection 1.1.3.
1-12
Synchronous Serial Port
Figure 1-9. Burst-Mode Serial Transmit Operation With Delayed Frame Sync External Frame Sync Mode
CLKX (TXM=0) (F0=1) XINT
Loaded with
Loaded with
Loaded with
Loaded with
operation serial port with external frame sync similar that with internal frame sync. Events occur when external frame sync appears. When external frame sync delayed, however, double buffer filled frozen until delayed frame sync appears, shown Figure 1-9. When delayed frame sync occurs, transmitted after transmit, DXR-to-XSR copy occurs, XINT generated. next frame sync after delayed frame sync caused transmitted Note that when loading into occurs, DXR-to-XSR copy does occur, XINT generated because been transmitted subsequent writes before delayed frame sync occurs would overwrite DXR.
1.1.3
Transmit Receive Operations (Continuous Mode)
continuous mode, frame sync signal FSX/FSR necessary consecutive packet transfers maximum packet frequency after initial pulse. Continuous mode selected setting FSM=0. Upon first store continuous mode, frame sync generated first transmission then more. long updated once every transmission, continuous mode continues. Falling update causes serial port halt, burst mode case (The XSREMPTY flag becomes asserted etc.). written after halt, device restarts continuous mode transmit generates FSX, assuming that frame sync internally generated. difference between transmits using internal external frame syncs similar discussed subsection 1.1.2 frame syncs externally generated (TXM=0), then should loaded, appearance external frame sync restarts
Serial Ports
1-13
Synchronous Serial Port
continuous mode transmit. been updated with external frame sync, remains high-impedance state. This different from burst mode operation, which covered subsection 1.1.2. continuous mode discontinued-in other words changed burst mode-only serial-port device reset. Changing during transmit halt guaranteed switch burst mode. transmit timing continuous mode shown Figure 1-10.
Figure 1-10. Serial Port Transmit Continuous Operation
CLKX (TXM=1) (F0=1) XINT
Loaded
Loaded
Reloaded
Reloaded
Transmit timing continuous mode similar continuous stream Figure 1-9. major difference lack frame sync pulse after initial one. long updated once transmission, this mode will continue. Overwrites behave just burst mode. data written last transmitted. operation disturbed. external pulse line will abort present transmission, cause data packet lost, initiate continuous mode transmit. this explained more detail subsection. receive operation similar transmit operation. After initial frame sync pulse FSR, more frame syncs needed. This mode will continue long read every transmission. read, serial port receive will halt (RSRFULL flag becomes active). Reading will restart continuous mode soon frame sync received. continuous mode must discontinued with serial port device reset. receive timing seen Figure 1-11.
1-14
Synchronous Serial Port
Figure 1-11. Serial Port Receive Continuous Operation
CLKR
(F0=1)
RINT Loaded From Loaded From
Receive timing continuous mode similar continuous stream Figure 1-9. major difference lack frame sync pulse after initial one. pulse occurs during transmission error), then receive operation aborted, packet lost, receive cycle begun. This discussed more detail page 1-16.
1.1.4
Error Conditions
Error conditions result from unprogrammed event occurring serial port. These conditions operational aberrations such overrun, underflow, frame sync pulse during transmission. need understand serial port handles these errors state acquires during these error conditions. Because they differ slightly burst continuous modes, error conditions discussed separately. burst mode, first error condition (discussed subsection 1.1.2) RSRFULL flag. Basically, this flag occurs when device read incoming data more data being sent, which indicated frame sync pulse FSR. processor halts serial port receives until read. Thus, further data sent lost. receive errors continue, frame sync occurs during receive (that data being shifted into from pin), then present receive aborted begins. Thus, data that being loaded into lost, data not. RSR-to-DRR copy occurs. Figure 1-12 shows serial port receive side behavior frame sync pulse during receive includes nonerror situations.
Serial Ports
1-15
Synchronous Serial Port
Figure 1-12. Receive Error (Normal Burst Mode)
pulse occurs
Receive progress Abort receive. Start next reception. DRR, thus, word lost)
RSRFULL active Ignore pulse
Start data receive
Transmit errors burst mode result when frame sync occurs during various conditions. Underrun burst mode considered error explained subsection transmission progress (that data being driven pin) when frame sync pulse occurs, then present transmit aborted, data lost. Then, whatever data time frame sync pulse transferred (DXR-to-XSR copy) transmitting. However, transmit interrupt XINT generated only been written after last transmit. Also, XSREMPTY active frame sync pulse appears, data shifted out. Figure 1-13 summarizes serial port transmit behavior with error (and nonerror) conditions.
Figure 1-13. Transmit Error (Normal Burst Mode)
pulse occurs
Transmit progress Abort transmit
since last transmit DXR-to-XSR copy. Transmit interrupt. Start transmit.
XSREMPTY low, DXR- to-XSR copy occurs. transmit interrupt. Start transmit.
written since last transmit
DXR-to-XSR copy. transmit interrupt. Start transmit.
DXR-to-XSR copy. Transmit interrupt. Start transmit (One word lost).
continuous mode, errors take broader meaning. Data transfer supposed occurring times continuous mode. Thus, underflow (=0)
1-16
Synchronous Serial Port
considered error continuous mode because data being transmitted. burst mode, overrun error, both these cause serial port receive transmit sections halt. operation both these flags explained subsection RSRFULL flags description. Underflow overrun errors fatal; they corrected reading writing DXR. write deactivate either frame sync pulse generated FSM=1) required FSM=0). receive side, however, after read deactivate RSRFULL, frame sync pulse required. receive side serial port keeps track word (either 16-bit) boundary, even though receiving data. When RSRFULL flag deactivated read from DRR, receiver begins read from correct bit. Another cause error appearance frame syncs during transmission. After initial frame sync continuous mode, others should occur. When frame sync pulse occurs during transmit, current transmit operation(that serially driving data onto pin) aborted, data lost. transmit cycle initiated., long updated once transmission afterward. During receive continuous mode, situation similar: frame sync pulse occurs, packet data (8-bit byte 16-bit word, depending lost. counter reset, data that being shifted into from lost. Data then driven shifted into RSR. Therefore, frame sync during transmission chart continuous mode looks like left half burst mode charts Figure Figure because receive transmit always progress. Figure 1-14 Figure 1-15 show receive transmit errors continuous mode. Note that frame sync occurs after deactivating RSRFULL flag reading before beginning next word (either 16-bit) boundary, receive abort condition occurs. Also, note major difference transmit continuous mode error compared with transmit burst mode error. XSREMPTY active continuous mode external frame sync occurs, data transmitted. Instead, since underflow continuous mode considered error, frame sync pulse ignored, remains high-impedance state.
Serial Ports
1-17
Synchronous Serial Port
Figure 1-14. Receive Error (Continuous Mode)
pulse occurs Ignore pulse, since RSRFULL active
Receive progress Abort current receive. Start next reception RSR-to-DRR copy; thus, current word lost)
Figure 1-15. Transmit Error (Continuous Mode)
pulse occurs
Transmit progress Abort transmit
Ignore pulse because written since last XMIT XSREMPTY low.
since last transmit
DXR-to-XSR copy. transmit interrupt. Start transmit.
DXR-to-XSR copy. Transmit interrupt. Start transmit. (Current word lost)
1-18
Synchronous Serial Port
1.1.5
Example
code examples that follow show one-way transmit from device device arithmetic sequence numbers. numbers written each device block from 9000h b000h data memory. Device waits loop ready receive signal (XF) from device initializes transfer with value zero. Only device transmit interrupt enabled; transmit writes value will send into memory.
Example 1-1.One-Way Transmit Operation from Device Device 1-Transmit Side
Device Transmit side ;Setup SPC0 source ;and internal frame sync ;Set TXM=MCM=FSM=1, ;DLB=FO=0. ;and into reset ;(XRST=RRST=0) ;Take reset ;Setup interrupts ;Clear ;Turn XINT0 ;Enable interrupts ;Wait ready-to-receive ;from other device ;First transmit/write ;Value ;Setup where write ;Write first value ;Transmit first value
S
#0038h,spc0
SSSRSBX ILOOP SENDZ
#00F8h,SPC0 #0FFFFh,IFR #020h,IMR 1,INSENDZ,BIO ILOOP #0,A #9000h,AR7 A,*AR7 A,DXR0
SSTL STLM SELF1 XMT_ISR ADDM STLM RETE
SELF1 ;Wait interrupts AR7,A ;Check past 0x0b000 #0B000h,A ;i.e. block END_SERP,AGEQ tight loop #1,*AR7 ;Add *AR7+,A A,DXR0 ;Transmit value END_SERP ;Sit tight loop after ;block complete.
END_SERP
code device follows. sends ready-to-receive signal (XF) device Only receive interrupt masked receive reads from DRR, writes block, checks reached block.
Serial Ports
1-19
Synchronous Serial Port
Example 1-2.One-Way Transmit Operation from Device Device 1-Receive Side
*Device Receive ;Set CLK, frame ;sync receive ;Set TXM=MCM=DLB=FO=0, FSM=1 ;And into reset ;(XRST=RRST=0) ;Take reset ;Setup interrupts ;Clear ;Turn RINT0 ;Enable interrupts ;Setup where write ;received data ;Signal ready receive ;Wait interrupts DRR0,A ;Load received value A,*AR7+ ;Write memory block AR7,A ;Check past 0x0b000 #0B000h,A ;i.e. block END_SERP,AGEQ tight loop ;Sit tight loop after ;block complete.
S
#0008h,SPC0
SSSRSBX SSSBX SELF1 RCV_ISR RETE END_SERP SELF1
#00C8h,SPC0 #0FFFFh,IFR #010h,IMR 1,IN#9000h,AR7 1,XF
END_SERP
1-20
Buffered Serial Port (BSP)
Buffered Serial Port (BSP)
Buffered Serial Port (BSP) comprised full-duplex, double-buffered Serial Port Interface (SPI) Autobuffering Unit (ABU). block enhanced version existing 320C54x devices. block which allows read/write directly 'C54x internal memory independent CPU. This results minimum overhead transactions faster data rates. When auto-buffering capability disabled (Standard Mode), transfers with done under user control (software). this mode, transparent; word based interrupts (WXINT WRINT) provided sent transmit interrupt (XINT) receive interrupt (RINT). When auto-buffering enabled, word transfers done directly between 'C54x internal memory using embedded address generators. on-chip full duplex serial interface (SPI) provides direct communication with serial devices such codecs, serial converters, other serial devices with minimum external hardware. double-buffered allows transfer continuous communication stream (8-,10-,12- 16-bit data packets). Data packets directed frame synchronization pulse every packet Burst Mode. Continuous Mode, serial operation, once initiated, requires further frame synchronization pulses. Frame signal well frequency programmable serial clock provided transmission. Polarity frame clock strobes programmed fully static thus will function arbitrarily clocking frequencies. maximum operating frequency CLKOUT (28.6 Mbit/s 35ns, Mbit/s ns). transmit section includes (Pulse Coded Modulation) mode that allows easy interface with line. circular addressing registers with corresponding address generation units. Memory buffers reside words 'C54x internal memory. length starting addresses buffers user programmable. buffer empty/full interrupt posted CPU. Buffering easily halted thanks auto disabling capability. autobuffering capability separately enabled transmit receive sections. When autobuffering disabled, operation similar 'C54x standard serial port operation.
Serial Ports
1-21
Buffered Serial Port (BSP)
1.2.1
Configuration 'C542
Memory-mapped registers: SPCE Data Receive Register Data Transmit Register Serial Port Control Register Control Extension Register (autobuffering unit) Transmit Address Register Transmit Buffer Size Register Receive Address Register Receive Buffer Size Register
Memory buffers: words on-chip located address range 0800h-0FFFh Interrupt locations:
Receive interrupt: vector location 50h, mask/flag located IMR/IFR[4:4] Transmit interrupt: vector location 54h, mask/flag located IMR/IFR[5:5]
1-22
Buffered Serial Port (BSP)
Figure 1-16. Buffered Serial Port Block Diagram Registers
C5XX DBUS
MEMORY ABUS
INTERFACE
Read
Write
C54X Interface
Module
CTRL
xrdy
rrdy
xbuf
rbuf
Interrupt Logic CLKX CLKR Module CTRL Wrint Wxint Interrupt Control RINT SPCE
XINT
Legend:
SPCE
16-bit Data Transmit Shift Register 16-bit Data Transmit Register 11-bit Address Transmit Register 11-bit Transmit Buffer Size Register 16-bit Data Receive Shift Register 16-bit Data Receive Register 11-bit Address Receive Register 11-bit Receive Buffer Size Register 16-bit Serial Port Interface Control Register 16-bit Serial Port Interface Control Register Extension Autobuffering Unit Control
Serial Ports
1-23
Buffered Serial Port (BSP)
1.2.2
Serial Port Interface (SPI) Operation
Three lines necessary transmission between transmitting device receiving device. transmission side, Transmit Frame Synchronization Signal (FSX) control that initiates transfer. Transmit Clock Signal (CLKX) clocks transmitted data that sent Serial Data Signal (DX). Corresponding pins receiver side Receive Frame Synchronization Signal (FSR),the Receive Clock Signal (CLKR),and Received Serial Data Signal (DR). Figure 1-17 showing 'C54x serial ports connected half duplex transmission. this setup, transmitting 'C54x providing Transmit Frame Transmit Clock.
Figure 1-17. Half-Duplex Communication Between TMS320C54xs
CLKX
CLKR
TMS320C5XX
TMS320C5XX
uses four memory-mapped registers (SPC, SPCE, DRR) shown Figure 1-18 other registers (XSR RSR) that accessible user permit double-buffering capability.
Figure 1-18. Module Block Diagram
CLKX CLKR WRINT SPCE Module WXINT CTRL
1-24
Buffered Serial Port (BSP)
control registers (SPC SPCE) control operation. Transmit data written Data Transmit Buffer (DXR) while received data read from Data Receive Register (DRR). transmit performed writing data which will copy data (Transmit Shift Register) when will requested (Frame Synchronization occurrence instance) shift data thus allowing another write DXR. process similar receive part. Data from shifted into Receive Shift Register (RSR) that copies Data Receive Register from which read. Thus serial port double-buffered because data transferred to/from DXR/DRR while another transmission/reception being performed. serial port being used, registers used general purpose registers. this case, should connected logic prevent possible receive operation from being initiated. Note that when autobuffering enabled Transmit Receive registers cannot accessed user program. register cannot written when receiver enabled (RRST=1).
1.2.2.1
Serial Port Interface Control Registers
control register 16-bit memory mapped register that configures SPI. Some bits read-only while others read/write. SPCE control register 16-bit extension control read/write register. LSBs SPCE dedicated control whereas MSBs used Autobuffering Unit Control (see paragraph 3.2). Figure 1-19 shows positions, Figure 1-20 shows SPCE positions. summary each given Table Table SPCE. register format identical 'C54x standard serial port register.
Figure 1-19. Register
RRST XRST FREE SOFT RSRFULL XSREMPTY XRDY RRDY
Note: Note: R=Read W=Write
Serial Ports
1-25
Buffered Serial Port (BSP)
Table 1-3. Register Bits Summary
Name Function Reserved Always read Digital Loop Back Mode Bit. When DLB=1, connected shown Figure 1-21. Additionally, CLKR driven CLKX MCM=1 taken from CLKR device MCM=0 allowing CLKX CLKR tied together externally supplied common external clock source. Note that must proper operation mode. Note also that signals appear device pins mode not. Format conjunction with (Format Extension Bit) SPCE register specifies word length. When format 16-bit words, when format 10-bit words, when format 8-bit words when format 12-bit words. Note that 8-,10-,12-bit words, received words right justified sign extended form 16-bit word. Words transmit must right justified Frame Sync Mode (FSM) specifies whether frame synchronization pulses required serial port operation. FSM=1, frame pulse required FSX/FSR transmission/ reception each word (Burst Mode). When serial port operating continuous mode, FSM=0. Clock Mode (MCM) specifies clock source CLKX. MCM=0, CLKX taken from CLKX pin. MCM=1, CLKX driven on-chip source having frequency equal 1/(CLKDV+1) CLKOUT. CLKDV programmable division factor specified SPCE register. Note that MCM=1 DLB=1, CLKR signal also supplied internal source. Transmit Mode (TXM) configures input (TXM=0) output (TXM=1). When TXM=1, frame sync pulses generated internally when data transferred from initiate transfer. internally generated frame sync signal synchronous with respect CLKX. When TXM=0, supplied external device. XRST RRST Transmit Reset (XRST) Receive Reset (RRST) signals reset transmitter receiver respectively. modified reconfigure serial port, total writes should made SPC. first write should write zeroes XRST RRST desired configuration bits 1-5. second write should write ones XRST RRST, taking reset. When zero written either these bits, activity corresponding section halts. When XRST=0 RRST=0, internal clocks serial port shut off, allowing device lower power mode operation. Notes: Writing zero XRST clears XSREMPTY sets XRDY 2-Writing zero RRST clears RSRFULL RRDY bit. 3-Writing while XRST effect XRDY bit. 1-26
Buffered Serial Port (BSP)
Table 1-3. Register Bits Summary
Name Function Input (IN0) Input (IN1) allow CLKR CLKX pins used inputs. bits reflections current levels CLKR CLKX pins device. levels these pins read reading SPC. They tested using BITT instructions. Note that IN0/IN1 sampled with clock, CLKX/CLKR frequency must least times CLKOUT frequency valid IN0/IN1 values. Note that used inputs used. Receive Ready Transmit Ready Bits. transition from RRDY indicates that received data been copied that data read. standard mode, receive interrupt generated upon this transition. When received data read software standard mode auto-buffering mode) RRDY reset RRDY upon device reset receive reset (RRST=0). RRDY XRDY transition from XRDY indicates that contents have been copied that ready loaded with data word. standard mode transmit interrupt generated upon transition. When written software standard mode auto-buffering mode), XRDY reset XRDY upon device reset transmit reset (XRST=0). XSREMPTY Transmit Shift Register Empty Flag. Note:XSREMPTY=0 upon device reset, transmit reset (XRST=0). RSRFULL Receive Shift Register Full Flag. This when word been shifted register current value been read (RRDY=1). RSRFULL=1, receiver halts waits read; data preserved data sent lost. Note:RSRFULL=0 upon device reset, receive reset (RRST=0). SOFT SOFT bit. This enabled when FREE FREE=0 SOFT selects immediate stop stop after word transmit completion page SOFT=0 upon device reset. FREE FREE bit. FREE=1 free selected regardless value SOFT bit. FREE=0 SOFT selects emulation mode described above. page FREE=0 upon device reset.
Serial Ports
1-27
Buffered Serial Port (BSP)
Figure 1-20. SPCE Register
ABU-Control CLKP CLKDV
Note: R=Read W=Write
Table 1-4. SPCE Register Bits Summary
Name Function
CLKDV
Internal Transmit Clock Division Factor. When register CLKX driven on-chip source having frequency equal 1/(CLKDV+1) CLKOUT. CLKDV range [0-31]. When CLKDV equal zero, CLKX duty cycle 50/50; when CLKDV even value (CLKDV=2p), CLKX high state duration (p+1)/(p) cycles state duration (p)/(p+1) cycles when polarity (CLKP) 0/1. CLKDV value upon device reset
Frame Sync Polarity Bit. When FSP=1, frame sync pulses (FSX FSR) active low. When FSP=0, frame sync pulses active high. FSP=0 upon device reset. Clocks Polarity When CLKP=1, data sampled receiver CLKR rising edge sent transmitter CLKX falling edge. When CLKP=0 data sampled receiver CLKR falling edge sent transmitter CLKX rising edge. CLKP=0 upon device reset.
CLKP
Format Extension Bit. Format conjunction with register specifies word length. When format 16-bit words, when format 10-bit words, when format 8-bit words when format 12-bit words. Note that 8-,10-,12-bit words, received words right justified sign extended form 16-bit word. Words transmit must right justified. upon device reset.
Frame Ignore Bit. This control operating only transmit continuous mode with external frame receive continuous mode. When frame pulses following first frame pulse that initiates operation ignored. When frame pulses following first frame restart SPI. Upon device reset FIG=0. Pulse Coded Modulation Mode. This mode active when PCM=1and affects transmitter only. mode, transmitted only 15th this transmitted high impedance during transmission period. transfer affected value. Reserved autobuffering unit control .See paragraph 3.2).
15-10
ABU-C
1-28
Buffered Serial Port (BSP)
Figure 1-21. Receiver Signal Multiplexers Digital Loop Back
(internal) CLKR (internal) Free Immediate stop Stop after completion word (internal)
CLKR
CLKX
Upon device reset values registers are:
0000h 0000h 000010XR00000000b SPCE 000000000000011b
respectively current levels CLKX CLKR pins. SOFT FREE (bits control register) special emulation bits that determine state serial port clock when breakpoint encountered high-level language debugger. FREE one, then upon software breakpoint, clocks continue (that free runs) data shifted shifted this case, SOFT don't care. FREE then SOFT takes effect. SOFT ,then clocks immediately stop. SOFT one, current transmission continues until completion word, then transmit clock halts, receiver affected this case. options follows:
default values these bits immediate stop (FREE=0,SOFT=0).
Serial Ports
1-29
FREE SOFT
Buffered Serial Port (BSP)
1.2.2.2
Serial Point Interface Transmit Operation
processes take place ensure transmission,a process filling register under control (user software) Standard Mode under control autobuffering unit (ABU) auto buffered mode process emptying register under control SPI. order synchronize monitor these processes,two signals used register. These signals XRDY (Transmit Ready) XSREMPTY (Transmit Shift Register Empty). Filling process illustrated with Figure 1-22, emptying process illustrated with Figure 1-23 (case Burst Mode with External frame).When written (filling process), XRDY signal cleared that process informed that value ready transmitted. When transferring this value transmit shift register (XSR), XRDY This transfer occurs upon various circumstances,depending which type Transmission Mode selected. same time transfer occurs,a Transmit Request sent interrupt (XINT) Standard Mode (BXE=0 ABUC control register) (xrdy) Buffered Mode (BXE ABUC register).In Standard Mode,the should written only XRDY =1,which guaranteed write made response transmit interrupt polling XRDY. Transmit Shift Register Empty (XSREMPTY) info used monitor state register. This only written SPI. When word (XRDY=0) been transferred from XSR,this while same time XRDY 1.When word been shifted transmit line (DX),this another transmission with word following current transmission.
Figure 1-22. Filling Process
XRDY autobuffering Mode XRST
WRITTEN
XRDY
XRDY Write DXR;
Standard Mode (User Software)
supports modes transmission,Burst Mode Continuous Mode which here below detailed. flowcharts timing diagrams used description featuring frame clock events, assumption
1-30
Buffered Serial Port (BSP)
made that clock polarity (CLKP) frame polarity (FSP) Operation with other polarity derived easily. Table giving list signals registers that used transmit flowcharts. modes operated with external clock (MCM=0) with internal clock (MCM=1). When clock internal, frequency user programmed thanks CLKDV field SPCE register Frequency equal 1/(CLKDV+1) CLKOUT. modes also operated Pulse Coded Modulation Mode when SPCE register When 1,word transmit shifted transmit data line (DX) position (MSB) 0,if this 1,DX line high impedance driven during transmission period.
Table 1-5. Transmit Flowcharts Signals Registers
Name Description Transmit Frame Sync signal (internal external) Transmit Serial Clock (internal external) Transmit Serial Data Signal. CLKX Data Transmit Memory-mapped register. Transmit Shift Register. XRDY Transmit Ready status/control register. XSREMPTY Transmit Shift Register Empty status register. Frame Ignore control SPCE register. XFRA Transmit Frame Acknowledge internal signal. This manages sync pulse acceptance/non acceptance during continuous mode when FIG=0/1. XFRA=1 upon device reset upon reset Transmit Section (XRST=0). Internal Transmit Counter data shifting. Number bits transmit (8,10,12 16). XCOUNT XBITS FSXLOW Internal Signal state monitoring. FSXLOW upon device reset upon reset Transmit Section (XRST=0) Pulse Coded Modulation SPCE register. Internal signal transmission high impedance state mode when word transmitted. Transmission request (XINT standard mode, request auto buffered mode). XREQ
Serial Ports
1-31
Buffered Serial Port (BSP)
Burst Mode (FSM=1) With External Frame SYNC (TXM=0)
this mode, data packet marked Fame Sync Pulse FSX. Some periods inactivity then occur between packets. flowchart Figure 1-23 showing detailed process embedding timing aspects. Figure 1-24 Figure 1-25 show timing aspects both short duration frame signal long duration frame signal. operation starts when frame signal becomes active,this event being sampled falling edge transmit clock. TRANS state next rising edge transmit clock),transfer from Transmit Shift Register (XSR) performed contents (XRDY=0) then XRDY XSREMPTY request next word transmit (XREQU) sent XINT interrupt (Standard Mode) (Auto buffered Mode).If contents (XRDY=1) then same value will transmitted Transmit Request will generated. same time, driven with first (MSB) transmit. will driven with this first long Frame Sync Pulse high. Following bits transmitted (SHIFT state) starting next rising edge Transmit Clock following Frame Sync Pulse event ,with event being detected Transmit Clock falling edge. After bits have been transmitted (TX_END state),DX high impedance driven XSREMPTY 0.Note that this last state reached Frame Sync Pulse occurred. This illustrated with Figure 1-26 (Continuous transmission Burst Mode) Figure 1-27 (Transmission Abort). Frame Sync Pulse occurs during transmission transmission restarted (TRANS state),the transmitted word same depending written with next word not. Figure 1-28 Figure 1-29 showing respectively XSREMPTY activation XSREMPTY deactivation.
1-32
Buffered Serial Port (BSP)
Figure 1-23. Transmit Process Burst Mode With External Frame (FSM=1 TXM=0)
clkx
FSXLOW= Then XRDY Then
XSREMPTY XREQU ;request
clkx
EndIf
XRDY FSXLOW TRANS
XCOUNT =XBITS (PCM= DX=HZ
(XSR(15:15)=
;PCM mode active
clkx
Else XSR(XBITS-1:XBITS-1) Endif Endif
clkx
XCOUNT
FSXLOW XCOUNT SHIFT
clkx
(XHZ Then Else DX=HZ XSR(XBITS-1:XBITS-1)
XCOUNT
clkx
Endif XSREMPTY
Serial Ports
1-33
Buffered Serial Port (BSP)
Figure 1-24. Short Pulse
Short Pulse With Going When CLKX High
CLKX
msb-1
Short Pulse With Going When CLKX
CLKX
msb-1
Figure 1-25. Long Pulse
Long Pulse With Going When CLKX High
CLKX
msb-1
1-34
Buffered Serial Port (BSP)
Long Pulse With Going When CLKX
CLKX
msb-1
Figure 1-26. Transmit Burst Mode With External Frame Continuous Operation
CLKX XRDY FSXLOW XSREMPTY Written
Figure 1-27. Transmit Burst Mode With External Frame (Transmit Aborts-Format Bits)
CLKX
Transmit Same XRDY Written FSXLOW XSREMPTY
Transmit
Serial Ports
1-35
Buffered Serial Port (BSP)
Figure 1-28. Transmit Burst Mode With External Frame-XSREMPTY Activation (Format Bits)
CLKX XRDY FSXLOW XSREMPTY
Figure 1-29. Transmit Burst Mode With External Frame-XSREMPTY Deactivation
CLKX Written
XRDY FSXLOW XSREMPTY
Burst Mode (FSM=1) With Internal Frame SYNC (TXM=1)
this mode, Frame Sync Pulse generated internally (Figure 1-30) Transmit Serial Clock rising edge following write register (XRDY going low).The Frame Sync Pulse active during full clock period. further steps, process similar External Frame mode. Thanks doublebuffering capability, continuous transmission done updated Transmit Interrupt (XINT) service routine. Standard Mode,transmission initiated external event (external interrupt instance) serial port receive interrupt (RINT). Auto Buffered Mode, this mode will result continuous transmission with frame generated each transmission start.
1-36
Buffered Serial Port (BSP)
Figure 1-30. Transmit Process Burst Mode With Internal Frame (FSM=1 TXM=1)
;generate frame
clkx
XRDY
clkx
XSREMPTY XREQU ;request XRDY
XCOUNT =XBITS TRANS
;reset frame sync (PCM=1) (XSR(15:15)=1) Then Else
clkx
XSR(XBITS-1:XBITS-1)
Endif XCOUNT SHIFT
XCOUNT
clkx
(XHZ=0) Then Else XSR(XBITS-1:XBITS-1)
XCOUNT XRDY=0
clkx
Endif
XCOUNT XRDY=1
clkx
XSREMPTY
Serial Ports
1-37
Buffered Serial Port (BSP)
Figure 1-31. Transmit Burst Mode Internal Frame(Format Bits)
CLKX
XRDY Written XSREMPTY
Continuous Mode (FSM=0) With External Frame SYNC (TXM=0)
continuous mode with external frame sync (Figure 1-33, Figure 1-34, Figure 1-35), only first frame sync signal necessary start transmit consecutive packets. long updated once every transmission, continuous mode will continue. Failing update will cause process reach SPI_END state high impedance driven XSREMPTY this case,new frame sync pulse required restart SPI. frame sync pulse occurs after initial one, restarted (Frame Ignore Bit) SPCE register FIG=1, this frame sync will ignored. Setting allows, instance, transmitting continuous bits format whereas frame sync occur every 8,10, bits. This result significant gain buffer size auto-buffered mode standard mode significant cycles gain standard mode. Figure 1-35 showing example with bits format sync pulse every byte.
1-38
Buffered Serial Port (BSP)
Figure 1-32. Transmit Process Continuous Mode With External Frame (FSM=0 TXM=0)
XFRA
clkx
FSXLOW Then XRDY Then XSREMPTY
clkx
EndIf
XREQU ;request XRDY FSXLOW TRANS XCOUNT =XBITS
(PCM=1) (XSR(15:15)=1) Then (FSX XFRA XFRA Else XSR(XBITS-1:XBITS-1)
clkx
Endif Endif FSXLOW
XCOUNT
clkx
SHIFT
(FIG ThenXFRA XCOUNT
clkx
(XHZ Then XCOUNT XRDY XCOUNT XRDY
clkx
Else Endif
XSR(XBITS-1:XBITS-1)
clkx
XSREMPTY XFRA
Serial Ports
1-39
Buffered Serial Port (BSP)
Figure 1-33. Transmit Continuous Mode With External Frame (Format Bits)
CLKX XRDY Written FSXLOW XSREMPTY
Figure 1-34. Transmit Continuous Mode With External Frame Transmission Stop (Format Bits)
CLKX XRDY FSXLOW XSREMPTY
1-40
Buffered Serial Port (BSP)
Figure 1-35. Transmit Continuous Mode With External Frame (Format 16-bits)
Frame Ignored CLKX XRDY
FSXLOW XSREMPTY
Continuous Mode (FSM=0) With Internal Frame SYNC (TXM=1)
this mode, Frame Sync Pulse generated internally (Figure 1-36 Figure 1-37) Transmit Serial Clock rising edge following write register (XRDY going low). Frame Sync Pulse active during full clock period. further steps, process similar External Frame mode. long updated once every transmission,the continuous mode will continue. Failing update will cause process reach SPI_END state high impedance driven XSREMPTY this case, will restarted soon will written (XRDY going
Serial Ports
1-41
Buffered Serial Port (BSP)
Figure 1-36. Transmit Continuous Mode With Internal Frame(FSM=0 TXM=1)
;generate frame
clkx
XRDY XFRA
clkx
XFRA XSREMPTY XREQ ;request XRDY reset frame sync XCOUNT XBITS If(PCM=1)&(XSR(15:15)=1)Then ELSE DX=XSR(XBITS-1:XBITS-1) XHZ=0 Endif
TRANS
clkx
XCOUNT
XCOUNT SHIFT
clkx
(XHZ=0) Then Else XSR(XBITS-1:XBITS-1)
XCOUNT XRDY
clkx
Endif
XCOUNT XRDY=
clkx
XSREMPTY XFRA
1-42
Buffered Serial Port (BSP)
Figure 1-37. Transmit Continuous Mode With Internal Frame (Format Bits)
CLKX
XRDY XSREMPTY Written
1.2.2.3
Serial Port Interface Receive Operation
processes take place ensure reception,a process filling register under control process emptying register under control user software Standard Mode under control autobuffering unit (ABU) auto buffered mode. order synchronize monitor these processes,two signals used register. These signals RRDY (Receive Ready) RSRFULL (Receive Shift Register Full).Emptying process illustrated with Figure 1-38 filling process illustrated with Figure 1-39 (case Burst Mode). When read (emptying process), RRDY signal cleared RSRFULL cleared that process informed that word been read received. When transferring this word from (Receive Shift Register) (Figure 1-39), RRDY This transfer occurs only RSRFULL cleared (Figure 1-39). transfer cannot performed because RSRFULL still then process ends only restarted read. RSRFULL then considered overflow event. same time transfer occurs, Receive Request sent interrupt (RINT) Standard Mode (BRE=0 SPCE control register) Auto Buffered Mode (BRE= BUFC register). Standard Mode, should read only RRDY which guaranteed read made response receive interrupt polling RRDY.
Serial Ports
1-43
Buffered Serial Port (BSP)
Figure 1-38. Emptying Process
RRDY Autobuffering Mode
READ
RSRFULL RRDY
READ
;Standard Mode ;(User Software)
supports modes reception,Burst Mode Continuous Mode which here below detailed. flowcharts timing diagrams used description featuring frame clock events,assumption made that clock polarity (CLKP) frame polarity (FSP) 0.Operation with other polarity derived easily. Table giving list signals registers that used receive flowcharts.
Table 1-6. Receive Flowcharts Signals Registers
Name Description Receive Frame Sync signal Receive Serial Clock Receive Data Signal. CLKR Data Receive Register. Receive Shift Register. RRDY Receive Ready status/control register. Receive Shift Register Full register Frame Ignore control SPCE register. RSRFULL RFRA Receive Frame Acknowledge internal signal. This manages sync pulse acceptance/non acceptance during continuous mode when FIG=0/1 RFRA=1 upon device reset upon reset Receive section (RRST=0). Internal Receive Counter data shifting. Number bits receive (8,10,12 16). RCOUNT RBITS RREQ Receive Request (RINT standard mode,request auto buffered mode). 1-44
Buffered Serial Port (BSP)
Burst Mode (FSM=1)
this mode,data packet marked Fame Sync Pulse FSR. Some periods inactivity then occur between packets. flowchart Figure 1-39 showing detailed process embedding timing aspects. Figure 1-40 Figure 1-41 show timing aspects both short duration frame signal long duration frame signal. operation starts when frame signal becomes active,this event being sampled falling edge receive clock. RX_START internal receive counter (RCOUNT) loaded with number bits receive (8,10,12, bits).First (MSB) shifted into Receive Shift Register falling edge Receive Clock sampling Frame Sync Pulse (FSR) level. After bits have been received, RRDY (last been read), RRDY Receive Interrupt (RINT) sent standard mode (BRE=0) request emptying sent auto buffered mode (BRE=1); RRDY still equal RSRFULL then restarted when next Frame Sync occurs only RSRFULL Thanks double buffering,reception maintained continuously (Figure 1-42). Frame Sync Pulse occurs during reception (Figure 1-43) reception restarted bits that have been shifted aborted reception lost. Figure 1-44 Figure 1-45 showing RSRFULL activation RSRFULL deactivation, respectively.
Serial Ports
1-45
Buffered Serial Port (BSP)
Figure 1-39. Receive Burst Mode (FSM=1
START RSRFULL RCOUNT RBITS-1
clkx
RSRFULL RCOUNT
clkx
clkx
SHIFT
RCOUNT RSR(0:0
RCOUNT
clkx
RSR(0:0) (RRDY Then RRDY RREQU ;request Receive TRANS RSR(RBITS-1:0) Else RSRFULL Endif
XCOUNT XRDY
clkx
XCOUNT XRDY=
clkx
1-46
Buffered Serial Port (BSP)
Figure 1-40. Short Pulse
Short Pulse With Going When CLKR High
CLKR
Short Pulse With Going When CLKR
CLKR
Figure 1-41. Long Pulse
Long Pulse With Going When CLKR High
CLKR
Serial Ports
1-47
Buffered Serial Port (BSP)
Long Pulse With Going When CLKR
CLKR
Figure 1-42. Receive Burst Mode-Continuous Reception (Format Bits)
CLKR
read RRDY
RSRFULL
1-48
Buffered Serial Port (BSP)
Figure 1-43. Receive Burst Mode With Reception Aborts
CLKR
Restart Reception
RRDY
RSRFULL
Figure 1-44. Receive Burst Mode-RSRFULL Activation (Format Bits)
CLKR
RRDY
RSRFULL
Serial Ports
1-49
Buffered Serial Port (BSP)
Figure 1-45. Receive Burst Mode-RSRFULL Deactivation
CLKR
read
RRDY
RSRFULL
Continuous Mode (FSM=0)
continuous mode with external frame sync (Figure 1-46, Figure 1-47, Figure 1-48), only first frame sync signal necessary start receive consecutive packets. long read every reception,the continuous mode will continue. Failing read will cause process reach RX_END state (RSRFULL =1).In this case,read frame sync pulse required restart SPI. frame sync pulse occurs after initial one,SPI restarted (Frame Ignore Bit) SPCE register 0;if FIG=1,this frame sync will ignored. Setting allows,for instance,receiving continuous bits format whereas frame sync occur every 8,10, bits. This result significant gain buffer size auto-buffered mode standard mode significant cycles gain standard mode. Figure 1-49 showing example with bits format sync pulse every byte.
1-50
Buffered Serial Port (BSP)
Figure 1-46. Receive Continuous Mode (FSM=0)
START RCOUNT RBITS
clkx
&RSRFULL RFRA
clkx
RFRA
RCOUNT
clkx
SHIFT
(FIG Then FRFA RCOUNT (0:0)
RCOUNT
clkx
(0:0) (RRDY Then RRDY TRANS RREQU ;request Receive (BITS-1:0) Else RSRFULL RFRA
RCOUNT RSRFULL
clkx
Endif
clkx
RSRFULL
Serial Ports
1-51
Buffered Serial Port (BSP)
Figure 1-47. Receive Continuous Mode (Format Bits)
CLKR
RRDY
read RSRFULL
Figure 1-48. Receive Continuous Mode-Stop (Format Bits)
CLKR
RRDY Reception Stop RSRFULL
1-52
Buffered Serial Port (BSP)
Figure 1-49. Receive Continuous Mode With FIG=1 (Frame Ignore, Format 16-Bits)
Frame Ignored CLKR
RRDY
RSRFULL
1.2.3
Autobuffering Unit (ABU)
Figure 1-50 showing block diagram Autobuffering Unit. using five memory-mapped registers (SPCE, AXR, BKX, BKR). Serial Port Control Extension Register (SPCE) controls operation. Address Transmit Register (AXR) Block Size Transmit Register (BKX) associated with circular addressing logic allow address generation reading word transferred from 'C54x internal memory Data Transmit Register (DXR). Address Receive Register (ARR) Block Size Receive Register (BKR) associated with circular addressing logic allow address generation writing Data Receive Register (DRR) 'C54x internal memory. Autobuffering used,the bits AXR, BKX, registers used general purpose registers. interrupt mechanism implemented order interrupt when transmit /receive buffer been halfway entirely emptied/filled. This mechanism features auto disabling capability. transmit receive parts enabled separately. When part disabled, operates Standard Mode. standard mode, transparent corresponding part. When autobuffering enabled, corresponding data serial port register (DXR DRR) more available access memory mapped register software. Burst Mode Continuous Mode described operation conjunction with autobuffering capability.
Serial Ports
1-53
Buffered Serial Port (BSP)
internal 'C54x memory used autobuffering consists word block dual access memory that configured user data data/program, like other dual access blocks. When enabled, this memory block still addressed accessing data or/and program. word block addressed same time ABU, memory access conflict occur some cases which fall basically categories:
transmit access occurs same time access internal buses (simple, dual, long data read program read) receive access occurs same time access internal buses (write dual read operations)
These conflicts automatically solved with cycle penalty side; priority given ABU. Other combinations ABU/CPU accesses same memory block don't generate conflict. Also, conflict appears when access different memory blocks. When enabled transmit receive transmit receive requests from happen same time, transmit request priority over receive request.
1-54
Buffered Serial Port (BSP)
Figure 1-50. Block Diagram
C5xx Memory Interface DBUS ABUS Read Write
C5xx Interface
Control
Module
RRDY
XRDY
RBUF
XBUF
Module
Interrupt Control
XINT RINT
Interrupt Logic
1.2.3.1
Autobuffering Control Register (SPCE)
bits SPCE control register configure ABU. Some bits read-only while others read/write. Figure 1-51 shows positions. summary each given Table 1-7.
Figure 1-51. ABUC Register
HALTR
HALTX
SPI_Control
Legend:
Read;
Write
Serial Ports
1-55
Buffered Serial Port (BSP)
Table 1-7. ABUC Register
Name SPIC Function Serial Port Interface Control Bits (see paragraph 2.2) Transmit Autobuffering Enable Bit. When BXE=1, autobuffering enabled transmitter. When BXE=0, autobuffering disabled operates Standard Mode. BXE=0 upon device reset. indicates which half transmit buffer been transmitted. instance, read when XINT interrupt occurs (interrupt program polling). XH=0 indicates that first half buffer been transmitted, XH=1 indicates that second half buffer been transmitted. Device reset clears bit. HALTX When HALTX=1, autobuffering halted when current half buffer been transmitted. same time, SPCE register cleared serial port operation continues operation standard mode. Device reset clears HALTX bit. Receive Autobuffering Enable Bit. When BRE=1, autobuffering enabled receiver. When BRE=0, autobuffering disabled operates Standard Mode. BRE=0 upon device reset. indicates which half receive buffer been received read when RINT interrupt occurs (interrupt program polling). RH=0 indicates that first half buffer been received, RH=1 indicates that second half buffer been received. Device reset clears bit. HALTR When HALTR=1, autobuffering halted when current half buffer been received. same time, SPCE register cleared serial port continues operation standard mode. Device reset clears HALTR bit.
value SPCE upon device reset 0000000000000011b
1.2.3.2
Autobuffering Process
Buffers autobuffering reside internal words block 'C54x internal memory. address size buffers within this block user programmable thanks 11-bit address registers (AXR ARR) 11-bit block size registers (BKX BKR). Transmit receive reside same area which allows transmitting buffer while receiving same buffer, overlapping areas different areas. Note that when 11-bit memory mapped registers read form 16-bit word, most significant bits read zeroes.
1-56
Buffered Serial Port (BSP)
Circular addressing auto buffered operation. Mechanism same transmit receive. each direction (transmit receive), registers specifying buffer size current address buffer. These registers transmit, receive. registers fully specifying bottom buffer. Figure 1-52 illustrates relationship between block size register type address register type), bottom circular buffer (BBA) circular buffer (TBA). register contains exact size buffer. split into parts; higher part (BKH) corresponds most significant bits range with bits equal lower part remaining bits with most significant position (position position defining parts (ARH ARL) address register. buffer address (TBA) defined concatenation with (N+1) bits equal least significant bits. bottom buffer address (BBA) concatenation minus (Figure 1-52). circular buffer size must then start N-bit boundary (i.e.,N least significant bits address register where smallest integer that satisfies 2**(N+1) (BK) must starts address 'C54x internal memory block. buffer consists halves, address range first half [0,BKL/2-1] [BKL/2,BKL-1] second half (Figure 1-52).
Serial Ports
1-57
Buffered Serial Port (BSP)
Figure 1-52. Circular Addressing Registers
ARH|0----0 Buffer
FIRST HALF
register ARH|BKL>>1 0---------10 SECOND HALF Second Half Start
register ARH|BKL
Bottom Buffer
Notes:
Minimum size Maximum size 2047, such buffer needs start relative address 0x0000. buffer size 1024 needs start relative address 0x0000. address pointer (AXR ARR) initialized with value that does with acceptable buffer range, pointer will incremented until meets next permitted buffer start address (see example below).
Example transmit buffer size (BKX=5) receive buffer size (BKR=8) described Figure 1-53. Transmit buffer start relative address that multiplier (address 0x0000,0x0008,0x0010,0x0018 0x07f8), receive buffer start relative address that multiplier (0x0000,0x0010,0x0020 ,0x07f0). this example, transmit buffer starts relative address 0x0008 receive buffer starts relative address 0x0010. pointer initialized with value [0x0008-0x000c] range pointer initialized with value [0x0010-0x0017] range. this example, initialized with value 0x000D (not modulo acceptable buffer), will incremented until reaches address 0x0010 which acceptable value modulo buffer.
1-58
Buffered Serial Port (BSP)
Figure 1-53. Example Transmit Buffer Receive Buffer Mapping
0x0000
Transmit
0x0008 0x000A 0x000c
0x0010 Receive 0x0014 0x0017
autobuffering process described Figure 1-54 transmit Figure 1-55 receive. When process activated upon request from (XRDY=1 RRDY=1), four actions performed, first 'C54x internal memory access, second address register update, third decision interrupt last auto disabling management. Interrupt generated when first half buffer second half buffer processed. Flags SPCE register allow user know which half been processed when interrupt occurs. When auto disabling (HALT set), then when next buffer boundary found, autobuffering enable SPCE (BXE BRE) cleared that autobuffering stopped does generate further request. When transmit autobuffering stopped, some data still sent (current contents last value loaded DXR). Then operation must stopped. user wants know that transmission actually ended, test condition XRDY=1 XSREMPTY=0 which will occur after last been transmitted.
Serial Ports
1-59
Buffered Serial Port (BSP)
Figure 1-54. Autobuffering Process Transmit
(AXR) ;memory access AXRL ;increment address
(AXRL=BKXL>>1) (AXRL=BKL) Then Generate XINT; Buffer boundary XRDY XRST BUF_X (AXRL=BKXL>>1) Then ;first half emptied Else ;buffer wrap around Endif (HALTX Then Endif Endif ;disconnect ;second half emptied
1-60
Buffered Serial Port (BSP)
Figure 1-55. Autobuffering Process Receive
(ARR) ARRL RRDY BRWE RRST BUF_R ;memory access ;increment address
(ARRL=BKRL>>1) (ARRL=BKRL) Then Generate RINT; Buffer boundary (ARRL=BKRL>>1) Then ;first half filled Else ;buffer wrap around ;second half filled Endif (HALTR Then Endif Endif ;auto disabling
;disconnect
1.2.4
Initialization Operation
order start restart operation given mode, following steps done through software. Assumption made that transmit receive interrupts used, polling (Interrupt flag register) could also used. Both transmit receive sections initialized same time.
Transmit Interrupt Initialization
INto have global disabling interrupts Enable transmit interrupt (Interrupt Mask register)
Transmit mode selection Configure mode writing register with XRST Configure additional modes required writing SPCE register
Once mode been internal hardware initialized. serial port clock provided externally mode internal clock (MCM=1) only receiver started (RRST transmit line (DX) high impedance line high impedance.
Serial Ports
1-61
Buffered Serial Port (BSP)
Start Operation
Clear transmit pending interrupt (Interrupt Flag Register) Initialize address pointers (ABU auxiliary registers) Start transmit operation writing XRST=1 register auto buffered mode, load first word transmit DXR. auto buffered mode, this will automatically done. INto have global enabling interrupts
Receive Interrupt Initialization INto have global disabling interrupts Enable receive Interrupt (Interrupt Mask register)
Receive Mode Selection Configure mode writing register with RRST Configure additional modes required writing SPCE register
Once mode been internal hardware initialized.
Start operation Clear receive pending interrupt (Interrupt Flag Register) Initialize address pointers (ABU auxiliary registers) Start receive operation writing RRST=1 register INto have global enabling interrupts
1.2.4.1
Clock Synchronization
(Serial Port Interface) operating with clocks that asynchronous with 'C54x internal clock that reach frequencies high 'C54x operating frequency. order achieve this performance, transmit receive operation start event done software (transition XRST RRST from needs re-synchronized with clock (CLKX CLKR). Once this synchronization occurred, operate with respect clock (CLKX CLKR). order achieve synchronization, clock periods CLKX CLKR) needed after transition XRST RRS. transmit, this valid with external internal clock. modes except transmit with internal frame (TXM=1), these cycles will result frame signal (FSX FSR)
1-62
Buffered Serial Port (BSP)
ignored frame signal events (transitions) occur during these cycles. transmit mode with internal frame (TXM=1), data ready transmitted after XRST transition, frame will constructed after CLKX period delay first transmission. Examples here below illustrating ignored frame pulses synchronization. Polarities FSP=0 CLKP=0. Example Figure 1-56 external frame (TXM=1) external clock mode (MCM=0) transmit operation. this example, pulse occurs during cycles synchronization window, resulting frame ignored (FSX pulse will initiate transmission, stays high impedance).
Figure 1-56. Pulse Occurs During Synchronization Window
CLKX
Xrst_sync
XRST
Example Figure 1-57 receive operation. this example, pulse occurs during cycles synchronization window, resulting frame ignored (FSR pulse will initiate reception). this case CLKR clock applied conjunction with (CLKR active before pulse), next pulse following RRST transition ignored.
Figure 1-57. Pulse Occurs During Synchronization Window
CLKR
Rrst_sync RRST
Serial Ports
1-63
Buffered Serial Port (BSP)
1.2.4.2
Memory-Mapped Registers Interrupt Locations
Memory-mapped registers: Address 0x20 Address 0x21 Address 0x22 SPCE Address 0x23 Address 0x38 Address 0x39 Address 0x3A Address 0x3B Interrupt locations:
Data Receive Register Data Transmit Register Serial Port Control Register Control Extension Register Transmit Address Register Transmit Buffer Size Register Receive Address Register Receive Buffer Size Register
1.2.4.3 Examples
receive interrupt vector located address 0x50. associated mask/flag number within IMR[0:15] IFR[0:15] registers. transmit interrupt vector located address 0x54. associated mask/flag number within IMR[0:15] IFR[0:15] registers.
examples given here below, entry conditions are: page page (DP=0) interrupts disabled (INTM=1).
Standard Mode Example 1-3.Transmit Burst Mode With External Frame (External Clock Format bits; Polarities=0; Mode Off)
#020h,IMR S#XTOP,AR1 *AR1+,A S#08h,SPC S#080h,SPCE
#020h,IFR
;enable transmit interrupt (XINT) ;init pointer with buffer ;address ;load accumulator with first word ;transmit ;reset configure serial port ;configure serial port SPCE register
;clear latched transmit interrupt
#040h,SPC STLM A,DXR
RSBX
1-64
IN
;start transmit part ;load first word transmit data ;transmit register (makes XRDY=0 that interrupt generated when ;FSX gets active) ;enable interrupts
Buffered Serial Port (BSP)
Example 1-4.Transmit Continuous Mode With Internal Frame (Internal Clock 1/16 CLKOUT Frequency; Polarities Format= Bits; Mode Off)
#020h,IMR S#XTOP,AR1 *AR1+,A S#034h,SPC S#08Fh,SPCE
#020h,IFR
;enable transmit interrupt (XINT) ;init pointer with buffer ;address ;load accumulator with first word ;transmit ;reset configure serial port ;configure serial port SPCE register
;clear latched transmit interrupt
#040h,SPC
STLM A,DXR
;start transmit part
;load first word transmit data ;transmit register (this makes XRDY=0 that interrupt generated when ;FSX gets active). This write ;generates FSX.
RSBX
IN
;enable interrupts
Example 1-5.Receive Burst Mode (Format= Bits; Polarities=1)
#010h,IMR S#RTOP,AR2 S#08h,SPC S#060h,SPCE #010h,IFR #080h,SPC RSBX IN;enable receive interrupt ;init pointer with buffer ;address ;reset configure serial port ;configure serial port SPCE register ;clear latched receive interrupt ;start receive part ;enable interrupts
Example 1-6.Receive Continuous Mode (Polarities Format= Bits; Frame Ignore Set)
#010h,IMR S#RTOP,AR2 S#04h,SPC S#0160h,SPCE #010h,IFR #080h,SPC RSBX IN;enable receive interrupt ;init pointer with buffer ;address ;reset configure serial port ;configure serial port SPCE register ;clear latched receive interrupt ;start receive part ;enable interrupts
Serial Ports
1-65
Buffered Serial Port (BSP)
Autobuffering Mode
Example codes shown below initialization ABU.
Example 1-7.Transmit Burst Mode With External Frame,External Clock Format= bits, Polarities=0, Mode
#020h,IMR S#08h,SPC S#01480h,SPCE S#XTOP,AXR S#XSIZE,BKX
#020h,IFR
;enable transmit interrupt (XINT) ;configure serial port register ;(XRST=0) ;configure serial port SPCE register ;init address buffer start ;init size buffer
;clear latched transmit interrupt
#040h,SPC RSBX IN
;start transmit part (SPI=1) ;enable interrupts
Transmit autobuffering transmission halts when half buffer transmitted (HALTX=1).
Example 1-8.Receive Continuous Mode Polarities Format= Bits, Frame Ignore Set, Receive Autobuffering Enabled
#010h,IMR S04h,SPC S#02160h,SPCE SRTOP,ARR S#RSIZE,BKR v#010h,IFR #080h,SPC RSBX IN;enable receive interrupt (RINT) ;reset configure serial port ;(RRST=0) ;configure serial port SPCE register ;init pointer with buffer ;address ;init size receive buffer ;clear latched receive interrupt ;start receive part ;enable interrupts
1.2.5
Operation During IDLE2
IDLE2 power down mode that invoked executing "IDLE instruction. During IDLE2 there complete shutdown core activities halted. on-chip peripheral circuits (timer, standard serial port) also stopped. Buffered Serial Port exception. receive side Buffered Serial Port will continue operate during IDLE2. transmit side Buffered Serial Port will continue operate during IDLE2 following conditions:
1-66
serial port clock CLKX frame external signals. serial port clock CLKX external signal, serial port frame internal generated before IDLE2 instruction executed, transmission continuous mode.
Buffered Serial Port (BSP)
ensure that pulse generated, there must minimum cycles assembler code between instruction which starts transmission "IDLE instruction. Once IDLE2 mode entered, extra pulses will generated from DSP. autobuffering mode, XINT transmit interrupt RINT receive interrupt used terminate IDLE2 power-down mode. These interrupts generated when first half buffer second half buffer processed. When programmed standard mode, XINT RINT interrupts also used terminate IDLE2 state. standard mode, these interrupts generated when word processed. either case (autobuffering standard mode), XINT RINT must enabled register wake whole device. INTM=0, processor enters corresponding interrupt service routine. INTM=1, processor continues with instruction following IDLE2 instruction.
Serial Ports
1-67
Time-Division-Multiplexed (TDM) Serial Port
Time-Division-Multiplexed (TDM) Serial Port
(time-division-multiplexed) serial port allows `C54x device communicate serially with seven other devices. port, therefore, provides simple efficient interface multiprocessing applications. serial port superset serial port described Section 1.1. means TSPC control register, port configured multiprocessing mode (TDM=1) stand-alone mode (TDM=0). When stand-alone mode, port operates described Section 1.1. When multiprocessing mode, port behaves described this section. port shut down power consumption XRST RRST bits, described Section 1.1.
1.3.1
Basic Operation
Time-division multiplexing division time intervals into number subintervals, with each subinterval representing communications channel according prespecified arrangement. Figure 1-58 shows 4-channel scheme. Note that first time slot labeled chan (channel next chan (channel etc. Channel active during first communications period during every fourth period thereafter. remaining three channels interleaved time with channel shown figure.
Figure 1-58. Time-Division Multiplexing
Full Interval (frame) Word Transfer Interval chan chan chan chan chan chan chan chan chan chan chan
time
'C54x port uses eight channels. Which device transmit, which device devices is/are receive each channel independently specified. This results high degree flexibility interprocessor communications.
1-68
Time-Division-Multiplexed (TDM) Serial Port
1.3.2
Serial Port Interface Operation
Figure 1-59(a) shows 'C54x port architecture. eight devices placed four-wire serial bus. This four-wire consists conventional serial port's clock, frame, data (TCLK, TFRM, TDAT) wires plus additional wire (TADD) that carries device addressing information. Note that TDAT TADD signals bidirectional signals often driven different devices during different time slots within given frame operation.
Figure 1-59. Four-Wire
Device Device Device TFRM TADD TCLK TDAT TFSX TFSR TCLKX TCLKR TFRM TADD TCLK TDAT
'C54x
TADD line, which driven particular device particular time slot, determines which device(s) configuration should execute valid receive during that time slot. This similar valid serial port read operation, described Section 1.1, except that some corresponding registers named differently. receive register TRCV, receive shift register TRSR. Data transmitted bidirectional TDAT line. Note that Figure 1-59(b). device pins tied together externally form TDAT line. Also, note that only device drive data address line (TDAT TADD) particular slot. other devices' TDAT TADD outputs should high-impedance state during that slot, which accomplished through proper programming port conSerial Ports
1-69
Time-Division-Multiplexed (TDM) Serial Port
trol registers (this described detail later this section). Meanwhile, that particular slot, devices (including driving that slot) sample TDAT TADD lines determine current transmission represents valid data read devices (this also discussed detail later this section). When device recognizes address which supposed respond, valid read then occurs, value transferred from TRSR TRCV register. receive interrupt generated, which indicates that TRCV valid receive data read. port operations synchronized TCLK TFRM signals. Each them generated only device (typically same device), referred TCLK TFRM source(s). word master used here because implies that device controls other, which case, TCSR must prevent slot contention. Consequently, remaining devices configuration these signals inputs. Figure 1-59(b) shows that TCLKX TCLKR externally tied together form TCLK line. Also, TFRM TADD originate from TFSX TFSR pins respectively. This done make serial port also easy standard mode. port operation controlled memory-mapped registers. layout these registers shown Figure 1-60. TRCV TDXR registers have same functions registers respectively, described Section 1.1. TSPC register identical register except that zero serves mode enable control TSPC. This configures port mode (TDM=1), stand-alone mode (TDM=0), which port operates standard serial port described Section 1.1. Refer subsection 1.2.2 additional information about function bits these registers.
TRCV TDXR TSPC Receive Data Transmit Data FREE SOFT XRDY RRDY RRST XRST TCSR TRTA TRAD
Figure 1-60. Port Registers
When mode selected, bits TSPC hard-configured resulting access digital loopback mode fixed word length bits different type loopback discussed example subsection 1.3.5). Also, value does affect port when TDM=1, states underflow overrun flags indeterminate
1-70
Time-Division-Multiplexed (TDM) Serial Port
(subsection 1.3.4 explains errors handled mode). TDM=1, changes made contents TSPC become effective upon completion channel current frame. Thus TSPC value cannot changed current frame; changes made will take effect next frame. source device TCLK TFRM timing signals bits, respectively. TCLK source device identified setting TSPC register Typically, this device same that supplies port clock signal TCLK. TCLKX configured input MCM=0 output MCM=1. latter case (internal 'C54x clock), device whose MCM=1 supplies clock (TCLK frequency=one fourth CLKOUT1 frequency) devices bus. clock supplied external source MCM=0 devices. TFRM also supplied externally TXM=0. external TFRM, however, must meet receive timing specifications with respect TCLK proper operation. more than device should have given time. specification which device supply clock framing signals typically made only once, during system initialization. channel select register (TCSR) given device specifies which time slot(s) that device transmit. more bits TCSR sets transmitter active during corresponding time slot. Again, system-level constraint that more than device transmit during same time slot; devices check contention, slots must consistently assigned. TSPC operation, write TCSR during particular frame valid only during next frame. However, given device transmit more than slot. This discussed more detail subsection 5.6.3, with emphasis utilization TRTA, TDXR, TCSR this respect. receive/transmit address register (TRTA) given device specifies pieces information. lower half specifies receive address device, while upper half TRTA specifies transmit address. receive address (LSB refer Figure 1-60) 8-bit value that device compares 8-bit value samples TADD line particular slot determine whether should execute valid receive. receive address, therefore, establishes slots which that device receive, dependent addresses present those slots, specified transmitting devices. This process occurs each device during every slot. transmit address, (LSB TA7, refer Figure 1-60), address that device drives TADD line during transmit operation assigned slot. transmit address establishes which receiving devices execute valid receive driven data.
Serial Ports
1-71
Time-Division-Multiplexed (TDM) Serial Port
Only device time drive transmit address TADD. Each processor bit-wise-logically-ANDs value samples TADD line with receive address (RA7-RA0). this operation results nonzero value, then valid receive executed processor(s) whose receive addresses match transmitted address. Thus, device transmit another, there must least upper half transmitting device's TRTA (the transmit address) with value that matches with value lower half TRTA (the receive address) receiving device. This method configuration TRTA allows device transmit more devices, device receive from more than transmitter. This also allow transmitting device control which devices receive, without receive address devices having changed. receive address register (TRAD) contains various information regarding status TADD line which polled verify previous values this signal verify relationship between instruction cycles port timing. Bits 13-11 (X2-X0) contain current slot number value, regardless whether valid data receive executed that slot not. This value latched middle slot retained only until middle slot. Bits 10-8 (S02-S0) hold number last slot plus (module eight) which data received (that last valid data read occurred slot five previous frame, these bits would contain number six). This value latched during receive interrupt (TRNT) slot which last valid data receive occurred, maintained until next slot which valid receive occurs. Bits (A7-A0) hold last address sampled TADD line, regardless whether valid data receive executed not. This value latched halfway through each slot value TADD shifted maintained until halfway through next slot, whether valid receive executed not.
1.3.3
Mode Transmit Receive Operations
Figure 1-61 shows timing port transfers. TCLK TFRM signals generated timing source device. TCLK frequency fourth frequency CLKOUT1 generated 'C54x device. TFRM pulse occurs every TCLK cycles, timed coincide with zero slot seven, with last previous frame. relationship TFRM TCLK allows data bits each eight time slots driven TDAT line, which also permits processor execute maximum
1-72
Time-Division-Multiplexed (TDM) Serial Port
instructions during each slot, assuming that 'C54x internal clock used. Beginning with slot zero with first, transmitter drives data bits each slot, with each having duration TCLK cycle, with exception first each slot, which lasts only half time. Note that data both clocked onto TDAT line transmitting device sampled from TDAT line receiving devices rising edge TCLK (refer Appendix detailed interface timings).
Figure 1-61. Serial Port Timing Mode
TCLK TDAT TADD TFRM
Simultaneous with data transfer, transmitting device also drives TADD line with transmit address each slot. This information, unlike that TDAT, only byte long transmitted with first first half slot. During second half slot (that last eight TCLK periods) TADD line driven low. receive logic samples TADD line only first eight TCLK periods, ignoring during second half slot. Therefore, transmitting device 'C54x) could drive TADD high during that time period. Note that, like TDAT, first TADD transmitted lasts only half TCLK cycle. device configured transmit slot (that none devices corresponding slot their TCSR register), that slot considered empty. empty slot, both TADD TDAT high impedance. This condition potential spurious receives, howe
Other recent searches
SPX29500 - SPX29500 SPX29500 Datasheet
RPM872 - RPM872 RPM872 Datasheet
HV9921 - HV9921 HV9921 Datasheet
GALI-6F+ - GALI-6F+ GALI-6F+ Datasheet
DPS50 - DPS50 DPS50 Datasheet
2SD2391 - 2SD2391 2SD2391 Datasheet
2SA733 - 2SA733 2SA733 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
