Shaku Anjanaiah Digital Signal Processing Solutions This document

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Shaku Anjanaiah Digital Signal Processing Solutions This document

Datasheet Thumbnail

Top Searches for this datasheet

TMS320C6000 McBSP Highway
Shaku Anjanaiah Digital Signal Processing Solutions
This document describes multi-channel buffered serial ports (McBSP) Texas Instruments (TITM) TMS320C6000 digital signal processors (DSP) used communicate time division multiplexed (TDM) data highway. provides multiple devices time slot performing data transfer. Thus multiple users multiple channels, each user channel(s) assigned transmission reception. McBSP support channels multi-channel mode. Each these channels enabled disabled software order communicate only those time slots that supposed When multiple users connected same data lines, contention issue during transmission. Although each device connected this highway channel assignment, possible that next device getting contend with last bit(s) previous channel. workaround this data contention problem addressed this document considering multiple McBSPs connected single data line.
Digital Signal Processing Solutions
November 1998
Contents
TMS320C6000 McBSP Highway Design Problem.3 Application Multi-channel Operation Overview Problem Description Software Solution.5 McBSP Initialization Conclusion
Figures
Figure Multiple McBSPs Time-Division Multiplexed Figure Sub-frames, Partitions, Channels Multi-channel Frame.4 Figure Timing Multichannel Operation Figure Three 'C6201s bus.6 Figure Dummy channel prevent Bus-contention.8
Tables
Table Switching characteristics Output 'C6201 McBSP.5 Table Data Transmission Setup Table Data Reception Setup
TMS320C6000 McBSP Highway
TMS320C6000 McBSP Highway Design Problem
multi-channel buffered serial port (McBSP) communicate over Time Division Multiplexed (TDM) data highway without contention?
Figure Multiple McBSPs Time-Division Multiplexed
'C6000 McBSP
Highway
'C6000 McBSP 'C6000 McBSP
Application
Multiple DSPs connected single communicate specific information specific group DSPs. Typical application would messaging, broadcasting, passing channels processed data required DSPs further processing simply data input. data transfer achieved using programmable McBSP DMA. serial port pins used data transfer, whereas CLK(R/X), FS(R/X) serve control signals clocking synchronization. responsible retrieving data from McBSP receiver storing in_buffer. then process in_buffer data required make available out_buffer write transmitter. important configure each send receive channels data certain time slots. This known time division multiplexing (TDM) ensures proper allocation data particular channels retrieval this data required DSP. Since there address lines used, multi-channel operation McBSP helps identifying destination data transit. DSP-specific message sent known channel, destination listens this channel enabling appropriate receive channel enable bit(s).
TMS320C6000 McBSP Highway
Multi-channel Operation Overview
McBSP perform multi-channel selection operation single-phase frames. Single-phase frames characterized group elements that have same element size. maximum number elements frame same number channels, which equal 128. Therefore each frame represents time-division multiplexed data stream with channels. programmable control registers McBSP specific multi-channel operation makes communication highway possible. They Multi-channel Control Register (MCR), Transmit Channel Enable Register (XCER), Receive Channel Enable Register (RCER). These registers explained detail TMS320C6201/C6701 Peripherals Reference Guide. channels frame divided into eight 16-channel sub-frames shown Figure Each channel have programmable data sizes (8-, 12-, 16-, 20-, 32-bits). channels frame have same data size. Odd-numbered sub-frames constitute Partition (represented (R/X)PABLK), even-numbered belong Partition (represented (R/X)PBBLK). Each channels enabled disabled both transmit receive. This achieved 32-bit (R/X)CER register. Therefore, channels enabled consecutive sub-frames, Partition Partition Channels enabled disabled time long does belong current active) sub-frame. active sub-frame viewed that time slot where transmission reception taking place. example, data transfer ongoing subframe (channels 32-47 (R/X)PABLK=1), lower 16-bits channel enable registers (which correspond Partition should changed since they would affect enabling current channels. This ensured using current block status bits (R/X)CBLK MCR.
Figure Sub-frames, Partitions, Channels Multi-channel Frame
SUB-FRAME (R/X)PABLK PARTITION (R/X)PBBLK PARTITION FS(R/X) 0-15 16-31 32-47 48-63 64-79 80-95 96-111 112-127 0-15
Problem Description
When multiple devices transmit over same line, care should taken avoid contention simultaneous overlapped write accesses more devices. Contention during transmission avoided ensuring enough dead time between last write device first write access next device.
TMS320C6000 McBSP Highway
Basically, disable time (tdis(CKXH-DXZ)) output should much smaller than enable delay time (td(CKXH-DX)) output next device avoid data collision. This shown Tdead Figure defined Tdead td(CKXH-DX) tdis(CKXH-DXZ)
Figure Timing Multichannel Operation
CLKX tdis(CKXH-DXZ) Tdead td(CKXH-DX) CPU2: Bit(n-1)
CPU0:
td(CKXH-DX) CPU2: Bit(n-2)
td(CKXH-DX) CPU2: Bit(n-3)
timing parameters their values `C6000 McBSP output datasheet shown Table inferred from timing numbers McBSP that delay time disable time same. Therefore, McBSPs transmitted successive channels, there contention. following sections will describe workaround this problem.
Table Switching characteristics Output 'C6201 McBSP
tdis(CKXH-DXZ) PARAMETER Disable time, CLKX high high impedance following last data Delay time, valid after CLKX high. first data bit, this assured design delay time data become impedance. CLKX CLKX td(CKXH-DX) CLKX CLKX UNIT
Software Solution
contention problem lack control output buffer's turn-on (delay) turn-off (disable) time. Contention avoided programming McBSP transfer extra (dummy) element channel than what necessary. This additional (dummy) channel should disabled XCER register since does represent data interest. disabled channel high-impedance state. dummy channel will provide necessary dead time between transfers from McBSPs thus prevent contention. Consider example where McBSP each three DSPs connected shown Figure Assume DSP1 clock frame master. Therefore DSP1 generates transmit receive clocks, transmit receive frame syncs. Figure D(R/X)00 represents D(R/X) pins McBSP0 DSP0. Similarly D(R/X)01 D(R/X)02 correspond McBSP0 DSP1 DSP2. this example, DX00 occupies sub-frame DX01 occupies sub-frame DX02 sub-frames receive side, DR00 listens sub-frame DR01 receives channels sub-frame lastly DR02 receives sub-frame
TMS320C6000 McBSP Highway
Figure Three 'C6201s
DSP0
DR00;; 16-31, 48-71 Highway DX01;; 17-31 DX00;; ch0-15, dummy DR02;; 0-15, 16-31 DR01;; 0-15, 48-63
DSP2
DX02;; 48-71 dummy
DSP1 Clock Frame Master
actual channels time slots) which each McBSPs transmit receive listed Table Table respectively. this available channels considered data transfer. Among these channels, only some enabled transmission reception. this example, some/all channels sub-frame enabled whereas sub-frame corresponding channels 3247 used therefore disabled. selectively choose channels, appropriate multi-channel mode chosen. this example, XMCM=RMCM=1 will suit application. (R/X)MCM=1 mode disables channels default, required channels enabled 16-channel sub-frames (R/X)P(A/B)BLK channel enable registers (R/X)CER.
Transmission
Since DSP1 clock frame master, will programmed generate frame sync every channels. frame period (FPER) depends serial element size frame number elements channels frame. DSP0 DSP2 slaves, therefore will start their respective data transfer upon receiving frame clock from master DSP1.
TMS320C6000 McBSP Highway
Table Data Transmission Setup
DSP# DSP#0 DX00 Sub-frame/ XP(A/B)BLK Sub-frame XPABLK XPBBLK Channels Transmitted Sub-frame channels: 0-15;; Enabled channels (XPABLK): 015;; Dummy channel: 16;; Disabled channels: others;; DSP#1 DX01 Sub-frame XPBBLK Sub-frame channels: 16-31;; Enabled channels (XPBBLK): 20-23; 25,27; 28-31;; Disabled channels: others;; DSP#2 DX02 Sub-frames XPBBLK Sub-frame channels: 48-63 64-79;; Enabled channels (XPBBLK): 52-54; 63;; Enabled channels (XPABLK): 6470;; Dummy channel: 71;; Disabled channels: others;; Assume transmit receive data delay frame sync from master initiates data transmission DSP0 since DSP0 enabled transmission channels 0-15. first data available clock after frame sync active. same time, DSP1 DSP2 enabled receive some channels sub-frame Note that more than device receive same channel(s). Now, next sub-frame (channels 16-31), DSP1 transmits starting from channel DSP0 programmed (channels 0-16) serial elements last element will disabled that will driven high-impedance state. This configuration because channel dummy channel prevent contention between DSP0 XCER 0xB55B007F XCER 0xFAFA0000 XCER 0x0000FFFF Register Value
XPABLK
TMS320C6000 McBSP Highway
Figure Dummy channel prevent Bus-contention
CLKX XDATDLY=1 Tdead Ch70: Ch71:Bn-B0 Dummy Channel (CPU2) Ch0:(n-1) Tdead Ch16:(n Dummy Channel (CPU0) Ch17:(n-1) Ch71:Bn-B0 Dummy Channe (CPU2)
transmission reception continues enabled channels channel Soon after channel transmitted DSP2, next frame starts channel This configuration because FPER programmed ((data-size bits also data delay This provides gaps between frames, which known maximum packet frequency. Since channel enabled, this again leads successive channels (channel channel being driven resulting contention. Therefore channel dummy channel therefore must disabled.
Reception
receive section DSP0, receive channel interest without restrictions overlapping channels shown Table However, note that DSP0 receives channels from sub-frames Sub-frame belong partition (RPBBLK) sub-frame RPABLK. Note that channels enabled subframe cannot changed when current transfer. Therefore, when DSP0 receiver sub-frame with particular channels enabled (via RCER RPBBLK RCER cannot changed order ready next sub-frame which falls under same partition. But, before sub-frame arrives, receiver should enabled appropriate channels (56, this case). this, current block status bits RCBLK Multi-channel Control Register (MCR) probed find current partition progress. RCBLK does point block then RCER programmed channel enabling sub-frame This also done transmit side using XCBLK, required.
Table Data Reception Setup
DSP# DSP#0 DR00 Sub-frame/ RP(A/B)BLK Sub-frames RPBBLK Channels Received Sub-frame channels: 16-31, 4863, 64-71;; Enabled channels (RPBBLK): 27;; Enabled channels (RPBBLK): RCER 0x05000000 Register Value
RCER 0x0A000000
TMS320C6000 McBSP Highway
RPBBLK RPABLK
58;; Enabled channels (RPABLK): 6470;; Disabled channels: others
RCER 0x0000007F
DSP#1 DR01
Sub-frames RPABLK
Sub-frame channels: 0-15, 4863;; Enabled channels (RPABLK): 07;; Enabled channels (RPBBLK): 52-54; 63;; Disabled channels: others;;
RCER 0xB05B00FF
RPBBLK
DSP#2 DR02
Sub-frames RPABLK
Sub-frame channels: 0-15, 1631;; Enabled channels (RPABLK): 015;; Enabled channels (RPBBLK): 20-23; 28-31;; Disabled channels: others;; RCER 0xF0FAFFFF
RPBBLK
McBSP Initialization
typical applications, consider that services McBSP. McBSP initialization procedure other typical applications described TMS320C6000 McBSP Initialization application note. following steps describe setup interrupts, DMA, McBSP required order example above. DSP0, DSP1, DSP2 McBSP0: Program Sample Rate Generator Register (SRGR), Serial Port Control Register (SPCR), Control Register (PCR), Receive Control Register (RCR), Multi-channel Control Register (MCR), Receive/Transmit Channel Enable Registers ((R/X)CER) required values. Caution: /GRST SPCR this step. Take DSP1's sample rate generator reset setting /GRST=1 SPCR. /GRST required DSP0 since clocks frames inputs, therefore sample rate generator used McBSP0. Enabling Interrupts: interrupts, have Global Interrupt Enable (GIE), Non-Maskable Interrupt Enable (NMIE) bits IER. receiver DSP0, end-of-subframe interrupt (RINTM=01b) used determine 16-channel sub-frame thereby change channel enabling even numbered sub-frame (see first Table Select channel want use. Enable interrupts that correspond channel that will used service McBSP. default mapping channel-complete interrupts used.
TMS320C6000 McBSP Highway
initialization: Program source/destination registers, primary control register required operation. Instruct run. example, START=01b channel's primary control register start without auto-initialization. Take transmitter receiver slave DSPs reset. They will await clock (CLKR/X) frame sync (FSR/X) from master DSP1. Take transmitter receiver master (DSP0) reset. /FRST=1 DSP1. This causes first frame sync output FS(R/X) after bit-clocks.
Conclusion
Multiple `C6x devices connected multi-processor environment with them clock frame master. This achieved using time-division multiplexing McBSP interface using multi-channel mode. programmable features multi-channel mode McBSP such channel enabling, detection current block that next similar-numbered (odd even) sub-frame channels enabled, various ways enabling unmasking channels (R/X)MCM bits make complex multi-channel applications simple.
TMS320C6000 McBSP Highway
Appendix Sample Code
tdm_mc1.c: Sample testcase apnote. McBSP0 configured master frame syncs clocks both transmit receive. McBSP0 transmits receives some channels between This selection enabled (R/X)MCM modes channel enable register (R/X)CER. #include "common.h" #define M0TO1 FALSE #define M1TO0 TRUE McBSP1 used #define #define #define #define CLKGDV1 FPER1 1023 FWID1 CLKSM1 CLK_MODE_CPU
#define M1TO0_MSTR TRUE #define XFER_SIZE #define XFER_TYPE DMA_XFER void void void void init_m0to1(void); init_M0_srgr(void); init_m1to0(void); init_M1_srgr(void);
void main(void) xfer_size; xfer_type; recv1_done FALSE; xmit1_done FALSE; mcsp1to0 M1TO0; mcsp0to1 M0TO1; xfer_size XFER_SIZE; xfer_type XFER_TYPE; SRGR values needed init_M1_srgr(); Now, initialize other control registers McBSP operation (mcsp1to0) init_m1to0();
TMS320C6000 McBSP Highway
Enable sample rate generator; /GRST=1 MCBSP_SAMPLE_RATE_ENABLE(1); Reset channels switch (xfer_type) case DMA_XFER: dma_reset(); set_interrupts();/* Initialize service McBSP (mcsp1to0) uses xmit recv*/ DMA0_SRC_ADDR MCBSP_DRR_ADDR(1); DMA0_DEST_ADDR (unsigned int) in1; REG_WRITE (DMA0_XFER_COUNTER_ADDR, xfer_size); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA0_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, DST_DIR, DST_DIR_SZ); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, SEN_REVT0, RSYNC, RSYNC_SZ); DMA_START(DMA_CH0); DMA2_SRC_ADDR (unsigned int) out1; DMA2_DEST_ADDR MCBSP_DXR_ADDR(1); REG_WRITE (DMA2_XFER_COUNTER_ADDR, xfer_size); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA2_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, SRC_DIR, SRC_DIR_SZ); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, SEN_XEVT0, WSYNC, WSYNC_SZ); DMA_START(DMA_CH2); SET_BIT (MCBSP_SPCR_ADDR(1), RRST); SET_BIT (MCBSP_SPCR_ADDR(1), XRST); SET_BIT (MCBSP_SPCR_ADDR(1), FRST); while (!xmit1_done !recv1_done); break; 0x00007000; PowerDown shut MCSP
void init_m1to0(void) Transmitter setup*/ LOAD_FIELD (MCBSP_PCR_ADDR(1), CLKX_POL_RISING, CLKXP, LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_POL_HIGH, FSXP, LOAD_FIELD (MCBSP_PCR_ADDR(1), M1TO0_MSTR, CLKXM, LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_MODE_INT, FSXM, SRGR setup LOAD_FIELD (MCBSP_SRGR_ADDR(1), FSX_FSG, FSGM, setup LOAD_FIELD (MCBSP_XCR_ADDR(1), SINGLE_PHASE, XPHASE,
TMS320C6000 McBSP Highway
LOAD_FIELD (MCBSP_XCR_ADDR(1), WORD_LENGTH_32, XWDLEN1, XWDLEN1_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(1), XFRLEN1, XFRLEN1_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(1), DATA_DELAY1, XDATDLY, XDATDLY_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(1), NO_COMPAND_MSB_1ST, XCOMPAND, XCOMPAND_SZ); setup Xmitter LOAD_FIELD (MCBSP_MCR_ADDR(1), XMCM_ENABLE, XMCM, XMCM_SZ); LOAD_FIELD (MCBSP_MCR_ADDR(1), XPABLK, XPABLK_SZ); ch0-15 LOAD_FIELD (MCBSP_MCR_ADDR(1), XPBBLK, XPBBLK_SZ); ch16-31 XCER setup enable xmit channels 15,13;;10,8;;7,5;;2,1 Partition enable xmit channels Partition SET_REG(MCBSP1_XCER, 0x9DADA5A6); Receiver setup*/ LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_POL_HIGH, FSRP, LOAD_FIELD (MCBSP_PCR_ADDR(1), M1TO0_MSTR, CLKRM, LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_MODE_INT, FSRM, setup LOAD_FIELD (MCBSP_RCR_ADDR(1), SINGLE_PHASE, RPHASE, LOAD_FIELD (MCBSP_RCR_ADDR(1), WORD_LENGTH_32, RWDLEN1, RWDLEN1_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), RFRLEN1, RFRLEN1_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), DATA_DELAY1, RDATDLY, RDATDLY_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), NO_COMPAND_MSB_1ST, RCOMPAND, RCOMPAND_SZ); setup Receiver LOAD_FIELD (MCBSP_MCR_ADDR(1), RMCM_ENABLE, RMCM, LOAD_FIELD (MCBSP_MCR_ADDR(1), RPABLK, RPABLK_SZ); ch0-15 LOAD_FIELD (MCBSP_MCR_ADDR(1), RPBBLK, RPBBLK_SZ); ch16-31 RCER setup enable recv channels Partition enable recv channels 15,14,12;;11,10,9;;23,22;;1,0 Partition SET_REG(MCBSP1_RCER, 0xDECADE03);
void init_M1_srgr(void) LOAD_FIELD (MCBSP_SRGR_ADDR(1), LOAD_FIELD (MCBSP_SRGR_ADDR(1), LOAD_FIELD (MCBSP_SRGR_ADDR(1), LOAD_FIELD (MCBSP_SRGR_ADDR(1), LOAD_FIELD (MCBSP_SRGR_ADDR(1), LOAD_FIELD (MCBSP_SRGR_ADDR(1), void set_interrupts(void) intr_init();
CLKGDV1, CLKGDV, CLKGDV_SZ); FWID1, FWID, FWID_SZ); FPER1, FPER, FPER_SZ); CLKSM1, CLKSM, CLKS_POL_RISING, CLKSP, GSYNC_OFF, GSYNC,
TMS320C6000 McBSP Highway
INTR_MAP_RESET(); Default interrupt mapping Hook interrupt service routine interrupt intr_hook (c_int11, CPU_INT11); intr_hook (c_int08, CPU_INT8); enable NMIE, default interrrupt corresponding channel INTR_ENABLE(CPU_INT_NMI);/* Enabl NMIE INTR_GLOBAL_ENABLE(); CSR*/ INTR_ENABLE(11); default interrupt corresponding channel INTR_ENABLE(8); return;
DATA TRANSFER COMPLETION ISRS interrupt void c_int11(void) xmit1_done TRUE; return; interrupt void c_int08(void) recv1_done TRUE; return;
/**************** tdm_mc1.c
COMMON.H V1.00 Copyright 1997 Texas Instruments Incorporated #include #include #include #include #include #include #include #include #include #include #include <dma.h> <emif.h> <intr.h> <timer.h> <cache.h> <hpi.h> <mcbsp.h> <regs.h> <stdio.h> <trgcio.h> <stdlib.h>
variables used tcase mcsp0to1;
TMS320C6000 McBSP Highway
mcsp1to0; volatile xmit1_done; volatile recv0_done; volatile xmit0_done; volatile recv1_done; #define CLKSTP_OFF #define CLKSTP_NO_DELAY #define CLKSTP_DELAY #define #define #define #define #define #define 0x00 0x02 0x03 0x00 0x01 0x02 0x03 0x00 0x01 CLKSTP mode disabled Clock starts without delay Clock starts with delay
XMCM_NO_SELECTION XMCM_ENABLE XMCM_UNMASK XMCM_SYM_ENABLE_UNMASK RMCM_NO_SELECTION RMCM_ENABLE
#define FALSE #define TRUE
BUFFERS DEFINED data6201.asm #define BUFFER_SIZE extern in1[BUFFER_SIZE]; extern out1[BUFFER_SIZE]; extern extern extern extern extern extern cregister cregister cregister cregister cregister cregister volatile volatile volatile volatile volatile volatile unsigned unsigned unsigned unsigned unsigned unsigned AMR; CSR; IFR; ISR; ICR; IER;
extern extern extern extern extern extern extern extern extern extern extern extern extern
interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt
void void void void void void void void void void void void void
c_nmi01(void); c_int04(void); c_int05(void); c_int06(void); c_int07(void); c_int08(void); c_int09(void); c_int10(void); c_int11(void); c_int12(void); c_int13(void); c_int14(void); c_int15(void);
#define DMA_XFER #define POLL_XFER #define INT_XFER #define GPIO #define DLB1 #define DLB2
TMS320C6000 McBSP Highway
#define #define #define #define #define #define #define #define #define #define
SPLIT_XFER HW_BYTE DMA_SPI DMA_STB DMA_MCM_FLY DMA_NEW_FRAMESYNC AUTO_INIT DMA_SORT SPLIT_SORT DMA_SYNCERR
#define DMA_BYTE #define DMA_HALFWORD extern void reset_mcbsp(void) slave wake before frame master that frames lost (mcsp0to1) (GET_BIT(MCBSP_PCR_ADDR(1), FSRM)) {/*(mcsp1->pcr.fsrm) SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(1), XRST); SET_BIT (MCBSP_SPCR_ADDR(1), FRST); else SET_BIT (MCBSP_SPCR_ADDR(1), RRST); SET_BIT (MCBSP_SPCR_ADDR(0), XRST); SET_BIT (MCBSP_SPCR_ADDR(0), FRST); (mcsp1to0) (GET_BIT(MCBSP_PCR_ADDR(0), FSRM)){ /*(mcsp0->pcr.fsrm) SET_BIT (MCBSP_SPCR_ADDR(1), XRST); SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(0), FRST); else SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(1), XRST); SET_BIT (MCBSP_SPCR_ADDR(1), FRST); extern void set_interrupts(void); extern void reg_dump(void);
/**************** common.h /**************** Begin data6201.asm
.global _in1, _out1 .data _out1: .eval
127,
TMS320C6000 McBSP Highway
.loop .word 0x80888880) sets bits check sign extension .word sign extension .eval .endloop _in1: .loop .word 0xDEADFACE .endloop
/**************** data6201.asm
TMS320C6000 McBSP Highway
INTERNET www.ti.com Register with TI&ME build custom information pages receive product updates automatically email.
Semiconductor Home Page http://www.ti.com/sc Distributors
PRODUCT INFORMATION CENTERS
Europe, Middle East, Africa Phone Deutsch +49-(0) 8161 3311 English +44-(0) 1604 3399 Francais +33-(0) 1-30 Italiano +33-(0) 1-30 +33-(0) 1-30-70 Email epic@ti.com Japan Phone International Domestic International Domestic Email Asia Phone International Domestic Australia
TMS320 Hotline email Americas Phone Email
+81-3-3457-0972 +0120-81-0026 +81-3-3457-1259 +0120-81-0036 pic-japan@ti.com
(281) 274-2320 (281) 274-2324 (281) 274-2323 dsph@ti.com +1(972) 644-5580 +1(972) 480-7800 sc-infomaster@ti.com
+886-2-3786800 1-800-881-011
Asia (continued) Number China Number Hong Kong Number India Number Indonesia Number Korea Malaysia Number Zealand Number Philippines Number Singapore Number Taiwan Thailand Number
-800-800-1450 10811 -800-800-1450 800-96-1111 -800-800-1450 000-117 -800-800-1450 001-801-10 -800-800-1450 080-551-2804 1-800-800-011 -800-800-1450 +000-911 -800-800-1450 105-11 -800-800-1450 800-0111-111 -800-800-1450 080-006800 0019-991-1111 -800-800-1450
Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain application using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. Copyright 1998, Texas Instruments Incorporated trademark Texas Instruments Incorporated. Other brands names property their respective owners.
IMPORTANT NOTICE
TMS320C6000 McBSP Highway

Shaku Anjanaiah Digital Signal Processing Solutions This document

Top Searches for this datasheet

Other recent searches