Shaku Anjanaiah Digital Signal Processing Solutions TMS320C6000 M

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Shaku Anjanaiah Digital Signal Processing Solutions TMS320C6000 M

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TMS320C6000 McBSP Interface
Shaku Anjanaiah Digital Signal Processing Solutions
TMS320C6000 Multi-channel Buffered Serial Port (McBSP) designed interface device that supports synchronous Serial Peripheral Interface (SPI). This document describes hardware interface between McBSP ROM. McBSP operates master user-specified clock stop (CLKSTP) mode order communicate with ROM. McBSP initialization control register programming also discussed.
Digital Signal Processing Solutions
July 1999
Contents
TMS320C6000 McBSP interface Solution. Configuration McBSP Initialization Timing Analysis Appendix
Figures
Figure McBSP Master interface slave device Figure Receive Control Register (RCR Master) Figure Transmit Control Register (XCR Master) Figure Sample Rate Generator Register (SRGR Master) Figure Control Register (PCR Master) Figure Serial Port Control Register (SPCR Master) Figure Clock Stop Mode Options Figure C6201 Master Timing, CLKSTP=11b, CLKXP=0
Tables
Table McBSP Register values 200MHz clock Table Timing Numbers McBSP Master. Table Timing Analysis Master Slave
TMS320C6000 McBSP Interface
TMS320C6000 McBSP interface
Design Problem
interface Serial Peripheral Interface (SPITM) TMS320C6201?
Solution
multi-channel buffered serial port (McBSP) TMS320C6000 interfaces with glue logic. system typically 4-wire interface comprising serial data serial data out, serial clock, device select. McBSP provides this 4-wire interface CLKX, pins, respectively. McBSP supports interface synchronous, full-duplex, variable element length (element length fixed given transfer), master slave mode back-to-back transmission reception. This feature achieved using clock-stop (CLKSTP) mode McBSP. This document discusses McBSP interface AtmelSPI serial CMOS EEPROM, which only slave. McBSP master, generates required control signals clocking slave.
Configuration
McBSP master interface, must configure CLKX pins serial port outputs only. CLKX generated either `C6000 clock external clock source input CLKS pin. mode, system clock other clock source drive CLKS present. clock divide down programmed application needs.
Figure McBSP Master interface slave device
`C6x McBSP Master CLKX SPI-compliant Slave MOSI MISO /HOLD
signal connectivity shown Figure connecting AtmelSPI serial CMOS EEPROM AT25 series which maximum clock rate range from 2.7V 5.5V. This slave device organized 1k/2k/4k/8k 8-bit data only supports modes
TMS320C6000 McBSP Interface
shown Figure CLKSTP scheme supports reception utilizing signals that correspond simultaneously receives data connecting CLKX signals internally. good practice, CLKR inputs.
back-to-back transmission transmitter. McBSP also outputs CLKR should programmed
McBSP Initialization
various McBSP control registers shown Figures through have initialized operation. serial port initialization procedure mode follows: McBSP reset state, /XRST /RRST SPCR. Program McBSP configuration registers XCR, RCR, SRGR, PCR, SPCR parameters required except CLKSTP bits SPCR. /GRST=1 SPCR sample rate generator reset. Wait CLKG clocks McBSP re-initialize. Write desired value into CLKSTP bit-fields SPCR. Figure shows various CLKSTP modes that supported McBSP. Either should followed. This step should performed used service McBSP. /XRST /RRST enable serial port. Note that value written SPCR this time should have only reset bits changed remaining bit-fields should have same value Step above. used perform data transfers, should first initialized with appropriate read/write syncs, src/dst addresses their update modes, transfer complete interrupt, other feature suitable application. Lastly, START bit. START state waits synchronization events occur. Then, pull McBSP reset. details initialization servicing McBSP, refer TMS320C6000 McBSP Initialization, TMS320C6000 Applications note.
Figure Receive Control Register (RCR Master)
RPHASE reserved RFRLEN2 RFRLEN1 RWDLEN1 RWDLEN2 RCOMPAND reserved RFIG RDATDLY
TMS320C6000 McBSP Interface
Figure Transmit Control Register (XCR Master)
XPHASE reserved XFRLEN2 XFRLEN1 XWDLEN1 XWDLEN2 XCOMPAND reserved XFIG XDATDLY
Figure Sample Rate Generator Register (SRGR Master)
GSYNC CLKSP CLKSM FSGM FWID FPER 0x5F CLKGDV
Figure Control Register (PCR Master)
0x0000 reserved XIOEN RIOEN FSXM FSRM CLKXM CLKRM CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP
Figure Serial Port Control Register (SPCR Master)
0x00 FRST22 GRST6 reserved XINXSYNCERR XEMPTY4 RIN3 RSYNCERR RFULL XRDY RRDY XRST0 RRST-
RJUST CLKSTP reserved reserved
Table McBSP Register values 200MHz clock
Register
SRGR
Value
0x00010000 0x00010000 0x2000005F
Description
single phase, 8-bit element frame, bit-clock delay single phase, 8-bit element frame, bit-clock delay serial clock CLKX generated clock (CLKSM=1) frame sync generated DXR-to-XSR transfer (FSGM=0) clock divide down clock generate 2.08 shift clock (CLKGDV=0x5F) active (FSXP=1) output (FSXM=1) active (FSRP=1) input (FSRM=0) CLKX output (CLKXM=1) starts with rising edge (CLKXP=0) CLKSTP=11b. Since CLKXP=0, this refers data transmitted rising edge received falling edge CLKX master. This parameter changed application needs.
0x00000A0C
SPCR[12:10]
TMS320C6000 McBSP Interface
example code Appendix initializes McBSP0 correct order SPI-mode communication between McBSP serial EEPROM.
Figure Clock Stop Mode Options
CLKX (CLKSTP=10b, CLKXP=0) CLKX (CLKSTP=11b, CLKXP=0) CLKX (CLKSTP=10b, CLKXP=1) CLKX (CLKSTP=11b, CLKXP=1) D(R/X) FS(R/X)
Timing Analysis
mode (0,0) corresponds McBSP mode with CLKSTP=11b CLKXP=0. master (McBSP) shifts data falling edge CLKX slave (SPI ROM) samples receive data rising edge CLKX. slave transmits/shifts data falling edge CLKX master samples receive data rising edge CLKX.
Figure C6201 Master Timing, CLKSTP=11b, CLKXP=0
CLKX Bit(n-1 (n-2) Bit(n-1)
(n-3)
(n-4)
(n-2)
(n-3)
(n-4)
timing diagram CLKSTP=11b, CLKXP=0 shown Figure corresponding values timing requirements switching characteristics 2.1MHz operation shown Table values derived from formula/numbers available TMS320C6201 datasheet.
TMS320C6000 McBSP Interface
Table Timing Numbers McBSP Master
th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) td(FXL-DXV) Switching Characteristics Hold time, after CLKX high Delay time, CLKX Delay time, CLKX high valid Disable time, high impedance following last data from CLKX high Delay time, valid =242 =243 UNIT
Timing Requirements tsu(DRV-CKXL) Setup time, valid before CLKX th(CKXL-DRV) Hold time, valid after CLKX NOTE: following true above calculations:
Since CLKGDV CLKX derived from clock will have duty cycle therefore H=L. Period CLKX, (1+CLKGDV) where 200MHz clock. Hence,
shown Table timing numbers McBSP match with that with sufficient timing margins. Note that timings correspond 2.7-5.5V range devices. Therefore voltage translation buffer (for example, SN54LVT16373) will have used between McBSP ROM. buffers will still meet necessary timing requirements/margins.
Table Timing Analysis Master Slave
Timing Requirements (min) Data Setup Time (min) Data Hold Time tcss(min) Setup time C6201 Timing Requirements tsu(DRV-CKXL)min Data Setup Time th(CKXL-DRV)min Data Hold Time C6201 Switching Characteristics td(FXL-CKXL)min td(FXL-DXV)max td(CKXH-DXV)min td(FXL-CKXL)min Switching Characteristics twl(min) tv(max) ;;where twh(min) tho(min) where UNIT
applications where McBSP used slave, please ensure that internal clock, CLKG runs least eight times that master clock. Typically, programming CLKGDV=1 using clock (CLKSM=1) (when McBSP slave) should suffice since clocks very slow.
TMS320C6000 McBSP Interface
Appendix
Proprietary Information spi3_dma.c: Tests CLKSTP mode where CLKSTP=11b CLKXP=0. McBSP0 master. other SPI-compliant device slave. #include "common.h" #define M0TO1 TRUE NOTE TRUE MEANS EXTERNAL SLAVE INTERNAL MSTR #define M0TO1_MSTR M0TO1 #define XFER_SIZE #define XFER_TYPE DMA_SPI #define CLKGDV0 #define CLKSM0 CLK_MODE_CPU void init_mcsp0_master(void); void init_M0_srgr(void); void set_clkstp(void); void main(void) xfer_size, xfer_type; mcsp0to1; mcsp0to1_rate; recv0_done FALSE; xmit0_done FALSE; mcsp0to1 M0TO1; mcsp0to1_rate (M0TO1_MSTR (CLKGDV0 CLKSM0); xfer_size XFER_SIZE; xfer_type XFER_TYPE; init_M0_srgr(); init_mcsp0_master(); Enable sample rate generator; /GRST=1 MCBSP_SAMPLE_RATE_ENABLE(0); MCBSP_SAMPLE_RATE_ENABLE(1); Wait clocks set_clkstp(); CLKSTP after pulling grst- switch (xfer_type) case DMA_SPI: dma_reset(); set_interrupts();/* Initialize service McBSP (mcsp0to1)
TMS320C6000 McBSP Interface
DMA2_SRC_ADDR (unsigned int) out0; DMA2_DEST_ADDR MCBSP_DXR_ADDR(0); REG_WRITE (DMA2_XFER_COUNTER_ADDR, xfer_size); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA2_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, SRC_DIR, SRC_DIR_SZ); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, SEN_XEVT0, WSYNC, WSYNC_SZ); DMA_START(DMA_CH2); DMA1_SRC_ADDR (unsigned int) in0; DMA1_DEST_ADDR MCBSP_DRR_ADDR(0); REG_WRITE (DMA1_XFER_COUNTER_ADDR, xfer_size); LOAD_FIELD (DMA1_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA1_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA1_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, SRC_DIR, SRC_DIR_SZ); LOAD_FIELD (DMA1_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA1_PRIMARY_CTRL_ADDR, SEN_REVT0, RSYNC, RSYNC_SZ); DMA_START(DMA_CH1); SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(0), XRST); while (!xmit0_done !recv0_done); break; 0x00007000; void init_mcsp0_master(void) setup*/ LOAD_FIELD (MCBSP_PCR_ADDR(0), LOAD_FIELD (MCBSP_PCR_ADDR(0), LOAD_FIELD (MCBSP_PCR_ADDR(0), LOAD_FIELD (MCBSP_PCR_ADDR(0), LOAD_FIELD (MCBSP_PCR_ADDR(0), LOAD_FIELD (MCBSP_PCR_ADDR(0), LOAD_FIELD (MCBSP_PCR_ADDR(0), PowerDown shut MCSP
M0TO1_MSTR, CLKXM, !M0TO1_MSTR, CLKRM, CLKX_POL_FALLING, CLKXP, FSYNC_POL_LOW, FSXP, FSYNC_POL_LOW, FSRP, FSYNC_MODE_INT, FSXM, FSYNC_MODE_EXT, FSRM,
SRGR setup LOAD_FIELD (MCBSP_SRGR_ADDR(0), FSX_DXR_TO_XSR, FSGM, setup LOAD_FIELD (MCBSP_XCR_ADDR(0), LOAD_FIELD (MCBSP_XCR_ADDR(0), LOAD_FIELD (MCBSP_XCR_ADDR(0), Master delay LOAD_FIELD (MCBSP_XCR_ADDR(0), LOAD_FIELD (MCBSP_XCR_ADDR(0), setup LOAD_FIELD (MCBSP_RCR_ADDR(0), LOAD_FIELD (MCBSP_RCR_ADDR(0), LOAD_FIELD (MCBSP_RCR_ADDR(0), LOAD_FIELD (MCBSP_RCR_ADDR(0), LOAD_FIELD (MCBSP_RCR_ADDR(0), SPCR
SINGLE_PHASE, XPHASE, WORD_LENGTH_20, XWDLEN1, XWDLEN1_SZ); XFRLEN1, XFRLEN1_SZ); DATA_DELAY1, XDATDLY, XDATDLY_SZ); NO_COMPAND_MSB_1ST, XCOMPAND, XCOMPAND_SZ);
SINGLE_PHASE, RPHASE, WORD_LENGTH_20, RWDLEN1, RWDLEN1_SZ); RFRLEN1, RFRLEN1_SZ); DATA_DELAY1, RDATDLY, RDATDLY_SZ); NO_COMPAND_MSB_1ST, RCOMPAND, RCOMPAND_SZ);
TMS320C6000 McBSP Interface
LOAD_FIELD (MCBSP_SPCR_ADDR(0), RXJUST_RJZF, RJUST, RJUST_SZ);
void init_M0_srgr(void) LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0),
CLKGDV0, CLKGDV, CLKGDV_SZ); CLKSM0, CLKSM, CLKS_POL_RISING, CLKSP, GSYNC_OFF, GSYNC,
void set_clkstp(void) SPCR LOAD_FIELD (MCBSP_SPCR_ADDR(0), CLKSTP_DELAY, CLKSTP, CLKSTP_SZ);
void set_interrupts(void) intr_init(); INTR_MAP_RESET(); Hook interrupt service routine interrupt intr_hook (c_int11, CPU_INT11); intr_hook (c_int09, CPU_INT9);
INTR_ENABLE(CPU_INT_NMI);/* Enable NMIE INTR_GLOBAL_ENABLE(); CSR*/ INTR_ENABLE(11); INTR_ENABLE(9); return; DATA TRANSFER COMPLETION ISRS interrupt void c_int11(void) xmit0_done TRUE; return; interrupt void c_int09(void) recv0_done TRUE; return; /**************** spi3_dma.c /**************** Begin count.asm Proprietary Information
TMS320C6000 McBSP Interface
count.asm .global _count_n_cpu_cycles
.text CLEARS REGISTERS SIMULATION PURPOSES _count_n_cpu_cycles: counts cycles where minimum gets value passed from main code LOOP LOOP CMPLT
LOOP ||[A2] [A1] LOOP [A1] LOOP LOOP: [A1] LOOP ||[A1] /**************** count.asm
COMMON.H V1.00 Copyright 1997 Texas Instruments Incorporated #include #include #include #include #include #include #include #include #include #include #include <dma.h> <emif.h> <intr.h> <timer.h> <cache.h> <hpi.h> <mcbsp.h> <regs.h> <stdio.h> <trgcio.h> <stdlib.h>
variables used tcase mcsp0to1; mcsp1to0; volatile xmit1_done; volatile recv0_done; volatile xmit0_done; volatile recv1_done; foll. CLKSTP defines should actually added mcbsp.h devlib #define CLKSTP_OFF 0x00 CLKSTP mode disabled
TMS320C6000 McBSP Interface
#define CLKSTP_NO_DELAY #define CLKSTP_DELAY #define FALSE #define TRUE 0x02 0x03 Clock starts without delay Clock starts with delay
BUFFERS DEFINED data6201.asm #define BUFFER_SIZE extern in0[BUFFER_SIZE]; extern out0[BUFFER_SIZE]; extern extern extern extern extern extern extern extern extern extern extern extern extern extern extern extern extern extern extern cregister cregister cregister cregister cregister cregister interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt volatile volatile volatile volatile volatile volatile void void void void void void void void void void void void void unsigned unsigned unsigned unsigned unsigned unsigned AMR; CSR; IFR; ISR; ICR; IER;
c_nmi01(void); c_int04(void); c_int05(void); c_int06(void); c_int07(void); c_int08(void); c_int09(void); c_int10(void); c_int11(void); c_int12(void); c_int13(void); c_int14(void); c_int15(void);
extern void set_interrupts(void); #define DMA_XFER #define POLL_XFER #define INT_XFER #define GPIO #define DLB1 #define DLB2 #define SPLIT_XFER #define HW_BYTE #define DMA_SPI /**************** common.h
TMS320C6000 McBSP Interface
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TMS320C6000 McBSP Interface

Shaku Anjanaiah Digital Signal Processing Solutions TMS320C6000 M

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