Gerald Capwell Fixed-Point Applications Abstract consumer el

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High-Density Design with MicroStarBGAs
Gerald Capwell Fixed-Point Applications
Abstract
consumer electronics industry constantly faces challenges design their solutions smaller less expensive. industry's most limiting design factors board real estate increasing cost. cost thought purely dollar terms more importantly, indirectly related lost revenue caused competitive disadvantage when competition's solution smaller, better does more. result, today's semiconductor, packaging printed circuit board (PCB) manufacturing technologies make possible camcorders palm your hand cell phones your shirt pocket. These applications require PCBs densely populated with components bottom sides board. solution CSPs (Chip Scale Packages) such MicroStarBall Grid Array (BGA). This application report describes mounting technique that increase board's chip density while decreasing routing complexity associated with fine-pitch packages.
Contents
High Density Techniques. Designing Vertically. Surface Mount Criteria. Summary References Appendix Package Drawings.
Figures
Figure Figure Figure Figure Figure Figure Figure Laser-Drilled Microvia. Bone Connecting Thru-Hole Burying Bone Layer Clean Power, Dirty Power Ground Pin-out. X-Ray TMS320VC549GGU Alignment. 144-Pin Package 176-Pin Package.
Tables
Table Coefficients Thermal Expansion
Digital Signal Processing Solutions
July 1998
High Density Techniques
most part, designing boards with packages difficult task. Designing high-density boards that maximize board space tricky. common problem when designing with packages total area required package density around chip periphery. total space mounting approach area needed TQFP (Thin-Quad-Flat-Pack). through pain changing packages there space-saving benefits? Actually, companies that have migrated BGAs find that BGAs hassle once thought. using high-density techniques, designer find that BGAs offer opportunity high-density boards with design manufacturing ease TQFP.
MicroStarBGA Packages
MicroStarBGA packages considered fine-pitch. This application report focuses (144-pins) (176-pins) packages. Both packages have 0.8mm pitch, each distinctly different array style. ball array wide channels four corners, providing inner balls with space routing connectivity. (See Appendix mechanical drawings MicroStarBGA packages. package solid four-row array configuration that cause difficulties when routing inner rows.
Conductor Width/Spacing
general default, many today's circuit board layouts based most conductor (line) width spacing. Given MicroStarBGA pitch roughly mils between ball pads, impossible satisfy both line width spacing requirements when routing between balls. manufacturers reduce line width with spacing. This allows least signal routed between ball pads. ball spacing worst case calculated assuming that diameter solder ball land mils (0.41mm).
Density
density, mentioned previously, limiting factor when designing highdensity board. density defined number vias particular board area. Using smaller vias increases routability board requiring less board space increasing density. invention microvia, shown Figure solved many problems associated with density.
High-Density Design with MicroStarBGAs
Figure Laser-Drilled Microvia
Microvias often created using laser penetrate first layers dielectric. laser penetrate thick dielectric layer, creating diameter microvia with depth (see Figure layout designer route first internal board layer. routing first layers necessary, diameter microvia with depth laser-drilled penetrating first layers (each thick).
Optimal Layers
number board layers increase board chip density functional count increases. example, TMS320VC549GGU digital signal processor (DSP) 144-pin package uses pins power ground. Roughly signals routed three layers. power ground planes increase board thickness five layers. sixth layer used bottom side place discrete components. Furthermore, increasing board layers, high-density applications possible with little mils between chips. Mounting TMS320VC549 DSPs directly opposite sides board estimated take layers, assuming sharing ground planes. Double-sided boards will have double functionality, each side. Unfortunately, placement bypass capacitors power pins required slightly reduce board's overall chip density. (See section, Placing Discrete Components, information placement bypass capacitors.)
Designing Vertically
relatively large density chip periphery, mentioned earlier, caused limited options when routing signal from ball. reduce eliminate density problem periphery chip, design vertically from through internal layers board, shown Figure Mechanical drilling vias between pads board working vertically creates `pick-andchoose' method pick your layer choose your route. bone method used connect thru-hole pad.
High-Density Design with MicroStarBGAs
Figure Bone Connecting Thru-Hole
This time-consuming method requires very small mechanical drill create either vias package. Although this method least expensive, disadvantage that vias through board, creating matrix vias bottom side board. Ideally, bottom layer used place bypass capacitors close power pins. Another disadvantage that clearance these vias reduce (and some case eliminate) copper between pads. area copper between pads critical connection between power plane power pins that located outside grid array. Furthermore, thru-hole bare copper, which exacerbate problems with solder ball collapse.
Burying Bone
other option, which purpose this application report, combination blind buried vias. Blind vias connect either bottom side board inner layers. Buried vias usually connect only inner layers. Figure illustrates this method using laser-drilled microvias center pads burying bone layer This technique minimizes probability complications from solder ball collapse.
High-Density Design with MicroStarBGAs
Figure Burying Bone Layer
Furthermore, since buried does extend through underside board, designer another laser-drilled blind microvias needed) connect bypass capacitors other discrete components bottom-side. buried (reducible mil) mechanical drilled hole with annular ring. This corresponds 10+9+9= area diameter. recommended that designers non-solder masked defined (NSMD) solder lands where balls adhere PCB. non-solder mask clearance should have annular ring mils. solder land diameter range from to18 mils. solder land chosen referenced board this application report.
Power Plane Considerations
Ideally power pins should connected much uniform copper plane possible. However, because mechanically drilled vias, (i.e., buried thru-hole) much larger than microvias, copper width spacing requirements become marginal. Consequently, there guarantee that solder lands dedicated device's power pins will connect power plane. Power pins most affected this problem internal balls (that pins outer row) adjacent pins with buried vias. Figure shows Clean (VCC 2.5V) Dirty (VDD 3.3V) power pins TMS320VC549GGU their location relative signal ground pins.
High-Density Design with MicroStarBGAs
Figure Clean Power, Dirty Power Ground Pin-out
Carefully selecting pins that routed layers dramatically increase routability power pins. Using laser-drilled microvias, route signals adjacent power pins signals that lead periphery chip layers two. These signals require buried vias, creating wider copper channel between balls power planes. example, Figure shows specific balls (balls with black dots) that should considered microvia routing layers two. Layer stack-up also help power plane routability. Power planes that reside first microvias) first microvias) layers routed easier since buried vias start next layer. same design rule applies bottom side board.
Placing Discrete Components
With advent buried capacitance buried resistance, future discrete components, such bypass capacitors pull-up resistors, will require physical surface space. Until then, board layout component density will limited certain physical form factors. board x-ray Figure oriented from bottom side looking toward layer, shows `VC549GGU (144-pin BGA) package mounted top. bypass capacitors mounted directly underneath package underside board. Depending required capacitive loading, bypass capacitors within physical form factor package (12mm 12mm). dark rectangles bypass capacitors connected power pins.
High-Density Design with MicroStarBGAs
Figure X-Ray TMS320VC549GGU Alignment
alternative populate topside board with bypass capacitors around periphery chip, leaving underside other discretes ICs. either solution, some component density lost.
Cost Analysis
Many applications, especially consumer electronics industry, particularly sensitive changes manufacturing costs. Increasing layers cost anywhere from percent layers. premium percent blind/buried vias expected. However, both options dramatically increase PCB's routability. These premiums mentioned above from board manufacturing build referenced design this report. premiums only estimates vary depending manufacturer, manufacturing volumes sets blind/buried vias.
Surface Mount Criteria
Solder Paste
Once design complete boards ready populated (reflowed), strongly recommended solder paste solder lands. manufacturing builds using solder paste, 10x-failure rate possible. There several advantages using solder paste. Some people believe using high silver (2%) solder paste make better reflow connection. Additionally, solder paste alleviate some coplanarity problems between solder ball solder lands. Furthermore, volume solder ball questionable wicking effect microvias, solder paste counteract this adding solder reflow.
High-Density Design with MicroStarBGAs
Reflow Profile
wide variety reflowing furnaces used MicroStarBGA packages. optimal solution `Full Convection" furnace, which helps minimize temperature differences board. reflow parameters plastic MicroStarBGA packages are:
Method: reflow Temp Time: 140°C 60-90 seconds
140°C 180°C 60-120seconds Time above 183°C 60-150 seconds. 230°C
Peak Temp:
Time within peak temp 10-20 seconds. Ramp down rate maximum 6°C/second.
Solder Ball Collapse
some packages solder ball collapse occur, creating interconnects between adjacent balls. overall package standoff function following:
Size solder ball (fixed) Solder paste volume board land (controllable). Board land diameter (see next paragraph). Package weight (fixed)
typical standoff mils package. designer should attempt change this standoff controlling diameter land. ensure proper reliability manufacturability, board land mils diameter. Reducing land diameter increases package standoff decreases cross-section area joint.
Finish
finish minimize coplanarity problems between solder balls solder lands. Immersion Gold finish recommended uniform application copper lands. However, Immersion Gold inferior Organic Solder Preservative (OSP) finish. This outside scope this report should investigated your discretion.
High-Density Design with MicroStarBGAs
Package Alignment
very reliable byproduct reflowing MicroStarBGAs package's capability automatically self-align over board solder lands. Figure shows package-land alignment that close ideal. This feature caused surface tension solder balls pulling device over pads. past, packages were heavy surface tension overcome alignment completely dependent placement machinery. MicroStarBGA packages very lightweight. fact, MicroStarpackages (GGU) have been seen auto-align when placement machinery 3040 percent.
Reliability
MicroStarBGAs other CSPs have characteristic that cause reliability problems addressed from design stage. characteristic involves joint fatigue failures during temperature cycling. coefficients thermal expansion (CTEs) chip very different. large disparity causes different expansion rates compounds creates joint fatigue between PCB's package. package defined being silicon since majority package silicon die. Epoxy resins, glass fibers copper influence PCB's FR4. Table shows differences CTEs silicon FR4.
Table
Coefficients Thermal Expansion
Material Silicon 25°C (PPM/°C)
general rule optimal joint reliability, land diameter should equal diameter MicroStarBGA package via. package via, which approximately mils diameter, connects ball package substrate. Matching diameters increases board level reliability optimizing package standoff reducing effects thermal expansion. most cases land diameter will never match package exactly. Furthermore, manufacturers require annular ring when laser-drilling lands. These restrictions would require minimum land diameter mils with microvias (5+4+5=14) land diameter with microvias. land diameter should exceed mils. further minimize probability joint fatigue failures, important follow surface mount process reflow parameters mentioned this report.
Summary
important remember that design technique mentioned this report only option. combination blind vias, buried vias depths valid design options. future, MicroStarpackage pin-out more configurable flex-circuit polyimide layer. signals connected could routed flex-circuit more convenient ball locations (i.e., outer row).
High-Density Design with MicroStarBGAs
Chip Scale Packages such MicroStarBGAs offer whole design possibilities. other hand, they introduce whole design rules. following simple design rules, designers create applications with levels component density never seen before industry. surface space increased effectively, allowing functionality square inch shoot through roof. Furthermore, with continued innovations laser drilling, blind/buried vias, buried components semiconductor integration, smaller packaging technology will required. Texas Instruments dedicated lead industry with exciting, packaging technologies believes giving customers "more your buck" continued semiconductor integration innovation.
References
Lyne, Kevin, "Ball Grid Arrays from Texas Instruments", Texas Instruments, December 1993.
Appendix Package Drawings
Figure 144-Pin Package
Notes: linear dimensions millimeters. This drawing subject change without notice.
High-Density Design with MicroStarBGAs
Figure 176-Pin Package
Notes: linear dimensions millimeters. This drawing subject change without notice. MicroStarBGA configuration
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Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain application using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. Copyright 1998, Texas Instruments Incorporated MicroStar trademarks Texas Instruments Incorporated. Other brands names property their respective owners.
High-Density Design with MicroStarBGAs

Gerald Capwell Fixed-Point Applications Abstract consumer el

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