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Interfacing TLV1544 Analog Digital Converter TMS320C50
Mixed-Signal Products
SLAA025A
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Contents
Introduction System Standard ADC-DSP Interface Power Supply Circuit Analog Input Buffer Circuit
Overview Signal Sequence ADC/DSP Interface TMS320C50 Features Serial Port 4.2.1 Signals Registers 4.2.2 Serial Port Operation 4.2.3 Serial Port Configuration 4.2.4 Transmit Receive Operations Burst Mode Hardware Timer 4.3.1 Timer Operation 4.3.2 Programming Timer Software Description Program-1 (Filename: C1544TIN.asm Timer Interrupt-Source) 5.1.1 Assembler Program-1 Description Program-2 (Filename: C1544CLK.asm Timer Clock-Source) 5.2.1 Assembler Program-2 Description Program-3 (Filename: C1544NOP.asm Timer Clock-Source delay-loop) 5.3.1 Assembler Program-2 Description
Summary References Appendix TLV1544 Program Files: Timer Interrupt Source) Boot Routine: BOOTIN.ASM C-Program: C1544T.C C-Callable Interface Program: C1544TIN.ASM Vector Table: VECTIN.ASM Appendix TLV1544 Program Files: Timer Clock Source Boot Routine: BOOTCLK.ASM C-Program: C1544C.C C-Callable Interface Program: C1544CLK.ASM Vector Table: VECCLK.ASM Appendix TLV1544 Program Files: NOPs Wait-Loop Boot Routine: BOOTNOP.ASM C-Program: C1544N.C C-Callable Interface Program: C1544NOP.ASM Vector Table: VECNOP.ASM
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Figures
List Figures
Data Acquisition System Using TLV1544 Standard ADC/DSP Interface Fixed Data Clock CLKX Typical Voltage Regulator Schematic Schematic Noninverting Analog Input Buffer Schematic Inverting Input Buffer Larger Input Signals Functional Block Diagram TLV1544 TLV1548 Interface Timing (16-Clock Transfer, Normal Sample Mode, High) Glueless ADC/DSP Interface Maximum Data Throughput Immediate Detection Serial Interface Low-Volt Operation High Data Throughput Glueless Interface Low-Volt Operation Serial Port Block Diagram Serial Port Control Register Configuring Activating Serial Port Operation Configuring Activating Serial Port 2.7-V Operation Transmit Receive Operation Burst Mode Timer Block Diagram Timing Diagram TDDR Timer Control Register Timer Interrupt, TINT, Indicates Glue-Less Interface Data Transfer Sequence When Using TINT Fast Conversion Mode Flowchart C1544IN.asm (Timer Interrupt Source) External Interrupt, INT3, Detects External Inverter Data Transfer Sequence When Using INT3 Slow Conversion Flowchart C1544CLK.asm (Timer Clock Source) Wait-loop Indicates Glueless Interface Low-Volt Application Data Transfer Sequence When Using Wait-Loop Low-Volt Application Flowchart C1544NOP.asm (Timer Clock Source delay) Interfacing TLV1544 with TMS320C50 Time Periods Between Consecutive Data Transfers Different Applications
List Tables
TLV1544/TLV1548 Control Words Conversion Times Fast Slow Conversion Clock Frequencies 5.5-V 2.7-V Operation Benefits Individual Interface Circuits Serial Port Registers Serial Port Control Register Bits Summary Configuration Interfacing TLV1544/48 Timer Control Register Bits Summary Local Global Variables Corresponding Programs Timer Application Corresponding Filenames
SLAA025A
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Thomas Kugelstadt David Quach
ABSTRACT This application report presents hardware solutions interfacing TLV1544 10-bit low-power analog-to-digital converter (ADC) TMS320C50 16-bit fixed-point digital signal processor (DSP). report describes interface hardware shows three C-callable software routines which support data transfer. addition, provides useful hints design typical system power supply shows input buffers analog inputs ADC.
Introduction
TLV1544/48 10-bit, low-power, successive approximation analog digital converter (ADC) with conversion time tconv TLV1544 four analog inputs; TLV1548 eight. device operates from maximum supply voltage down minimum supply voltage thus making suitable portable, low-power applications. With 5.5-V supply, maximum interface clock (I/OCLK) possible. With 2.7-V supply, maximum clock 2.89 MHz. serial interface port standard configuration provides only 5-MHz clock applied when operates second serial port configuration uses on-chip timer generate programmable clock rate between MHz. This configuration used clock interface when operates addition, this solution allows increasing data throughput factor two. interface configuration possibilities discussed detail Section 3.2.
System
System
While this report focuses interface between (see Figure includes informative hints power supply section buffering inputs.
TPS7101
V-REG
Input Amplifier Interface
TLV2772
TLV1544
TMS320C50
Figure Data Acquisition System Using TLV1544
Standard ADC-DSP Interface
Figure shows standard ADC/DSP interface fixed data clock rate CLKX. regulated supply voltage applied pin. 4.7-µF bulk capacitor keeps entire circuit supply stable against significant current changes during operation. 0.1-µF bypass capacitors keep supply, well positive reference voltage unused digital inputs, ripple-free. bypass capacitors should close possible individual pins. positive reference voltage (REF+), tied VCC; negative reference voltage, REF-, connected GND. This defines analog conversion range specifies maximum input signal level analog inputs, unused, active, digital control pins tied VCC. application with fixed data clock, interface between TLV1544 TMS320C50 requires additional control logic. sends initial chip-enable signal ADC. transmit clock output DSP, CLKX, provides fixed data clock into input into receive clock input, CLKR. transmit frame-sync output (FSX), initializes every data transfer sending frame-sync pulse input well receive frame-sync input, FSR. initializes transferring 4-bit control words from output into DATA input ADC. clocks digital conversion results DATA into DR-pin DSP. Section gives detailed information signal sequence, word-length clock rates.
SLAA025A
System
TMS320C50 TLV1544 CSTART REF+ REF- DATA DATA CLKR CLKX
Analog Inputs
NOTE: Fixed data clock only possible with
Figure Standard ADC/DSP Interface Fixed Data Clock CLKX
Power Supply Circuit
Figure shows typical voltage regulator schematic using adjustable low-dropout regulator (LDO) TPS7101. very dropout voltage output current IOUT very typical quiescent current remains independent output loading over full range output current, TPS7101 regulates input voltage range down adjusted output level. this application output adjusted through voltage divider equation governing output voltage
VREF
with Vref
reference voltage 1.178 typ.
Resistors should chosen approximately divider current. recommended value with adjusted desired output voltage. Smaller resistors used, offer inherent advantage consume more power. Larger values should avoided, leakage currents will introduce error. Solving Equation yields more useful equation choosing appropriate resistance:
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
System
Calculating VOUT results
1.178
low-power application TLV1544 operates minimum supply voltage Therefore, value changes
1.178
TPS7101
DVDD 0.01 AVDD 0.01
NOTES: Bypass capacitors should placed close device pins possible. total regulator output capacitors must maintain between max. Fair-Rite #27-44-044447 equivalent. Fair-Rite trademark Fair-Rite Products Corporation. internal connection.
Figure Typical Voltage Regulator Schematic input capacitors shown usually required; however, 0.1-µF ceramic bypass capacitor improves load transient response noise rejection TPS7101 located more than inches from power supply. higher capacitance electrolytic capacitor necessary large load transients with fast rise times anticipated. chosen output capacitors required stability. low-ESR 4.7-µF solid tantalum capacitor 0.1-µF high-frequency ceramic capacitor, connected from regulator output ground, sufficient ensure stability, provided that total maintained between additional low-pass filters, each consisting ferrite bead, 0.01-µF capacitor, block digital noise transients digital supply line, DVDD from analog supply, AVDD. more information type ferrite beads selection type low-ESR capacitors, refer TPS7101 Data Sheet, literature number SLVS092F TLV1544 User's Guide, literature number SLAU014.
SLAA025A
System
Analog Input Buffer Circuit
Figure Figure show schematics typical analog input buffers using TLV2772 dual operational amplifier. TLV2772 combines high slew rate bandwidth, rail-to-rail output swing, high output drive excellent precision. device provides 10.5 V/µs slew rate bandwidth while only consuming supply current channel. This performance much higher than current competitive CMOS amplifiers. rail-to-rail output swing high output drive make good choice driving analog input reference analog-to-digital converters. device also distortion while driving 600- load telecom systems. This amplifier input offset voltage, nV/Hz input noise voltage, input bias current measurement, medical, industrial applications. device operates from single supply voltage. power consumption makes good solution portable applications.
AVDD (GND) (VDD+) AVDD/2 TLV2772 Analog Inputs (A0,A1,A2,
Figure Schematic Noninverting Analog Input Buffer this configuration TLV2772 works noninverting amplifier with closed loop gain shown Equation
Gain
input voltage range therefore limited between AVDD/2. input low-pass filter consists circuit with corner frequency kHz. While filter optional, useful when operating noisy environment. low-pass filter op-amp output (RLP CLP), corner frequency
This filter limits input signal bandwidth, with operational amplifier inherent noise level which into ADC, thus improving signal-to-noise ratio system significantly. additional 0.1-µF bypass capacitor, connected between VDD+ (pin (pin device, ensures noise-free supply operational amplifier.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
System
Figure shows another input buffer circuit that allows ±10-V input signals into analog inputs ADC.
TLV2772
Figure Schematic Inverting Input Buffer Larger Input Signals this configuration TLV2772 operates inverting amplifier with closed loop gain 0.25 shown Equation
Gain
-0.25
Resistors bias output operational amplifier 2.5-V operating point. maximum input voltage ±10-V amplified -0.25 results output voltage ±2.5 negative sign gain factor represents phase shift 180° between input- output-signal.
SLAA025A
Overview
Overview
TLV1544 TLV1548 CMOS 10-bit switched capacitor successive approximation (SAR) ADCs. TLV1544 four analog inputs; TLV1548 eight. Figure shows functional block diagram devices. TLV1544 operates from minimum supply 2.7-V maximum supply 5.5-V allows high-speed data transfer from host 10-MHz maximum. addition on-chip multiplexer that select analog inputs three internal self-test voltages, provides versatile control capability. Through DATA pin, 4-bit control words initialize device for: analog input channels Power-down mode Slow fast conversion rate self-test voltages.
Sample Hold Function 10-Bit (Switch Capacitors)
CLOCK REF+ REF- Self-Test Reference
Output Data Register
A0-A3 (A7)
10-to-1 Data Selector Analog Control Logic Counters Input Data Register
DATA
CSTART DATA
Figure Functional Block Diagram TLV1544 TLV1548 4-wire serial interface (SPI QSPI allows data transfer microprocessor DSP. When interfacing TMS320 DSP, additional frame sync (FS) signal indicates start serial data frame. high chip-select activates device. data clock determines data rate between host. Through DATA 4-bit control words initialize desired operation mode select analog input. indicates conversion DATA provides conversion results 10-bit serial format.
QSPI trademarks Motorola, Inc.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Overview
high allows clock phase adjustment 180°.When operating extended sampling mode, CSTART controls sampling period sample-and-hold circuit starts conversion. this application, CSTART used therefore tied high.
Signal Sequence
Figure shows timing diagram data transfer between TLV1544 TMS320C50 through serial port. serves slave device operates master, supplying frame-sync signal, data transfer clock, CLK. Initially, with high being inactive, inputs, DATA CLK, disabled. DATA high-impedance state high. When activates taking providing data clock CLK, data transfer sequence begins. DATA enabled DATA removed from high-impedance state logic low. then sends pulse line, indicating start data frame. With falling edge provides 4-bit control word DATA (see Table control words) starting with most significant (MSB). same time, provides 10-bit conversion result (from previous conversion) DATA OUT, beginning with MSB. input data selects different mode selects different analog input channels. case control word being channel address, selected analog input channel accessed during first four clock cycles after falling edge Starting with falling edge fourth cycle, sample-and-hold (S&H) circuit samples selected analog input.
SLAA025A
Overview
Address Sampled
Rise After 10th Clock td(EOC-CS)
Clocks
Access
Sample Clocks)
Hold/Conversion
DATA
DATA
Hi-Z
NOTES: falling edge appear within clock cycles from falling edge TLV1544/48 data sheet specifies minimum time 100-ns after rising edge before next falling edge
Figure Interface Timing (16-Clock Transfer, Normal Sample Mode, High) tenth falling edge CLK, sample held analog-to-digital conversion starts. same time output changes from high low, indicating conversion start. initiates data transfer sequence taking high, which disables DATA DATA OUT. This happen between tenth clock rising edge EOC, indicating end-of-conversion. taken high immediately after tenth clock, DATA goes into high-impedance state and, following 10-bit conversion result, random signal levels clocked into next clock cycles. changes high somewhere between tenth clock going high, 10-bit result padded with maximum zeros complement 16-clock cycle DSP. case, bits following conversion result useless information should ignored interface software. entire data transfer sequence complete when returns high. delay time td(EOC after rising edge required before change again start data transfer.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Hi-Z
Overview
Table TLV1544/TLV1548 Control Words
INPUT DATA BYTE FUNCTION SELECT Analog channel TLV1548 Selected Analog channel TLV1548 Selected Analog channel TLV1548 Selected Analog channel TLV1548 Selected Analog channel TLV1548 Selected Analog channel TLV1548 Selected Analog channel TLV1548 Selected Analog channel TLV1548 Selected Software power down Fast conversion rate Slow conversion rate Self-test voltage (Vref+ Vref-)/2 selected Self-test voltage Vref- selected Self-test voltage Vref+ selected Reserved Reserved BINARY 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Analog channel TLV1544 1001b conversion result (cleared access) conversion result (cleared setting fast) conversion result (cleared setting slow) Output result 200h Output result 000h Output result 3FFh conversion result conversion result Analog channel TLV1544 Analog channel TLV1544 Analog channel TLV1544 COMMENT
ADC/DSP Interface
Following signal sequence description Section recalling that master slave device, following interconnections always stay same: output drives chip-enable signal into CS-pin ADC. FSX/FSR frame-sync pulse generated DSP. This signal sent from output into input into input synchronize transmitter receiver stages within serial port. Control data, which initialize TLV1544, driven from data transmit output, into DATAIN ADC. Conversion results from into data receive input, This section focuses mainly different options generating clock detecting end-of-conversion that possible with TLV1544/48. Figure shows standard interface between TLV1544/48 TMS320C50 with glueless interface.
SLAA025A
Overview
TLV1544 INT3 TOUT CLKX CLKR DATA DATA X2/CLKIN TINT Timer TMS320C50
Analog Inputs
Figure Glueless ADC/DSP Interface provides on-chip oscillator, which enabled connecting crystal, with fundamental frequency MHz, across X2/CLKIN. internal divide-by-two clock option provides clock MHz, which translates instruction cycle time generation clock happens with initialization serial port, which provides additional divide-by-four function sets data transfer clock CLKX MHz. information end-of-conversion status important, since previous conversion must completed before conversion start. application Figure does detect end-of-conversion signal, waits maximum conversion time pass. TLV1544 data sheet specifies typical maximum conversion times fast slow conversion, shown Table Table Conversion Times Fast Slow Conversion
PARAMETER Conversion time, tconv time Fast conversion from Slow conversion from DATA SHEET UNIT
interface software, on-chip timer-counter programmed with maximum conversion time selected conversion mode causes timer interrupt (TINT) once counter value reaches zero. following interrupt routine then initiate data transfer sequence. Table compares conversion times, measured series TLV1544 evaluation modules (EVMs) with maximum values specified data sheet. data differ factor from maximum possible conversion times. obvious that, even with glueless interface, waiting maximum conversion time pass highly time-inefficient. maximize data throughput over interface, conversion must detected soon occurs. Only then possible start data transfer with minimum latency. circuit Figure accomplishes this connecting output through inverter external interrupt input, INT3 DSP.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Overview
TLV1544 INT3 TOUT CLKX CLKR DATA DATA X2/CLKIN Timer TMS320C50
Analog Inputs
Figure Maximum Data Throughput Immediate Detection end-of-conversion signal (rising edge EOC) inverted into high-to-low transition INT3 causes external interrupt. initiated interrupt service routine start data transfer sequence. previous scenarios describe interface operation. low-power applications with supply voltages less, TLV1544 data sheet defines lower data clock frequencies CLK, when compared operation. Table Clock Frequencies 5.5-V 2.7-V Operation
PARAMETER Clock frequency fCLK CLK, 2.81 UNIT
circuit Figure shows operating from 2.7-V supply. required data clock nominal. Since only frequency provide CLKX fourth internal clock (CLKX MHz), on-chip timer initialized programmable clock source.
TLV1544 2-10 TOUT CLKX CLKR V-5.5 DATA DATA X2/CLKIN INT3 Timer TMS320C50
Analog Inputs
Figure Serial Interface Low-Volt Operation High Data Throughput
SLAA025A
Overview
period registers timer, TDDR, programmed divide clock timer generates periodic interrupts rate MHz. While interrupt requests masked CPU, 2-MHz signal still available data clock timer output, TOUT. more information timer functions Section 4.3. further advantage this adjustable clock generator that programmed clock rates half clock, TOUT MHz. Since timer serves here clock generator, longer available interrupt source indicate end-of-conversion (EOC) state TLV1544/48. previous application, this circuit detects inverting signal from into high-to-low transition INT3. external interrupt request starts interrupt service routine which initiates data transfer sequence. Figure shows that when external inverter removed, interface becomes glueless again.
TLV1544 V-5.5 DATA DATA CLKX CLKR X2/CLKIN 2-10 TOUT Timer INT3 TMS320C50
Analog Inputs
Figure Glueless Interface Low-Volt Operation Since neither inverter timer available detection, additional software required accomplish this task. lines software code, forming delay loop that waits maximum conversion time pass, need added interface program. additional wait loop consumes programming power reduces data throughput significantly. Applying this technique low-power application, which already operates slow conversion mode data transfer rate, reduces data throughput significantly. Depending requirements final application, simplicity glueless interface might outweigh benefits higher data throughput. Table summarizes pros cons interface circuits, shown Figure through Figure
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Overview
Table Benefits Individual Interface Circuits
FIGURE PROS Glueless interface operation fixed data clock Factor higher data through standard operation Flexible interface supply range from Flexible data clocks from Higher data throughput over whole supply range Glueless interface Flexible interface supply range from Flexible data clocks from CONS data throughput waiting maximum conversion time pass glueless interface external inverter glueless interface external inverter
data throughput waiting maximum conversion time pass
software description Section provides three examples interface programs circuits Figure through Figure
SLAA025A
TMS320C50
TMS320C50
TMS320C50 16-bit fixed-point, static CMOS digital signal processor. combination advanced Harvard architecture (separate buses program memory data memory), on-chip peripherals, on-chip memory, highly specialized instruction basis operational flexibility this device.
Features
'C50 offers following features: 16-bit On-Chip This on-chip, maskable, programmable memory used booting from slower, external EPROM program fast on-chip external SRAM. 1056 16-bit On-Chip Data data accessed twice machine cycle (dual-access RAM). This block memory primarily intended store data values but, when needed, used store programs well data. 16-bit On-Chip Program/Data This memory software configurable program and/or data memory space. Code booted from off-chip, nonvolatile memory then executed full speed, once loaded into this RAM. On-Chip Memory Security 'C50 maskable option protect contents on-chip memories. When related set, externally originating instruction access on-chip memory spaces. Address-Mapped Software Wait-State Generator device incorporates software wait-state logic interfacing with slower off-chip memory devices. This circuit consists wait-state generating circuits user programmable operate wait states. off-chip memory access, these wait state generators mapped 16K-word boundaries program memory, data memory, ports. User-Maskable Interrupts 'C50 four external-interrupt lines. These lines internally latched that asynchronous interrupt operations performed DSP. Also device possesses five internal interrupts: timer interrupt, TINT, four serial port interrupts. Parallel Ports 'C50 total ports, sixteen which memory-mapped data memory space. These ports addressed instruction instruction. memory-mapped ports accessed with instruction that reads writes data memory. Serial Ports high-speed serial ports capable operating one-fourth machine cycle rate (CLKOUT1). circuits synchronous, full-duplex serial port. transmitter receiver double buffered
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TMS320C50
individually controlled maskable, external interrupt signals. Data framed either bytes words. second circuit full-duplex serial port that configured either synchronous time-division multiple (TDM) access operations. Hardware Timer on-chip timer consists 16-bit counter 4-bit prescaler. This timer clocks between one-half one-thirty-second machine rate, depending upon programmable divide-down ratio. timer stopped, restarted, reset, disabled specific status bits.
From list features, serial port hardware timer on-chip peripherals that mainly used this application. Their block diagrams operation are, therefore, explained more detail following sections.
Serial Port
serial port provides communication with serial devices such codecs serial ADCs. Receive transmit operations double-buffered, thus allowing continuous communication stream either 16-bit data packets. internal clock mode, maximum transmission rate transmit receive operations clock divided four CLKOUT1 rate/4. Therefore, maximum rate megabits/s 20-MHz device. modes operation provided support wide range applications. Continuous mode provides operation that requires only pulse transmit several packets maximum frequency. Burst mode allows transmission single 16-bit word following pulse.
4.2.1 Signals Registers
serial port consists following basic signals: CLKX Transmit clock input output. This signal clocks data from transmit shift register (XSR) pin. serial port configured either generating internal clock, accepting external clock. port configured generating internal clock, CLKX becomes output, transmitting maximum frequency equal fourth clock. port configured accept external clock, CLKX changes input, receiving external clock signal. Transmit frame synchronization. indicates start transmission. port configured generating internal frame sync pulse, transmits pulse. port configured accepting external frame sync pulse, this receives pulse. Serial data transmit. transmits serial data from transmit shift register (XSR). Receive clock input. CLKR receives external clock clocking data from into receive shift register (RSR).
CLKR
SLAA025A
TMS320C50
Receive frame synchronization. initiates reception data beginning packet. Serial data receive. receives serial data, transferring into receive shift register (RSR).
serial port operates through three memory-mapped registers SPC, DXR, other registers, RSR, that accessible permit double-buffering capability. These five registers listed Table Table Serial Port Registers
REGISTERS DESCRIPTION Serial port control register Data transmit register Data receive register Transmit shift register Receive shift register
4.2.2 Serial Port Operation
Figure shows pins registers configured serial port double buffering implemented.
Data
Control Logic CLKR
RINT
XINT
Control Logic CLKX
Figure Serial Port Block Diagram Transmit data written DXR, while received data read from DRR. transmit executed writing data DXR, which copies data XSR. manages shifting data pin, thus allowing another write soon DXR-to-XSR copy completed. Upon completion DXR-to-XSR copy, 0-to-1 transition occurs transmit-ready bit, XRDY, SPC, generates transmit interrupt, XINT, that signals that ready word. process similar receive side. Data from shifted into RSR, which copies from which read. Upon completion RSR-to-DRR copy, 0-to-1 transition occurs receive ready bit, RRDY, SPC, generates receive interrupt, RINT.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TMS320C50
Thus, serial port double-buffered because data transferred from while another transmit receive being performed. burst mode, frame sync pulse synchronizes transfer timing described section 4.2.4 transmit receive operations burst mode.
4.2.3 Serial Port Configuration
While data registers mainly responsible shifting buffering data, configures entire serial port therefore most important register used interface programs. Figure shows 16-bit memory-mapped SPC. Some bits read-only while others read/write.
XSREMPTY XRDY
FREE SOFT RSRFULL
RRDY
RRST XRST
Figure Serial Port Control Register Table gives overview definition SPC. Only bits which important this application explained. detailed information functions refer TMS320C5x User's Guide. Table Serial Port Control Register Bits Summary
NAME Reserved Always read zero. digital loop-back mode allows connect transmitter output FSX) receiver input FSR). (This used application zero.) format specifies word length transmitter receiver. word length word length frame synch mode specifies when frame sync pulse needed. burst mode selected FS-pulse used each word) continuous Mode selected (only start pulse required) clock mode specifies clock source CLKX. on-chip clock source used with CLKX CLKOUT1 external clock source chosen transmit mode specifies source FSX-pulse generation generated on-chip synchronized CLKX needs applied from extern transmit receive reset signals activate deactivate transmitter receiver serial port. XRST/ RRST transmitter receiver active XRST/ RRST activity halts input input reflect levels CLKX CLKX pins. read only bits. receive transmit ready bits. Upon completion RSR-to-DRR copy DXR-to-XSR copy, these bits perform transition, indicating receive interrupt (RINT transmit interrupt (XINT) respectively. transmit shift register empty flag indicates whether transmitter experienced underflow. XSREMPTY read only bit. FUNCTION
XRST RRST RRDY XRDY XSREMPTY
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TMS320C50
Table Serial Port Control Register Bits Summary (Continued)
NAME RSRFULL SOFT FUNCTION receive shift register full flag indicates whether receiver experienced overrun. RSRFULL read only bit. SOFT emulation that aborts transmission when breakpoint encountered high-level language debugger. enabled when FREE SOFT stop after word completion SOFT immediate stop (This effective only emulation mode, otherwise zero). FREE selects free CLKX. FREE CLKX runs free FREE STOP enabled (This effective only emulation mode, otherwise zero).
FREE
When interfacing TLV1544/48 ADC, serial port TMS320C50 must configured shown Table Table Configuration Interfacing TLV1544/48
REQUIRED CONFIGURATION needs set-up master device, generating necessary frame sync pulse start data transfer. Because serial port inactivity during conversion process ADC, serial port must operate burst mode. AFFECTED BITS
communication between must 16-bit word format support 10-bit format conversion result. When operates on-chip clock source selected provide CLKX data transfer clock input ADC. When operates CLKX needs change input, receive clock signal from timer output, TOUT. When modified reconfigure serial port, transmitter receiver need reset. After modification complete, transmitter receiver need activated. XRST RRST XRST RRST
With exception bit, which needs comply with specific clock requirements 2.7-V supply, remaining bits stay same. When reconfiguring SPC, instructions required. first instruction resets transmitter receiver configures SPC. second instruction reactivates transmitter receiver. Figures show binary format code assembler instructions used configure activate serial port.
FREE Configure Port SPLK #0038h, Activate Port SPLK #00F8h, SOFT RSRFULL XSREMPTY XRDY RRDY RRST XRST
Figure Configuring Activating Serial Port Operation
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TMS320C50
FREE Configure Port SPLK #0028h, Activate Port SPLK #00E8h,
SOFT
RSRFULL
XSREMPTY
XRDY
RRDY
RRST
XRST
Figure Configuring Activating Serial Port 2.7-V Operation
4.2.4 Transmit Receive Operations Burst Mode
burst mode operation, there period serial port inactivity between packet transmits. Therefore each data packet needs marked frame sync pulse. transmit direction, after write DXR, pulse generated next rising edge CLKX. next falling edge CLKX, loaded with value from DXR. XRDY goes high, generating transmit interrupt, XINT. next rising edge CLKX cycle, first data (MSB first) driven pin. With fall frame sync pulse, remaining bits shifted out. When bits transferred, enters high-impedance state. receive direction, shifting into begins falling edge CLKX cycle after gone low. After bits have been received, content transferred falling edge CLKX. RRDY goes high, generating receive interrupt, RINT.
TOUT/CLKX/CLKR (MCM FXS/FSR (TXM Transmit Word XINT Transmit Word
Loaded Loaded Receive Word RINT Loaded
Loaded Loaded Receive Word
Figure Transmit Receive Operation Burst Mode
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TMS320C50
Hardware Timer
second on-chip peripheral used this application hardware timer. When operates less, timer serves data clock source, providing necessary clock rate MHz. applications where slow data clock required, timer programmed indicator.
4.3.1 Timer Operation
hardware timer fully programmable down counter. stopped, restarted, reset, disabled specific status bits. timer consists 16-bit main counter, TIM, 4-bit prescaler counter, PSC. Figure shows block diagram timer. Each counter loaded preceding register. loaded timer divide-down register, TDDR, loaded period register, PRD. When decrements zero, borrow-1 signal generated next CLK-1 cycle (with CLK-1 being identical CLKOUT1 cycle). that time value TDDR loaded into PSC, decrements one. Similarly, when decrements zero, borrow-2 signal generated next CLK-2 cycle (with CLK-2 being identical borrow-1 signal). This time, both counters reloaded. value loaded into TIM, content TDDR loaded into PSC. addition, borrow-2 pulse sent TOUT-pulse external timer output pin, TOUT, timer interrupt, TINT, CPU. TINT request sets TINT flag interrupt flag register, IFR, masked unmasked interrupt mask register, IMR. duration borrow-2 pulse TOUT equal that CLKOUT1 cycle. timing diagram Figure gives typical sequence events timer values, initial load-pulse, Load1 Load2, copies TDDR value into PSC, value into TIM. decrements each succeeding CLK-1 cycle (CLKOUT1) until reaches zero. next CLK-1 cycle, borrow-1 generated. TDDR loads divide-down count into PSC, decrements one. continue decrement same until decrements zero. next CLK-2 cycle, borrow-2 pulse generated. timer interrupt, TINT, sent CPU, borrow-2 pulse sent TOUT-pin. Both counters, PSC, reloaded their corresponding registers, TDDR, entire sequence repeated. decrements one, every (TDDR CLKOUT1 cycles. When either period registers, both registers, TDDR, nonzero, interrupt rate defined equation interrupt interval given equation
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TMS320C50
TINT[MHz] TINT
CLKOUT (TDDR 1[(MHz]
TDDR
example Figure TINT rate results
TINT[MHz]
CLKOUT 1[MHz1) CLKOUT1[MHz]
That means clock, CLKOUT1, divided every clock cycles, TINT pulse generated. NOTE: When both registers, TDR, zero, timer interrupt rate automatically sets CLKOUT1/2.
SRESET
Load2 Borrow-2 CLK-2
TDDR Load1 Borrow-1 CLK-1 CLKOUT1
TOUT
TINT
Figure Timer Block Diagram
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TMS320C50
CLKOUT1 Cycles CLKOUT1 CLK1 Load1 PSC1 PSC2 PSC4 PSC-Value Borrow1 CLK2 Load2 TIM1
TIM2 TIM-Value TINT/TOUT/ Borrow2
Figure Timing Diagram TDDR
4.3.2 Programming Timer
on-chip timer configured period register, PRD, timer control register, TCR. 16-bit, memory-mapped register that specifies initial period timer. 16-bit, memory-mapped register that contains status control bits operate timer. Figure shows status control bits within TCR, Table gives overview definition TCR.
Soft Free TDDR Reserved
Figure Timer Control Register
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TMS320C50
Table Timer Control Register Bits Summary
NAME TDDR timer stop status starts stops timer. Timer starts Timer stops timer reload resets timer. When set, reloaded with value PRD, loaded with value TDDR. (This always read zero). prescaler counter bits hold current prescale count timer. reloaded with contents TDDR cycle after reached zero, whenever software. FREE selects free timer. FREE Timer runs free FREE STOP enabled (This effective only emulation mode, otherwise zero). SOFT emulation that aborts transmission when breakpoint encountered high-level language debugger. enabled when FREE SOFT Timer stops after completion transmission SOFT Timer stops immediately (This effective only emulation mode, otherwise zero). Always read zero. FUNCTION timer divide-down register bits define divide-down ratio timer.
FREE
SOFT
Reserved
When programming timer interrupt rate using equation common specify initial timer period within keep TDDR value within zero. programming from 65536, possible generate timer interrupts, TINT, every 65536 cycles. lower interrupt rate required, additional divide-down value programmed into TDDR that extends interrupt interval desired factor. software description Section Program uses on-chip timer end-of-conversion indicator ADC. Thus timer generate only interrupt, TINT, length (which maximum conversion time ADC). With clock MHz, clock cycle interrupt period needs cycles. Solving equation keeping TDDR results
TINT
TDDR
ns10
following instructions configure timer program
SPLK #199, SPLK #0030h, SPLK #0008h, load timer period into reload PRD/TDDR stop timer clear pending timer interrupt (TINT)
Program uses on-chip timer programmable clock generator generate 2-MHz interface clock. With clock interrupt rate MHz, value needs
CLOCKOUT1 TINT-rate (TDDR MHz)
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TMS320C50
following instructions configure timer program
SPLK SPLK #0020h, load timer period into reload PRD/TDDR timer
NOTE: Since timer operates clock generator, timer interrupt, TINT, masked entire program. Therefore, additional instruction clear pending interrupts required.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Software Description
Software Description
interface software consists three C-callable assembler programs three corresponding C-programs. user specify certain data transfer parameters-such analog input channel, conversion mode, memory start address, number samples-through global variables file without modifying corresponding assembler program. When specific interface routine called, global variables specific file loaded into local variables assembler program. Table shows global local variables their corresponding files. Table Local Global Variables Corresponding Programs
PROGRAM C-files C1544T.C only C1544C.C only TYPE Global Global Global Global Global Local Local Assembler files Local Local Local Local VARIABLE _Samples _MemStart _Channel _ControlMode _Vcc ADWORD ADCOUNT ADMEM RINT_COUNT END_BIT TEMP DESCRIPTION User defined number samples acquired User defined memory pointer start User defined channel number sampled User defined conversion mode User defined voltage supply Control word Sample counter Memory pointer Number Receive Interrupts End-of-program Temporary register control mode receive data
Each three assembler programs executes following steps: Initialize serial port Load user defined values Activate initialize Acquire specified number data Disable Return program above sequence shows that assembler routines used solely acquire data. also shows that every time interface routine called, enabled data acquisition process disabled before routine returns program. Therefore neither self-test modes power-down instruction, which available list TLV1544 control words, used these routines. programs differentiated on-chip timer shown Table Program uses timer interrupt source called C1544TIN.ASM. Program uses timer clock generator called C1544CLK.ASM. end-of-conversion detected using output ADC. Program similar Program uses delay loop, which waits maximum conversion time pass. This wait-loop executes specified
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Software Description
number no-operation-instructions, NOPs, generate necessary delay, hence program name C1544NOP.ASM. Table Timer Application Corresponding Filenames
TIMER USED Interrupt source detect C1544TIN.asm (Program-1) C1544T.c Clock source, used from C1544CLK.asm (Program-2) C1544C.c Clock source, indicated after wait-loop C1544NOP.asm (Program-3) C1544N.c
following sections explain main assembler program detail. review individual file listings, refer Appendix Program-1, Appendix Program-2 Appendix Program-3.
Program-1 (Filename: C1544TIN.asm Timer Interrupt-Source)
Program supports glueless DSP-to-ADC interface Figure serial port programmed burst-mode operation. interface clock, CLKX MHz), frame-sync signal, generated chip. on-chip timer programmed generate interrupt, TINT, after maximum conversion time elapsed.
TLV1544 CLKX CLKR DATA DATA X2/CLKIN TINT INT3 TOUT Timer TMS320C50
Analog Inputs
Figure Timer Interrupt, TINT, Indicates Glueless Interface timing diagram Figure divides data transfer sequence into four steps: activates taking low. Then control word initialize loaded into serial port. actual data transfer happens. While sends control data configure operation mode, transmits conversion results serial port receiver. 16th clock cycle (CLKX) after gone low, receive interrupt, RINT, generated automatically. following interrupt service routine, RINT-ISR, disables starts on-chip timer. Then stores received data into memory returns from interrupt idle mode. continues idling during entire conversion time ADC. After timer period elapsed, timer interrupt, TINT, generated. following interrupt service routine, TINT-ISR, stops timer loads latest control word into serial port prepare data transfer.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Software Description
15.8 MHz)
Initial DATA
DATA
RINT Time Period TINT
Figure Data Transfer Sequence When Using TINT Fast Conversion Mode data transfer takes 15.8 when operates fast conversion mode, 30.8 when slow conversion mode.
5.1.1 Assembler Program-1 Description
Following flowchart Figure this section explains assembler program detail. NOTE: Each task flowchart appears header assembler program listing Appendix
TLV1544START
program starts with call main routine _C1544TIN from program. first, previously used pointers registers saved. These include following registers: frame stack pointer, status registers, auxiliary registers, wait-state registers, PDWSR CWSR processor mode status register PMST index register INDX
Previous Conversion Results Conversion Time
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Software Description
During initialization interrupts disabled, PMST updated, wait states zero. Then serial port configured burst-mode operation. signal CLKX programmed generated on-chip. Finally transmitter receiver stages activated. Now, user defined values (global variables program) loaded into local variables assembler routine. channel number stored into TEMP. memory start address loaded into ADMEM, number samples acquired saved into ADCOUNT. control mode, which fast slow conversion stored into ADWORD. following timer configuration writes default period into period register (PRD). Depending upon whether user selected slow fast conversion, content either overwritten keeps default value. After that, timer start/stop (TSS), timer control register (TCR), halt timer. Both internal interrupts, RINT TINT, enabled. Before initialization begins, variable RINT_COUNT RINT_COUNT specifies number receive interrupts that must occur before provide valid conversion results. local variable, END_BIT, which defines entire program, general output port (XF), driven enable through chip-select pin, variable ADWORD, which contains conversion mode, then copied into serial port data transmit register (DXR), sent ADC. Subsequently content TEMP, which specifies channel number, loaded into ADWORD. then resides idle mode waits receive interrupt (RINT), occur.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Software Description
TLV1544 START RINT Save Context Save Return Address, ST0, ST1, AR6, AR7, CWSR, PDWSR, PMST, INDX TINT
Disable Chip Select
Stop Timer
Initialize Disable Global Interrupts Configure PMST Wait-State Zero
Start Timer
Configure Enable Chip Select Send ADWORD Return From Interrupt
Initialize Serial Port Burst Mode, CLKX O/P, Internal Activate Transmitter Receiver
Read Serial Port Into TEMP
Valid Data Available (RINT_COUNT
Load User Defined Values Channel Into TEMP Memory Start Into ADMEM Samples Into ADCOUNT Control Mode Into ADWORD
Save Data Store TEMP Into Memory Increment Memory Address Decrement Samples Return From Interrupt
Configure Timer Timer Period Fast Conversion (Default) Check Whether Slow Conversion Selected Timer Period Slow Conversion Selected Reload Stop Timer
Samples Received (ADCOUNT
1544 Program END_BIT Disable RINT TINT
Enable RINT TINT Clear Pending RINT TINT Unmask RINT TINT Enable Global Interrupts
Return From RINT
Initialize RINT_COUNT END_BIT Enable Chip Select Send ADWORD TEMP Into ADWORD
Return From Interrupt
Exit 1544 Program (END_BIT Restore Context Restore Return Address, ST0, ST1, AR6, AR7, PDWSR, CWSR, PMST, INDX
IDLE Wait Interrupts
RINT
TINT
Return C-Program
Figure Flowchart C1544IN.asm (Timer Interrupt Source)
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Software Description
RINT (Receive Interrupt Routine)
With initialization into fast-conversion mode, starts first data transfer control data 16-bit data frame. Therefore, upon 16th clock cycle CLKX, RINT generated that forces execute RINT service routine (RINT-ISR). beginning RINT routine, output taken high, disabling ADC. Then zero start timer. After that content data receive register (DRR), stored into temporary (TEMP) register. following decision investigates receive data validity checking content RINT_COUNT value higher than two. Since takes data transfers configure completely-one specify conversion mode second select analog input channel-the conversion results from invalid both transfers. With each data transfer generating receive interrupt, number occurring RINTs (which stored RINT_COUNT) must three indicate that valid data available. valid data available, leaves RINT-ISR configure channel number timer interrupt service routine (TINT-ISR). valid data available, latest receive data, stored TEMP, saved into memory. Subsequently memory address increased incrementing content ADMEM, number samples decreased decrementing content ADCOUNT. second decision checks whether samples have been received. samples were received, END_BIT zero both interrupts, RINT TINT, disabled. program leaves RINT-ISR returns program through EXIT routine. samples were received, returns from RINT-ISR into idle mode waits timer interrupt occur.
TINT (Timer Interrupt Routine)
TINT routine loads serial port with transmit data initiates data transfer. Once timer period elapsed, timer interrupt generated that causes enter TINT service routine. beginning one, which stops timer immediately. Then initiates data transfer taking output enable ADC. channel number stored ADWORD loaded into serial port sent control word. Afterwards program returns from interrupt resides idle mode until next RINT occurs.
Exit 1544 program
This decision determines whether entire data transfer program terminated. long END-BIT one, diverts idle mode continue acquiring data. Once END_BIT been zero, previously saved registers save-context restored. exits interface routine returns program.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Software Description
Program-2 (Filename: C1544CLK.asm Timer Clock-Source)
Program supports non-glueless interface Figure this application operates from supply configured slow conversion mode. required transfer clock MHz. Since only frequency provide CLKX (1/2 clock), on-chip timer configured programmable clock source providing 2-MHz clock signal TOUT. Although this timer configuration required low-volt operation ADC, allows clock rate TOUT increased operates supply voltages above operate fast conversion mode, voltages below must operated slow conversion mode. Because timer serves here clock generator, longer available interrupt source indicate state TLV1544. Instead, signal inverted into external interrupt input, INT3, DSP. remaining configuration same program serial port configured burst-mode operation, generation pulse happens chip.
TLV1544 2-10 TOUT CLKX CLKR DATA DATA X2/CLKIN INT3 Timer TMS320C50
Analog Inputs
Figure External Interrupt, INT3, Detects External Inverter timing diagram Figure divides data transfer sequence into four steps: activates taking low. Then control word initialize loaded into serial port. Actual data transfer happens while sends control data configure operation mode, transmits conversion results serial port receiver. 16th clock cycle after gone low, RINT generated. following RINT-ISR disables ADC, stores received data into memory, returns from interrupt idle mode. idles remaining conversion time. conversion, signal causes external interrupt through INT3 input. following interrupt service routine, INT3-ISR, enables data transfer loads latest control word into serial port.
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Software Description
MHz)
DATA
DATA
RINT
INT3
Figure Data Transfer Sequence When Using INT3 Slow Conversion data transfer takes when operates slow conversion mode. I/OCLK MHz. When operating fast conversion mode, data transfer takes MHz.
5.2.1 Assembler Program-2 Description
flowchart Figure shows structure Program sequence tasks very similar Program major difference lies timer clock generator, detection through external interrupt pin, INT3.
TLV1544START
program starts with call main routine, C1544CLK from program. previously used pointers registers saved initialized. following initialization serial port configures CLKX input receive interface clock from timer output (TOUT). setup Burst-mode operation on-chip frame-sync generation remains same.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Initial Previous Conversion Results
Software Description
user-defined-values, control mode, been replaced variable, VCC. user select between (2.7 (5.5 supply voltage. During timer configuration, default values defined low-volt operation. ADWORD loaded with code slow conversion period register timer programmed provide interface clock TOUT. user selected then content both registers overwritten. content ADWORD changes fast conversion, reloaded with value that generates 5-MHz clock TOUT. selected, default values remain unchanged. Following configuration, timer started provide selected interface clock TOUT. Interrupts RINT INT3 enabled initialized. goes into idle mode until, 16th clock cycle after gone low, receive interrupt occurs.
RINT (Receive Interrupt Routine)
beginning RINT-ISR, disabled output DSP. receive data loaded into TEMP and, depending their validity, stored into memory. memory pointer incremented, sample counter decremented. check performed whether data have been received. answer yes, exits RINT-routine returns program. more samples need acquired, returns from RINT into idle mode, where resides until INT3 occurs.
INT3 (External Interrupt Routine)
INT3-ISR loads serial port with transmit data initiates data transfer. Once output changes from high, external interrupt generated that causes enter INT3 service routine. Immediately initiates data transfer enabling through pin. Afterwards, channel number stored ADWORD sent control word. Then returns from interrupt into idle mode waits until next RINT occurs.
Exit 1544 program
long END-BIT one, diverts idle mode continue acquiring data. Once END_BIT been zero, previously saved registers save-context restored. exits interface routine return program.
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Software Description
TLV1544 START
Save Context Save Return Address, ST0, ST1, AR6, AR7, CWSR, PDWSR, PMST, INDX
RINT
INT3
Disable Chip Select Initialize Disable Global Interrupts Configure PMST Wait-State Zero
Configure Enable Chip Select Send ADWORD Return From Interrupt
Read Serial Port Into TEMP
Initialize Serial Port Burst Mode, CLKX I/P, On-Chip Generation Activate Transmitter Receiver
Valid Data Available (RINT_COUNT
Load User Defined Values Channel Into TEMP Memory Start Into ADMEM Samples Into ADCOUNT
Save Data Store TEMP Into Memory Increment Memory Address Decrement Samples Return From Interrupt
Configure Timer Conversion Mode ADWORD Slow Conversion TOUT Rate (Default Reconfigure ADWORD Fast Conversion TOUT Rate Start Timer
Samples Received (ADCOUNT
1544 Program END_BIT Disable RINT
Enable RINT TIN3 Clear Pending RINT Unmask RINT Enable Global Interrupts Return From RINT Initialize RINT_COUNT END_BIT Enable Chip Select Send ADWORD TEMP Into ADWORD
Return From Interrupt
Exit 1544 Program (END_BIT
IDLE Wait Interrupts
RINT
INT3
Restore Context Restore Return Address, ST0, ST1, AR6, AR7, PDWSR, CWSR, PMST, INDX
Return C-Program
Figure Flowchart C1544CLK.asm (Timer Clock Source)
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Software Description
Program-3 (Filename: C1544NOP.asm Timer Clock-Source delay-loop)
Program supports glueless interface supply voltage only. Figure shows that this circuit almost identical Figure except this does need external inverter. operates from supply configured slow conversion mode only. on-chip timer provides required interface clock TOUT. configuration serial port same program serial port configured burst-mode operation, CLKX programmed inputs, generation happens on-chip. achieve glueless interface, external inverter, previously used indication, removed. Instead, delay loop no-operation (NOPs) instructions implemented, that waits maximum conversion time pass.
TLV1544 TOUT CLKX CLKR DATA DATA X2/CLKIN Timer TMS320C50
Analog Inputs
Figure Wait-loop Indicates Glueless Interface Low-Volt Application timing diagram Figure divides data transfer sequence into steps. Step actual data transfer, where sends control data transmits conversion results. Step represents execution phase entire RINT routine. Since RINT only interrupt used this program, task limited finishing transfer sequence saving data, also includes waiting maximum conversion time pass initiating next data transfer.
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Software Description
31.5 MHz)
Initial
DATA
DATA
RINT
Figure Data Transfer Sequence When Using Wait-Loop Low-Volt Application Since works from 2.7-V supply, device needs operate slow conversion mode. data sheet specifies maximum conversion time with thus expanding time data transfer 31.5
5.3.1 Assembler Program-2 Description
flowchart Figure shows structure Program which almost identical Program major difference that only interrupt routine used previous data transfer initiate next one.
TLV1544START
program starts with call main routine, C1544NOP from program. serial port initialized Program Since this program supports only glueless, low-volt interface, conversion mode interface clock fixed values. User-defined variables reduced three: channel number, memory start address, number samples. conversion mode slow conversion, time programmed provide 2-MHz interface clock through TOUT. After enabling receive interrupt initializing ADC, goes into idle mode waits next RINT occur.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Previous Conversion Results
Conversion Time
Software Description
TLV1544 START
Save Context Save Return Address, ST0, ST1, AR6, AR7, CWSR, PDWSR, PMST, INDX
RINT
Disable Chip Select Initialize Disable Global Interrupts Configure PMST Wait-State Zero
Read Serial Port Into TEMP
Initialize Serial Port Burst Mode, CLKX I/P, On-Chip Generation Activate Transmitter Receiver
Valid Data Available (RINT_COUNT
Load User Defined Values Channel Into TEMP Memory Start Into ADMEM Samples Into ADCOUNT
Save Data Store TEMP Into Memory Increment Memory Address Decrement Samples
Configure Timer Conversion Mode ADWORD Slow Conversion TOUT Rate
Samples Received (ADCOUNT 1544 Program END_BIT Stop Timer Disable RINT Return From Interrupt
Next Data Transfer Delay Enable Chip Select Send ADWORD Return From Interrupt
Enable RINT Clear Pending RINT Unmask RINT Enable Global Interrupts Return From Interrupt Initialize RINT_COUNT END_BIT Enable Chip Select Send ADWORD TEMP Into ADWORD Exit 1544 Program (END_BIT Restore Context Restore Return Address, ST0, ST1, AR6, AR7, PDWSR, CWSR, PMST, INDX Return From Interrupt
IDLE Wait Interrupts
RINT
Return C-Program
Figure Flowchart C1544NOP.asm (Timer Clock Source delay)
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Software Description
RINT (Receive Interrupt Routine)
root path RINT-ISR identical Program difference that further data transfers initiated second interrupt routine, bypass task within RINT routine itself. case valid data available samples received, program diverts bypass task, called Next Data Transfer. this task, wait loop, consisting NOPs instructions generates delay that sufficient maximum conversion time pass. next data transfer initiated enabling chip select sending channel number ADC. Then returns idle mode waits next RINT occur. During entire data acquisition process, jumps RINT-ISR. Once samples received, exits interrupt routine returns program same Program1.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Summary
Summary
This report discussed components low-cost, low-power data acquisition system shown Figure low-dropout voltage regulator, TPS7101, programmable through external voltage divider provide required supply voltages low-noise, dual operational amplifier, TLV2772, builds signal conditioning interface TLV1544 ADC. stage works noninverting amplifier with closed-loop gain interface small input signals between ADC. second stage operates inverting amplifier with gain 0.25, allowing large input signals interfaced ADC. TLV1544 10-bit, with four analog inputs. device interfaces easily with TMS320C50 build simple data acquisition system used battery powered applications well industrial control systems.
TPS7101 (218
TLV2772 TOUT CLKR CLKX INT3 TMS320C50 INT3 Timer TINT
CSTART REF+ 10-Bit DATA DATA REF-
TLV1544 TLV2772
SN74HC1G04
Figure Interfacing TLV1544 with TMS320C50 report also includes three C-callable interface programs, which support different hardware configurations serial interface between DSP. Depending supply voltage ADC, interface clock vary between MHz, conversion mode must adjusted either fast slow conversion.
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Summary
interfaces directly does require additional control logic. However, data throughput doubled external inverter used between output external interrupt inputs (INT0-INT3) DSP. Figure shows different periods between high-to-low transitions chip-select pin.
Glueless Interface 15.8
31.5
Interface With Inverter
Time
Figure Time Periods Between Consecutive Data Transfers Different Applications operate fast conversion mode with interface clock rate MHz. must work slow conversion mode. Also interface clock limited maximum 2.89 MHz. Since actual conversion time individual device differ from specified maximum factor two, overall data transfer period data throughput directly affected. Using glueless interface means that direct indication provided from ADC. Therefore, interface program must wait maximum conversion time pass before initiating data transfer. operates uses fast conversion mode, time between consecutive data transfers takes 15.8 This time increases 31.5 when operating slow conversion mode.
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
Summary
increase data throughput, actual conversion time needs detected immediately. external inverter, that connects output with interrupt inputs DSP, provides direct feedback status. This activated interrupt routine immediately initiate next data transfer. duration data transfer period reduced when operating takes only when operating
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References
References
additional information reference, following related documents: TMS320C5x User's Guide, literature number SPRU056 TMS320C5x Data Sheet, literature number SPRS030 TLV1544 Data Sheet, literature number SLAS139 TLV1544 Manual, literature number SLAU014 TLV2432 Data Sheet, literature number SLOS168B TPS7101 Data Sheet, literature number SLVS092F SN74AHC1G04 Data Sheet, literature number SCLS318G Switched-Capacitor Analog Input Calculations Application Report, literature number SLAA036
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
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TLV1544 Program Files: Timer Interrupt Source)
Appendix
TLV1544 Program Files: Timer Interrupt Source)
Boot Routine: BOOTIN.ASM
TITLE FILE DESCRIPTION AUTHOR REFERENCE TLV1544 boot routine (timer interrupt source)* BOOTTIN.ASM Boot routine initialize c-program 'main()' C1544T.C file. Application Group, Dallas CREATED 1998(C) TEXAS INSTRUMENTS INCORPORATED. TMS320C5x User's Guide, 1997
Data Acquisition Circuits, 1998 .mmregs Declare stack. _stack: .def .ref .text _c_int0: INITIALIZATION BODY .usect _c_int0 _main ".stack",0
INITIALIZATION SETC IN#0 #0038h, PMST disable global interrupts load data page configure PMST
INITIAL STACK FRAME POINTERS
LRLK LRLK AR0,_stack AR1,_stack *,AR1 _main frame pointer main routine stack pointer main routine pointer select jump program main
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: Timer Interrupt Source)
C-Program: C1544T.C
TITLE: File: TLV1544 program main routine (timer interrupt source) C1544T.C
Description: this c-program file user selects input channel, conversion mode, memory start address, number
samples.This c-program then calls C1544TIN() interface program execute
Programmed Operation Mode: Channel: Select TLV1544 channel Select TLV1544 channel Select TLV1544 channel Select TLV1544 channel (Vreg+ Vreg-)/2 Vreg- Vreg+ ControlMode: Software Power Down Fast Conversion Rate Slow Conversion Rate 0x08000 0x09000 0x0A000 Value: 0x0000 0x2000 0x4000 0x6000 0x0B000 0x0C000 0x0D000
extern ControlMode, Channel, Samples, MemStart; extern void C1544TIN(void); main() Fast Conversion Mode ControlMode 0x09000; Select channel Channel 0x2000; Take samples Samples 0x100; Memory Start Address MemStart 0x1000; Call TLV1544 Interface Program C1544TIN();
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TLV1544 Program Files: Timer Interrupt Source)
C-Callable Interface Program: C1544TIN.ASM
TITLE FILE FUNCTION DESCRIPTION AUTHOR REFERENCE TLV1544 C-Callable Interface routine (timer interrupt source) C1544TIN.ASM _C1544TIN Main routine transfer data between TLV1544 serial interface. first initializes ADC, then transfers data from stores them within pre-defined memory table. This program uses timer indicator.
timer waits conversion time pass,* then sends timer interrupt (TINT) CPU. data transfer procedure supported interrupt routines, RINT TINT. Application Group, Dallas. CREATED 1998(C) TEXAS INSTRUMENTS INCORPORATED. TMS320C5x User's Guide, 1997 Data Acquisition Circuits, 1998
.mmregs .sect ".vectors" .copy "VECTIN.asm" LOCALS .SET
Global Variables .global .global .global .global .global .global Local Variables .def .def .def .def .def .def AD_DP ADWORD ADCOUNT ADMEM ADWORD ADCOUNT ADMEM RINT_COUNT END_BIT TEMP .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", data page local variable control word counter samples memory pointer during interrupts _C1544TIN _Samples _MemStart _Channel _ControlMode _c_int0
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: Timer Interrupt Source)
RINT_COUNT END_BIT TEMP _Samples _MemStart _Channel _ControlMode .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", number receive interrupts end-of-data-transfer-program flag temporary data memory user defined number sample user defined memory pointer user defined channel user defined control mode
.sect ".text" TLV1544 START _C1544TIN: Save Context POPD ADRK LAMM SACL LAMM SACL LAMM SACL LAMM SACL AR0, AR1, ar0,*+,ar1 #LOCALS AR6, AR7, PDWSR CWSR PMST INDX save INDX register save PMST register save wait-state control register save return address save Frame Pointer (ar0) save Stack Pointer (ar1) set-up Frame Pointer set-up Stack Pointer save status register save status register save save save wait-sate register
Initialize SETC IN#0 #0038h, PMST #0000h, PDWSR #00F0h, CWSR disable global interrupts load data page Configure PMST wait-states zero wait-states zero
Initialize Serial Port SPLK #0038h,SPC Burst Mode, CLKX CLKOUT1 generated SPLK #00F8h,SPC activate transmitter receiver
Load User defined Values LACL SACL LACL #AD_DP _Channel TEMP _MemStart load data page AD_DP
LOAD _Channel into TEMP LOAD _MemStart into ADMEM
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TLV1544 Program Files: Timer Interrupt Source)
SACL LACL SACL LACL SACL ADMEM _Samples ADCOUNT _ControlMode ADWORD LOAD _Samples into ADCOUNT LOAD _ControlMode into ARWORD
Configure Timer SPLK CLRC BCND SPLK #199,PRD #0A000h TIMER_INI, #499, load timer period (slow mode) load data page load timer period 10us fast mode clear sign-extension mode compare slow mode
TIMER_INI: SPLK #00030h,TCR load data page reload PRD/TDDR stop timer
Enable RINT TINT #00018h,IFR interrupt CLRC #00018h,IMR clear pending RINT TINT unmask RINT TINT enable global interrupts
INITIALIZE SPLK SPLK LACL CLRC SAMM LACL SACL Idle Idle_Mode: IDLE Exit 1544 program LACL BCND #AD_DP END_BIT Idle_Mode,NEQ END_BIT Idle_Mode power down (IDLE), waiting interrupts #AD_DP #0h, RINT_COUNT #1h,END_BIT ADWORD TEMP ADWORD load data page AD_DP RINT_COUNT END_BIT load ADWORD (Conv.Mode) into (ACL) enable Chip Select Send ADWORD load TEMP (Channel into ADWORD
Restore Context LACL make Stack Pointer (ar1) active decrement Stack Pointer (ar1)
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: Timer Interrupt Source)
SAMM LACL SAMM LACL SAMM LACL SAMM SBRK PSHD INDX PMST CWSR PDWSR AR7, AR6, #(LOCALS+1) AR0, restore wait-state register restore restore restore restore de-allocate frame size restore Frame Pointer (ar0) push return address hardware stack restore wait-state control register restore PMST register restore INDX register
Return C-program return C-program
RINT receive interrupt routine (RINT) disables Chip Select signal stores received data into memory location specified ADMEM. increments memory pointer decrements number samples being transferred. RINT_IRQ: Disable Chip Select SETC disable Chip Select
Start Timer SPLK #20h,TCR load data page start timer
Read Serial Port LACC SACH DRR,10 #TEMP TEMP load content ACCh shift load data page #TEMP ACCH TEMP
Valid data available LACL SACL BCND RINT_COUNT RINT_COUNT RINT_END,LEQ ACCL RINT_COUNT increment RINT_COUNT ACCL skip saving data until RINT_COUNT
Save data #ADMEM *,AR7 AR7, ADMEM load data page #ADMEM select ADMEM
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TLV1544 Program Files: Timer Interrupt Source)
LACL SACL LACL SACL TEMP AR7, ADMEM ADCOUNT ADCOUNT load TEMP into (ACL) save sample memory increment memory address (ADMEM) load ADCOUNT into (ACL) decrement ADCOUNT ADCOUNT
samples received BCND RINT_END,NEQ ADCOUNT jump DISABLE_CS
1544 program SPLK SPLK SPLK #END_BIT #0h,END_BIT #0010h, #0018h,IFR #0FFE7h,IMR load data page #END_BIT END_BIT load data page stop timer clear pending RINT TINT mask RINT TINT
Return from RINT RINT_END: RETE return from RINT-ISR "Exit 1544 program
TINT interrupt routine internal interrupt, TINT, initiated timer. This routine enables Chip Select signal sends current control word, defined ADWORD, ADC. TINT_IRQ: Stop Timer SPLK #00010h,TCR load data page stop timer
Configure LACL CLRC SAMM RETE .copy "BOOTTIN.asm" #ADWORD ADWORD load data page #ADWORD load ADWORD into (ACL) enable Chip Select move ADWORD into return from TINT-ISR "Exit 1544 program
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: Timer Interrupt Source)
Vector Table: VECTIN.ASM
TITLE FILE TLV1544 Interface Vector routine (timer interrupt source) VECTIN.ASM
DESCRIPTION This file defines interrupt vector table. AUTHOR REFERENCE TINT occurs: vector points TINT_IRQ subroutine. RINT occurs: vector points RINT_IRQ subroutine. Application Group, Dallas CREATED 1998(C) TEXAS INSTRUMENTS INCORPORATED. TMS320C5x User's Guide, 1997
.global INT1 INT2 INT3 TINT RINT XINT TRNT TXNT INT4 _c_int0 INT1 INT2 INT3 TINT_IRQ RINT_IRQ XINT TRNT TXNT INT4 14*16 _main ;0x00; RESET ;0x02; external user interrupt ;0x04; external user interrupt ;0x06; external user interrupt ;0x08; internal timer interrupt ;0x0A; Serial Port receive interrupt ;0x0C; Serial Port transmit interrupt ;0x0E; receive interrupt ;0x10; transmit interrupt ;0x12; external user interrupt ;0x14-0x21; reserved area ;0x22; trap instruction vector ;0x24; non-maskable interrupt
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SLAA025A
TLV1544 Program Files: Timer Clock Source
Appendix
TLV1544 Program Files: Timer Clock Source
Boot Routine: BOOTCLK.ASM
TITLE FILE DESCRIPTION AUTHOR REFERENCE TLV1544 boot routine (timer clock source) BOOTCLK.ASM Boot routine initialize c-program 'main()' C1544C.C file. Application Group, Dallas CREATED 1998(C) TEXAS INSTRUMENTS INCORPORATED. TMS320C5x User's Guide, 1997
Data Acquisition Circuits, 1998 .mmregs Declare stack.
_stack: .def .ref .text _c_int0: INITIALIZATION BODY .usect _c_int0 _main ".stack",0
INITIALIZATION SETC IN#0 #0038h, PMST disable global interrupts load data page configure PMST
INITIAL STACK FRAME POINTERS
LRLK LRLK AR0,_stack AR1,_stack *,AR1 _main frame pointer main routine stack pointer main routine pointer select jump program main
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: Timer Clock Source
C-Program: C1544C.C
TITLE: File: TLV1544 program main routine (timer clock source) C1544C.C Value: 0x0000 0x2000 0x4000 0x6000 0x0B000 0x0C000 0x0D000 0x08000 0x09000 0x0A000
Description: this c-program file user selects start address, number samples. This c-program then calls C1544CLK() interface program execute
input channel, conversion mode, memory
Programmed Operation Mode: Channel: Select TLV1544 channel Select TLV1544 channel Select TLV1544 channel Select TLV1544 channel (Vreg+ Vreg-)/2 Vreg- Vreg+ ControlMode: Software Power Down Fast Conversion Rate Slow Conversion Rate
extern Vcc, Channel, Samples, MemStart; extern void C1544CLK(void); main() Select Vcc, Select channel Channel 0x2000; Take samples Samples 0x100; Memory Start Address MemStart 0x1000; Call TLV1544 Interface Program C1544CLK();
SLAA025A
TLV1544 Program Files: Timer Clock Source
C-Callable Interface Program: C1544CLK.ASM
TITLE: FILE: FUNCTION: DESCRIPTION: AUTHOR: REFERENCE: .mmregs .sect ".vectors" .copy "VECCLK.asm" LOCALS .SET _C1544CLK _Samples _MemStart _Channel _Vcc _c_int0 ADWORD ADCOUNT ADMEM RINT_COUNT END_BIT TEMP .usect ".variabl", .usect ".variabl", .usect ".variabl", data page local variable control word counter samples TLV1544 C-Callable Interface routine (timer clock source) C1544CLK.ASM _C1544CLK Main routine transfer data between TLV1544 serial interface.At first initializes ADC, then transfers data from stores them within pre-defined memdory table. This program uses signal TLV1544 ADC. data transfer procedure supported interrupt routines, RINT INT3.The timer configured clock source provide different clock rates Vcc,and Application Group, Dallas. CREATED 1998(C) TEXAS INSTRUMENTS INCORPORATED TMS320C5x User's Guide, 1997 Data Acquisition Circuits, 1998
Global Variables .global .global .global .global .global .global Local Variables .def .def .def .def .def .def AD_DP ADWORD ADCOUNT
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: Timer Clock Source
ADMEM RINT_COUNT END_BIT TEMP _Samples _MemStart _Channel _Vcc .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", memory pointer during interrupts number receive interrupts end-of-data-transfer-program flag temporary memory data user defined number sample user defined memory pointer user defined channel user defined
.sect ".text" TLV1544 START _C1544CLK: Save Context POPD ADRK LAMM SACL LAMM SACL LAMM SACL LAMM SACL AR0, AR1, ar0,*+,ar1 #LOCALS AR6, AR7, PDWSR CWSR PMST INDX save INDX register save PMST register save wait-state control register save return address save Frame Pointer (ar0) save Stack Pointer (ar1) set-up Frame Pointer set-up Stack Pointer save status register save status register save save save wait-sate register
Initialize SETC IN#0 #0038h, PMST #0000h, PDWSR #00F0h, CWSR disable global interrupts load data page Configure PMST wait-states zero wait-states zero
Initialize Serial Port SPLK #0028h,SPC Burst Mode, CLKX input generated SPLK #00E8h,SPC activate transmitter receiver
Load User defined Values LACL SACL #AD_DP _Channel TEMP point Data Page LOAD _Channel into (ACL) TEMP (ACL)
SLAA025A
TLV1544 Program Files: Timer Clock Source
LACL SACL LACL SACL LACL _MemStart ADMEM _Samples ADCOUNT _Vcc LOAD _MemStart into (ACL) ADMEM (ACL) LOAD _Samples into (ACL) ADCOUNT (ACC) LOAD _Vcc into (ACL)
Configure Timer conversion mode SPLK SPLK CLRC BCND SPLK SPLK #0A000h, ADWORD Timer_Start, #AD_DP #09000h, ADWORD load data page timer 5MHz load data page #AD_DP fast conversion mode Timer 2MHz clear sign extension mode check _Vcc slow conversion
Timer_Start: SPLK #00020h,TCR reload PRD/TDDR, start timer
Enable RINT INT3 CLRC #0014h,IFR #0014h,IMR clear RINT INT3 unmask RINT INT3 enable global interrupts
Iinitialize SPLK SPLK LACL CLRC SAMM LACL SACL Idle Idle_Mode: IDLE interrupts Exit 1544 program LACL BCND #AD_DP END_BIT Idle_Mode,NEQ Load END_BIT into (ACL) END_BIT Idle_Mode power down (IDLE), waiting #AD_DP #0h, RINT_COUNT #1h,END_BIT ADWORD TEMP ADWORD RINT_COUNT END_BIT Conversion Mode into enable Chip Select Send Conversion Mode Load Channel number into Save into ADWORD
Restore Context make Stack Pointer (ar1) active decrement Stack Pointer (ar1)
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: Timer Clock Source
LACL SAMM LACL SAMM LACL SAMM LACL SAMM SBRK PSHD INDX PMST CWSR PDWSR AR7, AR6, #(LOCALS+1) AR0, restore wait-state register restore restore restore restore de-allocate frame size restore Frame Pointer (ar0) push return address hardware stack return C-program restore wait-state control register restore PMST register restore INDX register
Return C-program RINT receive interrupt routine (RINT) disables Chip Select signal stores received data into memory location specified ADMEM. increments memory pointer decrements number samples being transferred. RINT_IRQ: Disable Chip Select SETC LACC SACH LACL SACL BCND DRR,10 #TEMP TEMP RINT_COUNT RINT_COUNT RINT_END,LEQ #ADMEM *,AR7 AR7, ADMEM select ADMEM disable Chip Select load data page load content ACCh; shift load data page #TEMP ACCH TEMP ACCL RINT_COUNT increment RINT_COUNT ACCL skip saving data until RINT_COUNT Read Serial Port
Valid data available
Save data
SLAA025A
TLV1544 Program Files: Timer Clock Source
LACL SACL LACL SACL TEMP AR7, ADMEM ADCOUNT ADCOUNT load sample into save sample memory increment memory address (ADMEM) ACCL ADCOUNT decrement ADCOUNT ADCOUNT
samples received BCND RINT_END,NEQ ADCOUNT jump RINT_END
1544 program SPLK SPLK SPLK #END_BIT #0h,END_BIT #0010h, #0014h, #0FFEBh,IMR END_BIT load data page stop timer clear pending RINT INT3 mask RINT INT3
Return from RINT RINT_END: RETE return from RINT-ISR "Exit 1544 program
INT3 interrupt routine external interrupt, INT3, initiated End-Of-Conversion signal sent from ADC. This routine enables Chip Select signal sends current control word, defined ADWORD, ADC. INT3_IRQ: Configure LACL CLRC SAMM RETE .copy "BOOTCLK.asm" #ADWORD ADWORD load ADWORD into enable Chip Select move ADWORD into return from INT3-ISR "Exit 1544 program
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: Timer Clock Source
Vector Table: VECCLK.ASM
TITLE FILE TLV1544 Interface Vector routine (timer clock source) VECCLK.ASM
DESCRIPTION This file defines interrupt vector table. AUTHOR INT3 occurs: vector points INT3_IRQ subroutine. RINT occurs: vector points RINT_IRQ subroutine. Application Group, Dallas CREATED 1998(C) TEXAS INSTRUMENTS INCORPORATED. TMS320C5x User's Guide, 1997
REFERENCE
.global INT1 INT2 INT3 TINT RINT XINT TRNT TXNT INT4 _c_int0 INT1 INT2 INT3_IRQ TINT RINT_IRQ XINT TRNT TXNT INT4 14*16 _main ;0x00; RESET ;0x02; external user interrupt ;0x04; external user interrupt ;0x06; external user interrupt ;0x08; internal timer interrupt ;0x0A; Serial Port receive interrupt ;0x0C; Serial Port transmit interrupt ;0x0E; receive interrupt ;0x10; transmit interrupt ;0x12; external user interrupt ;0x14-0x21; reserved area ;0x22; trap instruction vector ;0x24; non-maskable interrupt
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SLAA025A
TLV1544 Program Files: NOPs Wait-Loop
Appendix
TLV1544 Program Files: NOPs Wait-Loop
Boot Routine: BOOTNOP.ASM
TITLE FILE DESCRIPTION AUTHOR REFERENCE TLV1544 boot routine (NOPs wait-loop) BOOTNOP.ASM Boot routine initialize c-program 'main()' C1544N.C file. Application Group, Dallas CREATED 1998(C) TEXAS INSTRUMENTS INCORPORATED. TMS320C5x User's Guide, 1997
Data Acquisition Circuits, 1998 .mmregs Declare stack. _stack: .def .ref .text _c_int0: INITIALIZATION BODY .usect _c_int0 _main ".stack",0
INITIALIZATION SETC IN#0 #0038h, PMST disable global interrupts load data page configure PMST
INITIAL STACK FRAME POINTERS
LRLK LRLK AR0,_stack AR1,_stack *,AR1 _main frame pointer main routine stack pointer main routine pointer select jump program main
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: NOPs Wait-Loop
C-Program: C1544N.C
TITLE: File: Description: TLV1544 program main routine (NOPs wait-loop) C1544N.C this c-program file user selects input channel, memory start address number samples. This c-program then calls C1544NOP() interface program execute
Programmed Operation Mode: Channel: Select TLV1544 channel Select TLV1544 channel Select TLV1544 channel Select TLV1544 channel (Vreg+ Vreg-)/2 Vreg- Vreg+ ControlMode: Software Power Down Fast Conversion Rate Slow Conversion Rate 0x08000 0x09000 0x0A000 Value: 0x0000 0x2000 0x4000 0x6000 0x0B000 0x0C000 0x0D000
extern Channel, Samples, MemStart; extern void C1544NOP(void); main() Select channel Channel 0x2000;
Take samples Samples 0x100;
Memory Start Address MemStart 0x1000; Call TLV1544 Interface Program C1544NOP();
SLAA025A
TLV1544 Program Files: NOPs Wait-Loop
C-Callable Interface Program: C1544NOP.ASM
TITLE FILE FUNCTION DESCRIPTION AUTHOR REFERENCE TLV1544 C-Callable Interface routine (timer clock source) C1544NOP.ASM _C1544NOP Main routine transfer data between andTLV1544 serial interface. first initializes ADC, then transfers data from stores them within pre-defined memory table. This program uses delay loop indicator. delay loop waits conversion time pass,before staring data transfer. timer configured provide clock data transfer procedure supported receive interrupt routine only. Application Group, Dallas.
CREATED 1998(C) TEXAS INSTRUMENTS INCORPORATED. TMS320C5x User's Guide, 1997 Data Acquisition Circuits, 1998
.mmregs .sect ".vectors" .copy "VECNOP.asm"
LOCALS
.SET
Global Variables .global .global .global .global .global Local Variables .def .def .def .def .def .def AD_DP variable ADWORD ADCOUNT ADWORD ADCOUNT ADMEM RINT_COUNT END_BIT TEMP .usect ".variabl", .usect ".variabl", .usect ".variabl", data page local control word counter samples _C1544NOP _Samples _MemStart _Channel _c_int0
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: NOPs Wait-Loop
ADMEM interrupts RINT_COUNT interrupts END_BIT flag TEMP _Samples _MemStart _Channel .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", .usect ".variabl", memory pointer during number receive end-of-data-transfer-program temporary memory data user defined number sample user defined memory pointer user defined channel
.sect ".text" TLV1544 START _C1544NOP: Save Context POPD ADRK LAMM SACL LAMM SACL LAMM SACL LAMM SACL AR0, AR1, ar0,*+,ar1 #LOCALS AR6, AR7, PDWSR CWSR PMST INDX save INDX register save PMST register save wait-state control register save return address save Frame Pointer (ar0) save Stack Pointer (ar1) set-up Frame Pointer set-up Stack Pointer save status register save status register save save save wait-sate register
Initialize SETC IN#0 #0038h, PMST #0000h, PDWSR #00F0h, CWSR disable global interrupts load data page Configure PMST wait-states zero wait-states zero
Initialize Serial Port SPLK #0028h,SPC Burst Mode, CLKX input generated SPLK #00E8h,SPC activate transmitter receiver
Load User defined Values LACL #AD_DP _Channel point Data Page LOAD _Channel into TEMP
SLAA025A
TLV1544 Program Files: NOPs Wait-Loop
SACL LACL SACL LACL SACL TEMP _MemStart ADMEM _Samples ADCOUNT LOAD _Samples into ADCOUNT LOAD _MemStart into ADMEM
Configure Timer conversion mode SPLK SPLK CLRC SPLK #0A000h, ADWORD #00020h,TCR Timer 2MHz clear sign extension mode reload PRD/TDDR, start timer slow conversion
Enable RINT INT3 CLRC #0010h,IFR #0010h,IMR clear RINT unmask RINT enable global interrupts
Iinitialize SPLK SPLK LACL CLRC SAMM LACL SACL Idle Idle_Mode: IDLE interrupts Exit 1544 program LACL BCND #AD_DP END_BIT Idle_Mode,NEQ Load END_BIT into (ACL) END_BIT Idle_Mode power down (IDLE), waiting #AD_DP #0h, RINT_COUNT #1h,END_BIT ADWORD TEMP ADWORD RINT_COUNT END_BIT Conversion Mode into enable Chip Select Send Conversion Mode Load Channel number into Save into ADWORD
Restore Context LACL SAMM LACL SAMM LACL SAMM LACL SAMM INDX PMST CWSR PDWSR restore wait-state register restore wait-state control register restore PMST register restore INDX register make Stack Pointer (ar1) active decrement Stack Pointer (ar1)
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: NOPs Wait-Loop
SBRK PSHD AR7, AR6, #(LOCALS+1) AR0, restore restore restore restore de-allocate frame size restore Frame Pointer (ar0) push return address hardware stack
Return C-program return C-program
RINT receive interrupt routine (RINT) disables Chip Select signal stores received data into memory location specified ADMEM. increments memory pointer decrements number samples being transferred initiates next data transfer. RINT_IRQ: Disable Chip Select SETC disable Chip Select
Read Serial Port LACC SACH DRR,10 #TEMP TEMP load data page load content ACCh; shift load data page #TEMP ACCH TEMP
Valid data available LACL SACL BCND RINT_COUNT RINT_COUNT NEXT_DATA,LEQ ACCL RINT_COUNT increment RINT_COUNT ACCL skip saving data until RINT_COUNT
Save data LACL SACL LACL SACL #ADMEM *,AR7 AR7, ADMEM TEMP AR7, ADMEM ADCOUNT ADCOUNT select ADMEM load sample into save sample memory increment memory address (ADMEM) ACCL ADCOUNT decrement ADCOUNT ADCOUNT
samples received BCND NEXT_DATA,NEQ ADCOUNT jump NEXT_DATA
SLAA025A
TLV1544 Program Files: NOPs Wait-Loop
1544 program SPLK SPLK SPLK RETE Next Data Transfer NEXT_DATA: LACL CLRC SAMM RETE .copy "BOOTNOP.asm" #ADWORD ADWORD load ADWORD into Accu enable Chip Select send ADWORD return from RINT-ISR next data #18Fh NOPs delay #END_BIT #0h,END_BIT #0010h, #0010h, #0FFEFh,IMR END_BIT load data page stop timer clear pending RINT mask RINT return from RINT-ISR "Exit 1544 program
Interfacing TLV1544 Analog-to-Digital Converter TMS320C50
TLV1544 Program Files: NOPs Wait-Loop
Vector Table: VECNOP.ASM
TITLE FILE TLV1544 Interface Vector routine (NOPs wait-loop) VECNOP.ASM
DESCRIPTION This file defines interrupt vector table. AUTHOR REFERENCE RINT occurs: vector points RINT_IRQ subroutine. Application Group, Dallas CREATED 1998(C) TEXAS INSTRUMENTS INCORPORATED. TMS320C5x User's Guide, 1997
.global INT1 INT2 INT3 TINT RINT XINT TRNT TXNT INT4 _c_int0 INT1 INT2 INT3 TINT RINT_IRQ XINT TRNT TXNT INT4 14*16 _main ;0x00; RESET ;0x02; external user interrupt ;0x04; external user interrupt ;0x06; external user interrupt ;0x08; internal timer interrupt ;0x0A; Serial Port receive interrupt ;0x0C; Serial Port transmit interrupt ;0x0E; receive interrupt ;0x10; transmit interrupt ;0x12; external user interrupt ;0x14-0x21; reserved area ;0x22; trap instruction vector ;0x24; non-maskable interrupt
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SLAA025A
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