High Speed CMOS Logic Triple 3-Input Gate Harris CD54HCT11, CD74H
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CD54HCT11, CD74HC11, CD74HCT11
High Speed CMOS Logic Triple 3-Input Gate
Harris CD54HCT11, CD74HC11, CD74HCT11 logic gates utilize silicon gate CMOS technology achieve operating speeds similar LSTTL gates with power consumption standard CMOS integrated circuits. devices have ability drive LSTTL loads. 74HCT logic family functionally compatible with standard 74LS logic family.
August 1997
Features
Buffered Inputs Typical Propagation Delay: 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
/Title (CD54 HCT11 CD74 HC11, CD74 HCT11 /Subject (High
Ordering Information
PART NUMBER CD74HC11E CD74HCT11E CD74HC11M CD74HCT11M CD54HCT11F NOTES: When ordering, entire part number. suffix obtain variant tape reel. this part number available which meets electrical specifications. Please contact your local sales office Harris customer service ordering information. TEMP. RANGE (oC) PACKAGE PDIP PDIP SOIC SOIC CERDIP PKG. E14.3 E14.3 M14.15 M14.15 F14.3
Pinout
CD54HCT11, CD74HC11, CD74HCT11 (PDIP, CERDIP, SOIC) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
Harris Corporation 1997
File Number
1475.1
CD54HCT11, CD74HC11, CD74HCT11 Functional Diagram
TRUTH TABLE INPUTS OUTPUT
Logic Symbol
CD54HCT11, CD74HC11, CD74HCT11
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, IGND .±50mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) PDIP Package CERDIP Package SOIC Package Maximum Junction Temperature (Hermetic Package Die) 175oC Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range (TA) -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 Level Output Voltage Loads Input Leakage Current 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HCT11, CD74HC11, CD74HCT11
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load (Note NOTE: dual-supply systems theorectical worst case 2.4V, 5.5V) specification 1.8mA. -0.02 3.98 3.84 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
0.02
0.26
0.33
±0.1
Input Loading Table
INPUT UNIT LOADS
NOTE: Unit Load limit specified Electrical Specifications table, e.g. 360µA 25oC.
Switching Specifications Input
PARAMETER TYPES Propagation Delay, Input Output (Figure tPLH, tPHL 50pF Propagation Delay, Data Input Output tPLH, tPHL 15pF SYMBOL TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
CD54HCT11, CD74HC11, CD74HCT11
Switching Specifications Input
PARAMETER Transition Times (Figure SYMBOL tTLH, tTHL (Continued) Input Capacitance Power Dissipation Capacitance (Notes TYPES Propagation Delay, Input Output (Figure Propagation Delay, Data Input Output Transition Times (Figure Input Capacitance Power Dissipation Capacitance (Notes NOTES: used determine dynamic power consumption, gate. VCC2 (CPD where input frequency, output load capacitance, supply voltage. tPLH, tPHL tPLH, tPHL tTLH, tTHL 50pF 15pF 50pF 50pF 50pF 15pF 25oC -40oC 85oC -55oC 125oC UNITS
TEST CONDITIONS 50pF
Test Circuits Waveforms
INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V
tTHL
INVERTING OUTPUT
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
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Copyright 1999, Texas Instruments Incorporated
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