4-Bit Binary Fill Adder With Fast Carry CD74AC283 CD74ACT283 4-bi
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CD74AC283, CD74ACT283
4-Bit Binary Fill Adder With Fast Carry
CD74AC283 CD74ACT283 4-bit binary adders with fast carry that utilize Advanced CMOS Logic technology. These devices 4-bit binary numbers generate carry-out exceeds Because symmetry function, this device used with either active-HIGH operands (positive logic) with active-LOW operands (negative logic). When using positive logic, carry-in input must tied there carry-in.
August 1998 Revised January 2000
Features
Buffered Inputs Exceeds Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process Circuit Design Speed Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays Types Feature 1.5V 5.5V Operation Balanced Noise Immunity Supply ±24mA Output Drive Current Fanout FASTICs Drives Transmission Lines
Ordering Information
PART NUMBER CD74AC283E CD74ACT283E CD74AC283M CD74ACT283M NOTES: When ordering, entire part number. suffix obtain variant tape reel. Wafer this part number available which meets electrical specifications. Please contact your local TIsales office customer service ordering information. TEMP. RANGE (oC) PACKAGE PKG. E16.3 E16.3 M16.15 M16.15
70oC, PDIP 70oC, PDIP 70oC, SOIC 70oC, SOIC
Pinout
CD74AC283, CD74ACT283 (PDIP, SOIC) VIEW
Functional Diagram
COUT COUT
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis Trademark Fairchild Semiconductor. trademark Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated
CD74AC283, CD74ACT283
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±50mA Output Source Sink Current Output Pin, -0.5V 0.5V .±50mA Ground Current, IGND (Note .±100mA
Thermal Information
Thermal Impedance (Typical, Note (oC/W) PDIP Package 67oC/W SOIC Package 73oC/W Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, (Note Types. .1.5V 5.5V Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Slew Rate, dt/dv Types, 1.5V 50ns (Max) Types, 3.6V 5.5V 20ns (Max) Types, 4.5V 5.5V. 10ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: outputs device, ±25mA each additional output. Unless otherwise specified, voltages referenced ground. package thermal impedance calculated accordance with JESD
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 -0.05 -0.05 (Note (Note 3.85 2.58 3.94 1.65 3.85 2.48 3.85 1.65 3.85 3.85 1.65 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD74AC283, CD74ACT283
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Level Output Voltage SYMBOL (mA) 0.05 0.05 0.05 (Note (Note Input Leakage Current Quiescent Supply Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 (Note (Note Level Output Voltage 0.05 (Note (Note Input Leakage Current Quiescent Supply Current Additional Supply Current Input Inputs High Unit Load NOTES: Test output time 1-second maximum duration. Measurement made forcing current measuring voltage minimize power dissipation. Test verifies minimum transmission-line-drive capability 85oC, 125oC. -2.1 3.94 0.36 ±0.1 3.85 0.44 1.65 3.85 1.65 25oC 0.36 0.36 ±0.1 -40oC 85oC 0.44 0.44 1.65 -55oC 125oC 1.65 UNITS
Input Load Table
INPUT UNIT LOAD 1.66
NOTE: Unit load limit specified Electrical Specifications Table, e.g., 2.4mA 25oC.
CD74AC283, CD74ACT283
Switching Specifications Input 3ns, 50pF (Worst Case)
-40oC 85oC PARAMETER TYPES Propagation Delay, COUT COUT tPLH, tPHL (Note (Note Propagation Delay, tPLH, tPHL Input Capacitance Power Dissipation Capacitance TYPES Propagation Delay, COUT COUT Propagation Delay, Input Capacitance Power Dissipation Capacitance NOTES: Limits tested 100%. 3.3V 3.6V, 5.5V, 4.5V. used determine dynamic power consumption function. VCC2 (CPD ACT: VCC2 (CPD where input frequency, output load capacitance, supply voltage. tPLH, tPHL (Note 17.6 (Note 22.4 23.2 16.5 24.6 17.6 25.5 18.2 SYMBOL -55oC 125oC UNITS
tPLH, tPHL (Note
16.5
18.2
OUTPUT INPUT LEVEL OUTPUT LOAD 50pF (NOTE)
INPUT
NOTE: Series Only: When 1.5V, CD74AC
INVERTING OUTPUT
CD74ACT 1.5V
Input Level Input Switching Voltage, Output Switching Voltage,
tPHL
tPLH
FIGURE PROPAGATION DELAY TIMES
FIGURE PROPAGATION DELAY TIMES
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Copyright 2000, Texas Instruments Incorporated
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