Flip-Flop with Reset CD74AC174 CD74ACT174 flip-flops with reset t

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Flip-Flop with Reset CD74AC174 CD74ACT174 flip-flops with reset t

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CD74AC174, CD74ACT174
Flip-Flop with Reset
CD74AC174 CD74ACT174 flip-flops with reset that utilize Harris Advanced CMOS Logic technology. Information input transferred output positive-going edge clock pulse. flip-flops controlled common clock (CP) common reset (MR). Resetting accomplished voltage level independent clock.
September 1998
/Title (CD74 AC174 CD74 ACT17 /Subject (Hex FlipFlop with Reset) /Autho /Keywords (Harris Semiconductor, Advan CMOS Harris Semiconductor, Advan TTL) /Creator /DOCI
Features
Buffered Inputs Typical Propagation Delay 6.4ns 25oC, 50pF Exceeds Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process Circuit Design Speed Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays Types Feature 1.5V 5.5V Operation Balanced Noise Immunity Supply ±24mA Output Drive Current Fanout FASTICs Drives Transmission Lines
Ordering Information
PART NUMBER CD74AC174E CD74ACT174E CD74AC174M CD74ACT174M NOTES: When ordering, entire part number. suffix obtain variant tape reel. Wafer this part number available which meets electrical specifications. Please contact your local sales office Harris customer service ordering information. TEMP. RANGE (oC) PACKAGE PDIP PDIP SOIC SOIC PKG. E16.3 E16.3 M16.15 M16.15
Pinout
CD74AC174, CD74ACT174 (PDIP, SOIC) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis Trademark Fairchild Semiconductor. Copyright Harris Corporation 1998
File Number
1973.1
CD74AC174, CD74ACT174 Functional Diagram
TRUTH TABLE (EACH FLIP-FLOP) INPUTS RESET (MR) CLOCK DATA OUTPUTS
High Level (Steady State) Level (Steady State) Irrelevant Transition from High level Level before Indicated Steady-State Input conditions were established.
CD74AC174, CD74ACT174
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±50mA Output Source Sink Current Output Pin, -0.5V 0.5V .±50mA Ground Current, IGND (Note .±100mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package Maximum Junction Temperature (Plastic Package) 1505oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, (Note Types. .1.5V 5.5V Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Slew Rate, dt/dv Types, 1.5V 50ns (Max) Types, 3.6V 5.5V 20ns (Max) Types, 4.5V 5.5V. 10ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: outputs device, ±25mA each additional output. Unless otherwise specified, voltages referenced ground. measured with component mounted evaluation board free air.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 -0.05 -0.05 (Note (Note 3.85 2.58 3.94 1.65 3.85 2.48 3.85 1.65 3.85 3.85 1.65 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD74AC174, CD74ACT174
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Level Output Voltage SYMBOL (mA) 0.05 0.05 0.05 (Note (Note Input Leakage Current Quiescent Supply Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 (Note (Note Level Output Voltage 0.05 (Note (Note Input Leakage Current Quiescent Supply Current Additional Supply Current Input Inputs High Unit Load NOTES: Test output time 1-second maximum duration. Measurement made forcing current measuring voltage minimize power dissipation. Test verifies minimum transmission-line-drive capability 85oC, 125oC. -2.1 3.94 0.36 ±0.1 3.85 0.44 1.65 3.85 1.65 25oC 0.36 0.36 ±0.1 -40oC 85oC 0.44 0.44 1.65 -55oC 125oC 1.65 UNITS
Input Load Table
INPUT UNIT LOAD 0.83
NOTE: Unit load limit specified Electrical Specifications Table, e.g., 2.4mA 25oC.
CD74AC174, CD74ACT174
Prerequisite Switching Function
-40oC 85oC PARAMETER TYPES Data Set-Up Time (Note (Note Hold Time Removal Time, tREM Pulse Width Pulse Width Frequency fMAX TYPES Data Set-Up Time Hold Time Removal Time, Pulse Width Clock Pulse Width Frequency tREM fMAX (Note SYMBOL -55oC 125oC UNITS
Switching Specifications Input 3ns, 50pF (Worst Case)
-40oC 85oC PARAMETER TYPES Propagation Delay, tPLH, tPHL (Note (Note 17.2 12.3 18.9 13.5 SYMBOL -55oC 125oC UNITS
CD74AC174, CD74ACT174
Switching Specifications Input 3ns, 50pF (Worst Case)
PARAMETER Propagation Delay, SYMBOL tPLH, tPHL Input Capacitance Power Dissipation Capacitance TYPES Propagation Delay, Propagation Delay, Input Capacitance Power Dissipation Capacitance NOTES: Limits tested 100%. 3.3V 3.6V, 5.5V, 4.5V. used determine dynamic power consumption flip-flop. VCC2 VCC2 where input frequency, output frequency, output load capacitance, supply voltage. tPLH, tPHL tPLH, tPHL (Note (Note 12.6 14.1 15.5 (Note (Continued) -55oC 125oC 18.5 13.2 20.3 14.5 UNITS
-40oC 85oC
INPUT LEVEL tPHL tPLH
INPUT LEVEL INPUT LEVEL
tSU(L)
tH(L)
tSU(H)
tH(H)
FIGURE PROPAGATION DELAYS
FIGURE
INPUT LEVEL INPUT tPHL tREM
OUTPUT (NOTE)
OUTPUT LOAD
50pF
NOTE: Series Only: When 1.5V,
CD74AC FIGURE RESET PREREQUISITE PROPAGATION DELAYS Input Level Input Switching Voltage, Output Switching Voltage,
CD74ACT 1.5V
FIGURE PROPAGATION DELAY TIMES
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