8-Bit Serial-In/Parallel-Out Shift Register CD74AC164 CD74ACT164

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8-Bit Serial-In/Parallel-Out Shift Register CD74AC164 CD74ACT164

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CD74AC164, CD74ACT164
8-Bit Serial-In/Parallel-Out Shift Register
CD74AC164 CD74ACT164 8-bit serial-in/parallel-out shift registers with asynchronous reset that utilize Harris Advanced CMOS Logic technology. Data shifted positive edge clock (CP). Master Reset (MR) resets shift register outputs state regardless input conditions. Serial Data inputs (DS1 DS2) provided; either used Data Enable control.
September 1998
/Title (CD74 AC164 CD74 ACT16 /Subject (8Bit SerialIn/ParallelOut Shift Register) /Autho /Keywords (Harris Semiconductor, Advan CMOS Harris Semiconductor, Advan TTL) /Creator
Features
Buffered Inputs Typical Propagation Delay 25oC, 50pF Exceeds Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process Circuit Design Speed Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays Types Feature 1.5V 5.5V Operation Balanced Noise Immunity Supply ±24mA Output Drive Current Fanout FASTICs Drives Transmission Lines
Ordering Information
PART NUMBER CD74AC164E CD74ACT164E CD74AC164M CD74ACT164M NOTES: When ordering, entire part number. suffix obtain variant tape reel. Wafer this part number available which meets electrical specifications. Please contact your local sales office Harris customer service ordering information. TEMP. RANGE (oC) PACKAGE PDIP PDIP SOIC SOIC PKG. E14.3 E14.3 M14.15 M14.15
Pinout
CD74AC164, CD74ACT164 (PDIP, SOIC) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. FASTis Trademark Fairchild Semiconductor. Copyright Harris Corporation 1998
File Number
1954.1
CD74AC164, CD74ACT164 Functional Diagram
MODE SELECT TRUTH TABLE INPUTS OPERATING MODE RESET (CLEAR) SHIFT OUTPUTS
HIGH voltage level steady state. voltage level steady state. HIGH voltage level setup time prior LOW-to_HIGH clock transition. voltage level setup time prior LOW-to-HIGH clock transition. Don't care. Lowercase letters indicate state referenced output prior LOW-to-HIGH clock transition. LOW-to-HIGH clock transition.
CD74AC164, CD74ACT164
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±50mA Output Source Sink Current Output Pin, -0.5V 0.5V .±50mA Ground Current, IGND (Note .±100mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package SOIC Package Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, (Note Types. .1.5V 5.5V Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Slew Rate, dt/dv Types, 1.5V 50ns (Max) Types, 3.6V 5.5V 20ns (Max) Types, 4.5V 5.5V. 10ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: outputs device, ±25mA each additional output. Unless otherwise specified, voltages referenced ground. measured with component mounted evaluation board free air.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 -0.05 -0.05 (Note (Note 3.85 2.58 3.94 1.65 3.85 2.48 3.85 1.65 3.85 3.85 1.65 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD74AC164, CD74ACT164
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Level Output Voltage SYMBOL (mA) 0.05 0.05 0.05 (Note (Note Input Leakage Current Quiescent Supply Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage -0.05 (Note (Note Level Output Voltage 0.05 (Note (Note Input Leakage Current Quiescent Supply Current Additional Supply Current Input Inputs High Unit Load NOTES: Test output time 1-second maximum duration. Measurement made forcing current measuring voltage minimize power dissipation. Test verifies minimum transmission-line-drive capability 85oC, 125oC. -2.1 3.94 0.36 ±0.1 3.85 0.44 1.65 3.85 1.65 25oC 0.36 0.36 ±0.1 -40oC 85oC 0.44 0.44 1.65 -55oC 125oC 1.65 UNITS
Input Load Table
INPUT DS1, UNIT LOAD 0.74 0.71
NOTE: Unit load limit specified Electrical Specifications Table, e.g., 2.4mA 25oC.
CD74AC164, CD74ACT164
Prerequisite Switching Function
-40oC 85oC PARAMETER TYPES Max. Clock Frequency fMAX (Note (Note Pulse Width Pulse Width Set-up Time Hold Time Removal Time tREM TYPES Max. Clock Frequency Pulse Width Pulse Width Set-up Time Hold Time Removal Time fMAX tREM (Note SYMBOL -55oC 125oC UNITS
Switching Specifications Input 3ns, 50pF (Worst Case)
-40oC 85oC PARAMETER TYPES Propagation Delay, tPLH, tPHL (Note (Note 15.9 11.4 17.5 12.5 SYMBOL -55oC 125oC UNITS
CD74AC164, CD74ACT164
Switching Specifications Input 3ns, 50pF (Worst Case)
PARAMETER Propagation Delay, SYMBOL tPLH, tPHL Input Capacitance Power Dissipation Capacitance TYPES Propagation Delay, Propagation Delay, Input Capacitance Power Dissipation Capacitance NOTES: Limits tested 100%. 3.3V 3.6V, 5.5V, 4.5V. used determine dynamic power consumption device. CPDVCC2 (CLVCC2 ICC, where input frequency, output frequency, output load capacitance, supply voltage. tPLH, tPHL tPLH, tPHL (Note (Note 13.5 14.4 14.9 15.8 (Note (Continued) -55oC 125oC 17.7 12.6 19.5 13.9 UNITS
-40oC 85oC
INPUT tPHL INPUT tTLH tTHL
INPUT LEVEL
1/fMAX tPLH tPHL OUTPUT
tREC INPUT LEVEL
FIGURE
FIGURE
VALID
INPUT LEVEL INPUT LEVEL tREC INPUT LEVEL INPUT LEVEL
INPUT LEVEL
FIGURE
FIGURE
CD74AC164, CD74ACT164
OUTPUT (NOTE) OUTPUT LOAD 50pF
NOTE: Series Only: When 1.5V, CD74AC Input Level Input Switching Voltage, Output Switching Voltage, CD74ACT 1.5V
FIGURE PROPAGATION DELAY TIMES
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Copyright 1999, Texas Instruments Incorporated

8-Bit Serial-In/Parallel-Out Shift Register CD74AC164 CD74ACT164

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