LATCH-UP PROTECTION CMOS AN-31 Vinsant INTRODUCTION Mos

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LATCH-UP PROTECTION CMOS AN-31 Vinsant INTRODUCTION Mos

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LATCH-UP PROTECTION CMOS
LATCH-UP PROTECTION CMOS
AN-31 Vinsant
INTRODUCTION
Most CMOS ICs, given proper conditions, "latch," (like SCR), creating short circuit from positive supply voltage ground. This application note explains this occurs what done prevent
most applications, triggering parasitic results destruction only time destruction does occur when supply current device limited. this case, device will resume normal operation when parasitic unlatched cycling supply current through zero.
Construction CMOS
fabricating CMOS ICs, parasitic bipolar transistors formed by-product CMOS process (see Figure These transistors inherent CMOS structure can't eliminated. P-channel device parasitic N-channel parasitic. Through internal connections, parasitics form fourlayer structure (Figure schematic form (Figure parasitic turned N-channel drain raised above VS+. This action will bias drain parasitic (Q1's emitter), back through Q1's base, returning through bulk resistance similar situation occur drain N-channel MOSFET (emitter taken below supply. This emitter base junction parasitic bipolar parasitic diode that also found power MOSFETs. these diodes exists every CMOS structure both Nand P-channel devices; correspondingly, there exists parasitic bipolar every MOSFET including input transistors. Turn them action will occur.
INPUT FROM PREVIOUS STAGE
Preventing Triggering: Grounds
Clean grounds important system, especially important analog power processing circuits. This becomes even more critical when CMOS used. Poor ground practice result device latching. example this shown Figure this example, TC170 sends TC426 "low" signal which causes power MOSFET turn "on." ground return resistance (R1) sufficiently high, ground voltage TC426 will rise above that TC170, resulting input TC426 being negatively biased. This will cause TC426 latch. similar condition caused circuit inductance. Referring Figure again, assume replaced inductor. When MOSFET turns "on," current source lead builds very rapidly. Typical rise times would order example, assume that MOSFET switching circuit inductance From di/dt generate voltage shifts 0.83V 1.66V, depending upon rise time, more than enough trigger parasitic SCR. Troubleshooting this type problem facilitated placing series resistor, typically 100, between TC426 MOSFET. This slows MOSFET's transition circuit observed operation without
OUTPUT P-WELL P-CHANNEL N-CHANNEL
Figure Output Stage Layout
AN31-2
SOURCE
BULK RESISTANCE
DRAIN
P-CHANNEL PARASITIC
N-CHANNEL PARASITIC P-WELL RESISTANCE DRAIN SOURCE
Figure Equivalent Circuit
LATCH-UP PROTECTION CMOS AN-31
anything being destroyed. sure take into account increased dissipation MOSFET when using this technique. Figure shows proper "star" ground that will prevent latching. Notice grounds meet only point. board this means traces must meet point, that they connected same trace. (See Figures 4B.) transients occur. These transients generated combination fast peak currents being drawn parasitic inductances resistances power supply conductors. (See Figures 5B.) This problem very pronounced with driving large loads, case TC426 TC429 driving power MOSFET. Upon switching, TC429 draw several amperes current from supply, causing large transients local supply voltage. TC429's input very close system supply voltage, when being driven CMOS logic, then local supply drop significantly below input, triggering parasitic SCR. parasitic very fast this transition need last only nanoseconds latching occur.
Decoupling
Another source latch-up problems ripple noise power supply voltage. properly decoupled power supply, supply pins voltage
TC426
TC170
TC426
TRACE RESISTANCE POWER SUPPLY RETURN
(TOP VIEW)
Figure Improper Ground
Figure Improper Layout
TC426
TC170
TC426
STAR GROUND FROM POWER SUPPLY RETURN
(TOP VIEW) POWER SUPPLY RETURN
Figure Proper Layout
Figure Proper Ground
LATCH-UP PROTECTION CMOS AN-31
TRACE
TRACE
DECOUPLING CAPACITOR
TC426
TRACE
DECOUPLING CAPACITOR
obvious solution properly decouple supply that can't drop below value input signal. second, less obvious, solution reduce logic level applied input device. Although lowering input voltage will help these spikes that occur, they cause other same power supply suffer noise immunity problems from noise generated driver some applications, such portable instrumentation, desirable keep total power consumption minimum designers will commonly shut power unused portions system conserve battery life. This cause problems when input signal always present line turned "off." this case, resistor series with CMOS device's input will limit injected current value below that listed device data sheet "the maximum current into pin." When subsequently switched "on," action will prevented.
TRACE
CAPACITOR
Diodes
very reliable method preventing parasitic action guard susceptible pins with steering diodes. This most commonly done when MOSFET driver driving inductive load such long length wire pulse transformer. Placing reverse-biased diode between each supply rail input/output pins shown Figure 6B), limits applied voltage swing more than supply voltage plus forward voltage drop clamping diode. this reason, Schottky diodes usually best choice this technique, their forward voltage drop less than parasitic SCR's base emitter drop temperature. Philips/Mullard/Amperex BYV10-30, example, will work well higher power applications, such MOSFET drivers. BAT54 dual diode works well surface-mount applications with lower power ICs, such op-amps converters. Germanium diodes, such 1N270, will work well also, leaky some applications. Standard signal diodes, 1N4148 1N914 example, frequently used; their larger junctions having lower effective forward drop than parasitic junctions work effectively over/undervoltage clamps. some instances, where standard junction diodes leaky (such might case Figure 6B), very leakage junction (JFET), acting diode, will trick. These devices have leakages picoamps very quick responding. these applications, contact TelCom Semiconductor, Inc.
Figure TC426 Traces (Equivalent Circuit)
TC426
DECOUPLING CAPACITOR
Figure Typical Layout (TC426)
Aggravating this temperature dependence parasitic transistors. Their base emitter voltage decreases mV/°C temperature increases, making them increasingly more sensitive transients chip temperature rises. Many times system which performed admirably bench begins experience problems high temperatures because local decoupling marginal.
LATCH-UP PROTECTION CMOS AN-31
TC901
Will have been done unless series resistor large enough limit fault current safe value. This lowest cost solution prevent device damage. Using resistor limitations, however. resistor will limit current allowed decoupling capacitor, which limits frequency that circuit driven value. This method works very well op-amp circuits, op-amps draw very little peak current circuit only amplifying component problems.
Figure TC901 With Diode Clamps
TC170
Figure TC429's Driving Pulse Transformer
Resistors
applications where triggering parasitic concern, protecting from destruction only issue, then adding resistor series with power supply will prevent device destruction. Once been triggered, supply voltage will have brought momentarily zero rest SCR, damage
Sales Offices
TelCom Semiconductor 1300 Terra Bella Avenue P.O. 7267 Mountain View, 94039-7267 TEL: 650-968-9241 FAX: 650-967-1590 E-Mail: liter@c2smtp.telcom-semi.com TelCom Semiconductor Austin Product Center 9101 Burnet Suite Austin, 78758 TEL: 512-873-7100 FAX: 512-873-8236 TelCom Semiconductor H.K. Ltd. Chuk Street, Ground Floor Kong, Kowloon Hong Kong TEL: 852-2324-0122 FAX: 852-2354-9957
TC429
Advances CMOS Processing
stated earlier, parasitic intrinsic structure CMOS devices cannot eliminated. However, tamed, through advanced processing circuit design techniques pioneered TelCom Semiconductor, problem latch-up been eliminated.
CONCLUSION
Latch-up CMOS preventable. Simple circuit techniques attention system design details will ensure CMOS' full potential realized operating environments. Designers also look forward day, distant future, when even these simple precautions longer necessary. Synopsis: prevent latch-up: Properly decouple Clamp outputs with diodes when driving inductive loads. Clamp inputs with diodes input signal exceeds negative positive rails power supply. star grounds, possible, high-current applications.
Printed U.S.A. 9/5/95

LATCH-UP PROTECTION CMOS AN-31 Vinsant INTRODUCTION Mos

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