using low-cost microprocessors programcontrolled numerical-integration

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using low-cost microprocessors programcontrolled numerical-integration

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APPLICATION NOTE NUMERICAL-INTEGRATION TECHNIQUES SPEED DUAL-SLOPE CONVERSION
using low-cost microprocessors programcontrolled numerical-integration technique, achieve good noise rejection take full advantage higher speeds offered recently developed dual-slope converters such TC7109. This similar converters overcome speed limitations imposed logic-gate analog comparator delays earlier dual-slope devices, modern units operate rates high samples/sec. Nevertheless, operating them their maximum conversion rates often makes difficult impossible achieve high normal-mode line-frequency rejection that dual-slope converters inherently offer slower conversion rates. Thus, noise considerations have often precluded these converters their rated speeds especially industrial environments, where line-frequency other low-frequency noise components particular problem.
Normal-Mode Line-Frequency Rejection
understand normal-mode line-frequency rejection dual-slope converters, consider typical 12-bit converter (Figure timing diagram (Figure conversion cycle. Note that conversion depends charging integrating capacitor during fixed time interval; number counts necessary discharge capacitor zero proportional input voltage.
integrating converter integrates signal only certain time window, Figure shows. This limited integration period results normal-mode noise rejection only when integration period equal more periods noise signal (Figure 2a). time integral this noise over integer multiples noise period course, zero. Normal-mode noise-rejection performance thus represented function (Figure that reaches peaks fundamental harmonic frequencies period defined signal-integrate time minimum period which must equal noise period, been limiting factor conversion speed. example, minimum signal-integrate time 16.7 msec; it's msec. Because signal-integrate time only portion total conversion time, conversion rates significantly less than 1/T. standard, high-performance, dual-slope converter includes reference deintegrate phase, typically long, autozero period equal signal-integrate period total conversion time thus which, 60Hz rejection, yields maximum conversion rate samples/sec; yields 12.5 samples/sec. most serious constraint arises when want offer instrument international that reject both This feature attainable only when signal-integrate period contain cycles 60-Hz noise five cycles 50-Hz noise. resulting msec signal-integrate period dictates conversion/sec rate.
Integrator
Analog Input
Comparator
Signal Integration Window Zero Crossing Detected Integrator Output Integrate Phase 2048 Counts Deintegrate Phase
+or- Reference Voltage
Switch Driver Phase Control Polarity Control Control Logic Clock
Number Counts Zero Crossing Proportional
4096 Counts
Digital Output
12-Bit Counter
Figure dual-slope converter operates charging capacitor from input voltage during fixed time, then discharging zero. number clock periods discharge time corresponds analog input voltage. size integrating time window determines which normal-mode noise signals rejected.
AN27-1
NUMBER-INTEGRATION TECHNIQUES SPEED DUAL-SLOPE CONVERSION AN-27
SIGNAL-INTEGRATION WINDOW
NORMAL MODE REJECTION (dB)
MEASUREMENT PERIOD
0.1/T
INPUT FREQUENCY
10/T
Figure dual-slope converter, high normal-mode noise rejection occurs when integration period multiple noise signal's period.
can, however, overcome inherent conversionspeed limitation integrating converters. microprocessor with program-controlled numerical integration that complements converter's analog integration will speed dual-slope conversion considerably. achieve high normal-mode rejection specific frequencies with this method three conditions met. First, signal-integrate period must defined such that noise integration takes place segmented basis. Figure example, integrate window opens noise-wave-form segment that's one-third period long. Next, second signal-integrate period must point corresponding exactly point which first ended, third's beginning must correspond point which second ended. This condition only converter fixed conversion time, irrespective signal input. Finally, microprocessor must three conversions achieve total integration cycle noise. consideration these constraints TC7109 converter, example, leads relationship fNOISE where conversion rate, noise frequency number conversion results added. must number; Figure shows cannot even number. frequency that would require even number samples which integrate window locked phase with signal (i.e., converter signal periods synchronized). (fNOISE) (X/4) Figure 3b), result times error conversion.
Noise Amplitude
(Int Conversion Rate
Noise Amplitude
(Int Conversion Rate
Figure Data-conversion systems employing numerical-integration technique furnish noise rejection when number samples summed (a). Adding results conversions, though, yield twice much error does conversion (b). converter noise frequency synchronized.
NUMBER-INTEGRATION TECHNIQUES SPEED DUAL-SLOPE CONVERSION AN-27
NORMAL-MODE REJECTION (dB)
6070 NORMAL-MODE NOISE FREQUENCY (HZ) msec Signal Integrate Samples Summed 11.1 msec Sample 11.1 msec Signal Integrate
achieve desired normal-mode rejection, must, therefore, number A/D-converter results. accomplish this summation with firmware with user-interaction software. Consider example using TC7109 converter operating 22.5 samples/ sec. equation yields results Table Table indicates, converter operating 22.5 samples/sec reject harmonics maintain rolling average nine samples. This technique rejects it's equivalent sample taken rate samples/sec. curves Figure show normalmode rejection resulting from 9-sample averages rate 22.5 conversions/sec sample conversions/sec). Table TC7109 22.5 Samples/Sec fNOISE (Fundamental)
12.8
Figure normal-mode-rejection capability illustrated upper curve here demonstrates effectiveness taking nine conversion samples; system that curve represents rejects noise multiples lower curve shows result acquiring only sample employing 11.11-msec signal-integration period.
Samples Summed
Notes: CONVERTER UPDATES 22.5 CONV/SEC DISPLAY UPDATES CONV/SEC OUTPUT AVERAGE CONVERSIONS REJECTS BOTH CONTINUITY BUZZER RESPONDS mSEC CONVERSIONS) RANGE CHANGES mSEC
REF+ HIGH BYTE 184kHz CLOCK
1.11M
1-CHIP MICROCOMPUTER
PORT
DISPLAY DRIVE
BYTE DATA
RANGE SWITCH QAUD SPST
TC7109 12-BIT
STATUS LBEN HBEN PORT BUZZER
101k 0.068µF 0.12µF
STATUS
LBEN
HBEN
CE/LOAD
CHIP ENABLE
Figure
This 3/4-digit multimeter uses numerical-integration technique reject both normal-mode noise. Although DMM's display updates samples/sec, conversions take place 22.5 samples/sec.
NUMBER-INTEGRATION TECHNIQUES SPEED DUAL-SLOPE CONVERSION AN-27
What's point, ask, sampling higher rate must wait result during 9-period numerical integration? After first 9-period wait, system's pipeline full, then obtain result each cycle 22.5-samples/sec rate. numerical-integration technique many practical applications. Figure circuit, example, digit that uses TC7109 13-bit converter. updates display sample/sec rate easy readability, converts 22.5 samples/sec rate fast response during autoranging continuity checking. Because circuit averages nine samples, rejects both 50and 60-Hz noise. Because carry rolling average, capable changing number conversions summed; therefore accommodate specific, userprogrammable rejection frequencies. Figure shows connections system using TC7109 conjunction with 6502 processor 6522 peripheral interface adapter. adapter's programmable timer provides converter's clock, thereby simplifying testing noise rejection with different clock frequencies. This circuit allows evaluate numerical-integrationbased designs using either general-purpose µP-development system prototyping board (e.g., Rockwell's AIM65). Figure shows assembly-language listing system; flowchart appears Figure Table 16-Channel Multiplexer
Channels Scanned
100k
10µF
VOUT
REF- REF+ STATUS RUN/HOLD SEND LBEN HBEN CE/LOAD MODE CAP+ CAPINT TEST
TC7660
10µF
TC7109 CONVERTER
0.33µF 0.15µF 0.01µF INPUT ANALOG INPUT INPUT
SY6522 PORT
Figure evaluate numerical integration with circuit detailed this schematic. 6522 peripheral-interface adapted provides clocking interface dual-slope converter.
NUMBER-INTEGRATION TECHNIQUES SPEED DUAL-SLOPE CONVERSION AN-27
094D.ASM 000D 000D 000D 000D 000D 000D 000D 000D 000D A800 0080 0080 0083 0084 0280 0280 0282 0285 0288 028B 028D 0290 0293 0296 0298 029B 029E 029E 02B0 02B0 02B3 02B4 02B6 02B8 02B9 02BB 02BD 02BE 02C0 02C3 02C5 02C7 02C9 02CB 02CD 02CF 02D1 02D4 02D5 02D7 02DA 02DC 02DE 02E0 02E2 02E4 02E6 02E8 02EA 02EC 02ED SOFTWARE DEMONSTRATE NUMERICAL INTEGRATION USING TC7109 INTERFACED 6502 MICROPROCESSOR 6522 PORT RESULTS STORED 'RESLT' ZERO-PAGE MEMORY USER MUST PROVIDE INTERRUPT VECTOR FROM 6522'S INTERRUPT ROUTINE "INTSVC" ;-;SYSTEM EQUATES A800H ;ADDRESS 6522 PORT ;RESERVE ZERO-PAGE MEMORY ;16-BIT ACCUMULATOR RESULTS, BYTE SIGN ;STORAGE LOOP COUNTER ;SAVE HIGH BYTE 0280H ;SET PORT CONTROL TC7109 #0C0H ;PB6 OUTPUTS, IOPT TIMER OUTPUT IOPT+2 (FOR 7109 CLOCK) IOPT+0BH ;SQUARE WAVE OUTPUT PB-7 #12H ;LOAD CONSTANT IOPT+4 CLOCK TIMER SETREG ;ININTIALIZE MEMORY REGISTERS IOPT+5 START 7109 CLOCK #82H ;ENABLE INTERRUPT FROM IOPT+0EM 6522 INPUT MAINPRG ;I/O PORT SETUP COMPLET, JUMP O.S. MAIN PROGRAM ;INTERRUPT SERVICE ROUTINE 0280H IOPT ;GET HIGH BYTE ;SAVE #OFH ;ZERO MSBs ARITHMATIC STORHI ;SAVE ;GET SIGN BACK #10H ;ANALOG INPUT NEGATIVE? SUBTR YES, SUBTRACT ;RESULT POSITIVE RESLT ;GET BYTE THIS CONVERSION IOPT+1 PREVIOUS READINGS RESLT SAVE BYTE RESLT+1 ;GET BYTE CONVERSION STORHI RESLT+1 SAVE BYTE RESLT+2 ;GET SIGN CARRY BIT, RESLT+ SAVE LOOPCNT ;JUMP TEST CONVERSIONS ;SET CARRY SUBTRACTION RESLT POLARITY THIS CONVERSION IOPT+1 NEGATIVE, RESLT DOUBLE-PRECISION RESLT+1 SUBTRACTION STORHI RESLT+1 RESLT+2 RESLT+2 STORX ;HAVE DONE CONVERSIONS? DIVID YES, DIVIDE RETURN
Interrupt
RESLT STORX STORHI A9C0 CLOCK 8D00A8 8D02A8 8D0BA8 A912 8D04A8 20FA02 8D05A8 A982 8D0EA8 4C2303 AD00A8 INTSVC 290F 8584 2910 F017 A580 6D01A8 8580 A581 6584 8581 A582 6900 8582 4CE802 SUBTR A580 ED01A8 8580 A581 E584 8581 A582 E900 8582 C683 LOOPCNT F001 PAGE
10PT
Read High Byte
Strip Flags, Store Magnitude
Polarity Positive? Carry Subtraction
Clear Carry Addition
Subtract Conversion Magnitude From Total
Conversion Magnitude Total
Decrement Loop Counter
Have Nine Conv. Been Integrated?
Display Result Return From Interrupt
Figure This flowchart Figure assembly-language routine summarizes code necessary control Figure evaluation circuit.
Figure This assembly-language listing A/D-converter system Figure provides 9-sample numerical integration, thereby eliminating normal-mode noise frequencies that multiples
Adding Channels using analog multiplexers, take advantage these speed-improvement techniques multichannel systems. Solving equation given earlier using determine scan length number channels), keep noise-segment alignment proper phase. This segmented approach (for 16-channel system that requires summation three conversion) shown Figure scan length found dividing number available channels taking integer value, then multiplying adding Table shows relationship between number samples summed number channels scanned 16-channel multiplexer.
data-acquisition system using 16-channel multiplexer could TC7109 running conversions/sec reject harmonics (including, course, Hz), with 5-sample average taken microprocessor. system would still respond large signal deviations single conversion. change from analog signal integration noise hybrid analog/numerical integration entails some trade-offs. quantization error, example, always present; lead significant reduction normal-mode rejection noise period carved into many segments. additions, timing instability create other error sources. maximum stability, must control converter's timing with crystal oscillator.
NUMBER-INTEGRATION TECHNIQUES SPEED DUAL-SLOPE CONVERSION AN-27
CHANNEL SIGNAL INTEGRATE
CHANNEL SIGNAL INTEGRATE
CHANNEL SIGNAL INTEGRATE
CHANNEL SIGNAL INTEGRATE
AUTO ZERO
DEINTEGRATE
AUTO ZERO
DEINTEGRATE
AUTO ZERO
DEINTEGRATE
AUTO ZERO
DEINTEGRATE
fNOISE
SEGMENT CHANNEL
NOTES: SEGMENTS CHANNELS SCANNED CHANNEL MULTIPLEXER
SEGMENT CHANNEL
Figure multichannel capability enhanced-speed A/D-converter designs employing µP-based numerical integration.
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Printed U.S.A. 9/5/95

using low-cost microprocessors programcontrolled numerical-integration

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