WM9714L highly integrated input/output device designed mobile computin
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AC'97 Audio CODEC
WM9714L highly integrated input/output device designed mobile computing communications. chip architected dual CODEC operation, supporting Hi-Fi stereo Codec functions link interface, additionally supporting voice Codec functions type Synchronous Serial Port (SSP). third, auxiliary provided which used support generation supervisory tones, ring-tones different sample rates main codec. device connect directly mono stereo microphones, stereo headphones stereo speaker, reducing total component count system. Cap-less connections headphones, speakers, earpiece used, saving cost board area. Additionally, multiple analog input output pins provided seamless integration with analog connected wireless communication devices. device functions accessed controlled through single AC-Link interface compliant with AC'97 standard. 24.576 masterclock input directly generated internally from 13MHz other frequency) clock on-chip PLL. supports wide range input clock from 2.048MHz 78.6MHz. WM9714L operates supply voltages from 1.8V 3.6V. Each section chip powered down under software control save power. device available small leadless 7x7mm package, ideal hand-held portable systems.
WM9714L
FEATURES
AC'97 compatible stereo codec 94dB, -85dB 87dB, -86dB Variable Rate Audio, supports WinCE sample rates Tone Control, Bass Boost Enhancement On-chip 45mW headphone driver On-chip 400mW mono stereo speaker drivers Stereo, mono differential microphone input Automatic Level Control (ALC) insert button press detection Auxiliary mono (ring tone level generation) Seamless interface wireless chipset Additional PCM/I2S interface support voice CODEC derived audio clocks. Supports input clock ranging from 2.048MHz 78.6MHz 1.8V 3.6V supplies (digital down 1.62V, speaker 4.2V) 7x7mm 48-lead package
APPLICATIONS
Personal Digital Assistants (PDA) with without phone Smartphones Handheld Tablet Computers
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS
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WM9714L TABLE CONTENTS
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DESCRIPTION FEATURES.1 APPLICATIONS BLOCK DIAGRAM TABLE CONTENTS CONFIGURATION.4 ORDERING INFORMATION DESCRIPTION ABSOLUTE MAXIMUM RATINGS.6 RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS
AUDIO OUTPUTS. AUDIO INPUTS. AUXILIARY MONO (AUXDAC). VOICE (VXDAC) AUXILIARY ADC. COMPARATORS REFERENCE VOLTAGES DIGITAL INTERFACE CHARACTERISTICS.
POWER CONSUMPTION SIGNAL TIMING REQUIREMENTS
AC97 INTERFACE TIMING. AUDIO INTERFACE TIMING SLAVE MODE. AUDIO INTERFACE TIMING MASTER MODE
DEVICE DESCRIPTION.17
INTRODUCTION. AUDIO PATHS OVERVIEW. CLOCK GENERATION CLOCK DIVISION MODES MODE DIGITAL INTERFACES. AC97 INTERFACE INTERFACE
AUDIO ADCS
STEREO ADC. RECORD SELECTOR RECORD GAIN. AUTOMATIC LEVEL CONTROL.
AUDIO DACS
STEREO DAC. VOICE AUXILIARY DAC.
VARIABLE RATE AUDIO SAMPLE RATE CONVERSION AUDIO INPUTS
LINE INPUT MICROPHONE INPUT.
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WM9714L
MONOIN INPUT. PCBEEP INPUT DIFFERENTIAL MONO INPUT
AUDIO MIXERS.52
MIXER OVERVIEW HEADPHONE MIXERS SPEAKER MIXER MONO MIXER. MIXER OUTPUT INVERTERS.
ANALOGUE AUDIO OUTPUTS
HEADPHONE OUTPUTS HPR. MONO OUTPUT SPEAKER OUTPUTS SPKL SPKR AUXILIARY OUTPUTS OUT3 OUT4 THERMAL SENSOR JACK INSERTION AUTO-SWITCHING.
DIGITAL AUDIO (S/PDIF) OUTPUT.62 AUXILIARY ADDITIONAL FEATURES.69
BATTERY ALARM ANALOGUE COMPARATORS. GPIO INTERRUPT CONTROL.
POWER MANAGEMENT
INTRODUCTION. AC97 CONTROL REGISTER. EXTENDED POWERDOWN REGISTERS ADDITIONAL POWER MANAGEMENT. POWER RESET (POR)
REGISTER MAP.80
REGISTER BITS ADDRESS
APPLICATIONS INFORMATION .110
RECOMMENDED EXTERNAL COMPONENTS. LINE OUTPUT AC-COUPLED HEADPHONE OUTPUT. COUPLED (CAPLESS) HEADPHONE OUTPUT LOUDSPEAKER OUTPUT COMBINED HEADSET SPEAKER. COMBINED HEADSET SINGLE-ENDED SPEAKER. JACK INSERT DETECTION HOOKSWITCH DETECTION. TYPICAL OUTPUT CONFIGURATIONS
PACKAGE DIMENSIONS .118 IMPORTANT NOTICE .119
ADDRESS:.
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WM9714L CONFIGURATION
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ORDERING INFORMATION
DEVICE WM9714LGEFL/V WM9714LGEFL/RV Note: Reel quantity 2,200 TEMPERATURE RANGE +85oC +85oC PACKAGE 48-lead (Pb-free) 48-lead (Pb-free, tape reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260oC 260oC
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WM9714L
NAME DBVDD MCLKA MCLKB GPIO6 (ADA MASK) DGND1 SDATAOUT BITCLK DGND2 SDATAIN DCVDD SYNC RESETB GPIO7 AUX4 GPIO8 (S/PDIF) AVDD2 AGND3 PCBEEP MONOIN MIC1 MICCM LINEL LINER AVDD AGND VREF MICBIAS MIC2A COMP1 AUX1 MIC2B COMP2 AUX2 MONO CAP2 OUT4 SPKGND SPKL SPKR OUT3 SPKVDD HPGND AGND2 HPVDD TYPE Supply Digital Input Digital In/Out Supply Digital Input Digital Output Supply Digital Output Supply Digital Input Digital Analogue Supply Analogue Input Analogue Input Analogue Input Analogue Input Supply Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Supply Supply Analogue Output Analogue Output Analogue Input Analogue Input Analog output Analogue Analogue Output Supply Analogue Output Analogue Output Analogue Output Supply Analogue Output Supply Analogue Output Supply Supply Digital Buffer Supply Master Clock Input Master Clock Input GPIO6 (ADA output MASK input) Digital Ground (return path both DCVDD DBVDD) Serial Data Output from Controller Input WM9714L Serial Interface Clock Output Controller Digital Ground (return path both DCVDD DBVDD) Serial Data Input Controller Output from WM9714L Digital Core Supply Serial Interface Synchronisation Pulse from Controller Reset (asynchronous, active Low, resets registers their default) GPIO7 Auxiliary input GPIO8 (S/PDIF digital audio output) Analogue Supply connect connect connect connect Analogue Ground Line Input analogue audio mixers, typically used beeps Mono Input (RX) Microphone preamp input Microphone common mode input Left Line Input Right Line Input Analogue Supply (audio DACs, ADCs, PGAs, amps, mixers) Analogue Ground Internal Reference Voltage (buffered CAP2) Bias Voltage Microphones (buffered CAP2 1.8) Microphone preamp input COMP1 input Auxillary input Microphone preamp input COMP2 input Auxillary input Mono output driver (line headphone) Internal Reference Voltage (normally AVDD/2, overdriven) Auxillary output driver (speaker, line headphone) Speaker ground (feeds output buffers pins Left speaker driver (speaker, line headphone) Right speaker driver (speaker, line headphone) Auxillary output driver (speaker, line headphone) Speaker supply (feeds output buffers pins Headphone left driver (line headphone) Headphone ground (feeds output buffers pins Headphone right driver (line headphone) Analogue ground, chip substrate Headphone supply (feeds output buffers pins
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WM9714L
Notes: NAME GPIO1 PCMCLK GPIO2 GPIO3 PCMFS GPIO4 MASK PCMDAC GPIO5 S/PDIF PCMADC GND_PADDLE TYPE Digital Digital Digital Digital Digital DESCRIPTION GPIO interface clock GPIO (Interrupt Request) output GPIO frame signal
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GPIO (ADC data available) output Mask input input (DAC) data GPIO S/PDIF digital audio output output (ADC) data Paddle (Note
recommended that GND_PADDLE connected analogue ground. Refer "Recommended External Components" diagram "Package Dimensions" section further information.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings stress ratings only. Permanent damage device caused continuously operating beyond these limits. Device functional operating limits guaranteed performance specifications given under Electrical Characteristics test conditions specified. Sensitive Device. This device manufactured CMOS process. therefore generically susceptible damage from excessive static voltages. Proper precautions must taken during handling storage this device. Wolfson tests package types according IPC/JEDEC J-STD-020B Moisture Sensitivity determine acceptable storage conditions prior surface mount assembly. These levels are: MSL1 unlimited floor life <30°C Relative Humidity. normally stored moisture barrier bag. MSL2 storage year <30°C Relative Humidity. Supplied moisture barrier bag. MSL3 storage hours <30°C Relative Humidity. Supplied moisture barrier bag. Moisture Sensitivity Level each package type specified Ordering Information. CONDITION Digital supply voltages (DCVDD, DBVDD) Analogue supply voltages (AVDD, AVDD2, HPVDD) Speaker supply voltage (SPKVDD) Voltage range digital inputs Voltage range analogue inputs Operating temperature range, -0.3V -0.3V -0.3V DGND -0.3V AGND -0.3V
+3.63V +3.63V +4.2V DBVDD +0.3V AVDD +0.3V +85oC
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital input/output buffer supply range Digital core supply range Analogue supply range Speaker supply range Digital ground Analogue ground Difference AGND DGND Note: AGND normally same DGND1/DGND2 DCVDD DBVDD DCVDD AVDD DCVDD should >=2V when using SYMBOL DBVDD DCVDD AVDD, AVDD2, HPVDD SPKVDD DGND1, DGND2 AGND, AGND3, HPGND, SPKGND Note -0.3 TEST CONDITIONS 1.71 1.71 +0.3 UNIT
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WM9714L
ELECTRICAL CHARACTERISTICS
AUDIO OUTPUTS
Test Conditions DBVDD=3.3V, DCVDD 3.3V, AVDD=HPVDD=SPKVDD =3.3V, +25oC, 1kHz signal, 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Full-scale output (0dBFS) Signal Noise Ratio (A-weighted) Total Harmonic Distortion Power Supply Rejection PSRR -3dB output 100mV, 20Hz 20kHz signal AVDD 200mW SYMBOL TEST CONDITIONS AVDD 3.3V, gains UNIT
Line-Out (HPL/R, SPKL/R MONO with 50pF load)
Speaker Output (SPKL/SPKR with bridge tied load, INV=1) Output Power Abs. output power Total Harmonic Distortion Signal Noise Ratio (A-weighted) Output Power Abs. output power Total Harmonic Distortion Signal Noise Ratio (A-weighted) Output Power channel Total Harmonic Distortion POmax 0.05 (rms) (rms)
Stereo Speaker Output (SPKL/OUT4 SPKR/OUT3 with bridge tied load, INV=1) POmax 200mW 0.05 (rms) (rms)
Headphone Output (HPL/R, OUT3/4 SPKL/SPKR with load) Output power very closely correlated with THD; below. PO=10mW, RL=16 PO=10mW, RL=32 PO=20mW, RL=16 PO=20mW, RL=32 Signal Noise Ratio (A-weighted) Note: values valid output power level quoted above example, HPVDD=3.3V RL=16, -80dB when output power 10mW. Higher output power possible, will result deterioration THD.
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WM9714L
AUDIO INPUTS
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Test Conditions DBVDD=3.3V, DCVDD 3.3V, AVDD 3.3V, +25oC, 1kHz signal, 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Full Scale Input Signal Level (0dBFS) SYMBOL VINFS TEST CONDITIONS AVDD 3.3V AVDD 1.8V differential input mode AVDD 3.3V differential input mode AVDD 1.8V Input Resistance Input Capacitance Line input (LINEL, LINER, MONOIN) Signal Noise Ratio (A-weighted) Total Harmonic Distortion Power Supply Rejection Signal Noise Ratio (A-weighted) Total Harmonic Distortion PSRR -3dBFS input 20Hz 20kHz 20dB boost enabled 20dB boost enabled gain 12dB gain 25.6 10.4 0.545 0.273 38.4 15.6 UNIT Vrms
LINEL/R, MIC1/2A/2B MONOIN pins
Microphone input (MIC1/2A/2B pins)
AUXILIARY MONO (AUXDAC)
Test Conditions DBVDD=3.3V, DCVDD 3.3V, AVDD 3.3V, +25oC, 1kHz signal, 8kHz, 24-bit audio data unless otherwise stated. PARAMETER Resolution Full scale output voltage Signal Noise Ratio (A-weighted) Total Harmonic Distortion AVDD=3.3V SYMBOL TEST CONDITIONS UNIT bits Vrms
VOICE (VXDAC)
Test Conditions DBVDD=3.3V, DCVDD 3.3V, AVDD 3.3V, 1kHz signal, 8kHz, 24-bit audio data unless otherwise stated. PARAMETER Resolution Sample rates Full scale output voltage Signal Noise Ratio (A-weighted) Total Harmonic Distortion AVDD=3.3V SYMBOL TEST CONDITIONS UNIT bits Ks/s Vrms
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WM9714L
AUXILIARY
Test Conditions DBVDD 3.3V, DCVDD 3.3V, AVDD 3.3V, +25oC, unless otherwise stated. PARAMETER Input Voltage Input leakage current Resolution Differential Non-Linearity Error Integral Non-Linearity Error Offset Error Gain Error Power Supply Rejection Channel-to-channel isolation Throughput Rate Settling Time (programmable) 1111 (zero settling time) MCLK 24.576MHz PSRR selected input SYMBOL TEST CONDITIONS AGND ±0.25 AVDD UNIT bits
Input Pins AUX4, COMP1/AUX1, COMP2/AUX2
COMPARATORS
Test Conditions DBVDD 3.3V, DCVDD 3.3V, AVDD 3.3V, +25oC, unless otherwise stated. PARAMETER Input Voltage Input leakage current Comparator Input Offset (COMP1, COMP2 only) COMP2 delay (COMP2 only) MCLK 24.576MHz selected input SYMBOL TEST CONDITIONS AGND 10.9 AVDD UNIT
COMP1/AUX1 COMP2/AUX2 (pins when used inputs)
REFERENCE VOLTAGES
Test Conditions DBVDD=3.3V, DCVDD 3.3V, AVDD 3.3V, +25oC, 1kHz signal, 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Audio ADCs, DACs, Mixers Reference Input/Output Buffered Reference Output Microphone Bias Bias Voltage Bias Current Source Output Noise Voltage VMICBIAS IMICBIAS 20kHz 2.92 2.97 3.00 nV/Hz CAP2 VREF 1.63 1.64 1.65 1.65 1.66 1.67 SYMBOL TEST CONDITIONS UNIT
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WM9714L
DIGITAL INTERFACE CHARACTERISTICS
Test Conditions DBVDD 3.3V, DCVDD 3.3V, +25oC, unless otherwise stated. PARAMETER Input HIGH level Input level Output HIGH level Output level Clock Frequency Master clock (MCLKA pin) AC'97 clock (BIT_CLK pin) AC'97 sync pulse (SYNC pin) Note: audio non-audio sample rates other timing scales proportionately with master clock. signal timing AC-Link, please refer AC'97 specification (Revision 2.2) 24.576 12.288 SYMBOL source current sink current TEST CONDITIONS
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UNIT
Digital Logic Levels (all digital input output pins) CMOS Levels
POWER CONSUMPTION
power consumption WM9714L depends following factors: Supply voltages: Reducing supply voltages also reduces digital supply currents, therefore results significant power savings especially digital sections WM9714L. Operating mode: Significant power savings achieved always disabling parts WM9714L that used (e.g. audio ADC, DAC, AUXADC). Sample rates: Running lower sample rates will reduce power consumption significantly. figures below 48kHz (unless otherwise specified), many scenarios necessary this frequency, e.g. 8kHz voice call scenario uses only 11.4mW (see below). MODE DESCRIPTION AVDD Supply Current 0.01 0.014 2.37 3.644 3.733 4.801 DCVDD Supply Current 9.720 DBVDD Supply Current 0.005 0.005 0.006 2.974 2.789 2.814 Total Power (mW) 0.05 0.06 11.4 58.05 53.60 59.79
(lowest possible power) Clocks stopped. This default configuration after power-up. (Low Power Standby) VREF maintained using 1MOhm string Voice call (fs=8kHz) Record from mono microphone Stereo Playback link headphone) Stereo Playback link headphone) running with 13MHz input MCLKB Maximum Power everything Table Supply Current Consumption
10.973 10.504
13.656 15.472
2.938 105.82
Notes: Unless otherwise specified, figures +25C, audio sample rate 48kHz, with zero signal (quiescent), voltage references settled. power dissipated headphones speakers included above table.
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WM9714L
SIGNAL TIMING REQUIREMENTS
AC97 INTERFACE TIMING
CLOCK SPECIFICATIONS
tCLK_HIGH BITCLK tCLK_LOW
tCLK_PERIOD tSYNC_HIGH tSYNC_LOW
SYNC tSYNC_PERIOD
Figure Clock Specifications (50pF External Load) Test Conditions DBVDD 3.3V, DCVDD 3.3V, DGND1 DGND2 -25°C +85°C, unless otherwise stated. PARAMETER BITCLK frequency BITCLK period BITCLK output jitter BITCLK high pulse width (Note BITCLK pulse width (Note SYNC frequency SYNC period SYNC high pulse width SYNC pulse width Note: Worst case duty cycle restricted 45/55 tSYNC_PERIOD tSYNC_HIGH tSYNC_LOW tCLK_HIGH tCLK_LOW 40.7 40.7 20.8 19.5 tCLK_PERIOD SYMBOL 12.288 81.4 UNIT
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WM9714L
DATA SETUP HOLD
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Figure Data Setup Hold (50pF External Load) Note: Setup hold times SDATAIN with respect AC'97 controller, WM9713L. Test Conditions DBVDD 3.3V, DCVDD 3.3V, DGND1 DGND2 -25°C +85°C, unless otherwise stated. PARAMETER Setup falling edge BITCLK Hold from falling edge BITCLK Output valid delay from rising edge BITCLK SYMBOL tSETUP tHOLD UNIT
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WM9714L
SIGNAL RISE FALL TIMES
triseCLK BITCLK triseSYNC SYNC triseDIN SDATAIN triseDOUT SDATAOUT tfallDOUT tfallDIN tfallSYNC tfallCLK
Figure Signal Rise Fall Times (50pF External Load) Test Conditions DBVDD 3.3V, DCVDD 3.3V, DGND1 DGND2 -25°C +85°C, unless otherwise stated. PARAMETER SYMBOL UNIT BITCLK rise time BITCLK fall time SYNC rise time SYNC fall time SDATAIN rise time SDATAIN fall time SDATAOUT rise time SDATAOUT fall time triseCLK tfallCLK triseSYNC tfallSYNC triseDIN tfallDIN triseDOUT tfallDOUT
AC-LINK POWERDOWN
SYNC
SLOT
SLOT
BITCLK
SDATAOUT
WRITE 0X20
DATA
DON'T CARE
tS2_PDOWN SDATAIN
Figure AC-Link Powerdown Timing AC-Link powerdown occurs when (register 26h, (see "Power Management" section). PARAMETER Slot BITCLK SDATAIN SYMBOL tS2_PDOWN UNIT
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WM9714L
COLD RESET (ASYNCHRONOUS, RESETS REGISTER SETTINGS)
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Figure Cold Reset Timing Note: correct operation SDATAOUT SYNC must held entire RESETB active period otherwise device enter test mode. AC'97 specification Wolfson applications note WAN104 more details. PARAMETER RESETB active pulse width SYMBOL tRST_LOW UNIT
WARM RESET (ASYNCHRONOUS, PRESERVES REGISTER SETTINGS)
Figure Warm Reset Timing
PARAMETER SYNC active high pulse width SYNC inactive BITCLK startup delay
SYMBOL tSYNC_HIGH tRST2CLK
162.4
UNIT
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WM9714L
AUDIO INTERFACE TIMING SLAVE MODE
Figure Digital Audio Data Timing Slave Mode Test Conditions DBVDD 3.3V, DCVDD 3.3V, DGND1 DGND2 -25°C +85°C, unless otherwise stated. PARAMETER Audio Data Input Timing Information PCMCLK cycle time PCMCLK pulse width high PCMCLK pulse width PCMFS set-up time PCMCLK rising edge PCMFS hold time from PCMCLK rising edge PCMDAC set-up time from PCMCLK rising edge PCMDAC hold time from PCMCLK rising edge PCMADC propagation delay from PCMCLK falling edge Note: PCMCLK period should always greater than equal Voice period. tPCMY tPCMH tPCML tFSSU tFSH SYMBOL UNIT
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WM9714L
AUDIO INTERFACE TIMING MASTER MODE
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Figure Digital Audio Data Timing Master Mode (see Control Interface) Test Conditions DBVDD 3.3V, DCVDD 3.3V, DGND1 DGND2 -25°C +85°C, unless otherwise stated. PARAMETER Audio Data Input Timing Information PCMFS propagation delay from PCMCLK falling edge PCMADC propagation delay from PCMCLK falling edge PCMDAC setup time PCMCLK rising edge PCMDAC hold time from PCMCLK rising edge tDDA tDST tDHT SYMBOL UNIT
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WM9714L
DEVICE INTRODUCTION
WM9714L largely compatible upgrade WM9712, with voice codec added. This codec interfaced type audio interface which makes GPIO pins connection. designed meet mixed-signal requirements portable wireless smartphone systems. includes audio recording playback, battery monitoring, auxiliary GPIO functions, controlled through single 5-wire AC-Link interface. Additionally, voice codec functions supported through provision additional voice audio serial interface. included allow unrelated reference clocks used generation link system clock. Typically 13MHz 2.048MHz clock sources might used reference.
SOFTWARE SUPPORT
basic audio features WM9714L software compatible with standard AC'97 device drivers. However, better support additional functions, Wolfson Microelectronics supplies custom device drivers selected CPUs operating systems. Please contact your local Wolfson Sales Office more information.
AC'97 COMPATIBILITY
WM9714L uses AC'97 interface communicate with microprocessor controller. audio GPIO functions largely compliant with AC'97 Revision 2.2. following differences from AC'97 standard noted: Pinout: function some pins been changed support device specific features. PHONE PCBEEP pins have been moved different locations device package. Package: default package WM9714L leadless package. Audio mixing: WM9714L handles audio functions smartphone, including audio playback, voice recording, phone calls, phone call recording, ring tones, well simultaneous these features. AC'97 mixer architecture does fully support this. WM9714L therefore uses modified AC'97 mixer architecture with three separate mixers. Tone Control, Bass Boost Enhancement: These functions implemented digital domain therefore affect only signals being played through audio DACs, output signals stipulated AC'97.
Some other functions additional AC'97: On-chip loudspeaker driver mono stereo speakers On-chip driver speaker (phone receiver) Auxiliary mono ring tones, system alerts etc. Auxiliary Inputs Analogue Comparators Battery Alarm Programmable Filter Characteristics Tone Control Enhancement interface additional Voice existing audio ADCs create AC'97 system clock from unrelated reference clock input
CODEC
voice codec functions typically required mobile telephony devices provided extra voice WM9714L, which interfaced standard type data interface, which constructed through optional GPIO pins WM9714L. audio output data from both audio ADCs also output over this interface, allowing full voice codec function implemented. This interface supports sample rates from 48ks/s using standard AC'97 master clock. February 2008
WM9714L
AUDIO PATHS OVERVIEW
WM9713 Analogue
Note: PGAs summers inverting
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RECMUXR
40h:7 (Loopback) AC'97 Link Left Tone 40h:13 (3DE)
0Ch:12-8 00000 +12dB 11111 -34.5dB
MONOMIX
RECMUXL
PCBEEP
AUXDAC
MONOIN
HPMIXR
SPKMIX
HPMIXL
VXDAC
LINER
DACR
LINEL
DACL
MICA
MIC2
INV1
DACL slot
DACL
LINEL
MONOIN
0Ah:12-8 00000 +12dB 11111 -34.5dB
LINEL
MICA
MICB
PCBEEP
-15dB
LINEL
08h:12-8 00000 +12dB 11111 -34.5dB
MICA
-15dB
10h:
PCBEEP
MONOIN
LINER
Headphone Mixer
1Eh:15-13
INV2
MICB
-15dB
10h:4-0
5-11 14h:1
04h:12-8 00000 11111 -46.5dB
1Ch:7-6 HPMIXL
RECMUXL
-15dB
Zero-cross detect
MONOIN
RECMUXR
-15dB
Vmid
AUXDAC
-15dB
04h:14 (ZC) 04h:15 (MUTE)
VXDAC
-15dB
Link
PCBEEP
MONOIN
AUXDAC
SPKMIX VXDAC INV1 DACL
1Ch:13-11
VXDAC
RECMUXR RECMUXL LINER DACR LINEL DACL MICA MICB
HPMIXL
02h:12-8 00000 11111 -46.5dB
SPKL
Zero-cross detect
DACR
Vmid
LINEL
LINER -15dB
PCBEEP
16h7
02h:14 (ZC) 02h:15 (MUTE) MONO Mixer 08h:4-0 00000 11111 -46.5dB
1Ch:15-14
MICA
20dB
10h:7+5
10h:6
MONOMIX INV1
PCBEEP
0Eh:12-8 00000 +12dB 11111 -34.5dB
MICB
20dB
MONO
Zero-cross detect
RECMUXL
20dB
RECMUXR
20dB
Vmid
AUXDAC
-15dB
08h:6 (ZC) 08h:7 (MUTE)
VXDAC
-15dB
RECMUXR
PCBEEP
MONOIN
MONOMIX
RECMUXL
PCBEEP
MONOIN
AUXDAC
HPMIXR
LINER
LINEL
MICA
MICB
SPKMIX
HPMIXL
VXDAC
LINER
DACR
LINEL
DACL
MICA
MICB
INV1
INV2
06h:4-0 00000 11111 -46.5dB
1Ch:3-2 INV1
OUT3
Zero-cross detect
14h:5-3
12h:14 (GRL=0) 12h:11:8 0000 1111 +22.5dB 12h:14 (GRL=1) 12h:13-8 11111 +30dB 00000 -17.25dB
Vmid
14h:6 20dB
06h:6 (ZC) 06h:7 (MUTE) Variable Slot 5C:1-0 (ASS) 5C:3 (HPF) 5C:4 (ADCO) ALC:5Ch/60h/62h Vmid
Zero-cross detect
Sent Both Link AC'97 Link
1Ch:1-0 INV2
06h:12-8 00000 11111 -46.5dB
OUT4
06h:14 (ZC) 06h:15 (MUTE) 0Ch:4-0 00000 +12dB 11111 -34.5dB Tone 40h:13 (3DE)
RECMUXR
PCBEEP
PCBEEP
AUXDAC
MONOIN
MONOIN
HPMIXR
SPKMIX
HPMIXL
VXDAC
LINER
LINER
DACR
LINEL
LINEL
DACL
MICA
MICB
MICA
MICB
INV1
AC'97 Link Right
DACR slot
DACR
LINER
MONOIN
0Ah:4-0 00000 +12dB 11111 -34.5dB
PCBEEP
-15dB
LINER
MICA
-15dB
10h:4
Headphone Mixer
INV2
40h:7 (Loopback)
MONOMIX
RECMUXL
MICB
-15dB
10h:4-0
15-11 14h:
04h:4-0 00000 11111 -46.5dB
1Ch:5-4 HPMIXR
RECMUXL
-15dB
Zero-cross detect
RECMUXR
-15dB
Vmid
AUXDAC
-15dB
04h:6 (ZC) 04h:7 (MUTE)
Vmid AC'97 Link Resistor string 2Eh/64h
RECMUXR RECMUXL PCBEEP AUXDAC MONOIN VXDAC LINER DACR LINEL DACL MICA MICB
VXDAC
-15dB
Vmid
22h: 13-12
22h:11-10 +12dB +30dB
SPKMIX INV2 LINEL
1Ch:10-8
MIC1
HPMIXR
02h:4-0 00000 11111 -46.5dB
SPKR
Zero-cross detect
MIC2A
Vmid
LINER
DACL
DACR
0Ch:1
Vmid Speaker Mixer
02h:6 (ZC) 02h:7 (MUTE)
MIC2B
22h:9-8 +12dB +30dB
MONOIN
08h:14
-15dB
0Eh:4-0 00000 +12dB 11111 -34.5dB
PCBEEP
AUXDAC
-15dB
MICCM
PCBEEP MONOIN LINER LINEL MICA MICB
16h:1
VXDAC
-15dB
MONOMIX
HPMIXR
SPKMIX
HPMIXL
INV1
14h:2-0
Variable Slot 5C:1-0 (ASS) 5C:3 (HPF) 5C:4 (ADCO) ALC:5Ch/60h/62h
Sent Both Link AC'97 Link
LINEL
MONOIN
PCBEEP
LINER
MICA
MICB
1Eh:12-10
12h:6 (GRR=0) 12h:3:0 0000 1111 +22.5dB 12h:6 (GRR=1) 12h:5-0 11111 +30dB 00000 -17.25dB
PCBEEP
LINER
DACR
DACL
LINEL
MICA
MICB
RECMUXL
MONOIN
14h:6 20dB
RECMUXR
AUXDAC
VXDAC
INV1
HPMIXL
Code
Audio ADCs record Stereo Input PGAs mixers Refs, input PGAs, mixers output PGAs Output PGAs
Note: bits active i.e. "ON"; "OFF" Enable when (PR0 PR2) loAVDD AGND VREF
MONOMIX
HPMIXR
SPKMIX
INV2
INV2
VMICBIAS
Figure Audio Paths Overvie
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WM9714L
WM9714L supports clocking from separate sources, which selected AC'97 interface: External clock input MCLKA External clock input MCLKB
CLOCK GENERATION
source clock divided appropriate frequencies order AC'97 interface, interface, voice Hi-fi means programmable divider block. Clock rates changed during operation AC'97 link order support alternative modes, example power mode when voice data being transmitted only. present flexibility selection input clock frequencies, typical choices being 2.048MHz, 4.096MHz 13MHz.
INITIALISING AC'97 LINK
default, AC'97 link disabled therefore will running after power COLD reset event. Before register configuration begin, necessary start AC'97 link. This achieved sending WARM reset CODEC defined Figure Default mode power-up also assumes clock will present MCLKA with powered down. After WARM reset CODEC will start AC'97 link using MCLKA reference. This enables data clocked AC'97 link define desired clock divider mode whether needs activated. Note: MCLKA available frequency. When muxing between MCLKA MCLKB both clocks must active least clock cycles after switching event.
CLOCK DIVISION MODES
Figure shows clocking strategy WM9714L. Clocking controlled CLK_MUX, CLK_SRC S[6:0]. CLKAX2, CLKBX2 clock doublers inputs MCLKA MCLKB. CLK_MUX selects between MCLKA MCLKB. CLK_SRC selects between external derived clock reference. S[3:0] sets voice clock rate interface clock when master mode (division ratio available). S[6:4] sets hi-fi clocking rate (division ratio available).
registers used these switches accessed from register address (see Table mode change requires switching from external clock generated clock then recommended clock division ratios required clock scheme prior switching between clocks. This option accommodated means sets registers. SPLL[6:0] used divide ratio clock when mode SEXT[6:0] used divide clock when derived from external source. selected (CLK_SRC S[6:0] SPLL[6:0]. SPLL[6:0] defined register (see Table written using page address mode. More details page address mode controlling found page Register also contains number separate control bits relating PLL's function. external clock selected (CLK_SRC S[6:0] SEXT[6:0]. SEXT[6:0] defined register address 44h. Writing registers enables pre-programming required clock mode before output selected.
February 2008
WM9714L
Pre-Production
Figure Clocking Architecture WM9714L
INTERNAL CLOCK FREQUENCIES
internal clock frequencies defined follows (refer Figure 10): AC97 nominally 24.576MHz, used generate AC97 BITCLK 12.288MHz. HIFI HIFI playback 48ks/s HIFI 24.576MHz. Table voice only playback. Voice Table sample rate clock frequency. SAMPLE RATE 8ks/s voice HIFI 8ks/s voice only (power save) 16ks/s voice HIFI 16ks/s voice only (power save) 32ks/s voice HIFI 48ks/s voice HIFI Table Clock Division Mode Table VOICE FREQUENCY 2.048MHz 2.048MHz 4.096MHz 4.096MHz 8.192MHz 12.288MHz HIFI FREQUENCY 24.576MHz 4.096MHz 24.576MHz 8.192MHz 24.576MHz 24.576MHz
AUXADC
clock AUXADC nominally runs 768kHz derived from BITCLK. divisor clock generator PENDIV. This enables AUXADC clock frequency according power consumption conversion rate considerations.
February 2008
Pre-Production Clock mode division ratios controlled register shown Table REGISTER ADDRESS 14:12 LABEL SEXT[6:4] DEFAULT (div
WM9714L
DESCRIPTION Defines clock division ratio Hi-fi: DSP, ADCs DACs 000: 001: 111: Defines clock division ratio interface voice external clock mode only: 0000: 0001: 1111: f/16 Selects between clock External clock clock external clock Sets AUXADC clock divisor 000: f/16 001: f/12 010: 011: 100: 101: 110: 111: Clock doubler MCLKB Clock doubler MCLKA Selects between MCLKA MCLKB (N.B. power-up clock must present MCLKA must active clock cycles after switching MCLKB) SYSCLK=MCLKA SYSCLK=MCLKB
11:8
SEXT[3:0]
0000 (div
CLKSRC
(ext clk)
PENDIV
(div
CLKBX2 CLKAX2 CLKMUX
(Off) (Off) (MCLKA)
Table Clock Muxing Division Control
February 2008
WM9714L
MODE
Pre-Production
operation controlled register (see Table modes operation: Integer Fractional
been optimized nominal input clock (PLL_IN) frequencies range 8.192MHz 19.661MHz (LF=0) 2.048MHz 4.9152MHz (LF=1). Through clock divider (div input frequencies 78.6MHz accommodated. input clock divider enabled DIVSEL (0=Off) division ratio DIVCTL (0=div2, 1=div4).
Figure Architecture REGISTER ADDRESS 15:12 LABEL N[3:0] DEFAULT 0000 DESCRIPTION Divide Control 0000 Divide 0001 Divide 0010 Divide 1111 Divide Note: must between integer mode Frequency Input Control frequency mode (input clock 8.192MHz) Normal mode Enable Control Enable (required fractional mode) Disable Input Clock Division Control Divide Divide according DIVCTL Input Clock Division Value Control Divide Divide Pager Address Pager address bits access programming K[21:0] SPLL[6:0] Pager Data Pager data bits
DIVSEL
DIVCTL
PGADDR
PGDATA
0000
Table Clock Control
February 2008
Pre-Production
WM9714L
INTEGER MODE
nominal output frequency (PLL_OUT) 98.304MHz which divided achieve nominal system clock 24.576MHz. integer division ratio determined FPLL_out FPLL_IN N[3:0] must range integer operation (0101 1100 12). Note that setting LF=1 enables further division required input frequencies range 2.048MHz 4.096MHz. Integer mode selected setting SDM=0.
FRACTIONAL MODE
Fractional mode provides divide resolution 1/222 K[21:0] (register 46h, section). relationship between required division fractional division K[21:0] integer division N[3:0]
where rounded nearest whole number. example, PLL_IN clock 13MHz desired PLL_OUT clock 98.304MHz then desired division, 7.5618. N[3:0] will K[21:0] will 23F488h produce desired 98.304MHz clock (see Table INPUT CLOCK (PLL_IN) DESIRED OUTPUT (PLL_OUT) 98.304MHz 98.304MHz 98.304MHz 98.304MHz 98.304MHz DIVISION REQUIRED 7.5618 7.2818 FRACTIONAL DIVISION INTEGER DIVISION
2.048MHz 4.096MHz 12.288MHz 13MHz 27MHz (13.5MHz)**
0.5618 0.2818
12x4* 6x4*
*Divide enabled feedback path frequency inputs. **Divide enabled input frequencies 14.4MHz 38MHz (DIVSEL DIVCTL Table Modes Operation
February 2008
WM9714L
REGISTER PAGE ADDRESS MAPPING
Pre-Production
clock division control bits SPLL[6:0] fractional division bits accessed through register using sub-page address system. pager address allows blocks data words accessed whilst register address 46h. This means that when register address selected further cycles programming required page data bits. Control allocation these page addresses described Table PAGE ADDRESS 31:28 27:24 LABEL SPLL[6:4] SPLL[3:0] DEFAULT DESCRIPTION Clock division control SPLL[6:0]. Clock divider reads this control word enabled. Bits [6:4] [3:0] have same functionality [14:12] [11:8] respectively Reserved bits Sigma Delta Modulator control word fractional division. Division resolution 1/222
23:22 21:20 19:16 15:12 11:8
Reserved K[21:0]
Table Pager Control Allocation Powerdown internal clocks registers (see Table REGISTER ADDRESS LABEL DEFAULT (Off) DESCRIPTION Internal Clock Disable Control Disabled Enabled Disable Control Disabled Enabled
(Off)
N.B. both must asserted before enabled Table Powerdown Control
February 2008
Pre-Production
WM9714L
DIGITAL INTERFACES
WM9714L interfaces, data control AC'97 interface data only interface. AC'97 interface available through dedicated pins (SDATAOUT, SDATAIN, SYNC, BITCLK RESETB) sole control interface with access data streams device except Voice DAC. interface available through GPIO pins (PCMCLK, PCMFS, PCMDAC PCMADC) provides access Voice DAC. also transmit data from Stereo ADC. This useful, example, allow both sides phone conversation recorded mixing transmit receive paths channels transmitting over interface.
AC97 INTERFACE
INTERFACE PROTOCOL
WM9714L uses AC'97 interface both data transfer control. AC-Link wires: SDATAIN (pin carries data from WM9714L controller SDATAOUT (pin carries data from controller WM9714L BITCLK (pin clock, derived from either MCLKA MCLKB inputs supplied controller. SYNC synchronization signal generated controller passed WM9714L RESETB resets WM9714L default state
Figure AC-Link Interface (typical case with BITCLK generated AC97 codec) SDATAIN SDATAOUT signals each carry time-division multiplexed data streams (slots 12). complete sequence slots referred AC-Link frame, contains total bits. frame rate 48kHz. This makes possible simultaneously transmit receive multiple data streams (e.g. audio, AUXADC, control) sample rates 48kHz. Detailed information found AC'97 (Revision 2.2) specification, which obtained Note: SDATAOUT SYNC must held when RESETB applied. These signals must held entire duration RESETB pulse especially during low-to-high transition RESETB. SDATAOUT SYNC high during reset, WM9714L enter test modes. Information relating this operation available AC'97 specification Wolfson applications note WAN-0104 available www.wolfsonmirco.com.
February 2008
WM9714L
INTERFACE
OPERATION
Pre-Production
WM9714L implement voice codec function using dedicated VXDAC either both existing hi-fi ADC's. codec mode, VXDAC input output interfaced style port GPIO pins. This interface support channel, stereo/dual channels required, (two channels data sent frame back back words). voice only mode, link used only control information, audio data. Therefore will generally shut down (PR4=1), except when control data must sent. interface makes GPIO interface pins, clock, frame, data in/out. codec function enabled then GPIO pins used other functions.
INTERFACE PROTOCOL
WM9714L audio interface used input data Voice output data from Stereo ADC. When enabled, audio interface uses four GPIO pins: GPIO1/PCMCLK: clock GPIO3/PCMFS: Frame Sync GPIO4/PCMDAC: Voice data input GPIO5/PCMADC: Stereo data output
Depending mode operation (see "PCM Interface Modes"), least these four pins must output writing register (see Table 57). When enabled GPIOs used other functions WM9714L.
INTERFACE MODES
WM9714L audio interface configured four modes: Disabled Mode: WM9714L disables tri-states interface pins. clock input ignored ADC/DAC data transferred. Slave Mode: WM9714L accepts PCMCLK PCMFS inputs from external source. Master Mode: WM9714L generates PCMCLK PCMFS outputs. Partial Master Mode: WM9714L generates PCMCLK output, accepts PCMFS external input.
AUDIO DATA FORMATS
Four different audio data formats supported: mode Left justified Right justified
four these modes first. They described below. Refer Electrical Characteristic section timing information.
February 2008
Pre-Production
WM9714L
Interface configured Mono mode, where only channel data output. this mode interface should configured mode. short long frame sync supported available either (mode (mode rising edge VXCLK. Note that when operating stereo mode mono Voice always uses left channel data input.
1/fs PCMCLK
PCMFS
PCMCLK
PCMADC/ PCMDAC
Input Word Length (WL)
Figure Interface Mono Mode (mode FSP=0)
1/fs PCMCLK
PCMFS
PCMCLK
PCMADC/ PCMDAC
Input Word Length (WL)
Figure Interface Mono Mode (mode FSP=1)
February 2008
WM9714L
Pre-Production mode, left channel available either (mode (mode rising edge PCMCLK (selectable FSP) following rising edge PCMFS. Right channel data immediately follows left channel data. Depending word length, PCMCLK frequency sample rate, there unused PCMCLK cycles between right channel data next sample.
1/fs BCLK VXCLK
PCMFS
PCMCLK
LEFT CHANNEL PCMADC/ PCMDAC
RIGHT CHANNEL
Input Word Length (WL)
Figure Mode Audio Interface (mode FSP=0)
1/fs BCLK VXCLK
PCMFS
PCMCLK
LEFT CHANNEL PCMADC/ PCMDAC
RIGHT CHANNEL
Input Word Length (WL)
Figure Mode Audio Interface (mode FSP=1)
February 2008
Pre-Production
WM9714L
Left Justified mode, available first rising edge PCMCLK following PCMFS transition. other bits then transmitted order. Depending word length, PCMCLK frequency sample rate, there unused PCMCLK cycles before each PCMFS transition.
1/fs
LEFT CHANNEL PCMFS
RIGHT CHANNEL
PCMCLK
PCMADC/ PCMDAC
Figure Left Justified Audio Interface (assuming n-bit word length) Right Justified mode, available last rising edge PCMCLK before PCMFS transition. other bits transmitted before (MSB first). Depending word length, PCMCLK frequency sample rate, there unused PCMCLK cycles after each PCMFS transition.
1/fs
LEFT CHANNEL PCMFS
RIGHT CHANNEL
PCMCLK
PCMADC PCMDAC
Figure Right Justified Audio Interface (assuming n-bit word length) mode, available second rising edge PCMCLK following PCMFS transition. other bits then transmitted order. Depending word length, PCMCLK frequency sample rate, there unused PCMCLK cycles between sample next.
1/fs
LEFT CHANNEL PCMFS
RIGHT CHANNEL
PCMCLK
BCLK BCLK
PCMADC/ PCMDAC
Figure Justified Audio Interface (assuming n-bit word length)
February 2008
WM9714L
CONTROL
Pre-Production
register bits controlling audio format, word length operating modes summarised below. CTRL must override normal interface pins GPIOs, MODE must specify master/slave modes. REGISTER ADDRESS Control LABEL CTRL DEFAULT DESCRIPTION GPIO Configuration Control GPIO pins GPIOs GPIO pins configured interface controlled this register Interface Mode Control interface disabled [PCMCLK tristated, PCMFS tri-stated] interface slave mode [PCMCLK input, PCMFS input] interface master mode [PCMCLK output, PCMFS output] interface partial master mode [PCMCLK output, PCMFS input] PCMCLK Rate Control Voice clock Voice clock Voice clock Voice clock Voice clock other values reserved Voice Oversampling Rate Control PCMCLK Polarity Control Normal Inverted PCMFS Polarity Control Normal Inverted Mode Control Mode Mode
14:13
MODE
11:9
VDACOS
Output Channel Control Normal stereo Reverse stereo Output left data only Output right data only Data Word Length Control 16-bit 20-bit 24-bit 32-bit (not supported when FMT=00) Data Format Control Right justified Left justified mode
Table Codec Control Note: Right justified does support 32-bit data.
February 2008
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WM9714L
AUDIO ADCS
STEREO
WM9714L stereo sigma-delta digitize audio signals. achieves high quality audio recording power consumption. sample rate controlled writing control register (see "Variable Rate Audio"). independent sample rate. save power, left right ADCs separately switched using Powerdown bits ADCL ADCR (register 3Ch, bits 5:4), whereas disables both ADCs (see "Power Management" section). only running, same data appears both left right AC-Link slots. output from sent over either link usual, output interface which configured GPIO pins.
HIGH PASS FILTER
WM9714L audio incorporates digital high pass filter that eliminates bias from output data. filter enabled default. measurements, disabled writing (register 5Ch, This high pass filter corner frequency selected have different values WM9714L, suit applications such voice where higher cutoff frequency required. REGISTER ADDRESS LABEL DEFAULT DESCRIPTION Disable Control enabled (for audio) disabled (for measurements) Cut-Off Control fs=48kHz 82Hz fs=16kHz 82Hz fs=8kHz 170Hz fs=8kHz
HPMODE
Note: filter corner frequency proportional sample rate. Table Controlling Highpass Filter
SLOT MAPPING
default, output left audio appears slot SDATAIN signal (pin right data appears slot However, output data also sent other slots, setting (ADC slot select) control bits shown below. REGISTER ADDRESS Additional Functions LABEL DEFAULT DESCRIPTION Data Slot Mapping Control Left Data Table Slot Mapping Slot Slot Slot Slot Right Data Slot Slot Slot Slot
February 2008
WM9714L
RECORD SELECTOR
Pre-Production
record selector determines which input signals routed into audio ADC. left right channels selected independently. This useful recording phone call: channel used signal other signal, that both sides conversation digitized. REGISTER ADDRESS Record Routing Select LABEL RECBST DEFAULT DESCRIPTION Record Boost Control +20dB Note: RECBST gain addition microphone pre-amps (MPABST MPBBST bits) record gain (GRL bits). Left Record Source Control MICA (pre-PGA) MICB (pre-PGA) LINEL (pre-PGA) MONOIN (pre-PGA) HPMIXL SPKMIC MONOMIX Reserved Right Record Source Control MICA (pre-PGA) MICB (pre-PGA) LINEL (pre-PGA) MONOIN (pre-PGA) HPMIXL SPKMIC MONOMIX Reserved
RECSL
RECSR
Table Audio Record Selector
February 2008
Pre-Production
WM9714L
RECORD GAIN
amplitude signal that enters audio controlled Record (Programmable Gain Amplifier). gain programmed either writing Record Gain register, Automatic Level Control (ALC) circuit (see next section). When enabled, writes Record Gain register have effect. different gain ranges implemented: standard gain range defined AC'97 standard, extended gain range with smaller gain steps. circuit always uses extended gain range, this been found result better sound quality. REGISTER ADDRESS Record Gain LABEL DEFAULT DESCRIPTION Audio Input Mute Control Mute mute Note: This control applies both channels Left Gain Range Control Extended Standard Left Recording Volume Control Standard (GRL=0) XX0000: XX0001: +1.5dB (1.5dB steps) XX1111: +22.5dB Standard (GRL=0) XX0000: XX0001: +1.5dB (1.5dB steps) XX1111: +22.5dB
13:8
RECVOLL
000000
Zero Cross Control Zero cross enabled (volume changes when signal zero after time-out) Zero cross disabled (volume changes immediately) Right Gain Range Control Extended Standard Right Recording Volume Control Standard (GRR=0) XX0000: XX0001: +1.5dB (1.5dB steps) XX1111: +22.5dB Standard (GRR=0) XX0000: XX0001: +1.5dB (1.5dB steps) XX1111: +22.5dB
RECVOLR
000000
Table Record Gain Register output Record also mixed into phone and/or headphone outputs (see "Audio Mixers"). This makes possible function microphone signal smartphone application.
February 2008
WM9714L
REGISTER ADDRESS Record Routing 15:14 LABEL DEFAULT (mute)
Pre-Production
Record Headphone Mixer Path Control stereo left only right only 11=mute left right Record Headphone Mixer Path Volume Control +6dB (+3dB steps) -15dB Record Mono Mixer Path Control stereo left record only right record only mute left right Record Headphone Mixer Boost Control +20dB
13:11
R2HVOL
(0dB)
10:9
(mute)
R2MBST
(OFF)
Table Record Routing Control
February 2008
Pre-Production
WM9714L
AUTOMATIC LEVEL CONTROL
WM9714L automatic level control that aims keep constant recording volume irrespective input signal level. This achieved continuously adjusting gain that signal level input remains constant. digital peak detector monitors output changes gain necessary.
input signal
gain
signal after
target level
hold time
decay time
attack time
Figure Operation function enabled using ALCSEL control bits. When enabled, recording volume programmed between -6dB -28.5dB (relative full scale) using ALCL register bits. HLD, control hold, decay attack times, respectively.
HOLD TIME
Hold time time delay between peak level detected being below target gain beginning ramp programmed power-of-two (2n) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. 43.7s. Alternatively, hold time also zero. hold time only applies gain ramp-up, there delay before ramping gain down when signal level above target.
DECAY (GAIN RAMP-UP) TIME
Decay time time that takes gain ramp across range (e.g. from -15B 27.75dB). time takes recording level return target value therefore depends both decay time gain adjustment required. gain adjustment small, will shorter than decay time. decay time programmed power-of-two (2n) steps, from 24ms, 48ms, 96ms, etc. 24.58s.
ATTACK (GAIN RAMP-DOWN) TIME
Attack time time that takes gain ramp down across range (e.g. from 27.75dB down -15B gain). time takes recording level return target value therefore depends both attack time gain adjustment required. gain adjustment small, will shorter than attack time. attack time programmed power-of-two (2n) steps, from 6ms, 12ms, 24ms, etc. 6.14s.
February 2008
WM9714L
Pre-Production When operating stereo, peak detector takes maximum left right channel peak values, gain setting applied both left right PGAs, that stereo image preserved. However, function also enabled channel only. this case, only controlled mechanism, while other channel runs independently with gain through control register. When channel unused, peak detector disregards that channel. function also operate when outputs mixed mono digital domain, they mixed mono analogue domain, before entering ADCs. REGISTER ADDRESS Noise Gate Control 15:14 LABEL ALCSEL DEFAULT (OFF) DESCRIPTION function select (PGA gain register) Right channel only Left channel only Stereo (PGA registers unused) gain limit +30dB +24dB .(6dB steps) -6dB -12dB Programmable zero cross timeout (delay 12.288MHz BITCLK): 2^17 tbitclk (10.67 2^16 tbitclk (5.33 2^15 tbitclk (2.67 2^14 tbitclk (1.33 target sets signal level input 0000 -28.5dB 0001 -27.0dB (1.5dB steps) 1110 -7.5dB 1111 -6dB hold time before gain increased. 0000 0001 2.67ms 0010 5.33ms (time doubles with every step) 1111 43.691s decay (gain ramp-up) time 0000 24ms 0001 48ms 0010 96ms (time doubles with every step) 1010 higher 24.58s attack (gain ramp-down) time 0000 0001 12ms 0010 24ms (time doubles with every step) 1010 higher 6.14s
13:11
MAXGAIN
(+30dB)
10:9
ZCTIMEOUT
Control
15:12
ALCL
1011 (-12dB)
11:8
0000 (0ms)
0011 (192ms)
0010 (24ms)
Table Control
February 2008
Pre-Production
WM9714L
MAXIMUM GAIN
MAXGAIN register sets maximum gain value that whilst under control ALC. This effect when enabled.
PEAK LIMITER
prevent clipping when large signal occurs just after period quiet, circuit includes limiter function. input signal exceeds 87.5% full scale (-1.16dB), gain ramped down maximum attack rate when 0000), until signal level falls below 87.5% full scale. This function automatically enabled whenever enabled. (Note: 0000, then limiter makes difference operation ALC. designed prevent clipping when long attack times used).
NOISE GATE
When signal very quiet consists mainly noise, function cause "noise pumping", i.e. loud hissing noise during silence periods. WM9714L noise gate function that prevents noise pumping comparing signal level input pins (i.e. before record PGA) against noise gate threshold, NGTH. Provided that noise gate function enabled (NGAT noise gate cuts when: Signal level [dB] NGTH [dB] gain [dB] Boost gain [dB] This equivalent Signal level input [dB] NGTH [dB] gain then held constant (preventing from ramping normally would when signal quiet). set, output also muted when noise gate cuts table below summarises noise gate control register. NGTH control bits noise gate threshold with respect full-scale range. threshold adjusted 1.5dB steps. Levels extremes range cause inappropriate operation, care should taken with set-up function. Note that noise gate only works conjunction with function, always operates same channel(s) (left, right, both, none). REGISTER ADDRESS Noise Gate Control LABEL NGAT DEFAULT DESCRIPTION Noise gate function enable enable disable Noise gate type gain held constant mute output Noise gate threshold 00000: -76.5dBFS 00001: -75dBFS steps 11110: -31.5dBFS 11111: -30dBFS
NGTH(4:0)
00000
Table Noise Gate Control
February 2008
WM9714L AUDIO DACS
STEREO
Pre-Production
WM9714L stereo sigma-delta that achieves high quality audio playback power consumption. Digital tone control, adaptive bass boost enhancement functions operate digital audio data before passed stereo DAC. (Contrary AC'97 specification, they have effect analogue input signals signals played through auxiliary DAC. Nevertheless, bits reset register, 00h, indicate that WM9714L supports tone control bass boost.) output volume control. sample rate controlled writing control register (see "Variable Rate Audio"). independent sample rate. When DACs separately powered down using Powerdown register bits DACL DACR (register 3Ch, bits [7:6]).
STEREO VOLUME
volume output signal controlled (Programmable Gain Amplifier). Each mixed into headphone, speaker mono mixer paths (see "Audio Mixers") controlled register 0Ch. Each DAC-to-mixer path independent mute bit. When DAC-to-mixer paths muted muted automatically. When PGAs powered down using Powerdown register bits DACL DACR (register 3Ch, bits [7:6]). REGISTER ADDRESS Volume LABEL DEFAULT DESCRIPTION Headphone Mixer Mute Control Mute mute Speaker Mixer Mute Control Mute mute Mono Mixer Mute Control Mute mute Left Mixers Volume Control 00000 +12dB (1.5dB steps) 11111 -34.5dB Right Mixers Volume Control 00000 +12dB (1.5dB steps) 11111 -34.5dB Automute Status (Read-Only) muted auto-muted Automute Control Disabled Enabled (DAC automatically muted when digital input zero)
12:8
DACL
01000 (0dB)
DACR
01000 (0dB)
Additional Functions
AMUTE
AMEN
Table Stereo Volume Control
February 2008
Pre-Production
WM9714L
TONE CONTROL BASS BOOST
WM9714L provides separate controls bass treble with programmable gains filter characteristics. This function operates digital audio data before passed audio DACs. Bass control take different forms: Linear bass control: bass signals amplified attenuated user programmable gain. This independent signal volume, very high bass gains loud signals lead signal clipping. Adaptive bass boost: bass volume amplified variable gain. When bass volume low, boosted more than when bass volume high. This method recommended because prevents clipping, usually sounds more pleasant human ear.
Treble control applies user programmable gain, without adaptive boost function. Treble, linear bass enhancement produce signals that exceed full-scale. order avoid limiting under these conditions, recommended attenuate digital input signal 6dB. gain outputs should increased compensate attenuation. Cut-only tone adjustment (i.e. bass treble gains adaptive bass boost cannot produce signals above full-scale therefore require set. REGISTER ADDRESS Tone Control LABEL DEFAULT DESCRIPTION Bass Mode Control Linear bass control Adaptive bass boost Bass Cut-off Frequency Control (130Hz 48kHz sampling) High (200Hz 48kHz sampling) Bass Intensity Control BB=0 0000 +9dB 0001 +9dB (1.5dB steps) 0111 (1.5dB steps) 1011-1110 -6dB 1111 Bypass (off) BB=0 0000 +9dB 0001 +9dB (1.5dB steps) 0111 (1.5dB steps) 1011-1110 -6dB 1111 Bypass (off)
11:8
BASS
1111 (off)
Pre-DAC Attenuation Control -6dB Treble Cut-off Frequency Control High (8kHz 48kHz sampling) (4kHz 48kHz sampling) Treble Intensity Control 0000 +9dB 0001 +9dB (1.5dB steps) 0111 (1.5dB steps) 1011-1110 -6dB 1111 Bypass (off)
TRBL
1111 (off)
Table Tone Control Note: cut-off frequencies change proportionally with sample rate.
February 2008
WM9714L
STEREO ENHANCEMENT
Pre-Production
stereo enhancement function artificially increases separation between left right channels amplifying (L-R) difference signal frequency range where human sensitive directionality. programmable depth setting controls degree stereo expansion introduced function. Additionally, upper lower limits frequency range used enhancement selected using 3DFILT control bits.
REGISTER ADDRESS General Purpose Control
LABEL
DEFAULT (disabled)
DESCRIPTION Enhancement Control Enabled Disabled Lower Cut-off Frequency Control High (500Hz 48kHz sampling) (200Hz 48kHz sampling) Upper Cut-off Frequency Control (1.5kHz 48kHz sampling) High (2.2kHz 48kHz sampling) Depth Control 0000 (6.67% steps) 1111 100%
3DLC
3DUC
3DDEPTH
0000
Table Stereo Enhancement Control Note: cut-off frequencies change proportionally with sample rate.
February 2008
Pre-Production
WM9714L
VOICE
VXDAC 16-bit mono intended playback voice signals input interface. Performance been optimised operating 8ks/s 16ks/s. VXDAC will function other sample rates 48ks/s, this recommended. analogue output VXDAC routed directly into output mixers. signal gain into each mixer adjusted mixer inputs using control register 18h. When VXDAC powered down using Powerdown register VXDAC (register 3Ch, 12). REGISTER ADDRESS Powerdown VXDAC Output Control LABEL VXDAC DEFAULT DESCRIPTION VXDAC Disable Control Disabled Enabled VXDAC Headphone Mixer Mute Control Mute mute VXDAC Headphone Mixer Volume Control +6dB (+3dB steps) -15dB VXDAC Speaker Mixer Mute Control Mute mute VXDAC Speaker Mixer Volume Control +6dB (+3dB steps) -15dB VXDAC Mono Mixer Mute Control Mute mute VXDAC Mono Mixer Volume Control +6dB (+3dB steps) -15dB
14:12
V2HVOL
(0dB)
10:8
V2SVOL
(0dB)
V2MVOL
(0dB)
Table VXDAC Control
AUXILIARY
AUXDAC simple 12-bit mono DAC. used generate signals (with numeric input written into control register), signals such telephone-quality ring tones system beeps (with input signal supplied through AC-Link slot). mode (XSLE input data binary offset coded; mode (XSLE there offset. analogue output AUXDAC routed directly into output mixers. signal gain into each mixer adjusted mixer inputs using control register 12h. slot mode (XSLE AUXDAC also supports variable sample rates (See "Variable Rate Audio" section). When auxillary powered down using Powerdown register AUXDAC (register 3Ch, 11).
February 2008
WM9714L
REGISTER ADDRESS Powerdown AUXDAC Input Control LABEL AUXDAC DEFAULT DESCRIPTION AUXDAC Disable Control Disabled Enabled
Pre-Production
XSLE
AUXDAC Input Select Control From AUXDACVAL[11:0] (for signals) From AC-Link (for signals) AUXDAC Input Control (XSLE=1) Slot bits 8-19 Slot bits 8-19 Slot bits 8-19 Slot bits 8-19 Slot bits 8-19 Slot bits 8-19 Slot bits 8-19 Reserved AUXDAC Input Control (XSLE=0) 000h Minimum FFFh Full scale AUXDAC Headphone Mixer Mute Control Mute mute AUXDAC Headphone Mixer Volume Control +6dB (+3dB steps) -15dB AUXDAC Speaker Mixer Mute Control Mute mute AUXDAC Speaker Mixer Volume Control +6dB (+3dB steps) -15dB AUXDAC Mono Mixer Mute Control Mute mute AUXDAC Mono Mixer Volume Control +6dB (+3dB steps) -15dB
14:12
AUXDAC
11:0
AUXDAC
000h
AUXDAC Output Control
14:12
A2HVOL
(0dB)
10:8
A2SVOL
(0dB)
A2MVOL
(0dB)
Table AUXDAC Control
February 2008
Pre-Production
WM9714L
VARIABLE RATE AUDIO SAMPLE RATE CONVERSION
using AC'97 Rev2.2 compliant audio interface, WM9714L record playback commonly used audio sample rates, offer full split-rate support (i.e. DAC, AUXDAC sample rates completely independent each other combination possible). default sample rate 48kHz. register set, then other sample rates selected writing registers 2Ch, 2Eh. AC-Link continues frames second irrespective sample rate selected. However, sample rate less than 48kHz, then some frames carry audio sample. REGISTER ADDRESS Extended Audio Stat/Ctrl LABEL DEFAULT (OFF) DESCRIPTION Variable Rate Audio Control Enable Disable (ADC 48kHz) Note: When VRA=1, sample rates controlled 2Ch, Stereo Sample Rate Control 1F40h 8kHz 2B11h 11.025kHz 2EE0h 12kHz 3E80h 16kHz 5622h 22.05kHz 5DC0h 24kHz 7D00h 32kHz AC44h 44.1kHz BB80h 48kHz other value defaults nearest supported sample rate Stereo Sample Rate Control Values DACSR AUXDAC Sample Rate Control Values DACSR
Audio Sample Rate
15:0
DACSR
BB80h (48kHz)
Audio Sample Rate AUXDAC Sample Rate
15:0
ADCSR
BB80h (48kHz) BB80h (48kHz)
15:0
AUXDA
Table Audio Sample Rate Control Note: Changing sample rate will only effective ADC's DAC's enabled powered before sample rate changed. This done setting relevant bits registers 3Ch, well register 2Ah. process follows: Enable power ADC's DAC's registers 3Ch. Enable 2Ah, Change sample rate respective register.
February 2008
WM9714L AUDIO INPUTS
Pre-Production
following sections give overview analogue audio input pins their function. more information recommended external components, please refer "Applications Information" section.
LINE INPUT
LINEL LINER inputs designed record line level signals, and/or into analogue outputs. Both pins directly connected record selector. record adjusts recording volume, controlled register function. analogue mixing, line input signals pass through separate PGA, controlled register 0Ah. signals mixed into headphone, speaker mono mixer paths (see "Audio Mixers"). Each LINE-to-mixer path independent mute bit. When LINE-to-mixer paths muted line muted automatically. When line inputs used, line switched save power (see "Power Management" section). LINEL LINER biased internally reference voltage VREF. Whenever inputs muted device placed into standby mode, inputs remain biased VREF using special antithump circuitry suppress audible clicks when changing inputs. REGISTER ADDRESS LABEL DEFAULT DESCRIPTION LINE Headphone Mixer Mute Control Mute mute LINE Speaker Mixer Mute Control Mute mute LINE Mono Mixer Mute Control Mute mute LINEL Mixers Volume Control 00000 +12dB (1.5dB steps) 11111 -34.5dB LINER Mixers Volume Control 00000 +12dB (1.5dB steps) 11111 -34.5dB
12:8
LINEL
01000 (0dB)
LINER
01000 (0dB)
Table Line Input Control Additionally, line inputs used single-ended microphone inputs through record provide clickless function bypassing offset introduced through microphone pre-amps. Note that line inputs mixers should deselected this input configuration used.
February 2008
Pre-Production
WM9714L
MICROPHONE INPUT
MICROPHONE PRE-AMPS
There microphone pre-amplifiers, MPB, which configured variety ways accommodate selectable differential microphone inputs differential microphone inputs operating simultaneously stereo noise cancellation. microphone input circuit shown Figure
Vmid
MIC1
Vmid 22h: 13-12
22h:11-10 +12dB +30dB
MIC2A
Vmid
MICA MICB
MIC2B
22h:9-8 +12dB +30dB
MICCM
Figure Microphone Input Circuit input pins used microphones MIC1, MICCM, MIC2A MIC2B. Note that input pins MIC2A MIC2B multi-function inputs must configured microphone inputs when required. This achieved using MICCMPSEL[1:0] register (see Table 23). input microphone pre-amp selected from three microphone inputs MIC1, MIC2A MIC2B using MPASEL[1:0]. Each pre-amp independent boost control from +12dB +30dB four steps. This controlled MPABST[1:0] MPBBST[1:0]. When each microphone pre-amp powered down using Powerdown register bits (register 3Eh, bits [1:0]). When disabled inputs tied Vmid (for MIC2A MIC2B this only applies when they selected microphone inputs, otherwise they left floating). REGISTER ADDRESS 15:14 LABEL MICCMPSEL DEFAULT DESCRIPTION MIC2A/MIC2B Function Control MIC2A MIC2B inputs MIC2A input only MIC2B input only MIC2A MIC2B inputs Pre-Amp Source Control MIC1 MIC2A MIC2B Reserved Pre-Amp Volume Control +12dB +18dB +24dB +30dB Pre-Amp Volume Control MPABST February 2008
13:12
MPASEL
11:10
MPABST
MPBBST
Table Microphone Pre-amp Control
WM9714L
SINGLE OPERATION
Pre-Production
three microphones connected single-ended configuration. three MICs selected input using MPASEL[1:0] (Register 22h, bits 13:12). Only microphone MIC2B selected MPB. Note that MPABST always sets gain selected input microphone. MIC2B selected input recommended that disabled.
DUAL OPERATION
microphones connected dual differential configuration. This suitable stereo microphone noise cancellation applications. Mic1 connected between MIC2A MICCM inputs mic2 connected between MIC2B MICCM inputs shown Figure Additionally, another microphone supported MIC1 selected through input mux. Note that microphones connected single-ended configuration.
Figure Dual Microphone Configuration
February 2008
Pre-Production
WM9714L
MICROPHONE BIASING CIRCUIT
MICBIAS output provides noise reference voltage suitable biasing electret type microphones associated external resistor biasing network. Refer Applications Information section recommended external components. MICBIAS voltage altered MBVOL register 22h. MICBIAS=0.75*AVDD. When MBVOL=0, MICBIAS=0.9*AVDD when MBVOL=1,
microphone bias driven dedicated MICBIAS enabled MPOP1EN register 22h. also configured drive GPIO8 enabled MPOP2EN register 22h. When microphone bias powered down using Powerdown register MICBIAS (register 3Eh, 14). REGISTER ADDRESS LABEL MBOP2EN DEFAULT (Off) DESCRIPTION MICBIAS Output Enable Control Enable MICBIAS output GPIO8 (pin Disable MICBIAS output GPIO8 (pin MICBIAS Output Enable Control Enable MICBIAS output MICBIAS (pin Disable MICBIAS output MICBIAS (pin MICBIAS Output Voltage Control 0.75 AVDD AVDD
MBOP1EN
(On)
MBVOL
Table Microphone Bias Voltage Control internal MICBIAS circuitry shown Figure Note that maximum source current capability MICBIAS 3mA. external biasing resistors therefore must large enough limit MICBIAS current 3mA.
Figure Microphone Bias Schematic
February 2008
WM9714L
MICBIAS CURRENT DETECT
Pre-Production
WM9714L includes microphone bias current detect circuit with programmable thresholds microphone bias current, above which interrupt will triggered. There separate interrupt bits, MICDET e.g. distinguish between microphones connected WM9714L, MICSHT detect shorted microphone (mic button press). microphone current detect threshold MCDTHR[2:0], MICDET, MCDSCTHR[1:0] MICSHT. Thresholds each code shown Table When microphone bias current detect circuit powered down using Powerdown register (register 3Eh, 15). GPIO Interrupt Controller sections details interrupt status readback these MICBIAS current detection features. REGISTER ADDRESS LABEL MCDTHR DEFAULT DESCRIPTION Detect Threshold Control 100µA (100µA steps) 800µA Note: These values 3.3V supply scale with supply voltage (AVDD). Detect Short Circuit Threshold Control 600µA 1200uA 1800uA 2400µA Note: These values 3.3V supply scale with supply voltage (AVDD).
MCDSCTR
Table Microphone Current Detect Control
February 2008
Pre-Production
WM9714L
MICROPHONE PGAS
microphone pre-amps drive into microphone PGAs whose gain controlled register 0Eh. signals routed into headphone mixers mono mixer, speaker mixer prevent forming feedback loop) controlled register 10h. When signals selected input mixers outputs PGAs muted automatically. When microphone PGAs powered down using Powerdown register bits (register 3Eh, bits [3:2]). REGISTER ADDRESS Volume 12:8 LABEL MICAVOL DEFAULT 01000 (0dB) DESCRIPTION MICA Volume Control 00000 +12dB (1.5dB steps) 11111 -34.5dB MICB Volume Control 00000 +12dB (1.5dB steps) 11111 -34.5dB
MICBVOL
01000 (0dB)
Table Microphone Volume Control REGISTER ADDRESS Routing LABEL MA2M DEFAULT DESCRIPTION MICA Mono Mixer Mute Control Mute mute MICB Mono Mixer Mute Control Mute mute Mono Mixer Boost Control +20dB Headphone Mixer Path Control stereo MICA only MICB only mute MICA MICB Headphone Mixer Path Volume Control +6dB (+3dB steps) -15dB
MB2M
MIC2MBST
MIC2H
MIC2HVOL
(0dB)
Table Microphone Routing Control
February 2008
WM9714L
MONOIN INPUT
Pre-Production
(MONOIN) mono input designed connect receive path telephony device. connects directly record selector phone call recording (Note: record both sides phone call, channel should record MONOIN signal while other channel records signal). record adjusts recording volume, controlled register function (see "Record Gain" "Automatic Level Control" sections). REGISTER ADDRESS Record Routing 15:14 LABEL DEFAULT (mute) DESCRIPTION Record Headphone Mixer Path Control stereo left record only right only 11=mute left right Record Headphone Mixer Path Volume Control +6dB (+3dB steps) -15dB Record Mono Mixer Path Control stereo left record only right record only mute left right Record Headphone Mixer Boost Control +20dB
13:11
R2HVOL
(0dB)
10:9
(mute)
R2MBST
(0dB)
Table Record Routing Control listen MONOIN signal, signal passes through separate PGA, controlled register 08h. signal routed into headphone mixer (for normal phone call operation) and/or speaker mixer (for speakerphone operation), into mono mixer prevent forming feedback loop). When signal selected input mixers output muted automatically. When MONOIN powered down using Powerdown register MOIN (register 3Eh, MONOIN biased internally reference voltage VREF. Whenever input muted device placed into standby mode, input remains biased VREF using special anti-thump circuitry suppress audible clicks when changing inputs. REGISTER ADDRESS MONOIN Routing LABEL DEFAULT DESCRIPTION MONOIN Headphone Mixer Mute Control Mute mute MONOIN Speaker Mixer Mute Control Mute mute MONOIN Mixers Volume Control 00000 +12dB (1.5dB steps) 11111 -34.5dB February 2008
12:8
MONOIN
01000 (0dB)
Table Mono Control
Pre-Production
WM9714L
(PCBEEP) mono, line level input intended externally generated signal warning tones. routed directly record selector three output mixers, without input amplifier. signal gain into each mixer independently controlled, with separate mute each signal path. PCBEEP biased internally reference voltage VREF. When signal selected input mixers input remains biased VREF using special anti-thump circuitry suppress audible clicks when changing inputs. REGISTER ADDRESS PCBEEP input LABEL DEFAULT DESCRIPTION PCBEEP Headphone Mixer Mute Control Mute mute PCBEEP Headphone Mixer Volume Control +6dB (+3dB steps) -15dB PCBEEP Speaker Mixer Mute Control Mute mute PCBEEP Speaker Mixer Volume Control +6dB (+3dB steps) -15dB PCBEEP Mono Mixer Mute Control Mute mute PCBEEP Mono Mixer Volume Control +6dB (+3dB steps) -15dB
PCBEEP INPUT
14:12
B2HVOL
(0dB)
10:8
B2SVOL
(0dB)
B2MVOL
(0dB)
Table PCBEEP Control
DIFFERENTIAL MONO INPUT
PCBEEP MONOIN inputs configured provide differential mono input. This achieved mixing inputs together using headphone mixers speaker mixer. Note that gain MONOIN must match gain PCBEEP mixer input achieve balanced differential mono input.
February 2008
WM9714L AUDIO MIXERS
MIXER OVERVIEW
Pre-Production
WM9714L four separate low-power audio mixers cover audio functions required smartphones, PDAs handheld computers. These mixers used drive audio outputs HPL, HPR, MONO, SPKL, SPKR, OUT3 OUT4. There also inverters used provide differential output signals (e.g. driving loads)
HEADPHONE MIXERS
There headphone mixers, headphone mixer left headphone mixer right (HPMIXL HPMIXR). These mixers stereo output driver source. They used drive stereo outputs HPR. They also used drive SPKL SPKR outputs and, when used conjunction with OUT3 OUT4, they configured drive complementary signals through output inverters support bridge-tied load (BTL) stereo loudspeaker outputs. following signals mixed into headphone path: MONOIN (controlled register 08h, "Audio Inputs") LINEL/R (controlled register 0Ah, "Audio Inputs") output Record (controlled register 14h, "Audio ADC", "Record Gain") stereo signal (controlled register 0Ch, "Audio DACs") signal (controlled register 10h, "Audio Inputs") PC_BEEP (controlled register 16h, "Audio Inputs") VXDAC signal (controlled register 18h, "Audio DACs") AUXDAC signal (controlled register 1Ah, "Auxiliary DAC")
typical smartphone application, headphone signal MONOIN VXDAC sidetone (for phone calls) stereo signal (for music playback). When headphone mixers powered down using Powerdown register bits HPLX HPRX (register 3Ch, bits [3:2]).
SPEAKER MIXER
speaker mixer (SPKMIX) mono source. typically used drive mono loudspeaker configuration. following signals mixed into speaker path: MONOIN (controlled register 08h, "Audio Inputs") LINEL/R (controlled register 0Ah, "Audio Inputs") stereo signal (controlled register 0Ch, "Audio DACs") PC_BEEP (controlled register 16h, "Audio Inputs") VXDAC signal (controlled register 18h, "Audio DACs") AUXDAC signal (controlled register 1Ah, "Auxiliary DAC")
typical smartphone application, speaker signal AUXDAC (for system alerts ring tone playback), MONOIN VXDAC (for speakerphone function), PC_BEEP (for externally generated ring tones). Note that when selected stereo input pairs LINEL/R DACL/R summed attenuated -6dB that 0dBFS signals each channel give 0dBFS mono signal. When speaker mixer powered down using Powerdown register SPKX (register 3Ch,
February 2008
Pre-Production
WM9714L
MONO MIXER
mono mixer drives MONO pin. following signals mixed into MONO: LINEL/R (controlled register 0Ah, "Audio Inputs") output Record (controlled register 14h, "Audio ADC", "Record Gain") stereo signal (controlled register 0Ch, "Audio DACs") signal (controlled register 10h, "Audio Inputs") PC_BEEP (controlled register 16h, "Audio Inputs") VXDAC signal (controlled register 18h, "Audio DACs") AUXDAC signal (controlled register 12h, "Auxiliary DAC")
typical smartphone application, MONO signal amplified microphone signal (possibly with Automatic Gain Control) enabled) audio playback signal from stereo auxiliary DAC. Note that when selected stereo input pairs LINEL/R DACL/R summed attenuated -6dB that 0dBFS signals each channel give 0dBFS mono signal. When mono mixer powered down using Powerdown register (register 3Ch,
MIXER OUTPUT INVERTERS
There general purpose mixer output inverters, INV1 INV2. Each inverter selected drive HPMIXL, HPMIXR, SPKMIX, MONOMIX HPMIXL HPMIXR outputs inverters used generate complimentary signals drive configured loads) provide greater flexibility output driver configurations. INV1 selected source SPKL, MONO OUT3 INV2 source SPKR OUT4. input source each inverter selected using INV1[2:0] INV2[2:0] register (see Table 31). When input selected inverter powered down. REGISTER ADDRESS 15:13 LABEL INV1 DEFAULT (OFF) DESCRIPTION INV1 Source Select input (tri-stated) MONOMIX SPKMIX HPMIXL HPMIXR HPMIXMONO Reserved VMID INV2 Source Select input (tri-stated) MONOMIX SPKMIX HPMIXL HPMIXR HPMIXMONO Reserved VMID
12:10
INV2
(OFF)
Table Mixer Inverter Source Select
February 2008
WM9714L ANALOGUE AUDIO OUTPUTS
Pre-Production
following sections give overview analogue audio output pins. WM9714L three outputs capable driving loads down (headphone line drivers) HPL, MONO four outputs capable driving loads down (loudspeaker line drivers) SPKL, SPKR, OUT3 OUT4. combination output drivers, mixers mixer inverters means that many output configurations supported. examples typical output mixer configurations please refer "Typical Output Configuration" section. more information recommended external components, please refer "Applications Information" section. Each output driven with gain range -46.5dB -1.5dB steps. Each input source mux, mute zero-cross detect circuit (delaying gain changes until zero-cross detected, after time-out).
HEADPHONE OUTPUTS
outputs (pins designed drive headphone load. They also used line outputs. They used coupled coupled (capless) configuration. available input sources HPMIXL/R Vmid (see Table 32). REGISTER ADDRESS Output Select LABEL DEFAULT (Vmid) DESCRIPTION Source Control VMID input (tri-stated disabled 3Eh) HPMIXL Reserved Source Control VMID input (tri-stated disabled 3Eh) HPMIXR Reserved
(Vmid)
Table Input Source signal volume independently adjusted under software control writing register 04h. When powered down using Powerdown register bits (register 3Eh, bits [10:9]). minimise pops clicks when powered down recommended that Vmid input selected during power down cycle. This ensures same level maintained output throughout.
February 2008
Pre-Production REGISTER ADDRESS Headphone Volume LABEL DEFAULT (Mute)
WM9714L
DESCRIPTION Mute Control Mute mute Zero Cross Control Zero cross enabled (change volume only zero crossings, after time-out) Zero cross disabled (change volume immediately) Volume Control 000000 (maximum) (1.5dB steps) 011111 -46.5dB 1xxxxx -46.5dB Mute Control Mute mute Zero Cross Control Zero cross enabled (change volume only zero crossings, after time-out) Zero cross disabled (change volume immediately) Volume Control 000000 (maximum) (1.5dB steps) 011111 -46.5dB 1xxxxx -46.5dB
13:8
HPLVOL
000000 (0dB)
(Mute)
HPRVOL
000000 (0dB)
Table Control
MONO OUTPUT
MONO output (pin designed drive headphone load also used line output. available input sources MONOMIX, INV1 Vmid (see Table REGISTER ADDRESS Output Select 15:14 LABEL MONO DEFAULT (Vmid) DESCRIPTION MONO Source Control VMID input (tri-stated MONO disabled 3Eh) MONOMIX INV1
Table MONO Input Source signal volume MONO independently adjusted under software control writing register 08h. When MONO powered down using Powerdown register MONO (register 3Eh, 13). minimise pops clicks when powered down recommended that Vmid input selected during power down cycle. This ensures same level maintained output throughout.
February 2008
WM9714L
REGISTER ADDRESS MONO LABEL DEFAULT (Mute)
Pre-Production DESCRIPTION MONO Mute Control Mute mute MONO Zero Cross Control Zero cross enabled (change volume only zero crossings, after time-out) Zero cross disabled (change volume immediately) MONO Volume Control 000000 (maximum) (1.5dB steps) 011111 -46.5dB 1xxxxx -46.5dB
MONOVOL
000000 (0dB)
Table Mono Control
SPEAKER OUTPUTS SPKL SPKR
SPKL SPKR (pins designed drive loudspeaker load down also used line outputs headphone outputs. They designed drive load coupled (capless) configuration. available input sources HPMIXL/R, SPKMIXL/R, INV1/2 Vmid (see Table 36). REGISTER ADDRESS Output Select 13:11 LABEL SPKL DEFAULT (Vmid) DESCRIPTION SPKL Source Control VMID input (tri-stated SPKL disabled 3Eh) HPMIXL SPKMIX INV1 other values reserved SPKR Source Control VMID input (tri-stated SPKR disabled 3Eh) HPMIXR SPKMIX INV2 other values reserved
10:8
SPKR
(Vmid)
Table SPKL SPKR Input Source signal volume SPKL SPKR independently adjusted under software control writing register 02h. When SPKL SPKR powered down using Powerdown register bits SPKL SPKR (register 3Eh, bits [8:7]). minimise pops clicks when powered down recommended that Vmid input selected during power down cycle. This ensures same level maintained output throughout.
February 2008
Pre-Production REGISTER ADDRESS Speaker Volume LABEL DEFAULT (Mute)
WM9714L
DESCRIPTION SPKL Mute Control Mute mute SPKL Zero Cross Control Zero cross enabled (change volume only zero crossings, after time-out) Zero cross disabled (change volume immediately) SPKL Volume Control 000000 (maximum) (1.5dB steps) 011111 -46.5dB 1xxxxx -46.5dB SPKR Mute Control Mute mute SPKR Zero Cross Control Zero cross enabled (change volume only zero crossings, after time-out) Zero cross disabled (change volume immediately) SPKR Volume Control 000000 (maximum) (1.5dB steps) 011111 -46.5dB 1xxxxx -46.5dB
13:8
SPKLVOL
000000 (0dB)
(Mute)
SPKRVOL
000000 (0dB)
Table SPKL SPKR Control Note: speaker drive, recommended that both PGAs have same gain setting.
AUXILIARY OUTPUTS OUT3 OUT4
OUT3 OUT4 outputs (pins designed drive loudspeaker load down also used line outputs headphone outputs. They designed drive load coupled (capless) configuration used midrail buffer drive headphone outputs capless configuration. available input sources INV1/2 Vmid (see Table 38). REGISTER ADDRESS Output Select LABEL OUT3 DEFAULT (Vmid) DESCRIPTION OUT3 Source Control VMID input (tri-stated OUT3 disabled 3Eh) INV1 Reserved OUT4 Source Control VMID input (tri-stated OUT4 disabled 3Eh) INV2 Reserved
OUT4
(Vmid)
Table OUT3 OUT4 Input Source signal volume OUT3 OUT4 independently adjusted under software control writing register 06h.
February 2008
WM9714L
Pre-Production When OUT3 OUT4 powered down using Powerdown register bits OUT3 OUT4 (register 3Eh, bits [11:12]). minimise pops clicks when powered down recommended that Vmid input selected during power down cycle. This ensures same level maintained output throughout. REGISTER ADDRESS Speaker Volume LABEL DEFAULT (Mute) DESCRIPTION OUT4 Mute Control Mute mute OUT4 Zero Cross Control Zero cross enabled (change volume only zero crossings, after time-out) Zero cross disabled (change volume immediately) OUT4 Volume Control 000000 (maximum) (1.5dB steps) 011111 -46.5dB 1xxxxx -46.5dB OUT3 Mute Control Mute mute OUT3 Zero Cross Control Zero cross enabled (change volume only zero crossings, after time-out) Zero cross disabled (change volume immediately) OUT3 Volume Control 000000 (maximum) (1.5dB steps) 011111 -46.5dB 1xxxxx -46.5dB
13:8
OUT4VOL
000000 (0dB)
(Mute)
OUT3VOL
000000 (0dB)
Table OUT3 OUT4 Control
THERMAL SENSOR
speaker headphone outputs drive very large currents. protect WM9714L from becoming hot, thermal sensor been built chip temperature reaches approximately 150°C, set, WM9714L deasserts GPIO register 54h, virtual GPIO that generate interrupt (see "GPIO Interrupt Control" section). REGISTER ADDRESS LABEL TSHUT DEFAULT DESCRIPTION Thermal Shutdown Disable Control Disabled Enabled Thermal Sensor (virtual GPIO) Temperature below 150°C Temperature above 150°C also "GPIO Interrupt Control" section.
Table Thermal Cutout Control
February 2008
Pre-Production
WM9714L
JACK INSERTION AUTO-SWITCHING
phone application, speaker connected across MONO HPL, stereo headphone stereo speakers SPKL, SPKR, OUT3 OUT4 (see Figure 23). Typically, only these three output devices used given time: when headphone plugged speaker stereo speakers active, otherwise headphone used.
Figure Typical Output Configuration presence headphone detected using GPIO1/6/7/8 (pins external pull-up resistor (see Figure page circuit diagram). When jack inserted, GPIO pulled switch socket. When jack removed GPIO pulled high resistor. JIEN set, WM9714L automatically switches between headphone other output configuration, typically speaker stereo speaker that been Powerdown Output Select registers. Note: Please refer WAN_0182 further information jack detect configuration addition typical configuration explained above, WM9714L also support automatic switching between following three configurations speaker headphone. REGISTER ADDRESS Output Volume Mapping (Jack Insert) LABEL EARSPKSEL DEFAULT DESCRIPTION Speaker Source Control Default, speaker configuration selected. MONO driver selected speaker. OUT3 driver selected speaker. OUT4 driver selected speaker.
Table Speaker Configuration example OUT4 selected speaker, user should select EARSPKSEL then OUT4 tri-stated jack insert prevent sound across speaker during headphone operation volume OUT4 volume jack ensure correct speaker operation. should noted that other outputs except HPL, selected
February 2008
WM9714L
Pre-Production speaker driver disabled internally connected VREF jack insert. This maintains VREF those outputs helps prevent pops when outputs enabled. Finally user wishes couple headphone outputs user needs select between OUT3 OUT4 mid-rail output buffer driver. selected mid-rail output buffer enabled jack insert. jack defaults whatever configuration been Powerdown Output Select registers. REGISTER ADDRESS Output Volume Mapping (Jack Insert) LABEL DCDRVSEL DEFAULT DESCRIPTION Jack Insert Headphone Reference Control coupled headphones, source OUT3 mid-rail output buffer Reserved OUT4 mid-rail output buffer
Table Coupled Headphone Configuration summary: JIEN set: Outputs work normal selected Powerdown Output Select registers. JIEN set: jack insert GPIO1/6/7/8 pulled low, enabled, DCDRVSEL decides headphones coupled configures OUT3 OUT4 suit, EARSPKSEL decides MONO, OUT3 OUT4 need tri-stated ensure sound ear-speaker finally other outputs disabled explained above prevent pops re-enabling. jack GPIO1/6/7/8 pulled high, outputs work normal selected Powerdown Output Select registers except that Volume controlled EARSPKSEL ensure correct speaker operation.
REGISTER ADDRESS Output Volume Mapping (Jack Insert) Additional Functions
LABEL JIEN
DEFAULT (OFF)
DESCRIPTION Jack Insert Control Disable jack insert circuitry Enable jack insert circuitry Jack Detect Input Control GPIO1 GPIO6 GPIO7 GPIO8
JSEL
(GPIO1)
Table Jack Insertion Auto-Switching
February 2008
Pre-Production
WM9714L
MONO STATE
VOLUME
VOLUME
MODE DESCRIPTION GPIO1
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled User Controlled User Controlled
Jack Insert Detection Enabled. Headphone plugged Speaker Selected. Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged MONO Speaker Selected. Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged OUT3 Speaker Selected. Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged OUT4 Speaker Selected. Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged OUT4 Speaker Selected. OUT3 Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged out. Speaker Selected. Jack Insert Detection Enabled. Headphone plugged out. OUT4 Speaker Selected.
Volume
Volume
Enabled
Enabled
Volume
Volume
Tri-Stated
Enabled
Enabled
Volume
Volume
Tri-Stated
Enabled
Enabled
Volume
Volume
Tri-Stated
Enabled
Enabled
Volume
Volume
Tri-Stated
Enabled
Enabled
VMID
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
Table Jack Insertion Auto-Switching
February 2008
User Controlled
OUT4 Volume
User Controlled
User Controlled
Jack Insert Detection Disabled.
SPKR STATE
SPKL STATE
OUT3 STATE
OUT4 STATE
EARSPKSEL
STATE
STATE
DCDRVSEL
JIEN
WM9714L DIGITAL AUDIO (S/PDIF) OUTPUT
Pre-Production
WM9714L supports S/PDIF standard. Pins used output S/PDIF data. Note that pins also used GPIO pins. bits (register 56h, select between GPIO S/PDIF functionality pins respectively (see "GPIO Interrupt control" section). Register read/write register that controls S/PDIF functionality manages fields propagated channel status sub-frame case). With exception this register should only written when S/PDIF transmitter disabled (S/PDIF register `0'). Once desired values have been written this register, contents should read back ensure that sample rate particular supported, then S/PDIF validity SPCV register should read ensure desired configuration valid. Only then should S/PDIF enable register set. This ensures that control status information start correctly beginning S/PDIF transmission.
February 2008
Pre-Production REGISTER ADDRESS Extended Audio LABEL SPCV DEFAULT
WM9714L
S/PDIF Validity (Read Only) Valid valid S/PDIF Slot Assignment Control Slots Slots Slots Slots Note: This control only valid when ADCO=0 S/PDIF Output Enable Control Enabled Disabled S/PDIF Validity Valid valid Indicates that WM9713L does support double rate S/PDIF output (read-only) Indicates that WM9713L only supports 48kHz sampling S/PDIF output (readonly) S/PDIF L-bit Control Programmed required user S/PDIF Category Code Control Category code; programmed required user S/PDIF Pre-emphasis Indication Control pre-emphasis 50/15µs pre-emphasis S/PDIF Copyright Indication Control Copyright asserted Copyright asserted S/PDIF Non-audio Indication Control data Non-PCM data (e.g. DTS) S/PDIF Professional Indication Control Consumer mode Professional mode S/PDIF Data Source Control From SDATAOUT (pin Output from audio Note: Slot selected SPSA
SPSA
S/PDIF Control Register
13:12
SPSR
10:4
0000000
COPY
AUDIB
Additional Function Control
ADCO
Table S/PDIF Output Control
February 2008
WM9714L AUXILIARY
Pre-Production
WM9714L includes very power, 12-bit successive approximation type which used battery auxiliary measurements. Three pins that used auxiliary inputs: MIC2A COMP1 AUX1 (pin MIC2B COMP2 AUX2 (pin AUX4 (pin
Pins also used comparator inputs (see "Battery Alarm Analogue Comparators"), auxiliary measurements still taken these pins time. Additionally, speaker supply (SPKVDD) used auxillary input through onchip potential divider giving input auxillary SPKVDD/3. This input referred AUX3 input.
Figure Auxiliary Inputs accessed controlled through AC-Link interface.
AUXADC POWER MANAGEMENT
save power, AUXADC independently disabled when used. AUXADC powered-down using PADCPD, register state controlled following bits. REGISTER ADDRESS LABEL PADCPD DEFAULT DESCRIPTION AUXADC Disable Control Disabled Enabled Additional Enable AUXADC Disabled Reserved Reserved Enabled
15:14
Table AUXADC Power Management
February 2008
Pre-Production
WM9714L
INITIATION MEASUREMENTS
WM9714L AUXADC interface supports both polling routines (direct memory access) control flow data from host CPU. polling routine, starts each measurement individually writing POLL (register 74h, This automatically resets itself when measurement completed. REGISTER ADDRESS LABEL POLL DEFAULT DESCRIPTION Poll Measurement Control Writing initiates measurement (when CTC=0) AUXADC Measurement Mode Polling mode Continuous mode (for DMA) Continuous Mode Conversion Rate Continuous mode rate (DEL 1111) 93.75 (every AC-Link frames) (every AC-Link frames) 153.75 (every AC-Link frames) 187.5Hz (every AC-Link frames) Continuous mode "fast rate" (DEL 1111) (every AC-Link frames) (every four AC-Link frames) (every other AC-Link frame) (every AC-Link frame) Table Control (Initiation Measurements) continuous mode (CTC WM9714L autonomously initiates measurements sets measurements) rate supplies measured data unused AC'97 time slots. DMA-enabled CPUs write data directly into FIFO without intervention core. This reduces loading speeds execution user programs handheld systems. Note that measurement frequency continuous mode also affected bits. faster rates achieved when 1111 useful when used multiple measurements.
February 2008
WM9714L
MEASUREMENT TYPES
Pre-Production
ADCSEL control bits determine which type measurement performed (see below). REGISTER ADDRESS LABEL ADCSEL_AUX4 DEFAULT DESCRIPTION AUX4 Measurement Enable Control Disable AUX4 measurement (pin Enable AUX4 measurement (pin ADCSEL_AUX3 AUX3 Measurement Enable Control Disable AUX3 measurement (SPKVDD/3) Enable AUX3 measurement (SPKVDD/3) AUX2 Measurement Enable Control Disable AUX2 measurement (pin Enable AUX2 measurement (pin AUX1 Measurement Enable Control Disable AUX1 measurement (pin Enable AUX1 measurement (pin
ADCSEL_AUX2
ADCSEL_AUX1
Note: Only 74h[7:4] should time Table Control (Measurement Types) WM9714L performs single measurement either polling mode continuously, indicated bit. type measurement specified ADCSEL[7:4] bits. Only ADCSEL[7:4] bits should set.
CONVERSION RATE
AUXADC conversion rate specified bits (reg 76h). 93.75Hz (every AC-Link Frames), 120Hz (every AC-Link Frames), 153.75Hz (every AC-Link frames) 187.5Hz (every AC-Link frames). only ADRSEL[7:1] then each individual conversion occurs rate specified multiple ADRSEL[7:1] bits then complete conversions requested completed rate specified
February 2008
Pre-Production
WM9714L
DATA READBACK
AUXADC measured data stored register 7Ah, retrieved reading register usual manner (see AC-Link Interface section). Additionally, data also passed controller AC-Link time slots used audio functions. output data word interface consists three parts: Unused (Ignore). Output data from bits) ADCSRC: additional bits that indicate source data.
data being read back using polling method, there several ways determine when measurement finished: Reading back POLL bit. been reset `0', then measurement finished. Monitoring signal, GPIO interrupt section. goes high after every single conversion. Reading back until data appears
REGISTER ADDRESS AC-Link slot selected
14:12
LABEL ADCSRC
DEFAULT
DESCRIPTION AUXADC Source measurement Reserved Reserved Reserved COMP1/AUX1 measurement (pin COMP2/AUX2 measurement (pin AUX3 measurements (SPKVDD/3) AUX4 measurement (pin AUXADC Data (Read-only) AUXADC Data Control Overwrite existing data with data Retain existing data until read
11:0
ADCD
000h
WAIT
Table Data avoid losing data that been read, WM9714L delay overwriting register with conversions until data been read. This function enabled using WAIT bit. SLEN `1', then data appears AC-Link slot selected control bits, shown below. Slot `tag' corresponding selected time slot asserted whenever there data that slot.
February 2008
WM9714L
REGISTER ADDRESS LABEL SLEN DEFAULT
Pre-Production
Slot Readback Enable Control Disabled (readback through register only) Enabled (readback slot selected SLT) AC'97 Slot AUXADC Data Control Slot Slot Slot Slot Slot Slot Slot Reserved
Table Returning Data Through AC-Link Time Slot
MASK INPUT CONTROL
Sources glitch noise, such signals driving display, feed through inputs affect measurement accuracy. order minimise this effect, signal applied MASK (pin delay synchronise sampling input ADC. effect MASK signal depends bits register (bits [7:6]), described below. REGISTER ADDRESS LABEL DEFAULT DESCRIPTION Mask Input Control Table details
Table MASK Input Control MSK[1-0] EFFECT SIGNAL MASK Mask effect conversions GPIO input disabled (default) Static; `hi' MASK stops conversions, `lo' effect. Edge triggered; rising falling edge MASK delays conversions amount DEL[3-0] register. Conversions asynchronous MASK signal. Synchronous mode; conversions wait until rising falling edge MASK initiates cycle; screen starts driven when edge arrives, conversion sample being taken period DEL[3-0] after edge.
Table Controlling MASK Feature Note that also used GPIO (see "GPIO Interrupt Control" section), output signal (see below).
SIGNAL
Whenever data becomes available from AUXADC, internal (ADC Data Available) signal goes high remains high until data been read from register SLEN until been sent AC-Link slot SLEN goes high after every AUXADC conversion normal mode, COO=0) used generate interrupt, (register 52h, (see "GPIO interrupt control" section) also possible output signal this used GPIO. GE4/6 must achieve this (see "GPIO interrupt control" section). Alternatively, read from register 54h.
February 2008
Pre-Production
WM9714L
ADDITIONAL FEATURES
BATTERY ALARM ANALOGUE COMPARATORS
battery alarm function differs from battery measurement that does actually measure battery voltage. Battery alarm only indicates "OK", "Low" "Dead". advantage battery alarm function that does require clock therefore used low-power sleep standby modes.
Figure Battery Alarm Example Schematic typical schematic dual threshold battery alarm shown above. This alarm thresholds, "dead battery" (COMP1) "low battery" (COMP2). threshold voltages. Their values about order keep battery current [IALARM VBATT (R1+R2+R3)] minimum (higher resistor values affect accuracy system leakage currents into input pins become significant). Dead battery alarm: COMP1 triggers when VBATT VREF (R1+R2+R3) (R2+R3) dead battery alarm highest priority interrupt system. should immediately save unsaved data shut down system. GP15, GS15 GW15 bits must generate this interrupt. battery alarm: COMP2 triggers when VBATT VREF (R1+R2+R3) battery alarm lower priority than dead battery alarm. Since threshold voltage higher than dead battery alarm, there enough power left battery give user warning and/or shut down "gracefully". When VBATT gets close battery threshold, spurious alarms filtered COMP2 delay function. purpose capacitor remove from comparator inputs high frequency noise glitches that present battery (for example, noise generated charge pump). forms pass filter with pass cutoff [Hz] (R2+R3))) Provided that cutoff frequency several orders magnitude lower than noise frequency this simple circuit achieve excellent noise rejection. Noise rejection [dB] circuit shown above also allows measuring battery voltage VBATT. This achieved simply setting AUXADC input either COMP1 (ADCSEL 100) COMP2 (ADCSEL 101) (see also Auxiliary Inputs).
February 2008
WM9714L
Pre-Production WM9714L on-chip comparators that used implement battery alarm function, other functions such window comparator. Each comparator inputs tied COMP1 (pin COMP2 (pin 30), other tied voltage reference. voltage reference either internally generated (VREF AVDD/2) externally connected AUX4 (pin 12). comparator output signals passed GPIO logic block (see "GPIO Interrupt Control" section), where they used send interrupt AC-Link pin, wake WM9714L from sleep mode. COMP1/AUX1 (pin corresponds GPIO COMP2/AUX2 (pin30) REGISTER ADDRESS LABEL DEFAULT DESCRIPTION COMP1 Polarity Control Alarm when COMP1 voltage below VREF Alarm when COMP1 voltage above VREF Note: also "GPIO Interrupt Control" COMP2 Polarity Control Alarm when COMP2 voltage below VREF Alarm when COMP2 voltage above VREF Note: also "GPIO Interrupt Control" Battery Alarm Delay Control delay AC-link frames (0.17s) AC-link frames (0.34s) AC-link frames (0.68s) AC-link frames (1.4s) AC-link frames (2.7s) AC-link frames (5.5s) AC-link frames (10.9s)
15:13
COMP2
Table Comparator Control REGISTER ADDRESS Additional Analogue Functions LABEL C1REF DEFAULT DESCRIPTION Comparator Reference Voltage Select AVDD/2 AUX4 (pin Comparator Signal Source AVDD/2 when C1REF=1, else COMP1 powered down COMP1/AUX1 (pin COMP2/AUX2 (pin Reserved Comparator Reference Voltage Select AVDD/2 AUX4 (pin Comparator Signal Source AVDD/2 when C2REF=1, else COMP2 powered down COMP1/AUX1 (pin COMP2/AUX2 (pin Reserved
13:12
C1SRC
C2REF
10:9
C2SRC
Table Comparator Reference Source Control
February 2008
Pre-Production
WM9714L
COMP2 DELAY FUNCTION
COMP2 optional delay function when input signal noisy. When COMP2 triggers delay enabled (i.e. COMP2DEL non-zero), then GPIO does change state immediately, interrupt generated. Instead, WM9714L starts delay timer checks COMP2 again after delay time passed. COMP2 still active, then GPIO interrupt generated (depending state GW14 bit). COMP2 longer active, GPIO set, i.e. register bits COMP2 never triggered.
COMP2 TRIGGERS
C2W?
COMP2 DEL?
non-zero
START TIMER
WAIT time=COMP2DEL SHUT DOWN TIMER
COMP2?
Inactive
[FALSE ALARM]
Active
GI14
Figure COMP2 Delay Flow Chart
February 2008
WM9714L
GPIO INTERRUPT CONTROL
Pre-Production
WM9714L eight GPIO pins that operate defined AC'97 Revision specification. Each GPIO input output, corresponding bits register slot state GPIO output determined sending data through slot outgoing frames (SDATAOUT). Data returned from GPIO input reading register bit, examining slot incoming frames (SDATAIN). GPIO inputs made sticky, programmed generate interrupt, transmitted either through AC-Link through dedicated, level-mode interrupt (GPIO2/IRQ, 45). addition, GPIO pins used interface setting register (see "PCM Codec" section). Setting this disables GPIO functions selected these pins. REGISTER ADDRESS Codec Control LABEL CTRL DEFAULT DESCRIPTION GPIO Configuration Control GPIO pins used GPIOs GPIO pins used interface Note: interface, more these pins (depending master/slave/partial master mode) must output writing register (see Table Toggle GPIO function secondary function enabled GPIO enabled
GPIO Sharing
(GPIO)
Table GPIO Additional Function Control GPIO pins multi-purpose pins that also used other (non-GPIO -PCM) purposes, e.g. S/PDIF output. This controlled register (see Table Note that GPIO6/7/8 each have additional function independent GPIO auxillary functions discussed above. these pins used GPIO then independent function needs disabled using control registers, e.g. GPIO then RESETB function needs disabled (RSTDIS, register 5Ah, Independently GPIO pins, WM9714L also seven virtual GPIOs. These signals from inside WM9714L, which treated they were GPIO input signals. From software perspective, virtual GPIOs same GPIO pins, they cannot outputs, tied actual pin. This allows simple, uniform processing different types signals that generate interrupts (e.g. battery warnings, jack insertion, high-temperature warning, GPIO signals).
February 2008
Pre-Production
WM9714L
Figure GPIO Logic GPIO SLOT TYPE GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Virtual GPIO Virtual GPIO Virtual GPIO Virtual GPIO Virtual GPIO Virtual GPIO [MICDET] [MICSHT] [Thermal Cutout] [ADA] [COMP2] [COMP1] GPIO1 GPIO2 enabled only when used GPIO3 GPIO4 MASK enabled only when used GPIO5 S/PDIF_OUT enabled only when used S/PDIF_OUT GPIO6 MASK Enabled only when used GPIO7 GPIO8 S/PDIF_OUT enabled only when used S/PDIF_OUT Internal microphone bias current detect, generates interrupt above threshold (see MICBIAS Current Detect) Internal shorted microphone detect, generates interrupt above threshold (see MICBIAS Current Detect) Internal thermal cutout signal, indicates when internal temperature reaches approximately 150°C (see "Thermal Sensor") Internal (ADC Data Available) Signal enabled only when AUXADC active Internal COMP2 output (Low Battery Alarm) enabled only when COMP2 Internal COMP1 output (Dead Battery Alarm) enabled only when COMP1
Table GPIO Bits Pins Note: GPIO7 (Pin independent RESETB function. This must disabled using RSTDIS (Register 5Ah, before using GPIO.
February 2008
WM9714L
REGISTER ADDRESS LABEL DEFAULT
Pre-Production properties GPIOs controlled through registers 52h, shown below.
GPIO Configuration Control Output Input (GC9-15 always inputs) GPIO Polarity Type Input (GCn Active Acitve high Input (GCn Active Acitve high
GPIO Sticky Control sticky Sticky GPIO Wake-up Control wake-up interrupts generated GPIO) Wake-up (generate interrupts from GPIO) GPIO Status Read Returns status GPIO Write Writing clears sticky bits
Table GPIO Control following procedure recommended handling interrupts: When controller receives interrupt, check register 54h. each GPIO descending order priority, check `1'. yes, execute corresponding interrupt routine, then write corresponding 54h. continue next lower priority GPIO. After GPIOs have been checked, check interrupt still present yes, repeat procedure. then jump back process that before interrupt. system cannot execute such interrupt routine, preferable switch internal signals directly onto GPIO pins. However, this case interrupt signals cannot made sticky, more GPIO pins tied both WM9714L CPU.
February 2008
Pre-Production REGISTER ADDRESS GPIO pins function select LABEL DEFAULT
WM9714L
GPIO2 (Pin Function Control controlled GPIO logic controlled GPIO logic Note: When GE2=0, GC2=0 output GPIO4 (Pin Function Control controlled GPIO logic controlled GPIO logic Note: When GE4=0, GC4=0 output GC4=1 input MASK GPIO5 (Pin Function Control controlled GPIO logic controlled GPIO logic Note: When GE5=0, GC5=0 output S/PDIF GPIO6 (Pin Function Control controlled GPIO logic controlled GPIO logic Note: When GE6=0, GC6=0 output signal GC6=1 input MASK signal GPIO8 (Pin Function Control controlled GPIO logic controlled GPIO logic Note: When GE8=0, GC8=0 output S/PDIF
Table Using GPIO Pins Non-GPIO Functions
February 2008
WM9714L POWER MANAGEMENT
INTRODUCTION
Pre-Production
WM9714L includes standard power down control register defined AC'97 specification (register 26h). Additionally, also allows more specific control over individual blocks device through register Powerdown registers 3Eh. Each particular circuit block active when both relevant register relevant Powerdown registers `0'. Note that default power-up condition OFF.
AC97 CONTROL REGISTER
REGISTER ADDRESS Powerdown/ Status register LABEL DEFAULT (disabled) (disabled) (disabled) (disabled) DESCRIPTION Output PGAs Disable Control Disabled Enabled Internal Clock Disable Control Disabled Enabled AC-Link Disable Control Disabled Enabled Analogue Disable Control Disabled Enabled Note: This control disables VREF, input PGAs, DACs, ADCs, mixers outputs Input PGAs Mixers Disable Control Disabled Enabled Stereo Disable Control Disabled Enabled Stereo Record Disable Control Disabled Enabled VREF Ready (Read Only) VREF ready VREF ready Analogue Mixers Ready (Read Only) Analogue mixers ready Analogue mixers ready Stereo Ready (Read Only) ready ready Stereo Ready (Read Only) ready ready
(disabled) (disabled) (disabled)
Table Powerdown Status Register (Conforms AC'97 2.2)
February 2008
Pre-Production
WM9714L
REGISTER ADDRESS Powerdown LABEL PADCPD DEFAULT (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) DESCRIPTION AUXADC Disable Control Disabled Enabled 1Meg VMID String Disable Control Disabled Enabled Thermal Shutdown Disable Control Disabled Enabled Voice Disable Control Disabled Enabled AUXDAC Disable Control Disabled Enabled VREF Disable Control Disabled Enabled Disable Control Disabled Enabled Left Disable Control (see Note Disabled Enabled Right Disable Control (see Note Disabled Enabled Left Disable Control Disabled Enabled Right Disable Control Disabled Enabled Left Headphone Mixer Disable Control Disabled Enabled Right Headphone Mixer Disable Control Disabled Enabled Speaker Mixer Disable Control Disabled Enabled Mono Mixer Disable Control Disabled Enabled
EXTENDED POWERDOWN REGISTERS
VMID1M
TSHUT
VXDAC
AUXDAC
VREF
DACL
DACR
ADCL
ADCR
HPLX
HPRX
SPKX
Note: When analogue inputs outputs disabled, they internally connected VREF through large resistor (VREF=AVDD/2 except when VREF VMID1M both OFF). This maintains potential that node helps eliminate pops when pins re-enabled. Table Extended Power Down Register (Additional AC'97 2.2) Note: When disabling PGA, always ensure that muted first.
February 2008
WM9714L
REGISTER ADDRESS Powerdown LABEL DEFAULT (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled) (disabled (disabled) (disabled) (disabled) (disabled) (disabled)
Pre-Production
Microphone Current Detect Disable Control Disabled Enabled Microphone Bias Disable Control (see Note Disabled Enabled MONO Disable Control (see Note Disabled Enabled OUT4 Disable Control (see Note Disabled Enabled OUT3 Disable Control (see Note Disabled Enabled Disable Control (see Note Disabled Enabled Disable Control (see Note Disabled Enabled SPKL Disable Control (see Note Disabled Enabled SPKR Disable Control (see Note Disabled Enabled LINEL Disable Control (see Note Disabled Enabled LINER Disable Control (see Note Disabled Enabled MONOIN Disable Control (see Note Disabled Enabled MICA Disable Control (see Note Disabled Enabled MICB Disable Control (see Note Disabled Enabled Pre-amp Disable Control Disabled Enabled Pre-amp Disable Control Disabled Enabled
MICBIA MONO
OUT4
OUT3
SPKL
SPKR
MOIN
Note: When analogue inputs outputs disabled, they internally connected VREF through large resistor (VREF=AVDD/2 except when VREF VMID1M both OFF). This maintains potential that node helps eliminate pops when pins re-enabled. Table Extended Power Down Register (Additional AC'97 2.2) Note:
February 2008
Pre-Production When disabling PGA, always ensure that muted first.
WM9714L
ADDITIONAL POWER MANAGEMENT
Mixer output inverters: "Mixer output Inverters" section. Inverters disabled default.
SLEEP MODE
Whenever (reg. 26h) set, AC-Link interface disabled, WM9714L sleep mode. There fact very large number different sleep modes, depending other control bits. example, low-power standby mode described below sleep mode. desirable sleep modes whenever possible, this will save power. following functions require clock therefore operate sleep mode: Analogue-to-analogue audio (DACs ADCs unused), e.g. phone call mode GPIO interrupts Battery alarm analogue comparators
WM9714L awake from sleep mode result warm reset AC-Link (according AC'97 specification) signal GPIO configured input, with wake-up enabled "GPIO Interrupt Control" section) virtual GPIO event such battery alarm, etc. (see "GPIO Interrupt Control" section)
POWER STANDBY MODE
bits registers 26h, except VMID1M (register 3Ch, 14), then WM9714L low-power standby mode consumes very little current. resistor string remains connected across AVDD generate VREF. This necessary on-chip analogue comparators used (see "Battery Alarm Battery Measurement" section), helps shorten delay between wake-up playback readiness. VREF required, resistor string disabled setting VMID1M bit, reducing current consumption further.
SAVING POWER SUPPLY VOLTAGES
analogue supplies WM9714L from 1.8V 3.6V. default, analogue circuitry optimized 3.3V. This set-up also good other supply voltages down 1.8V. However, lower voltages, possible save power reducing internal bias currents used analogue circuitry. This controlled shown below. REGISTER ADDRESS LABEL VBIAS DEFAULT DESCRIPTION Analogue Bias Optimization Control Default bias current, optimized 3.3V bias current, optimized 2.5V Lowest bias current, optimized 1.8V
Table Analogue Bias Selection
POWER RESET (POR)
WM9714L internal power reset (PORB) which ensures that reset applied registers until supply threshold been exceeded. circuitry monitors voltage both AVDD DCVDD will release internal reset signal once these supplies both nominally greater than 1.36V. inter
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