9DOXH 36,3& 3&&203/,$173&,72,6$%5,'*( 5HYLVLRQ 0DUFK
|
|
|
Top Searches for this datasheet
'HOLYHULQJ
9DOXH
36,3&
3&&203/,$173&,72,6$%5,'*(
5HYLVLRQ 0DUFK
97&$
9,$7(&+12/2*,(6,1&
&RS\ULJKW1RWLFH
&RS\ULJKW
(6(59('
7HFKQRORJLHV ,QFRUSRUDWHG
3ULQWHG 8QLWHG 6WDWHV
,*+76
SDUW WKLV GRFXPHQW UHSURGXFHG WUDQVPLWWHG WUDQVFULEHG VWRUHG UHWULHYDO V\VWHP WUDQVODWHG LQWR ODQJXDJH IRUP PHDQV HOHFWURQLF PHFKDQLFDO PDJQHWLF RSWLFDO FKHPLFDO PDQXDO RWKHUZLVH ZLWKRXW SULRU ZULWWHQ SHUPLVVLRQ 7HFKQRORJLHV ,QFRUSRUDWHG
97&$ 97&% 6XSHU 6RXWK RQO\ XVHG LGHQWLI\ SURGXFWV 7HFKQRORJLHV
UHJLVWHUHG WUDGHPDUN ,QWHUQDWLRQDO %XVLQHVV 0DFKLQHV &RUS 3HQWLXP% 3HQWLXP3UR% 3HQWLXP,,% 3HQWLXP,,,% &HOHURQ%DQG *7/% UHJLVWHUHG WUDGHPDUNV ,QWHO &RUS :LQGRZV :LQGRZV :LQGRZV 3OXJ 3OD\% UHJLVWHUHG WUDGHPDUNV 0LFURVRIW &RUS 3&,% UHJLVWHUHG WUDGHPDUN 6SHFLDO ,QWHUHVW *URXS WUDGHPDUNV SURSHUWLHV WKHLU UHVSHFWLYH RZQHUV
UHJLVWHUHG WUDGHPDUN 7HFKQRORJLHV ,QFRUSRUDWHG
'LVFODLPHU1RWLFH
OLFHQVH JUDQWHG LPSOLHG RWKHUZLVH XQGHU SDWHQW SDWHQW ULJKWV 7HFKQRORJLHV 7HFKQRORJLHV PDNHV ZDUUDQWLHV LPSOLHG RWKHUZLVH UHJDUG WKLV GRFXPHQW SURGXFWV GHVFULEHG WKLV GRFXPHQW LQIRUPDWLRQ SURYLGHG WKLV GRFXPHQW EHOLHYHG DFFXUDWH UHOLDEOH SXEOLFDWLRQ GDWH WKLV GRFXPHQW +RZHYHU 7HFKQRORJLHV DVVXPHV UHVSRQVLELOLW\ HUURUV WKLV GRFXPHQW )XUWKHUPRUH 7HFKQRORJLHV DVVXPHV UHVSRQVLELOLW\ PLVXVH LQIRUPDWLRQ WKLV GRFXPHQW SDWHQW LQIULQJHPHQWV WKDW DULVH IURP WKLV GRFXPHQW LQIRUPDWLRQ SURGXFW VSHFLILFDWLRQV ZLWKLQ WKLV GRFXPHQW VXEMHFW FKDQJH WLPH ZLWKRXW QRWLFH ZLWKRXW REOLJDWLRQ QRWLI\ SHUVRQ VXFK FKDQJH
2IILFHV
2IILFH
0LVVLRQ &RXUW
7DLSHL 2IILFH )ORRU
)UHPRQW
&KXQJ&KHQJ 5RDG +VLQ7LHQ 7DLSHL 7DLZDQ
2QOLQH6HUYLFHV
+RPH 3DJH 6HUYHU
http://www.via.com.tw http://www.viatech.com ftp.via.com.tw
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
REVISION HISTORY
Document Release 1.23 Date 2/10/98 3/98-12/98 1/15/99 4/15/99 5/17/99 Revision Initial release based 82C596 "Mobile South" Data Sheet revision Misc additions corrections internal review Corrected feature bullets, typos, ROMCS# description, f0Rx8, f4Rx2 Fixed block diagram, pinouts, register descriptions electrical specs Fixed GPIO, PCS/MCCS, DRQ/DACK#, DACK option, Fixed SuperIO RxF0-1,F6; Fixed DRVDEN name, moved PME#, added MCCS# SCIOUT# Fixed F0Rx42,74,76, F1Rx43, F5/6Rx48, Rx44 1.3x created document CD/CE only (info version removed) Updated U5/U8 defs; fixed Rx74[5,7],76[4-3],77[0],PMUIO Rx44[5,3-1] Fixed typo SUSST1# description; Fixed Super-I/O RxF8 table Modified Rx59, F2/3 Rx4142,80-84, Rx4C[0], Rx42[2-1],44[2-1], F5/6 Rx4A-4B, Base Rx12[6] Fixed typo PDIOR#/SDIOR# descriptions Func Rx42[4] Added SCIOUT# GPIO11 (pin U8), fixed typos CHAS description Fixed typos Serial Port register descriptions, changed logo format Changed "OD" types "O"; fixed table port address range Fixed summary tables (superIO superIO FDCbase+4,7; LPTbase+402; COM1/2 index value refs divisor offset Changed silicon version CF/CG same programming pinout Fixed description, parallel port index, index base+7 Fixed typo Func Rx48, changed Mgmt Rx44[3-2] Added internal APIC names; fixed name polarity diagram Corrected Rx41[6],58,74[7],77[4], Rx54[5], F2/3 Rx43, Rx4D[3],54[3-2],55[2], Rx0[8], added APIC regs Fixed feature bullet typos, APIC/GPI/GPO descriptions, Rx76[4],77[4] Fixed Func AC97 summary tables; Ctrl bit-3 changed reserved Fixed direction APICD0-1 pins (changed from Fixed defaults register tables Func Rx40, Added note Rx41[3] Rx45; fixed Rx45[1-0] misc typos Fixed APIC descriptions, removed GPI12/13, descriptions Updated/fixed descriptions MC97IRQ, FDCIRQ/DRQ, DRQ2/DACK2#, SERIRQ, GPI3, GPO8-11, GPO19, GPIOD, LID, VREF (voltage) Func fixed Rx42[2-0], clarified 75[3-1], 76[7-6], removed Rx7D-7C Func fixed Summary table fixed Rx50,58[5-4], 4[0] Removed "high speed baud rate support", Fixed F0Rx74[7], F1Rx50[26-24] Fixed SUSA# description, Changed VREF output fixed elec specs Removed ambient temp, added pwr/current spec table, fixed orientation Corrected VCCH GNDH descriptions; Fixed Function Rx43 Function fixed defaults Rx6, fixed definitions Rx4[7,1], 6[4], 10-23 lsbs, 42[7-6], 45[4], 50[26-24], 54[1], 70[1], 78[1], 54[3-2] Changed 3.3V spec Added power supply current specs Fixed PMIO Rx10[10]; Fixed typos F1Rx45[2] PMIO Rx40, Added SDIN, SDIN2, EXTSMI# suspend power plane Fixed pinout table formatting errors; Removed ATEST/DTEST Fixed STPCLK# errors Rx4C[0] PMIO Rx10[9], 2C[3] Initials
1.24 1.42
6/18/99 6/25/99 6/25/99 7/7/99
1.43 1.45
10/7/99 12/3/99 12/21/99
1.51
1/7/00
1.52
1/17/00
1.53 1.54
2/8/00 2/25/00
5/22/00
8/1/00
12/12/00
1.81 1.82
2/2/01 3/2/01
Revision 1.82 March 2001
Revision History
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
TABLE CONTENTS
REVISION HISTORY.I TABLE CONTENTS. LIST FIGURES.IV LIST TABLES OVERVIEW PINOUTS DIAGRAM. LISTS. DESCRIPTIONS. REGISTERS REGISTER OVERVIEW REGISTER DESCRIPTIONS. Legacy Ports
Keyboard Controller Registers. Controller Registers Interrupt Controller Registers Timer Counter Registers CMOS Registers.
Super-I/O Configuration Index Data Registers Super-I/O Configuration Registers Super-I/O Ports
Floppy Disk Controller Registers. Parallel Port Registers. Serial Port Registers. Serial Port Registers.
SoundBlaster Port Registers.
Registers Mixer Registers Sound Processor Registers
Game Port Registers Configuration Space I/O. Function Registers Bridge.
Configuration Space Header Control. Plug Play Control Distributed Serial Control Miscellaneous General Purpose I/O.
Function Registers Enhanced Controller
Configuration Space Header IDE-Controller-Specific Confiiguration Registers Registers.
Function Registers Controller Ports
Configuration Space Header USB-Specific Configuration Registers. Registers.
Function Registers Controller Ports
Configuration Space Header USB-Specific Configuration Registers. Registers.
Revision 1.82 March 2001
-ii-
Table Contents
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Function Regs Power Management, SMBus HWM.
Configuration Space Header Power Management-Specific Configuration Registers Hardware-Monitor-Specific Configuration Registers System Management Bus-Specific Configuration Registers Power Management I/O-Space Registers System Management I/O-Space Registers. Hardware Monitor Space Registers
Function Registers AC97 Audio Modem Codecs
Configuration Space Header Function Audio Configuration Space Header Function Modem. Function Codec-Specific Configuration Registers Base Registers -Audio/Modem Scatter/Gather DMA. Base Registers Audio Status Registers Base Registers MIDI Game Port. Memory Mapped APIC Registers Silicon). Indexed APIC 32-Bit Registers Silicon)
FUNCTIONAL DESCRIPTIONS POWER MANAGEMENT
Power Management Subsystem Overview Processor States System Suspend States Power Plane Control General Purpose Ports. Power Management Events System Processor Resume Events Legacy Power Management Timers System Primary Secondary Events Peripheral Events
ELECTRICAL SPECIFICATIONS. ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS. POWER CHARACTERISTICS PACKAGE MECHANICAL SPECIFICATIONS
Revision 1.82 March 2001
-iii-
Table Contents
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
LIST FIGURES
FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE SYSTEM CONFIGURATION USING VT82C686A VT82C686A BALL DIAGRAM (TOP VIEW). VT82C686A LIST (NUMERICAL ORDER) VT82C686A LIST (ALPHABETICAL ORDER). STRAP OPTION CIRCUIT. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM MECHANICAL SPECIFICATIONS BALL GRID ARRAY PACKAGE.
LIST TABLES
TABLE TABLE TABLE TABLE TABLE DESCRIPTIONS. SYSTEM REGISTERS. KEYBOARD CONTROLLER COMMAND CODES CMOS REGISTER SUMMARY.
Revision 1.82 March 2001
-iv-
Table Contents
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
VT82C686A PSIPC
SUPER-I/O INTEGRATED PERIPHERAL CONTROLLER PC99 COMPLIANT PCI-TO-ISA BRIDGE WITH INTEGRATED SUPER-I/O (FDC, LPT, COM1/2, IR), INTEGRATED HARDWARE SOUNDBLASTER/DIRECT SOUND AC97 AUDIO, ULTRADMA-33/66 MASTER MODE PCI-EIDE CONTROLLER, CONTROLLER, KEYBOARD CONTROLLER, RTC, DISTRIBUTED DMA, SERIAL IRQ, PLUG PLAY, ACPI, ENHANCED POWER MANAGEMENT, SMBUS, TEMPERATURE, VOLTAGE, FAN-SPEED MONITORING
Inter-operable with other Host-to-PCI Bridges Combine with VT82C598 complete Super-7 (66/75/83/100MHz) system (Apollo MVP3) Combine with VT8501 complete Super-7 system with integrated graphics (Apollo MVP4) Combine with VT82C693 complete Socket-370 Slot-1 system (Apollo Pro133) Combine with VT8601 complete Socket-370 Slot-1 system with integrated Inter-operable with Intel other Host-to-PCI bridges complete PC99 compliant system Bridge Integrated Controller with integrated DMA, timer, interrupt controller Integrated Keyboard Controller with mouse support Integrated DS12885-style Real Time Clock with extended byte CMOS Day/Month Alarm ACPI Integrated Controller with root four function ports Integrated UltraDMA-33/66 master mode EIDE controller with enhanced commands PCI-2.2 compliant with delay transaction remote power management Eight double-word line buffer between level post-write buffer Supports type transfers Distributed support legacy across Serial interrupt docking non-docking applications Fast reset Gate operation Edge trigger level sensitive interrupt Flash EPROM, EPROM combined BIOS support Supports positive subtractive decoding
graphics (Apollo ProMedia)
Revision 1.82 March 2001
Features
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
UltraDMA-33 Master Mode EIDE Controller Dual channel master mode supporting four Enhanced devices Transfer rate 33MB/sec cover mode multi-word mode drives, UltraDMA-33 interface Increased reliability using UltraDMA-66 transfer protocols Thirty-two levels (doublewords) prefetch write buffers Dual engine concurrent dual channel operation master programming interface SFF-8038i rev.1.0 Windows-95 compliant Full scatter gather capability Support ATAPI compliant devices including devices Support native compatibility modes Complete software driver support Integrated Super Controller Supports serial ports, port, parallel port, floppy disk controller functions UARTs Complete Serial Ports
Programmable character lengths (5,6,7,8) Even, odd, stick parity generation detection Programmable baud rate generator Independent transmit/receiver FIFOs Modem Control Plug play with base address options Infrared-IrDA (HPSIR) (Amplitude Shift Keyed) port multiplexed COM2 Multi-mode parallel port Standard mode, support Plug play with base address, options Floppy Disk Controller bytes FIFO Data rates 1Mbps Perpendicular recording driver support FDDs with drive swap support Plug play with base address, options
SoundBlaster Hardware Direct Sound Ready AC97 Digital Audio Controller Dual full-duplex Direct Sound channels between system memory AC97 link master interface with scatter gather bursting capability byte FIFO each direct sound channel Host based sample rate converter mixer Standard v1.0 v2.0 AC97 Codec interface single cascaded AC97 Codec's from multiple vendors Loopback capability re-directing mixed audio streams into 1394 speakers Hardware SoundBlaster Windows real-mode legacy compatibility Plug play with IRQ, DMA, space options SoundBlaster MIDI hardware Hardware assisted synthesis legacy compatibility Direct game ports MIDI port interface Complete software driver support Windows-95/98/2000 Windows-NT Voltage, Temperature, Speed Monitor Controller Five positive voltage (one internal), three temperature (one internal) fan-speed monitoring Programmable control, status, monitor alarm flexible desktop management External thermister internal bandgap temperature sensing Automatic clock throttling with integrated temperature sensing Internal core voltage sensing Flexible external voltage sensing arrangement (any positive supply battery)
Revision 1.82 March 2001
Features
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Universal Serial Controller v.1.1 Intel Universal v.1.1 compatible Eighteen level (doublewords) data FIFO with full scatter gather capability Root four function ports Integrated physical layer transceivers with optional over-current detection status inputs Legacy keyboard PS/2 mouse support System Management Interface Host interface processor communications Slave interface external SMBus masters Sophisticated PC99-Compatible Mobile Power Management Supports both ACPI (Advanced Configuration Power Interface) legacy (APM) power management ACPI v1.0 Compliant v1.2 Compliant clock throttling clock stop control complete ACPI state support clock run, Power Management Enable (PME) control, PCI/CPU clock generator stop control Supports multiple system suspend types: power-on suspends with flexible CPU/PCI reset options,
suspend DRAM, suspend disk (soft-off), with hardware automatic wake-up Multiple suspend power plane controls suspend status indicators idle timer, peripheral timer general purpose timer, plus 24/32-bit ACPI compliant timer Normal, doze, sleep, suspend conserve modes Global local device power control System event monitoring with event classes Primary secondary interrupt differentiation individual channels Dedicated input pins power sleep buttons, external modem ring indicator, notebook open/close system wake-up general purpose input ports output ports Multiple internal external sources flexible power management models programmable chip select microcontroller chip select Enhanced integrated real time clock (RTC) with date alarm, month alarm, century field Thermal alarm either external combination three internal temperature sensing circuits docking support leakage control
Plug Play Controller interrupts steerable interrupt channel Steerable interrupts integrated peripheral controllers: USB, floppy, serial, parallel, audio, soundblaster, MIDI Steerable channels integrated floppy, parallel, soundblaster controllers additional steerable interrupt channel on-board plug play devices Microsoft Windows 98TM, Windows NTTM, Windows 95and plug play BIOS compliant Integrated APIC (Advanced Peripheral Interrupt Controller) Silicon) Built-in NAND-tree scan test capability 0.35um, 3.3V, power CMOS process Single chip 27x27
Revision 1.82 March 2001
Features
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
OVERVIEW
VT82C686A PSIPC (PCI Super-I/O Integrated Peripheral Controller) high integration, high performance, power-efficient, high compatibility device that supports Intel non-Intel based processor bridge functionality make complete Microsoft PC99-compliant PCI/ISA system. addition complete extension functionality, VT82C686A includes standard intelligent peripheral controllers: Master mode enhanced controller with dual channel engine interlaced dual channel commands. Dedicated FIFO coupled with scatter gather master mode operation allows high performance transfers between devices. addition standard mode operation, VT82C686A also supports UltraDMA-33 standard allow reliable data transfer rates 33MB/sec throughput. VT82C686A also supports UltraDMA-66 standard. controller SFF-8038i v1.0 Microsoft Windows-family compliant. Universal Serial controller that v1.1 Universal v1.1 compliant. VT82C686A includes root with four function ports with integrated physical layer transceivers. controller allows plug play isochronous peripherals inserted into system with universal driver support. controller also implements legacy keyboard mouse support that legacy software transparently non-USB-aware operating system environment. Keyboard controller with mouse support. Real Time Clock with byte extended CMOS. addition standard functionality, integrated also includes date alarm, century field, other enhancements compatibility with ACPI standard. Notebook-class power management functionality compliant with ACPI legacy requirements. Multiple sleep states (power-on suspend, suspend-to-DRAM, suspend-to-Disk) supported with hardware automatic wake-up. Additional functionality includes event monitoring, clock throttling stop (Intel processor protocol), clock stop control, modular power, clock leakage control, hardware-based software-based event handling, general purpose I/O, chip select external SMI. Hardware monitoring subsystem managing system motherboard voltage levels, temperatures, speeds Full System Management (SMBus) interface. 16550-compatible serial ports with infrared communications port option second port. Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible sound system. Hardware soundblaster-pro hardware-assisted blocks included Windows real-mode compatibility. Loopback capability also implemented directing mixed audio streams into 1394 speakers high quality digital audio. game ports MIDI port ECP/EPP-capable parallel port Standard floppy disk drive interface Distributed capability support legacy over bus. Serial also supported docking non-docking applications. Plug Play controller that allows complete steerability interrupts internal interrupts channels interrupt channel. additional steerable interrupt channel provided allow plug play reconfigurability onboard peripherals Windows family compliance. Internal APIC (Advanced Programmable Interrupt Controller)
Revision 1.82 March 2001
Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
VT82C686A also enhances functionality standard peripherals. integrated interrupt controller supports both edge level triggered interrupts channel channel. integrated controller supports type addition standard modes. Compliant with PCI-2.2 specification, VT82C686A supports delayed transactions remote power management that slower peripherals block traffic bus. Special circuitry built allow concurrent operation without causing dead lock even PCI-to-PCI bridge environment. chip also includes eight levels (doublewords) line buffers from further enhance overall system performance.
Cache Sideband Signals: Init CPUreset StopClk FERR IGNNE SLP# (Slot-1) Boot Crystal Expansion Cards North Bridge MA/Command Ports Keyboard Mouse Expansion MIDI Game Ports Cards Parallel Port Serial Ports Infrared Comm Port Primary Secondary Floppy Disk Interface AC97 Link Hardware Monitor Inputs GPIO, Power Control, Reset System Memory DIMM Module
VT82C686A
Figure System Configuration Using VT82C686A
Revision 1.82 March 2001
Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
PINOUTS
Diagram
Figure VT82C686A Ball Diagram (Top View)
P0USB P2USB C/BE SMEM IOCH SMEM
PRT# DATA#
ERR# PIRQ
DATA# GATE#
ACK# BUSY SLCT
PIRQ RST#
CHG# SEL#
AUTO PIRQ INIT# SLCT PIRQ OBE#
DACK
DEN1 DEX# DIR# DEN0 P3GND STEP# SLP#
DACK RFSH# IOCS BHE# CHK# IRQ6 SLPB
C/BE FRM# RDY# RDY#
DACK SA15
SDD15
SEL# STOP# SERR# CBE1# CS3# C/BE
DRQ2 BALE SIRQ
INIT
DACK DACK DACK DACK
PREQ# PGNT# CS1#
DACK#
IOR# IOW#
SA14 SA13 SA12 SA11 SA10
SDD14 SDD13 SDD12 SDD11 SDD10
SDD9
SDD8
SDD7
SDD6
XDIR
THRM GPIO SDD10 VREF DATA PME# JAB2 GPIO
SDD5
SDD4
SDD3
SOE# SMI#
SDD7 SDD5 SDD12 LOW# SENS1 ACRS JBB2 CS1# CS3#
SDD2
SDD1
SPKR RST# FERR# RST# CLK# INTR
GPIO SDD9 SDD3 SDD1 ST1# RING# STP# SENS2 SYNC
DACK#
SDD0
IRQ8# SDD6 SDD11 SDD13 SDD0 ALRT# RUN# SENS1 SENS3 JAB1 JBB1 BTCK IOR# IOW# SDD8 SDD4 SDD2 SDD14 SDD15 SMI# BTN# STP# SENS2 SENS4 SDI2
VBAT
Note: Some pins above have alternate functions alternate names. table above contains only name (usually most often used function), lists descriptions contain names.
Revision 1.82 March 2001
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Lists
Figure VT82C686A List (Numerical Order)
Name SMEMR# IOCHRDY USBP0+ USBP2+ KBDT KBRC WRTPRT# WDATA# DS1# CTS2# DCD2# TXD1 DCD1# WRTPRT# ERROR#/HDSL# PIRQA# AD31 AD28 AD26 AD25 SMEMW# USBP0USBP2USBP3+ RDATA# WGATE# DS0# DTR2# RXD2 RTS1# RXD1 ACK# DS1# RDATA# INDEX# PCIRST# PIRQD# AD29 AD27 AD24 ROMCS#/KBCS# IOW# USBCLK USBP1+ MSDT IRQ12 DSKCHG# HDSEL# MTR1# RI2# DSR2# CTS1# DSR1# BUSY MTR1# DSKCHG# PINIT# DIR# AUTOFD#/DRV0 PIRQC# AD30 CBE3# IDSEL IOR# DACK3#/ACIRQ DRQ3 USBP1MSCK IRQ1 DRVDEN1 INDEX# DIR# DRVDEN0 TXD2 DTR1# Name IRRX GPO15 WDATA# TRK00# STROBE# PIRQB# AD23 AD22 AD21 DACK1# IDEIRQB DRQ1 RFSH# KBCK/A20GATE USBP3TRK00# STEP# MTR0# RTS2# RI1# IRTX GPO14 SLCT WGATE# SLCTIN# STEP# PCLK AD20 AD19 AD18 AD17 MCS16# SBHE# IOCS16# IOCHCK# GPI0 IRQ7 GNDU VCCU AD16 CBE2# FRAME# IRDY# TRDY# IRQ6/I4/SLPBTN# IRQ5 IRQ4 IRQ3 DACK2#/I13/O25/OC0# DEVSEL# STOP# SERR# CBE1# BALE DRQ2/I12/O24/SQ/OC1 IRQ9 BCLK AD15 AD14 AD13 Name AD12 AD11 RSTDRV LA23 LA22 LA21 LA20 AD10 AD09 AD08 CBE0# AD07 SA19 SA18 IRQ10 IRQ11 IRQ15 AD06 AD05 AD04 AD03 AD02 IRQ14 DACK0#/IA DRQ0 DACK5#/MI SD08 AD01 AD00 PREQ# PGNT# PDCS1# DRQ5 SD09 DACK6#/UA SD10 DRQ6 PDCS3# PDA0 PDA2 PDA1 PDDACK# SD11 DACK7#/UB SD12 DRQ7 SD13 Name PDRDY PDIOR# PDIOW# PDDRQ PDD15 SD14 SD15 SA17 SA16 SA15 SDD15 PDD00 PDD14 PDD01 PDD13 PDD02 SA14 SDD14 SA13 SDD13 SA12 SDD12 SA11 SDD11 SA10 SDD10 VCCS VCCS VCCH GNDH PDD12 PDD03 PDD11 PDD04 PDD10 SA09 SDD9 SA08 SDD8 SA07 SDD7 SA06 SDD6 XDIR/O12/PCS0# INIT SLP# GPO7 GPO0 SLOWCLK SMBDATA SUSCLK APICD1 THRM PME# FAN1 VREF GPIOA/8/GPOWE# SDD10 JAB2 PDD05 PDD09 PDD06 PDD08 PDD07 SA05 SDD5 SA04 SDD4 SA03 SDD3 MEMR# SOE#/O13/MCCS# SMI# GPIOD/SO#/MCCS# SMBCLK GPI3 WSC# BATLOW#/GPI2 FAN2/GPIOB(9) Name VSENS1 (2.0V) SDD07 SDD05 SDD12 JBB2 SDCS1# SDCS3# SDA0 SDA2 SA02 SDD2 SA01 SDD1 SD05 KBIN4 MEMW# SPKR RSMRST# FERR# CPURST SUSA#/O1/APD0 SUSST1# GPO3 RING# GPI7 PCISTP#/GPO5 VSENS2 (2.5V) GPIOC(10)/CHAS SDD09 SDD03 SYNC SDD01 SDA1 SDDACK# SDRDY SA00 SDD0 SD02 SD04 KBIN3 SD07 KBIN6 RTCX2 PWRGD STPCLK# INTR SUSB# GPO2 SMBALRT#/GPI6 IRQ8#/GPI1 PCKRUN# TSENS1 VSENS3 (5V) SDD06 SDD11 JAB1 SDD13 JBB1 SDD00 BTCK SDIOR# SDIOW# SD00 SD01 SD03 SD06 KBIN5 RTCX1 VBAT A20M# IGNNE# SUSC# EXTSMI# PWRBTN# CPUSTP#/GPO4 TSENS2 VSENS4 (12V) SDD08 SDD04 SDD02 SDI2 SDD14 SDD15 SDDRQ
Revision 1.82 March 2001
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Figure VT82C686A List (Alphabetical Order)
Name A20M# ACK# DS1# AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AUTOFD#/DR0 BALE BATLOW#/GPI2 BCLK BUSY MTR1# CBE0# CBE1# CBE2# CBE3# CPURST CPUSTP#/GPO4 CTS1# CTS2# DACK0#/IDEA DACK1#/IDEB DAK2#/I13/O25 DACK3#/AIRQ DACK5#/MIRQ DACK6#/USBIA DACK7#/USBIB DCD1# DCD2# DEVSEL# DIR# DRQ0 DRQ1 D2/I12/O24/SQ DRQ3 DRQ5 DRQ6 DRQ7 DRVDEN0 DRVDEN1 DS0# DS1# DSKCHG#
Name DSR1# DSR2# DTR1# DTR2# ERROR#/HDSEL# EXTSMI# FAN1 FAN2/GPIOB(9) FERR# FRAME# GNDH GNDU GPIOA(8)/GPOWE# GPIOC(10)/CHAS GPIOD/SO#/MCCS GPO0 SLOWCLK HDSEL# IDSEL IGNNE# INDEX# INIT INTR IOCHCK# GPI0 IOCHRDY IOCS16# IOR# IOW# IRDY# IRQ3 IRQ4 IRQ5 IRQ6/I4/SLPBTN# IRQ7 IRQ8# GPI1 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 IRRX GPO15 IRTX GPO14 KBCK A20GATE KBDT KBRC LA20
Name LA21 LA22 LA23 LID/GPI3/WSC# MCS16# MEMR# MEMW# MSCK IRQ1 MSDT IRQ12 MTR0# MTR1# PCKRUN# PCLK PCIRST# PCISTP#/GPO5 INDEX# TRK00# WRTPRT# RDATA# DSKCHG# PDA0 PDA1 PDA2 PDCS1# PDCS3# PDD00 PDD01 PDD02 PDD03 PDD04 PDD05 PDD06 PDD07 PDD08 PDD09 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDDACK# PDDRQ PDIOR# PDIOW# PDRDY WDATA# PGNT# PINIT# DIR# PIRQA# PIRQB# PIRQC# PIRQD# PREQ# PWRBTN# PWRGD RDATA# RFSH# RI1# RI2# RING# GPI7 ROMCS#/KBCS# RSMRST# RSTDRV RTCX1
Name RTCX2 RTS1# RTS2# RXD1 RXD2 SA00 SDD0 SA01 SDD1 SA02 SDD2 SA03 SDD3 SA04 SDD4 SA05 SDD5 SA06 SDD6 SA07 SDD7 SA08 SDD8 SA09 SDD9 SA10 SDD10 SA11 SDD11 SA12 SDD12 SA13 SDD13 SA14 SDD14 SA15 SDD15 SA16 SA17 SA18 SA19 SBHE# SD00 SD01 SD02 SD03 SD04 KBIN3 SD05 KBIN4 SD06 KBIN5 SD07 KBIN6 SD08 SD09 SD10 SD11 SD12 SD13 SD14 SD15 SDA0 SDA1 SDA2 SDCS1# SDCS3# SDD00 BTCK SDD01 SDD02 SDI2 SDD03 SYNC SDD04 SDD05 SDD06 SDD07 SDD08 SDD09 SDD10 JAB2 SDD11 JAB1 SDD12 JBB2 SDD13 JBB1 SDD14 SDD15 SDDACK# SDDRQ SDIOR# SDIOW# SDRDY SERR# SLCT WGATE# SLCTIN#/STEP#
Name SLP# GPO7 SMBALRT# GPI6 SMBCLK SMBDATA SMEMR# SMEMW# SMI# SOE#/GPO13/MCCS# SPKR STEP# STOP# STPCLK# STROBE# SUSA# APICD0 SUSB# GPO2 SUSC# SUSCLK APICD1 SUSST1# GPO3 THRM PME# TRDY# TRK00# TSENS1 TSENS2 TXD1 TXD2 USBCLK USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ VBAT VCCH VCCS VCCS VCCU VREF VSENS1 (2.0V) VSENS2 (2.2V) VSENS3 (5V) VSENS4 (12V) WDATA# WGATE# WRTPRT# XDIR/GPO12/PCS0#
Revision 1.82 March 2001
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Descriptions
Table Descriptions
Interface
Signal Name AD[31:0] C/BE[3:0]# FRAME# IRDY# TRDY# STOP# DEVSEL# (see list) C19, F17, G20, Signal Description Address/Data Bus. standard address data lines. address driven with FRAME# assertion data driven received following cycles. Command/Byte Enable. command driven with FRAME# assertion. Byte enables corresponding supplied requested data driven following clocks. Frame. Assertion indicates address phase transfer. Negation indicates that more data transfer desired cycle initiator. Initiator Ready. Asserted when initiator ready data transfer. Target Ready. Asserted when target ready data transfer. Stop. Asserted target request master stop current transaction. Device Select. VT82C686A asserts this signal claim transactions through positive subtractive decoding. input, DEVSEL# indicates response VT82C686A-initiated transaction also sampled when decoding whether subtractively decode cycle. Parity. single parity provided over AD[31:0] C/BE[3:0]#. System Error. SERR# pulsed active device that detects system error condition. Upon sampling SERR# active, VT82C686A programmed generate CPU. Initialization Device Select. IDSEL used chip select during configuration read write cycles. Connect this AD18 using resistor. Interrupt Request. These pins typically connected INTA#INTD# pins follows: PIRQA# PIRQB# PIRQC# PIRQD# Slot INTA# INTB# INTC# INTD# Slot INTB# INTC# INTD# INTA# Slot INTC# INTD# INTA# INTB# Slot INTD# INTA# INTB# INTC# Request. This signal goes North Bridge request bus. Grant. This signal driven North Bridge grant access VT82C686A. Clock. PCLK provides timing transactions Bus. Clock Run. This signal indicates whether clock will stopped (high) running (low). VT82C686A drives this signal when clock running (default reset) releases when stops clock. External devices assert this signal request that clock restarted prevent from stopping. Connect this ground using resistor function used. Refer "PCI Mobile Design Guide" "Apollo MVP4 Design Guide" more details. Reset. Active reset signal bus. VT82C686A will assert this during power-up from control register.
SERR#
IDSEL PIRQA-D#
A16, D17, C17,
PREQ# PGNT# PCLK PCKRUN#
PCIRST#
Revision 1.82 March 2001
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Interface
Signal Name CPURST Signal Description Reset. VT82C686A asserts CPURST reset during power-up. Interrupt. INTR driven VT82C686A signal INTR that interrupt request pending needs service. Non-Maskable Interrupt. used force non-maskable interrupt CPU. VT82C686A generates when either SERR# IOCHK# asserted. Initialization. VT82C686A asserts INIT detects shut-down INIT special cycle soft reset initiated register Stop Clock. STPCLK# asserted VT82C686A STPCLK# throttle processor clock. System Management Interrupt. SMI# asserted VT82C686A SMI# response different Power-Management events. FERR# Numerical Coprocessor Error. This signal tied coprocessor error signal CPU. Internally generates interrupt active. Ignore Numeric Error. This connected "ignore error" IGNNE# CPU. Sleep (Rx75[7] Used sleep. Used with slot-1 SLP# GPO7 CPUs only. currently used with socket-7 CPUs. Mask. Connect mask input control address bitA20M# generation. Logical combination A20GATE input (from internal external keyboard controller) Port bit-1 (Fast_A20). Note: Connect each above signals 4.7K pullup resistors VCC3.
Advanced Programmable Interrupt Controller (APIC)
Signal Name WSC# (CG) GPI3 APICREQ# Signal Description Write Snoop Complete. Asserted north bridge indicate that snoop activity initiated last PCI-to-DRAM write complete that safe perform APIC interrupt. This WSC# internal APIC enabled APICREQ# external APIC enabled. APIC Data internal APIC enabled. APIC Data internal APIC enabled. Output. external APIC enabled.
APICD0 (CG) GPO1 SUSA# APICD1 (CG) SUSCLK SCIOUT# (CG) GPI11 GPO11 GPIOD programming information, refer Function Rx74,77, Function Rx54[3-2], Memory Mapped Indexed APIC registers. particular, Rx74[7] "External APIC Enable" Rx77[4] "Internal APIC Enable". external APIC connection, also Rx5C[2]. Note also that clock source used chip clock internal APIC (14.31818 MHz), must externally connected APIC clock input.
Revision 1.82 March 2001
-10-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Universal Serial Interface
Signal Name USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2USBP3+ USBP3USBCLK USBOC0# GPO25 DACK2# FDCIRQ USBOC1# GPO24 DRQ2 FDCDRQ SERIRQ Signal Description Port Data Port Data Port Data Port Data Port Data Port Data Port Data Port Data Clock. 48MHz clock input interface Port Over Current Detect. Port disabled low. USBOC0# Rx76[7] Rx76[6] Port Over Current Detect. Port disabled this input low. Direct inputs provided overcurrent protection ports which used alternate functions these pins required. overcurrent protection desired four ports desired alternate functions these pins), external buffer used drive state USBOC[3-0]# onto SD[3-0] during refresh cycles (i.e., while RFSH# low, that RFSH# used buffer enable). USCOC1# Rx76[7] Rx76[6] Port Over Current Detect Port Over Current Detect Port Over Current Detect Port Over Current Detect Interrupt Request Output internal block. Interrupt Request Output internal block.
USBOC0# (SD2 RFSH#) USBOC1# (SD1 RFSH#) USBOC2# (SD0 RFSH#) USBOC3# (SD3 RFSH#) USBIRQA DACK6# USBIRQB DACK7#
(W2) (Y2) (Y1) (Y3)
System Management (SMB) Interface (I2C Bus)
Signal Name SMBCLK SMBDATA SMBALRT# GPI6 Signal Description Clock. Data. Alert. (System Management space Rx08[3] When chip enabled allow assertion generates interrupt power management resume event. same used General Purpose Input whose value reflected Rx48[6] function space
Revision 1.82 March 2001
-11-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
UltraDMA-33 Enhanced Interface
Signal Name PDRDY PDDMARDY PDSTROBE Signal Description EIDE Mode: Primary Channel Ready. Device ready indicator UltraDMA Mode: Primary Device Ready. Output flow control. device assert DDMARDY pause output transfers Primary Device Strobe. Input data strobe (both edges). device stop DSTROBE pause input data transfers EIDE Mode: Secondary Channel Ready. Device ready indicator UltraDMA Mode: Secondary Device Ready. Output flow control. device assert DDMARDY pause output transfers Secondary Device Strobe. Input data strobe (both edges). device stop DSTROBE pause input data transfers EIDE Mode: Primary Device Read. Device read strobe UltraDMA Mode: Primary Host Ready. Primary channel input flow control. host assert HDMARDY pause input transfers Primary Host Strobe. Output data strobe (both edges). host stop HSTROBE pause output data transfers EIDE Mode: Secondary Device Read. Device read strobe UltraDMA Mode: Secondary Host Ready. Input flow control. host assert HDMARDY pause input transfers Host Strobe Output strobe (both edges). host stop HSTROBE pause output data transfers EIDE Mode: Primary Device Write. Device write strobe UltraDMA Mode: Primary Stop. Stop transfer: Asserted host prior initiation UltraDMA burst; negated host before data transferred UltraDMA burst. Assertion STOP host during after data transfer UltraDMA mode signals termination burst. EIDE Mode: Secondary Device Write. Device write strobe UltraDMA Mode: Secondary Stop. Stop transfer: Asserted host prior initiation UltraDMA burst; negated host before data transferred UltraDMA burst. Assertion STOP host during after data transfer UltraDMA mode signals termination burst. Primary Device Request. Primary channel request Secondary Device Request. Secondary channel request Primary Device Acknowledge. Primary channel acknowledge Secondary Device Acknowledge. Secondary channel acknowledge
SDRDY SDDMARDY SDSTROBE
PDIOR# PHDMARDY PHSTROBE
SDIOR# SHDMARDY SHSTROBE
PDIOW# PSTOP
SDIOW# SSTOP
PDDRQ SDDRQ PDDACK# SDDACK#
Revision 1.82 March 2001
-12-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
UltraDMA-33 Enhanced Interface (continued)
Signal Name PDCS1# PDCS3# SDCS1# SDCS3# PDA[2-0] SDA[2-0] PDD[15-0] M18, M19, U20, V18, N20, P17, P19, R16, R18, R20, T17, T19, T20, T18, T16, R19, R17, P20, P18, R1-R5, T1-T4, U1U3, Signal Description Primary Master Chip Select. This signal corresponds CS1FX# primary connector. Primary Slave Chip Select. This signal corresponds CS3FX# primary connector. Secondary Master Chip Select. This signal corresponds CS17X# secondary connector. Secondary Slave Chip Select. This signal corresponds CS37X# secondary connector. Primary Disk Address. PDA[2:0] used indicate which byte either command block control block being accessed. Secondary Disk Address. SDA[2:0] used indicate which byte either command block control block being accessed. Primary Disk Data
SDD[15-0] SA[15-0]
SDD[15] MSI, SDD[14] MSO, SDD[13] JBB1, SDD[12] JBB2, SDD[11] JAB1, SDD[10] JAB2, SDD[9] GPO23, SDD[8] GPO22, SDD[7] GPI23, SDD[6] GPI22, SDD[5] ACRST, SDD[4] SDOUT, SDD[3] SYNC, SDD[2] SDIN2, SDD[1] SDIN, SDD[0] BITCLK IDEIRQA DACK0# IDEIRQB DACK1#
Y19, Y18, W17, U16, W16, T15, V15, Y15, U14, W15, U15, Y16, V16, Y17, V17,
Secondary Disk Data muxed with Address (Audio Enabled) Address only (Audio Disabled Dedicated Secondary Data) Note: Audio enabled strapping SPKR high with 4.7K ohms disabled strapping SPKR with 4.7K ohms. Secondary Disk Data (SPKR strap AC-Link/Game Ports (SPKR strap Secondary Disk Data Midi Serial Secondary Disk Data Midi Serial Secondary Disk Data Game Port Joystick Button Secondary Disk Data Game Port Joystick Button Secondary Disk Data Game Port Joystick Button Secondary Disk Data Game Port Joystick Button Secondary Disk Data Game Port Joystick X-axis Secondary Disk Data Game Port Joystick Y-axis Secondary Disk Data Game Port Joystick X-axis Secondary Disk Data Game Port Joystick Y-axis Secondary Disk Data AC97 Reset Secondary Disk Data AC97 Serial Data Secondary Disk Data AC97 Sync Secondary Disk Data AC97 Serial Data Secondary Disk Data AC97 Serial Data Secondary Disk Data AC97 Clock Interrupt Request Output internal block. Interrupt Request Output internal block.
Revision 1.82 March 2001
-13-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
MIDI Interface
Signal Name SDD[15] SDD[14] Signal Description MIDI Serial MIDI Serial Secondary Disk Data (SPKR strap Secondary Disk Data (SPKR strap
AC97 Audio Modem Interface
Signal Name ACRST SDD[5] SDOUT SDD[4] SYNC SDD[3] SDIN2 SDD[2] SDIN SDD[1] BITCLK SDD[0] AC97IRQ DACK3# MC97IRQ DACK5# SERIRQ GPO19 Signal Description Secondary Disk Data (SPKR strap AC97 Reset AC97 Serial Data Secondary Disk Data (SPKR strap Secondary Disk Data (SPKR strap AC97 Sync AC97 Serial Data Secondary Disk Data (SPKR strap Secondary Disk Data (SPKR strap AC97 Serial Data Secondary Disk Data (SPKR strap AC97 Clock AC97 Interrupt Request. Output internal block. MC97 Interrupt Request. Output internal block. Rx77[7] Rx77[3] Rx74[6]
Game Port Interface
Signal Name JAB1 SDD[11] JAB2 SDD[10] JBB1 SDD[13] JBB2 SDD[12] SDD[9] GPO23 SDD[8] GPO22 SDD[7] GPI23 SDD[6] GPI22 Function Rx77[6] Signal Description Joystick Button Joystick Button Joystick Button Joystick Button Joystick X-axis Joystick Y-axis Joystick X-axis Joystick Y-axis Secondary Disk Data (SPKR strap Secondary Disk Data (SPKR strap Secondary Disk Data (SPKR strap Secondary Disk Data (SPKR strap Secondary Disk Data (SPKR strap Secondary Disk Data (SPKR strap Secondary Disk Data (SPKR strap Secondary Disk Data (SPKR strap
Revision 1.82 March 2001
-14-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Floppy Disk Interface
Signal Name DRVDEN0 DRVDEN1 MTR0# MTR1# DS0# DS1# DIR# STEP# INDEX# HDSEL# TRK00# RDATA# WDATA# WGATE# DSKCHG# WRTPRT# FDCIRQ DACK2# USBOC0# GPO25 FDCDRQ DRQ2 USBOC1# GPO24 SERIRQ Signal Description Drive Density Select Drive Density Select Motor Control Select motor drive Motor Control Select motor drive Drive Select Select drive Drive Select Select drive Direction. Direction head movement inward motion, outward motion) Step. pulse each track-to-track movement head. Index. Sense detect that head positioned over beginning track Head Select. Selects side operations side side Track Sense detect that head positioned over track Read Data. serial stream from drive read operatrions. Write Data. Encoded data drive write operations. Write Gate. Signal drive enable current flow write head. Disk Change. Sense that drive door open diskette been changed since last drive selection. Write Protect. Sense detection that diskette write protected (causes write commands ignored) Interrupt Request. Rx75[2] Request. Rx75[3]
Revision 1.82 March 2001
-15-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Parallel Port Interface
Signal Name PINIT# DIR# STROBE# AUTOFD# DRVEN0 SLCTIN# STEP# SLCT WGATE# ACK# DS1# ERROR# HDSEL# Signal Description Initialize. Initialize printer. Output standard mode, ECP/EPP mode. Strobe. Output used strobe data into printer. ECP/EPP mode. Auto Feed. Output used cause printer automatically feed line after each line printed. ECP/EPP mode. Select Output used select printer. ECP/EPP mode. Select. Status output from printer. High indicates that powered Acknowledge. Status output from printer. indicates that received data ready accept data Error. Status output from printer. indicates error condition printer. Busy. Status output from printer. High indicates ready accept data. Paper End. Status output from printer. High indicates that paper. Parallel Port Data.
BUSY MTR1# WDATA# A13, E14, D14, C14, DSKCHG#, B14, RDATA#, A14, WRTPRT#, D15, TRK00#, INDEX# shown alternate functions above, mobile applications parallel port pins chip version optionally selected function floppy disk interface attachment external floppy drive using parallel port connector (see Super Configuration Index F6[5]).
Revision 1.82 March 2001
-16-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Serial Ports Infrared Interface
Signal Name TXD1 TXD2 IRTX GPO14 RXD1 RXD2 IRRX GPO15 RTS1# Signal Description Transmit Data Serial port transmit data out. Transmit Data Serial port transmit data out. Infrared Transmit. transmit data (Rx76[5] from serial port General Purpose Output Rx76[5] Receive Data Serial port receive data Receive Data Serial port receive data Infrared Receive. receive data (Rx76[5] serial port General Purpose Output Rx76[5] Request Send Indicator that serial output port ready transmit data. Typically used hardware handshake with CTS1# level flow control. Designed direct input external RS-232C driver. Request Send Indicator that serial output port ready transmit data. Typically used hardware handshake with CTS2# level flow control. Designed direct input external RS-232C driver. Clear Send Indicator serial port that external communications device ready receive data. Typically used hardware handshake with RTS1# level flow control. Designed input from external RS-232C receiver. Clear Send Indicator serial port that external communications device ready receive data. Typically used hardware handshake with RTS2# level flow control. Designed input from external RS-232C receiver. Data Terminal Ready Serial port indicator that port powered, initialized, ready. Typically used hardware handshake with DSR1# overall readiness communicate. Designed direct input external RS-232C driver. Data Terminal Ready Serial port indicator that port powered, initialized, ready. Typically used hardware handshake with DSR2# overall readiness communicate. Designed direct input external RS-232C driver. Data Ready Indicator serial port that external serial communications device powered, initialized, ready. Typically used hardware handshake with DTR1# overall readiness communicate. Designed direct input from external RS-232C receiver. Data Ready Indicator serial port that external serial communications device powered, initialized, ready. Typically used hardware handshake with DTR2# overall readiness communicate. Designed direct input from external RS-232C receiver. Data Carrier Detect Indicator serial port that external modem detecting carrier signal (i.e., communications channel currently open). direct connect environments, this input will typically driven DTR1# part DTR/DSR handshake. Designed direct input from external RS-232C receiver. Data Carrier Detect Indicator serial port that external modem detecting carrier signal (i.e., communications channel currently open). direct connect environments, this input will typically driven DTR2# part DTR/DSR handshake. Designed direct input from external RS-232C receiver. Ring Indicator Indicator serial port that external modem detecting ring condition. Used software initiate operations answer open communications channel. Designed direct input from external RS-232C receiver (whose input typically connected direct connect environments). Ring Indicator Indicator serial port that external modem detecting ring condition. Used software initiate operations answer open communications channel. Designed direct input from external RS-232C receiver (whose input typically connected direct connect environments).
RTS2##
CTS1#
CTS2#
DTR1#
DTR2#
DSR1#
DSR2#
DCD1#
DCD2#
RI1#
RI2#
Revision 1.82 March 2001
-17-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Interface
Signal Name SA[19:16], SA[15-0] SDD[15-0] Signal Description System Address Bus. SA[19-16] connected SA[19-16] directly. SA[19-17] also connected LA[19-17] bus. audio interface disabled (SPKR strapped low), SA[15-0] connected directly address pins SA[15-0] (the audio interface pins used secondary data bus). audio interface enabled (SPKR strapped high), SA[15-0] multiplexed with Secondary Data Bus. this case, SA[15-0] connected both SDD[15-0] SA[15-0]. However, address loading concern, 74F245 transceivers used externally drive address pins SA[15-0]. this case, these pins would connect directly secondary data transceiver pins address would connect transceiver pins. SOE# would used control transceiver output enables MASTER# signal would drive transceiver direction controls. System "Latched" Address Bus: LA[23:20] address lines bi-directional. These address lines allow accesses physical memory 16Mbytes. LA[19-17] connected SA[19-17] (see notes above). System Data. SD[15:0] provide data path devices residing bus. X-Bus data signals XD[7:0] derived needed from SD[7:0] using external 74F245-type transceiver (see XDIR description transceiver connection details). SD7:4 strap options keyboard inputs (see Function Rx5A) System Byte High Enable. SBHE# indicates, when asserted, that byte being transferred upper byte (SD[15:8]) data bus. SBHE# negated during refresh cycles. Read. IOR# command slave device that slave drive data data bus. Write. IOW# command slave device that slave latch data from data bus. Memory Read. MEMR# command memory slave that drive data onto data bus. Memory Write. MEMW# command memory slave that latch data from data bus. Standard Memory Read. SMEMR# command memory slave, under 1MB, which indicates that drive data onto data Standard Memory Write. SMEMW# command memory slave, under 1MB, which indicates that latch data from data bus. Address Latch Enable. BALE active high signal asserted VT82C686A indicate that address (SA[19:0], LA[23:17] SBHE# signal) valid 16-Bit Chip Select. This signal driven devices indicate that they support 16-bit cycles. Memory Chip Select slaves that 16-bit memory devices drive this line indicate they support 16-bit memory cycles. Channel Check (Rx74[0] When this signal asserted, indicates that parity uncorrectable error occurred memory device Bus. same optionally used General Purpose Input Channel Ready (Rx74[0] This signal normally high. Devices assert IOCHRDY indicate that additional time (wait states) required complete cycle. Address Enable. asserted during cycles prevent slaves from misinterpreting cycles valid cycles.
LA[23:20]
SD[15:0]
SBHE#
IOR# IOW# MEMR# MEMW# SMEMR# SMEMW# BALE
IOCS16# MCS16# IOCHCK# GPI0 IOCHRDY
Revision 1.82 March 2001
-18-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Interface (continued)
Signal Name RFSH# IRQ1 MSCK IRQ3 IRQ4 IRQ5 IRQ6 GPI4 SLPBTN# IRQ7 IRQ8# GPI1 IRQ9 IRQ10 IRQ11 IRQ12 MSDT IRQ14 IRQ15 DRQ7 GPI21 (CF/CG), DRQ6 GPI20, DRQ5 GPI19, DRQ3 GPI18, DRQ2 FDCDRQ SERIRQ GPO24 USBOC1# DRQ1 GPI17, DRQ0 GPI16 DACK7# USBIRQB GPO21, DACK6# USBIRQA GPO20, DACK5# MC97IRQ GPO19 SERIRQ, DACK3# AC97IRQ GPO18, DACK2# USBOC0# GPO25 FDCIRQ DACK1# IDEIRQB GPO17, DACK0# IDEIRQA GPO16 SPKR strap I/I/I I/I/I /O/I O/O/O O/O/O O/O/O O/O/O O/I/O O/O/O O/O/O Signal Description Refresh. Indicates when refresh cycle progress. Also driven 16-bit masters indicate refresh cycle. Interrupt Request (Rx5A[1] Interrupt Request Interrupt Request Interrupt Request Interrupt Request Interrupt Request Interrupt Request from disabled (Rx5A[2] Interrupt Request Interrupt Request Interrupt Request Interrupt Request (Rx5A[1] Interrupt Request Interrupt Request Request. Used request services from internal controller.
DRQ2: Rx68[3] Rx75[3] Rx75[1] also Function Rx77[7]
Acknowledge. Used internal controller indicate that request service been granted. DACK5#: Rx77[7]
DACK2#: Rx68[3] Rx75[3] Rx75[2] also Function Rx77[7], Rx77[3], Rx58
SOE# (default function) GPO13 MCCS# (CF/CG)
Terminal Count. Terminal count indicator asserted slaves. Speaker Drive. Output internal timer/counter Also functions strap input sampled reset determine function Audio Game interface pins: 0=Disable Audio Game interface (pins used Secondary Data SDD[15-0]; SA[15-0] pins used only), 1=Enable Audio Game interface (pins used Audio/Game functions; SDD[15-0] multiplexed with SA[15-0] with SOE# MASTER# control.). Address (SA) Output Enable. Asserted when address (SA) valid (deasserted when valid) when multiplexed pins 15-0 (i.e., when SPKR strapped enable audio interface pins). SOE# tied directly output enable 74F245 transceivers that buffer Secondary data ISA-address (see pins more information).
Revision 1.82 March 2001
-19-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Interface
Signal Name XDIR PCS0# GPO12 Signal Description X-Bus Data Direction. (Rx76[1]=0) Asserted read cycles memory read cycles programmed BIOS address space. XDIR tied directly direction control 74F245 transceiver that buffers X-Bus data ISA-Bus data. transceiver output enable grounded. SD0-7 connect side transceiver XD0-7 connect side. XDIR high indicates that SD0-7 drives XD0-7.
Serial
Signal Name SERIRQ DRQ2 GPO24 FDCDRQ USBOC1# SERIRQ DACK5# GPO19 MC97IRQ Signal Description Serial (Rx68[3] Rx74[6] Rx75[3]
Serial (Rx68[3] Rx74[6]
Revision 1.82 March 2001
-20-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Internal Keyboard Controller
Signal Name MSCK IRQ1 Signal Description MultiFunction (Internal mouse controller enabled Rx5A[1]) Rx5A[1]=1 Mouse Clock. From internal mouse controller. Rx5A[1]=0 Interrupt Request Interrupt input MultiFunction (Internal mouse controller enabled Rx5A[1]) Rx5A[1]=1 Mouse Data. From internal mouse controller. Rx5A[1]=0 Interrupt Request Interrupt input MultiFunction (Internal keyboard controller enabled Rx5A[0]) Rx5A[0]=1 Keyboard Clock. From internal keyboard controller Rx5A[0]=0 Gate A20. Input from external keyboard controller. MultiFunction (Internal keyboard controller enabled Rx5A[0]) Rx5A[0]=1 Keyboard Data. From internal keyboard controller. Rx5A[0]=0 Keyboard Reset. From external keyboard controller (KBC) CPURST# generation Keyboard Chip Select (Rx5A[0]=0). external keyboard controller chip. Power-Up Configuration Strap (Sampled Reset): 4.7K Socket-7, 4.7K VCC3 Socket-370 Slot-1 Keyboard Inputs 6-3. Sampled reset SD[7-4] latched into Rx5A[7-4].
MSDT IRQ12
KBCK A20GATE
KBDT KBRC
KBCS# ROMCS# strap
O/O/I
KBIN[6-3] SD[7-4]
Chip Selects
Signal Name ROMCS# KBCS# strap O/O/I Signal Description Chip Select (Rx5A[0]=1). Chip Select BIOS ROM. Power-Up Configuration Strap (Sampled Reset): 4.7K Socket-7, 4.7K VCC3 Socket-370 Slot-1 Programmable Chip Select (Rx76[1] Rx76[4] (CD/CE) Rx8B[0] (CF/CG)). Asserted during cycles programmable read write port ranges. Addressed devices drive data pins (XDIR disabled X-Bus implemented). also Rx59[3] Rx77[2]. Microcontroller Chip Select (Rx74[5] Rx74[7] Rx76[3] Rx76[4] Asserted during read write accesses ports 66h. Microcontroller Chip Select (Rx76[3] Rx76[4] Rx77[0] Asserted during read write accesses ports 66h.
PCS0# GPO12 XDIR
MCCS# GPIOD GPIO11 (CD/CE) MCCS# GPO13 SOE# (CF/CG)
Revision 1.82 March 2001
-21-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
General Purpose Inputs
Signal Name GPI0 IOCHCK# GPI1 IRQ8# GPI2 BATLOW# GPI3 WSC# APICREQ# GPI4 IRQ6 SLPBTN# GPI5 THRM PME# GPI6 SMBALRT# GPI7 RING# GPI8 GPO8 GPIOA GPOWE# GPI9 GPO9 GPIOB FAN2 GPI10 GPO10 GPIOC CHAS GPI11 GPO11 GPIOD SCIOUT# GPI16 DRQ0 (CF/CG) GPI17 DRQ1 (CF/CG) GPI18 DRQ3 (CF/CG) GPI19 DRQ5 (CF/CG) GPI20 DRQ6 (CF/CG) GPI21 DRQ7 (CF/CG) GPI22 SDD6 (CF/CG) GPI23 SDD7 (CF/CG) GPI[23-22] (SD[7-6] RFSH# (CF) GPI[23-16] (SD[7-0] RFSH#) (CG) also Function Rx77[7-6] Signal Description General Purpose Input (Rx74[0] General Purpose Input (Rx5A[2] General Purpose Input General Purpose Input (see Rx74[7] Rx77[3]) General Purpose Input General Purpose Input (Read state Rx48[5]) General Purpose Input General Purpose Input General Purpose Input (Rx74[2] General Purpose Input (Rx74[3] General Purpose Input (Rx74[4] General Purpose Input (Rx74[5] General Purpose Input (Rx77[7] Read 44[2] General Purpose Input (Rx77[7] Read 44[3] General Purpose Input (Rx77[7] General Purpose Input (Rx77[7] General Purpose Input (Rx77[7] General Purpose Input (Rx77[7] General Purpose Input (Rx77[6] audio ena, game disa) General Purpose Input (Rx77[6] audio ena, game disa) General Purpose Inputs 16-23 (enabled RFSH# active) Rx77[6] (CF) Rx77[7] (CG), that
Revision 1.82 March 2001
-22-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
General Purpose Outputs
Signal Name GPO0 SLOWCLK GPO1 SUSA# APICACK# GPO2 SUSB# APICCS# GPO3 SUSST1# GPO4 CPUSTP# GPO5 PCISTP# GPO7 SLP# (OD) GPO8 GPI8 /GPIOA GPOWE# GPO9 GPI9 GPIOB FAN2 GPO10 GPI10 GPIOC CHAS GPO11 GPI11 GPIOD SCIOUT# Signal Description General Purpose Output (Function Rx54[1-0] 00). Output value determined Rx4C[0] General Purpose Output (Rx74[7] Function Rx54[2] General Purpose Output (Rx74[7] Function Rx54[3] General Purpose Output (Function Rx54[4] General Purpose Output (Rx75[4] General Purpose Output (Rx75[5] General Purpose Output (Rx75[7] General Purpose Output (Rx74[2] Rx76[0] General Purpose Output (Rx74[3] General Purpose Output (Rx74[4] Rx76[2] General Purpose Output (CG: Rx74[5] Rx76[3] (CF: Rx74[5] 74[7]=0, 76[4] General Purpose Output (Rx76[1] Rx76[4] General Purpose Output (Rx77[0] also Rx76[4-3] General Purpose Output (Rx76[5] General Purpose Output (Rx76[5] General Purpose Output (Rx77[7] Rx77[3] General Purpose Output (Rx77[7] Rx77[3] General Purpose Output (Rx77[7] Rx77[3] General Purpose Output (Rx77[7] Rx77[3] Rx74[6]
GPO12 XDIR PCS0# GPO13 SOE# MCCS#(CF/CG) GPO14 IRTX GPO15 IRRX GPO16 DACK0# (CF/CG) GPO17 DACK1# (CF/CG) GPO18 DACK3# (CF/CG) GPO19 DACK5# (CF/CG) SERIRQ MC97IRQ General Purpose Output (Rx77[7] Rx77[3] GPO20 DACK6# (CF/CG) General Purpose Output (Rx77[7] Rx77[3] DACK7# (CF/CG) GPO21 General Purpose Output (Rx77[6] audio enabled, game disabled) GPO22 SDD8 (CF/CG) General Purpose Output (Rx77[6] audio enabled, game disabled) GPO23 SDD9 (CF/CG) General Purpose Output (Rx75[3] Rx75[1]=1 Rx68[3]=0) GPO24 DRQ2 FDCDRQ USBOC1# SERIRQ General Purpose Output (Rx75[3] Rx75[2]=1 Rx68[3]=0) GPO25 DACK2# FDCIRQ USBOC0# General Purpose Output 23-16 (Rx74[7]=0) latched GPOWE# rising GPO[23-16] (latched from SD[7-0]) General Purpose Output Write Enable (Rx74[2] Rx76[0] GPOWE# GPIOA GPI8 GPO8 Default functions underlined table above (with default level following parentheses) also Function Rx77[7-6]
General Purpose I/Os
Signal Name GPIOA GPI8 GPO8 GPOWE# GPIOB GPI9 GPO9 FAN2 GPIOC GPI10 GPO10 CHAS GPIOD GPI11 GPO11 SCIOUT# MCCS# (CD/CE) Signal Description General Purpose (Rx76[0] GPOWE# Rx76[0] also Rx74[2] General Purpose also Rx74[3] General Purpose (Rx76[2] also Rx74[4] General Purpose (Rx76[3] also Rx74[5]
Revision 1.82 March 2001
-23-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Hardware Monitoring
Signal Name VSENS1 VSENS2 VSENS3 VSENS4 VREF TSENS1 TSENS2 FAN1 FAN2 GPIOB GPIO9 CHAS GPIOC GPIO10 Signal Description Voltage Sense 2.0V. Monitor core voltage. Voltage Sense 2.5V. Monitor North Bridge core voltage. Voltage Sense Voltage Sense 12V. Connect +12V through resistive voltage divider insure input (see MVP4 Design Guide details). Voltage Reference Thermal Sensing (2.48V ±5%) Temperature Sense Temperature Sense Speed Monitor (3.3V only) Speed Monitor Chassis Intrusion Detect (Func Rx76[2] Used system security purposes.
Revision 1.82 March 2001
-24-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Power Management
Signal Name THRM GPI5 PME# PWRBTN# Signal Description Thermal Alarm Monitor (Rx74[1] Power Button. Used Power Management subsystem monitor external system on/off button switch. VT82C686A performs 200us debounce this input Function Rx40[5] (3.3V only) Sleep Button. Used Power Management subsystem monitor external system sleep button switch. (Function Rx40[6]=1) (10K used) Resume Reset. Resets internal logic connected VCCS power plane also resets portions internal logic. External System Management Interrupt. When enabled allow falling edge this input causes SMI# generated enter mode. (10K VCCS used) (3.3V only) Power Management Event. (Rx74[1]=0) VCCS used) Alert (System Management space Rx08[3] When chip enabled allow assertion generates power management event. (10K VCCS used) Notebook Computer Display Open Closed Monitor. Used Power Management subsystem monitor opening closing display notebook computers. used detect either low-to-high and/or high-to-low transitions generate SMI#. VT82C686A performs usec debounce this input Function Rx40[5] (10K VCCS used) Ring Indicator. connected external modem circuitry allow system re-activated received phone call. (10K VCCS used) Battery Indicator. (10K VCCS used) (3.3V only) Clock Stop (Rx75[4] Signals system clock generator disable clock outputs. connected used. also Rx2C[3]. Clock Stop (Rx75[5] Signals system clock generator disable clock outputs. connected used. Suspend Plane Control (Rx74[7]=0, Rx77[4]=0, Rx54[2]=0). Asserted during power management POS, STR, suspend states. Used control primary power plane. (10K VCCS used) Suspend Plane Control (Rx74[7]=0 Rx54[3]=0). Asserted during power management suspend states. Used control secondary power plane. (10K VCCS used) Suspend Plane Control. Asserted during power management suspend state. Used control tertiary power plane. Also connected power-on circuitry. Suspend Status (Function Rx54[4] GPO3). Typically connected North Bridge provide information host clock status. Asserted when system stop host clock, such Stop Clock during POS, STR, suspend states. Connect VCCS. Suspend Clock. 32.768 output clock North Bridge (e.g., Apollo MVP3 MVP4) DRAM refresh purposes. Stopped during Suspend-to-Disk Soft-Off modes. Connect VCCS.
SLPBTN# IRQ6 GPI4
I/I/
RSMRST# EXTSMI#
PME# GPI5 THRM SMBALRT# GPI6
GPI3 WSC# (CG) APICREQ# (CG)
RING# GPI7
BATLOW# GPI2 CPUSTP# GPO4
PCISTP# GPO5 SUSA# GPO1 APICD0 (CG)
SUSB# GPO2
SUSC#
SUSST1# GPO3
SUSCLK APICD1 (CG)
Revision 1.82 March 2001
-25-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Resets Clocks
Signal Name PWRGD PCIRST# RSTDRV BCLK RTCX1 RTCX2 SLOWCLK GPO0 Signal Description Power Good. Connected PWRGOOD signal Power Supply. Reset. Active reset signal bus. VT82C686A will assert this during power-up from control register. Reset Drive. Reset signal bus. Connect through inverter chipset north bridge RESET# input RESET#. Clock. clock. Oscillator. 14.31818 clock signal used internal Timer. Crystal Input: 32.768 crystal oscillator input. This input used internal power-well power management logic. Crystal Output: 32.768 crystal output Slow Clock. .Frequency selectable function Rx54[1-0] nonzero (set 11).
Power Ground
Signal Name F10, F12-F14, H15, J15, K15, M15, N15, R7-R8, R11, F11, F15, G15, J9-J12, K9K12, L9-L12, L15, M9-M12, P15, R9-R10 Signal Description Core Power. 3.3V nominal (3.15V 3.45V). This supply turned only when mechanical switch power supply turned PWRON signal conditioned high. This should connected same voltage circuitry. Internally connected hardware monitoring system voltage detection circuitry 3.3V monitoring. Ground. Connect primary motherboard ground plane.
VCCS
VBAT VCCH
GNDH VCCU
GNDU
Suspend Power. Always available unless mechanical switch power supply turned off. "soft-off" state implemented, then this connected VCC. Signals powered referenced this plane are: PWRGD, RSMRST#, EXTSMI#, PWRBTN#, SMBCLK, SMBDATA, SUSCLK, SUSA# GPO1, SUSB# GPO2, SUSC#, SUSST1# GPO6, GPI1 IRQ8#, GPI2 BATLOW#, GPI3 LID, GPI5 PME#, GPI6 SMBALRT#, GPI7 RING#, GPO0, SDIN, SDIN2 Battery. Battery input internal (RTCX1, RTCX2) Hardware Monitor UDMA66 Power. Power hardware monitoring subsystem (voltage monitoring, temperature monitoring, speed monitoring) UDMA66 controller internal PLL. Connect through ferrite bead. Hardware Monitor UDMA66 Ground. Connect through ferrite bead. Differential Output Power. Power differential outputs (USBP0+, P0-, P1+, P1-, P2+, P2-, P3+, P3-). Connect through ferrite bead. Differential Output Ground. Connect through ferrite bead.
Revision 1.82 March 2001
-26-
Pinouts
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
REGISTERS
Register Overview
following tables summarize configuration registers VT82C686A. These tables also document power-on default value ("Default") access type ("Acc") each register. Access type definitions used (Read/Write), (Read/Only), reserved used (essentially same RO), just (Read Write Clear individual bits). Registers indicated have some read/only bits that always read back fixed value (usually unused); registers designated have some read-only read write bits (see individual register descriptions details). Detailed register descriptions provided following section this document. offset default values shown hexadecimal unless otherwise indicated Port 00-1F 20-3F 40-5F 60-6F (60h) (61h) (64h) 70-77 78-7F 81-8F 90-91 93-9F A0-BF C0-DF E0-FF 100-CF7
Table System
Function Actual Port Decoding Master Controller 0000 0000 000x nnnn Master Interrupt Controller 0000 0000 001x xxxn Timer Counter 0000 0000 010x xxnn Keyboard Controller 0000 0000 0110 xnxn Data 0000 0000 0110 x0x0 Misc Functions Spkr Ctrl0000 0000 0110 xxx1 Command Status 0000 0000 0110 x1x0 RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn -available system use- 0000 0000 0111 1xxx -reserved- (debug port) 0000 0000 1000 0000 Page Registers 0000 0000 1000 nnnn -available system use- 0000 0000 1001 000x System Control 0000 0000 1001 0010 -available system use- 0000 0000 1001 nnnn Slave Interrupt Controller 0000 0000 101x xxxn Slave Controller 0000 0000 110n nnnx -available system use- 0000 0000 111x xxxx -available system use*
CF8-CFB Configuration Address 0000 1100 1111 10xx CFC-CFF Configuration Data 0000 1100 1111 11xx D00-FFFF -available system use-
On-Chip Super-I/O Functions PC-Standard Port Addresses 200-20F Game Port 2E8-2EF COM4 2F8-2FF COM2 378-37F Parallel Port (Standard EPP) 3E8-3EF COM3 3F0-3F1 Configuration Index Data 3F0-3F7 Floppy Controller 3F8-3FF COM1 778-77A Parallel Port (ECP Extensions) (Port 378+400)
Revision 1.82 March 2001
-27-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Table Registers
Legacy Registers Port Master Controller Registers Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Read Write Mask Default Default
Legacy Registers (continued) Port Port Page Registers Page Channel Page Channel Page Channel Page Channel Page Channel Page Channel Page Channel Page Channel System Control Registers System Control Default Default
Port Master Interrupt Controller Regs Master Interrupt Control Master Interrupt Mask Master Interrupt Control Shadow Master Interrupt Mask Shadow shadow registers disabled Port Port Timer/Counter Registers Timer Counter Count Timer Counter Count Timer Counter Count Timer Counter Control Keyboard Controller Registers Keyboard Controller Data Misc Functions Speaker Control Keyboard Ctrlr Command Status
Port Slave Interrupt Controller Regs Default Slave Interrupt Control Slave Interrupt Mask Slave Interrupt Control Shadow Slave Interrupt Mask Shadow accessible shadow registers disabled Port Slave Controller Registers Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Read Write Mask Default
Default Default
Port CMOS Registers Default CMOS Memory Address Disa CMOS Memory Data (128 bytes) CMOS Memory Address CMOS Memory Data (256 bytes) CMOS Memory Address CMOS Memory Data (256 bytes) Disable port (CMOS Memory Address) bit-7. control occurs specific CMOS data locations (0-Dh). Ports 72-73 used access locations CMOS. Ports 74-75 used access CMOS internal disabled.
Revision 1.82 March 2001
-28-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Super-I/O Ports Offset 00-01 Offset 400h 401h 402h Offset Offset Floppy Disk Controller (Base -reservedFDC Command -reservedFDC Main Status Data Rate Select Data -reservedDisk Change Status Parallel Port (Base Parallel Port Data Parallel Port Status Parallel Port Control Address Data Port Data Port Data Port Data Port Data Configuration Configuration Extended Control Serial Port (Base Transmit (Wr) Receive (Rd) Buffer Interrupt Enable FIFO Control Interrupt Status UART Control Handshake Control UART Status Handshake Status Scratchpad Baud Rate Generator Divisor -undefinedSerial Port (Base Transmit (Wr) Receive (Rd) Buffer Interrupt Enable FIFO Control Interrupt Status UART Control Handshake Control UART Status Handshake Status Scratchpad Baud Rate Generator Divisor -undefinedDefault -Default
Super-I/O Configuration Registers (I/O Space) Port Super-I/O Configuration Registers Super-I/O Config Index (Rx85[1]=1) Super-I/O Config Data (Rx85[1]=1) Default
Super-I/O Configuration Registers (Indexed Port 3F0/1) Offset 00-DF E4-E5 E9-ED F9-FB FD-FF Super-I/O Control -reservedSuper-I/O Device Super-I/O Device Revision Function Select Floppy Ctrlr Base Addr (def 3F0-7) -reservedParallel Port Base Addr (def 378-F) Serial Port Base Addr (def 3F8-F) Serial Port Base Addr (def 2F8-F) -reservedSerial Port Configuration Power Down Control Parallel Port Control Serial Port Control Test Mode Program) -reservedTest Mode Program) -reservedFloppy Controller Configuration -reservedFloppy Controller Drive Select -reservedGeneral Purpose -reservedDefault
Default -Default
Revision 1.82 March 2001
-29-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Function Registers PCI-to-ISA Bridge Configuration Space PCI-to-ISA Bridge Header Registers Offset 10-27 28-2B 2F-2C 30-33 34-3B Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code -reserved- (cache line size) -reserved- (latency timer) Header Type Built Self Test (BIST) -reserved- (base address registers) -reserved- (unassigned) Subsystem Read -reserved- (expan. base addr) -reserved- (unassigned) -reserved- (interrupt line) -reserved- (interrupt pin) -reserved- (min gnt) -reserved- (max lat) Default 1106 0686 0087 0200 Offset Plug Play Control Default Request Control Routing Routing COM2 COM1 -reserved00 Edge Level Select Routing INTA Routing INTB-C Routing INTD APIC Output Control -reserved04 Control Internal Test Mode Control 5D-5E -reserved00 -reserved- program) power-up default depends external strapping Offset 61-60 63-62 65-64 67-66 69-68 6B-6A 6D-6C 6F-6E Offset 71-73 79-78 7B-7A 7D-7C 7F-7E 86-87 8D-8C 8F-8E 90-FF -30Distributed Channel Base Address Enable Channel Base Address Enable Channel Base Address Enable Channel Base Address Enable Serial Control Channel Base Address Enable Channel Base Address Enable Channel Base Address Enable Default 0000 0000 0000 0000 0000 0000 0000 0000
Configuration Space PCI-to-ISA Bridge-Specific Registers Offset 4F-4E Control Control Test Mode Clock Control Decode Control Keyboard Controller Control Type Control Miscellaneous Control Miscellaneous Control Miscellaneous Control -reservedIDE Interrupt Routing -reservedDMA Master Access Control Master Access Control Master Access Control Default 0300
Miscellaneous Default Subsystem Write -reserved00 GPIO Control GPIO Control GPIO Control GPIO Control PCS0# Port Address 0000 0000 PCS1# Port Address 0000 0000 Channel Enable 0000 32-Bit Control 0000 Programmable Chip Select Mask Positive Decoding Control Positive Decoding Control Positive Decoding Control Positive Decoding Control Extended Function Enable IRQ/DRQ Test program) Test Control PCS2/3 Port Address Mask Control PCS2# Port Address 0000 PCS3# Port Address 0000 -reserved00 Register Overview
Revision 1.82 March 2001
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Function Registers Controller Configuration Space Header Registers Offset Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code -reserved- (cache line size) Latency Timer Header Type Built Self Test (BIST) 13-10 Base Address Data Command 17-14 Base Address Control Status 1B-18 Base Address Data Command 1F-1C Base Address Control Status 23-20 Base Address Master Control 24-2F -reserved- (unassigned) 30-33 -reserved- (expan base addr) Capability Pointer 35-3B -reserved- (unassigned) Interrupt Line Interrupt Minimum Grant Maximum Latency Configuration Space IDE-Specific Registers (continued) Offset Configuration Space Registers Default 53-50 UltraDMA Extd Timing Ctrl CD/CE: 03030303 CF/CG: 07070707 UltraDMA FIFO Control 55-5F -reserved00 61-60 Primary Sector Size 0200 62-67 -reserved00 69-68 Secondary Sector Size 0200 69-6F -reserved00 Primary Status Primary Intrpt Control (CF/CG) 72-73 -reserved00 Primary Command (CD/CE) Primary Command (CD/CE) 76-77 -reserved00 Secondary Status Secondary Intrpt Ctrl (CF/CG) 7A-7B -reserved00 Secondary Command (CD/CE) Secondary Command (CD/CE) 7E-7F -reserved00 83-80 Primary Descriptor Address 0000 0000 84-87 -reserved00 8B-88 Secondary Descriptor Addr 0000 0000 8C-BF -reserved00 C3-C0 Block (CF/CG) 0201 C7-C4 Block (CF/CG) 0000 C8-FF -reserved00 Registers Controller (SFF 8038 v1.0 Compliant Default Offset Registers Primary Channel Command -reserved00 Primary Channel Status -reserved00 Primary Channel Table Addr Secondary Channel Command -reserved00 Secondary Channel Status -reserved00 Secondary Channel Table Addr
Default 1106 0571 0080 0290 000001F0 000003F4 00000170 00000374 0000CC01
Configuration Space IDE-Specific Registers Offset Configuration Space Registers Default Chip Enable Configuration Configuration FIFO Configuration Miscellaneous Control Miscellaneous Control Miscellaneous Control A8A8A8A8 4B-48 Drive Timing Control Address Setup Time -reserved- program) Non-1F0 Port Access Timing Non-1F0 Port Access Timing
Revision 1.82 March 2001
-31-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Function Registers Controller Ports Configuration Space Header Registers Default 1106 3038 0000 0200 00000301 Offset 10-1F 23-20 24-3B 3E-3F Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST -reservedUSB Register Base Address -reservedInterrupt Line Interrupt -reservedDefault 1106 3038 0000 0200 00000301
Function Registers Controller Ports Configuration Space Header Registers Offset 10-1F 23-20 24-3B 3E-3F Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST -reservedUSB Register Base Address -reservedInterrupt Line Interrupt -reserved-
Configuration Space USB-Specific Registers Offset 44-45 46-47 48-5F 61-7F 83-80 85-BF C1-C0 C2-FF Control Miscellaneous Control Miscellaneous Control FIFO Control (CF/CG) FIFO Control (CG) -reserved- (test, program) -reserved- (test) -reservedUSB Serial Release Number -reservedPM Capability (CF/CG) Capability Status (CF/CG) -reservedUSB Legacy Support -reservedAcc 0002 0001 2000 Default
Configuration Space USB-Specific Registers Offset 44-45 46-47 48-5F 61-7F 83-80 85-BF C1-C0 C2-FF Control Default Miscellaneous Control Miscellaneous Control FIFO Control (CF/CG) FIFO Control (CG) -reserved- (test only, program) -reserved- (test) -reserved00 Serial Release Number -reserved00 Capability (CF/CG) 0002 0001 Capability Status (CF/CG) -reserved00 Legacy Support 2000 -reserved00
Registers Controller Offset 11-10 13-12 14-1F Registers Command Status Interrupt Enable Frame Number Frame List Base Address Start Frame Modify Port Status Control Port Status Control -reservedDefault 0000 0000 0000 0000 00000000 0080 0080
Registers Controller Offset 11-10 13-12 14-1F Registers Command Status Interrupt Enable Frame Number Frame List Base Address Start Frame Modify Port Status Control Port Status Control -reservedDefault 0000 0000 0000 0000 00000000 0080 0080
Revision 1.82 March 2001
-32-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Function Registers Power Management Configuration Space Power Management Header Registers Default Offset Configuration Space Header Vendor 1106 Device 3057 Command 0000 Status 0280 Revision Programming Interface Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST 10-3F -reserved00 default values these registers changed writing offsets 61-63h (see below). Configuration Space Power Management Registers Offset 45-44 47-46 4B-48 4E-4F 53-50 56-57 5B-60 64-7F Default Power Management General Configuration General Configuration ACPI Interrupt Select Internal Timer Read Test Primary Interrupt Channel 0000 Secondary Interrupt Channel 0000 Power Mgmt Base (256 Bytes) 0000 0001 Host Power Management Control Throttle Clock Stop Control -reserved00 Timer Control 0000 0000 Power Well Control Wakeup Control -reserved00 Timer Control Timer Timer -reserved00 Write value Offset (Prog Intfc) Write value Offset (Sub Class) Write value Offset (Base Class) -reserved00 Configuration Space Hardware Monitor Registers Offset 71-70 72-73 75-8F System Management Hardware Base (128 Bytes) -reservedHardware Monitor Control -reservedDefault 0001
Configuration Space SMBus Registers Offset 93-90 94-D1 D7-FF System Management Default SMBus Base Bytes) 0000 0001 -reserved00 SMBus Host Configuration SMBus Host Slave Command SMBus Slave Address Shadow Port SMBus Slave Address Shadow Port SMBus Revision -reserved00
Revision 1.82 March 2001
-33-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Space System Management Registers Default 0000 0000 0000 0000 0000 Default 0000 0000 Default 0000 0000 0000 Default 0000 0000 0010 0000 0000 0000 0000 0000 0000 Default input input Offset System Management SMBus Host Status SMBus Slave Status SMBus Host Control SMBus Host Command SMBus Host Address SMBus Host Data SMBus Host Data SMBus Block Data SMBus Slave Control SMBus Shadow Command SMBus Slave Event SMBus Slave Data -reservedDefault 0000 0000
Space Power Management- Registers Offset Offset 13-10 16-1F Offset 21-20 23-22 25-24 26-27 Offset 29-28 2B-2A 2D-2C 33-30 37-34 3B-38 3C-3F Offset 46-47 4B-48 4F-4C 50-FF Basic Control Status Registers Power Management Status Power Management Enable Power Management Control -reservedPower Management Timer -reservedProcessor Registers Processor Control Processor LVL2 Processor LVL3 -reservedGeneral Purpose Registers General Purpose Status General Purpose Enable General Purpose Enable -reservedGeneric Registers Global Status Global Enable Global Control -reservedSMI Command Primary Activity Detect Status Primary Activity Detect Enable Timer Reload Enable -reservedGeneral Purpose Registers Extended Trap Status (CF/CG) -reservedExtended Trap Enable (CF/CG) -reservedExternal Input Value Resume Status -reservedGPI Port Input Value Port Output Value -reserved-
03FF FFFF
Revision 1.82 March 2001
-34-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Space Hardware Monitor Registers Offset 00-3F 00-12 18-1C Hardware Monitor Value -reservedAnalog Data 15-8 Analog Data Digital Data Channel Counter Data Valid Channel Indicators -reservedTSENS3 Limit TSENS3 Hysteresis TSENS3 (Int) Temp Reading TSENS1 (W13) Temp Reading TSENS2 (Y13) Temp Reading VSENS1 (U13) Voltage Reading VSENS2 (V13) Voltage Reading Internal Core Voltage Reading VSENS3 (W14) Voltage Reading VSENS4 (Y14) Voltage Reading -reserved- (-12V Voltage Reading) -reserved- (-5V Voltage Reading) FAN1 (T12) Count Reading FAN2 (U12) Count Reading VSENS1 (CPU) Voltage High Limit VSENS1 (CPU) Voltage Limit VSENS2 (NB) Voltage High Limit VSENS2 (NB) Voltage Limit Internal Core High Limit Internal Core Limit VSENS3 (5V) Voltage High Limit VSENS3 (5V) Voltage Limit VSENS4 (12V) Voltage High Limit VSENS4 (12V) Voltage Limit -reserved- (-12V Sense High Limit) -reserved- (-12V Sense Limit) -reserved- (-5V Sense High Limit) -reserved- (-5V Sense Limit) TSENS1 High Limit TSENS1 Hysteresis FAN1 Count Limit FAN2 Count Limit TSENS2 High Limit TSENS2 Hysteresis Stepping Number Default Offset 45-46 4C-FF Hardware Monitor (continued) Hardware Monitor Configuration Hardware Monitor Interrupt Status Hardware Monitor Interrupt Status Hardware Monitor Interrupt Mask Hardware Monitor Interrupt Mask -reservedHardware Monitor Configuration -reservedHW Temp Value Lo-Order Bits -reservedTemperature Interrupt Configuration -reservedDefault
Revision 1.82 March 2001
-35-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Function Registers AC97 MC97 Codecs Function Configuration Space AC97 Header Registers Offset 13-10 17-14 1B-18 1F-1C 23-20 27-24 28-29 2F-2C 33-30 35-3B 3E-3F Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST Base Address Control/Status Base Address Status Base Address MIDI Port (CF/CG) Base Address (reserved) Base Address (reserved) Base Address (reserved) -reservedSubsys SubVendor (CF/CG) Expansion (reserved) Capture Pointer (CF/CG) -reservedInterrupt Line Interrupt -reservedDefault 1106 3058 0000 0210 0000 0001 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Function Configuration Space MC97 Header Registers Offset 13-10 17-14 1B-18 1F-1C 23-20 27-24 28-29 2F-2C 33-30 35-3B 3E-3F Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST Base Address Control/Status Base Address Status Base Address MIDI Port (CF/CG) Base Address (reserved) Base Address (reserved) Base Address (reserved) -reservedSubsys SubVendor (CF/CG) Expansion (reserved) Capture Pointer (CF/CG) -reservedInterrupt Line Interrupt -reservedDefault 1106 3068 0000 0200 0000 0001 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Configuration Space Audio Codec-Specific Registers Offset Audio Codec Link Control Default AC-Link Interface Status AC-Link Interface Control Function Enable Plug Play Control MC97 Interface Control 45-47 -reserved00 Control -reserved00 4B-4A Game Port Base Address 0000 4C-FF -reserved00 Note that these registers same function except offset (Read Write function
Configuration Space Modem Codec-Specific Registers Offset Modem Codec Link Control Default AC-Link Interface Status AC-Link Interface Control Function Enable Plug Play Control MC97 Interface Control 45-47 -reserved00 Control -reserved00 4B-4A Game Port Base Address 0000 4C-FF -reserved00 Note that these registers same function except offset (Read Only function
Revision 1.82 March 2001
-36-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Function Base Registers MC97 Modem Offset 47-44 4B-48 4F-4C 57-54 5B-58 5F-5C 60-7F Offset 83-80 87-84 8B-88 8F-8C 90-FF MC97 Registers Read Channel Status Read Channel Control Read Channel Type -reservedSGD Read Chan Table Pointer Base Read Channel Current Address -reserved- (Test) Read Chan Current Count Write Channel Status Write Channel Control Write Channel Type -reservedSGD Write Chan Table Pointer Base Write Channel Current Address Reserved (Test) Write Channel Current Count -reservedAC97 Modem Codec Registers AC97 Controller Command Status Status Shadow Modem Codec Intr Status GPIO Modem Codec Interrupt Enable -reservedDefault 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Default 0000 0000 0000 0000 0000 0000 0000 0000
Function Base Registers AC97 Audio Offset 17-14 1B-18 1F-1C 27-24 2B-28 2F-2C 30-7F Offset 83-80 87-84 88-FF AC97 Registers Read Channel Status Read Channel Control Read Channel Type -reservedSGD Read Chan Table Pointer Base Read Channel Current Address Reserved (Test) Read Chan Current Count Write Channel Status Write Channel Control Write Channel Type -reservedSGD Write Chan Table Pointer Base Write Channel Current Address Reserved (Test) Write Channel Current Count Channel Status Channel Control Type -reservedSGD Channel Table Pointer Base Channel Current Address Reserved (Test) Channel Current Count -reservedAC97 Audio Codec Registers AC97 Controller Command Status Status Shadow -reservedDefault 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Default 0000 0000 0000 0000
Function Base Registers Status Offset Status Registers Status Data Index -reservedDefault
Function Base Registers MIDI Game Port Offset Status Registers MIDI Port Base Game Port Base Default 0330 0200
Revision 1.82 March 2001
-37-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Registers Game Port Default -Offset Game Port (200-20F typical) -reservedGame Port Status Start One-Shot -reservedDefault
Registers SoundBlaster Offset Registers (220 240h typ) Left Channel Index Status Left Channel Data Right Channel Index Status Right Channel Data Mixer Index Mixer Data Sound Processor Reset -reservedFM Index Status (Both Channels) Data (Both Channels) Sound Processor Data -reservedSound Processor Command Data Sound Processor Buffer Status -reservedSnd Processor Data Available Status -reserved-
Port Regs (same offsets Default 388h Index Status 389h Data above group registers emulates "FM", "Mixer", "Sound Processor" functions SoundBlaster Pro.
Revision 1.82 March 2001
-38-
Register Overview
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Port Misc Functions Speaker Control. .always reads Reserved IOCHCK# Active This when IOCHCK# signal asserted. Once set, this cleared setting bit-3 this register. Bit-3 should cleared enable recording next IOCHCK#. IOCHCK# generates enabled. Timer/Counter Output.RO This reflects output Timer/Counter without synchronization. Refresh Detected.RO This toggles every rising edge REFRESH# signal. IOCHCK# Disable.RW Enable IOCHCK# assertions default Force IOCHCK# inactive clear "IOCHCK# Active" condition bit-6 .RW, default=0 Reserved Speaker Enable Disable. default Enable Timer/Ctr output drive SPKR Timer/Counter Enable Disable. default Enable Timer/Counter Port System Control. Hard Disk Activity Status default .always reads Reserved Power-On Password Bytes Inaccessable .default=0 .always reads Reserved Address Line Enable disable forced (real mode) default address line enable High Speed Reset Normal Briefly pulse system reset switch from protected mode real mode
Register Descriptions
Legacy Ports This group registers includes Controllers, Interrupt Controllers, Timer/Counters well number miscellaneous ports originally implemented using discrete logic original PC/AT motherboards. registers listed integrated on-chip. These registers implemented precise manner backwards compatibility with previous generations hardware. These registers listed information purposes only. Detailed descriptions actions programming these registers included numerous industry publications (duplication that information here beyond scope this document). these registers reside space.
Revision 1.82 March 2001
-39-
Register Descriptions Legacy Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Port Keyboard Mouse Status Parity Error parity error (odd parity received). default Even parity occurred last byte received from keyboard mouse General Receive Transmit Timeout error default Error Mouse Output Buffer Full Mouse output buffer empty. default Mouse output buffer holds mouse data Keylock Status Locked Free Command Data Last write data write default Last write command write System Flag Power-On Default default Self Test Successful Input Buffer Full Input Buffer Empty. default Input Buffer Full Keyboard Output Buffer Full Keyboard Output Buffer Empty. default Keyboard Output Buffer Full Control Register .(R/W Commands 20h/60h) .always reads Reserved Compatibility Disable scan conversion Convert scan codes format; convert 2byte break sequences 1-byte PC-compatible break codes default Mouse Disable Enable Mouse Interface default Disable Mouse Interface Keyboard Disable Enable Keyboard Interface default Disable Keyboard Interface .always reads Reserved System Flag .default=0 This read back status register bit-2 Mouse Interrupt Enable Disable mouse interrupts default Generate interrupt IRQ12 when mouse data comes output bufer Keyboard Interrupt Enable Disable Keyboard Interrupts. default Generate interrupt IRQ1 when output buffer been written.
Keyboard Controller Registers keyboard controller handles keyboard mouse interfaces. ports used: port port Reads from port return status byte. Writes port command codes (see command code list following register descriptions). Input output data transferred port "Control" register also available. accessable writing commands command port (port 64h); control byte written first sending command port, then sending control byte value. control register read sending command port 64h, waiting "Output Buffer Full" status then reading control byte value from port 60h. Traditional (non-integrated) keyboard controllers have "Input Port" "Output Port" with specific pins dedicated certain functions other pins available general purpose I/O. Specific commands provided these pins high low. outputs "open-collector" allow input these pins, output value that would high (non-driving) desired input value read input port. These ports defined follows: Input Port Code Code Keyboard Data Mouse Data Turbo (PS/2 mode only) user-defined user-defined user-defined user-defined undefined Output Port Code Code SYSRST (1=execute reset) GATEA20 (1=A20 enabled) Mouse Data Mouse Clock Keyboard Interrupt (IRQ1) Mouse Interrupt (IRQ Keyboard Clock Keyboard Data Test Port Code Code Keyboard Clock Mouse Clock Note: Command code transfers input port data output buffer. Command code copies output port values output buffer. Command code transfers test input port data output buffer. Port Keyboard Controller Input Buffer Only write port port bit-1 (1=full). Port Keyboard Controller Output Buffer Only read from port port bit-0 (0=empty).
Revision 1.82 March 2001
-40-
Register Descriptions Legacy Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Port Keyboard Mouse Command. This port used send commands keyboard mouse controller. command codes recognized VT82C686A listed table below. Note: VT82C686A Keyboard Controller compatible with VT82C42 Industry-Standard Keyboard Controller except that integrated nature, many input output port pins available externally general purpose pins (even though P13-P16 power-up strapping options). other words, many commands below provided "work", otherwise perform useful function (e.g., commands that P12-P17 high low). Also note that setting P10-11, P22-23, P26-27, T0-1 high directly serves useful purpose, since these bits used implement keyboard mouse ports directly controlled keyboard controller logic.
Table Keyboard Controller Command Codes
Code 21-3Fh 61-7Fh Keyboard Command Code Description Read Control Byte (next byte Control Byte) Read SRAM Data (next byte Data Byte) Write Control Byte (next byte Control Byte) Write SRAM Data (next byte Data Byte) Write nibble (bits 0-3) P10-P13 Output Keyboard Controller Version Test Password installed (always returns indicate installed) Disable Mouse Interface Enable Mouse Interface Mouse Interface Test (puts test results port 60h) (value: 0=OK, 1=clk stuck low, 2=clk stuck high, 3=data stuck 4=data stuck FF=general error) self test (returns not) Keyboard Interface Test (see Mouse Test) Disable Keyboard Interface Enable Keyboard Interface Return Version high high high high high high high high Code Keyboard Command Code Description Read input port (read P10-17 input data output buffer) Poll input port (read input data P11-13 repeatably bits status Poll input port high (same except P15-17) Unblock P22-23 (use before change active mode) Reblock P22-23 (protection mechanism Read mode (output mode info port output buffer (bit-0=0 ISA, PS/2) Read Output Port (copy P10-17 output port values port Write Output Port (data byte following written keyboard output port came from keyboard) Write Keyboard Output Buffer clear status bit-5 (write following byte keyboard) Write Mouse Output Buffer status bit-5 (write following byte mouse; value mouse input buffer appears have come from mouse) Write Mouse (write following byte mouse) Read test inputs (T0-1 read bits resp byte) P23-P21 command bits Pulse P23-P20 6usec command bits
other codes listed undefined.
Revision 1.82 March 2001
-41-
Register Descriptions Legacy Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Controller Registers Ports 00-0F Master Controller Channels Master Controller control System Channels 0-3. There Master Controller registers: Address Bits 15-0 0000 0000 000x 0000 0000 0000 000x 0001 0000 0000 000x 0010 0000 0000 000x 0011 0000 0000 000x 0100 0000 0000 000x 0101 0000 0000 000x 0110 0000 0000 000x 0111 0000 0000 000x 1000 0000 0000 000x 1001 0000 0000 000x 1010 0000 0000 000x 1011 0000 0000 000x 1100 0000 0000 000x 1101 0000 0000 000x 1110 0000 0000 000x 1111 Register Name Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Mask Bits Ports 80-8F Page Registers There eight Page Registers, each channel. These registers provide bits 16-23 24-bit address each channel (bits 0-15 stored registers Master Slave Controllers). They located following Port addresses: Address Bits 15-0 0000 0000 1000 0111 0000 0000 1000 0011 0000 0000 1000 0001 0000 0000 1000 0010 0000 0000 1000 1111 0000 0000 1000 1011 0000 0000 1000 1001 0000 0000 1000 1010 Register Name Channel Page (M-0).RW Channel Page (M-1).RW Channel Page (M-2).RW Channel Page (M-3).RW Channel Page (S-0) Channel Page (S-1) Channel Page (S-2) Channel Page (S-3)
Controller Shadow Registers Controller shadow registers enabled setting function Rx77 shadow registers enabled, they read back indicated port instead standard controller registers (writes unchanged). Port -Channel Base Address Port -Channel Byte Count. Port -Channel Base Address Port -Channel Byte Count. Port -Channel Base Address Port -Channel Byte Count. Port -Channel Base Address Port -Channel Byte Count. Port -1st Read Channel Command Register Port -2nd Read Channel Request Register. Port -3rd Read Channel Mode Register Port -4th Read Channel Mode Register Port -5th Read Channel Mode Register Port -6th Read Channel Mode Register Port -Channel Read Mask Port -Channel Base Address. Port -Channel Byte Count Port -Channel Base Address. Port -Channel Byte Count Port -Channel Base Address. Port -Channel Byte Count Port -1st Read Channel Command Register. Port -2nd Read Channel Request Register. Port -3rd Read Channel Mode Register Port -4th Read Channel Mode Register Port -5th Read Channel Mode Register Port -6th Read Channel Mode Register Port -Channel Read Mask
Ports C0-DF Slave Controller Channels Slave Controller control System Channels 4-7. There Slave Controller registers: Address Bits 15-0 0000 0000 1100 000x 0000 0000 1100 001x 0000 0000 1100 010x 0000 0000 1100 011x 0000 0000 1100 100x 0000 0000 1100 101x 0000 0000 1100 110x 0000 0000 1100 111x 0000 0000 1101 000x 0000 0000 1101 001x 0000 0000 1101 010x 0000 0000 1101 011x 0000 0000 1101 100x 0000 0000 1101 101x 0000 0000 1101 110x 0000 0000 1101 111x Register Name Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Read/Write Mask Bits
Note that bits address decoded. Master Slave Controllers compatible with Intel 8237 Controller chip. Detailed description 8237 controller operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
Revision 1.82 March 2001
-42-
Register Descriptions Legacy Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Interrupt Controller Shadow Registers following shadow registers enabled setting function Rx47[4]. shadow registers enabled, they read back indicated port instead standard interrupt controller registers (writes unchanged). Port Master Interrupt Control Shadow Port Slave Interrupt Control Shadow .always reads Reserved OCW3 (POLL) OCW3 (RIS) OCW3 (SMM) OCW2 ICW4 (SFNM) ICW4 (AEOI) ICW1 (LTIM) Port Master Interrupt Mask Shadow Port Slave Interrupt Mask Shadow .always reads Reserved T7-T3 Interrupt Vector Address Timer Counter Registers Ports 40-43 Timer Counter Registers There Timer Counter registers: Address Bits 15-0 0000 0000 010x xx00 0000 0000 010x xx01 0000 0000 010x xx10 0000 0000 010x xx11 Register Name Timer Counter Count Timer Counter Count Timer Counter Count Timer Counter Mode
Interrupt Controller Registers Ports 20-21 Master Interrupt Controller Master Interrupt Controller controls system interrupt channels 0-7. registers control Master Interrupt Controller. They are: Address Bits 15-0 0000 0000 001x xxx0 0000 0000 001x xxx1 Register Name Master Interrupt Control Master Interrupt Mask
Note that bits address decoded. Master Interrupt Controller compatible with Intel 8259 Interrupt Controller chip. Detailed descriptions 8259 Interrupt Controller operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
Ports A0-A1 Slave Interrupt Controller Slave Interrupt Controller controls system interrupt channels 8-15. slave system interrupt controller also occupies register locations: Address Bits 15-0 0000 0000 101x xxx0 0000 0000 101x xxx1 Register Name Slave Interrupt Control Slave Interrupt Mask
Note that address bits decoded. Slave Interrupt Controller compatible with Intel 8259 Interrupt Controller chip. Detailed descriptions 8259 Interrupt Controller operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
Note that bits address decoded. Timer Counters compatible with Intel 8254 Timer Counter chip. Detailed descriptions 8254 Timer Counter operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
Timer Counter Shadow Registers following shadow registers enabled readback setting function Rx47[4]. shadow registers enabled, they read back indicated port instead standard timer counter registers (writes unchanged). Port Counter Base Count Value (LSB 2nd)RO Port Counter Base Count Value (LSB 2nd)RO Port Counter Base Count Value (LSB 2nd)RO
Revision 1.82 March 2001
-43-
Register Descriptions Legacy Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Offset Description Binary Range Range 00-3Bh 00-59h Seconds 00-3Bh 00-59h Seconds Alarm 00-3Bh 00-59h Minutes 00-3Bh 00-59h Minutes Alarm 12hr: 01-1Ch 01-12h Hours 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h 01-12h Hours Alarm 12hr: 01-1Ch 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h 01-07h Week Sun=1: 01-07h 01-1Fh 01-31h Month 01-0Ch 01-12h Month 00-63h 00-99h Year Register Update Progress DV2-0 Divide (010=ena keep time) RS3-0 Rate Select Periodic Interrupt Register SQWE 24/12 Register IRQF Register
CMOS Registers Port CMOS Address.RW Disable. Enable Generation. asserted encountering IOCHCK# SERR# bus. Disable Generation .default CMOS Address (lower bytes). Port CMOS Data.RW CMOS Data (128 bytes) Note: Ports 70-71 accessed Rx5A bit-2 select internal RTC. Rx5A bit-2 zero, accesses ports 70-71 will directed external RTC.
Port CMOS Address.RW CMOS Address (256 bytes). Port CMOS Data.RW CMOS Data (256 bytes) Note: Ports 72-73 accessed Rx5A bit-2 select internal RTC. Rx5A bit-2 zero, accesses ports 72-73 will directed external RTC.
Port CMOS Address.RW CMOS Address (256 bytes). Port CMOS Data.RW CMOS Data (256 bytes) Note: Ports 74-75 accessed only Function Rx5B bit-1 enable internal SRAM Rx48 bit-3 (Port 74/75 Access Enable) enable port 74/75 access. Ports 70-71 compatible with industrystandards used access lower bytes 256-byte on-chip CMOS RAM. Ports 72-73 used access full extended 256byte space. Ports 74-75 used access full on-chip extended 256-byte space cases where on-chip disabled. system Real Time Clock (RTC) part "CMOS" block. control registers located specific offsets CMOS data area (00Dh 7D-7Fh). Detailed descriptions CMOS operation programming obtained from VT82887 Data Book numerous other industry publications. reference, definition register locations bits summarized following table:
Inhibit Update Transfers Periodic Interrupt Enable Alarm Interrupt Enable Update Ended Interrupt Enable function (read/write bit) Data Mode (0=BCD, 1=binary) Hours Byte Format (0=12, 1=24) Daylight Savings Enable
Note:
Interrupt Request Flag Periodic Interrupt Flag Alarm Interrupt Flag Update Ended Flag Unused (always read
Reads VBAT voltage Unused (always read
0E-7C Software-Defined Storage Registers (111 Bytes) Offset Extended Functions Date Alarm Month Alarm Century Field Binary Range Range 01-1Fh 01-31h 01-0Ch 01-12h 13-14h 19-20h
Note:
80-FF Software-Defined Storage Registers (128 Bytes)
Table CMOS Register Summary
Revision 1.82 March 2001
-44-
Register Descriptions Legacy Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Super-I/O Configuration Registers These registers accessed port index data register pair using indicated index values below
Super-I/O Configuration Index Data Registers Super-I/O configuration registers accessed performing operations from index data pair registers system space port addresses 3F0h 3F1h. configuration registers accessed using this mechanism used configure Super-I/O registers (parallel port, serial ports, port, floppy controller). Super configuration accomplished three steps: Enter configuration mode (set Function Rx85[1] Configure chip Write index port Read write data from port Repeat desired registers Exit configuration mode (set Function Rx85[1]
Index Super-I/O Device (3Ch) Super-I/O default Index Super-I/O Device Revision (00h) Super-I/O Revision Code .default Index Super-I/O Function Select (03h). .always reads Reserved Floppy Controller Enable Disable. default Enable Serial Port Enable Disable. default Enable Serial Port Enable Disable. default Enable Parallel Port Mode Enable Unidirectional mode Parallel Port Disable default Index Floppy Controller Base Address (00h). Address 9-4.default Must .default Index Parallel Port Base Address (00h). Address 9-2.default enabled, parallel port locations 4-byte boundaries from 100h 3FCh. enabled, parallel port locations 8-byte boundaries from 100h 3F8h. Index Serial Port Base Address (00h) Address 9-3.default Must .default Index Serial Port Base Address (00h) Address 9-3.default Must .default
Port 3F0h Super-I/O Configuration Index.RW Index value Function configuration space register Rx85[1] must enable access Super-I/O configuration registers. Port 3F1h Super-I/O Configuration Data Data value This register shares port with Floppy Status Port (which read only). This port accessible only when Rx85[1] (the floppy status port accessed Rx85[1]
Revision 1.82 March 2001
-45-
Register Descriptions Super-I/O Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Index Parallel Port Control (00h) Type BiDirectionl Parallel Port Disable. default Enable Direction Register Disable. default Enable EPP+ECP Disable. default Enable Version Version default Version .always reads Reserved
Index Serial Port Configuration (00h) Serial Port High Speed Enable Disable .default Enable Serial Port High Speed Enable Disable .default Enable Serial Port Mode Standard .default IrDA (HIPSIR) Amplitude shift keyed 500KHz -reserved1xx -reserved2 Serial Port Half Duplex Disable .default Enable Serial Port Output Inversion Disable .default Enable Serial Port Input Inversion Disable .default Enable
Index Power Down Control (00h) always reads Reserved Clock Power Down Normal operation .default Power Down Parallel Port Power Down Normal operation .default Power Down Serial Port Power Down Normal operation .default Power Down Serial Port Power Down Normal operation .default Power Down Power Down Normal operation .default Power Down Power Down Normal operation .default Power Down
Index Serial Port Control (00h) .always reads Reserved Loop Back Disable. default Enable Serial Port Power-Down State Normal. default Tristate output power down mode Serial Port Power-Down State Normal. default Tristate output power down mode Dedicated (IRTX/IRRX) Select IRTX IRRX Output from Serial Port Function Rx76[5] IRRX output from dedicated IRTX output from dedicated .always reads Reserved
Index Test Mode Program) Index Test Mode Program)
Revision 1.82 March 2001
-46-
Register Descriptions Super-I/O Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Index Floppy Drive Control Floppy Drive (see table below) Floppy Drive (see table below) Floppy Drive (see table below) Floppy Drive (see table below) DRVEN1 DRATE0 DRATE0 DRATE0 DRATE1 DRVEN0 DENSEL DRATE1 DENSEL# DRATE0
Index Floppy Controller Configuration.RW always reads Reserved Floppy Drive Parallel Port (CF/CG) Parallel Port (SPP) Mode .default Mode This used notebook applications allow attachment external floppy drive using parallel port connector: Mode STROBE# ACK# BUSY SLCT AUTOFD# ERROR# PINIT# SLCTIN# Type Mode Type INDEX# TRK00# WRTPRT# RDATA# DSKCHG# DS1# MTR1# WDATA# WGATE# DRVEN0 HDSEL# DIR# STEP#
3-Mode Disable .default Enable always reads Reserved Four Floppy Drive Option Internal 2-Drive Decoder .default External 4-Drive Decoder Non-Burst Burst .default Non-Burst Swap Disable .default Enable
Revision 1.82 March 2001
-47-
Register Descriptions Super-I/O Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Super-I/O Ports Floppy Disk Controller Registers These registers located ports which offsets from "FDCBase" (index Super-I/O configuration registers). FDCBase typically allow these ports accessed standard floppy disk controller address range 3F0-3F7h. Port FDCBase+2 Command.RW Motor (unused VT82C686A: MTR3# pin) Motor (unused VT82C686A: MTR2# pin) Motor Motor Motor Motor Motor Motor Channels Disable Enable Reset Execute Reset Enable Drive Select Select Drive Select Drive -reservedPort FDCBase+4 Main Status.RO Main Request Data register ready Data register ready Data Input Output Non-DMA Mode mode mode Busy inactive active always reads Reserved Drive Active Drive inactive Drive performing positioning change Drive Active Drive inactive Drive performing positioning change Port FDCBase+4 Data Rate Select Software Reset Normal operation. default Execute reset (this self clearing) Power Down Normal operation. default Power down logic .always reads Reserved Precompensation Select Selects amount write precompensation used WDATA output: Default default 41.7 93.3 125.0 166.7 208.3 250.0 (disable) Data Rate Drive Type 500K 250K 1.2MB 1.44 300K 150K 360KB 250K 125K 720KB default illegal Note: these bits changed software reset Port FDCBase+5 Data. Port FDCBase+7 Disk Change Status. Disk Change Floppy changed. default Floppy changed since last instruction Undefined always reads Data Rate Kbit/sec (1.2MB 1.44 drive) Kbit/sec (360KB drive) Kbit/sec (720KB drive) Mbit/sec
Revision 1.82 March 2001
-48-
Register Descriptions Super-I/O Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Parallel Port Registers These registers located ports which offsets from "LPTBase" (index Super-I/O configuration registers). LPTBase typically allow these ports accessed standard parallel port address range 37837Fh. Port LPTBase+0 Parallel Port Data Parallel Port Data Port LPTBase+1 Parallel Port Status.RO BUSY# Printer busy, offline, error Printer busy ACK# Data transfer printer complete Data transfer printer progress Paper available paper available SLCT Printer offline Printer online ERROR# Printer error Printer always read bits Reserved Port LPTBase+3 Parallel Port Address. Port LPTBase+4 Parallel Port Data Port Port LPTBase+5 Parallel Port Data Port Port LPTBase+6 Parallel Port Data Port Port LPTBase+7 Parallel Port Data Port
Port LPTBase+400h Parallel Port Data Port LPTBase+401h Parallel Port Config Port LPTBase+402h Parallel Port Extd Ctrl. Parallel Port Mode Select Standard Mode. default PS/2 Mode FIFO Mode Mode Mode -reserved110 -reserved111 Configuration Mode Parallel Port Interrupt Disable Enable interrupt pulse generated high edge fault. interrupt will also generated fault condition asserted this written from Disable interrupt generated asserting edge fault condition Parallel Port Enable Disable unconditionally Enable Parallel Port Interrupt Pending Interrupt pending Interrupt pending (DMA interrupts disabled) This hardware must written re-enable interrupts FIFO Full FIFO least free byte FIFO full cannot accept byte FIFO Empty. FIFO contains least byte data FIFO completely empty
Port LPTBase+2 Parallel Port Control Undefined always read back Hardware Interrupt Disable .default Enable Printer Select Deselect printer .default Select printer Printer Initialize Initialize Printer.default Allow printer operate normally Automatic Line Feed Host handles line feeds.default Printer does automatic line feeds Strobe data transfer .default Transfer data printer
Revision 1.82 March 2001
-49-
Register Descriptions Super-I/O Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Port COM1Base+4 Handshake Control Undefined always read Loopback Check Normal operation Loopback enable General Purpose Output (unused 82C686A) General Purpose Output (unused 82C686A) Request Send Disable Enable Data Terminal Ready Disable Enable Port COM1Base+5 UART Status. Undefined always read Transmitter Empty byte transmit hold transmit shift register bytes transmit hold transmit shift regs Transmit Buffer Empty byte transmit hold register Transmit hold register empty Break Detected break detected Break detected Framing Error Detected error Error Parity Error Detected error Error Overrun Error Detected error Error Received Data Ready received data available Received data receiver buffer register Port COM1Base+6 Handshake Status. Status (1=Active, 0=Inactive) Status (1=Active, 0=Inactive) Status (1=Active, 0=Inactive) Status (1=Active, 0=Inactive) Changed (1=Changed Since Last Read) Changed (1=Changed Since Last Read) Changed (1=Changed Since Last Read) Changed (1=Changed Since Last Read) Port COM1Base+7 Scratchpad Scratchpad Data
Serial Port Registers These registers located ports which offsets from "COM1Base" (index Super-I/O configuration registers). COM1Base typically allow these ports accessed standard serial port address range 3F83FFh. Port COM1Base+0 Transmit Receive Buffer Serial Data Port COM1Base+1 Interrupt Enable Undefined .always read Interrupt Handshake Input State Change Intr Parity, Overrun, Framing Error Break Interrupt Transmit Buffer Empty Interrupt Receive Data Ready Port COM1Base+1-0 Baud Rate Generator Divisor.RW 15-0 Divisor Value Baud Rate Generator Baud Rate 115,200 Divisor (e.g., setting this register selects 115.2 Kbaud) Port COM1Base+2 Interrupt Status Undefined .always read Interrupt (0=highest priority) Priority (Handshake Input Changed State) Priority (Transmit Buffer Empty) Priority (Data Received) Priority (Serialization Error Break) Interrupt Pending Interrupt Pending Interrupt Pending Port COM1Base+2 FIFO Control Port COM1Base+3 UART Control.RW Divisor Latch Access Access xmit enable regs Access baud rate generator divisor latch Break Break condition Break condition Parity None Even Mark Space Stop Bits Data Bits
Revision 1.82 March 2001
-50-
Register Descriptions Super-I/O Ports
7HFKQRORJLHV
'HOLYHULQJ 9DOXH
VT82C686A
Port COM2Base+4 Handshake Control Undefined always read Loopback Check Normal operation Loopback enable General Purpose Output (unused 82C686A) General Purpose Output (unused 82C686A) Request Send Disable Enable Data Terminal Ready Disable Enable Port COM2Base+5 UART Status. Undefined always read Transmitter Empty byte transmit hold transmit shift register bytes transmit hold transmit shift regs Transmit Buffer Empty byte transmit hold register Transmit hold register empty Break Detected break detected Break detected Framing Error Detected error Error Parity Error Detected error Error Overrun Error Detected error Error Received Data Ready received data available Received data receiver buffer register Port COM2Base+6 Handshake Status. Status (1=Active, 0=Inactive) Status (1=Active, 0=Inactive) Status (1=Active, 0=Inactive) Status (1=Active, 0=Inactive) Changed (1=Changed Since Last Read) Changed (1=Changed Since Last Read) Changed (1=Changed Since Last Read) Changed (1=Changed Since Last Read) Port COM2Base+7 Scratchpad Scratchpad Data
Serial Port Registers These registers located ports which offsets from "COM2Base" (index Super-I/O configuration registers). COM2Base typically allow these ports accessed standard serial port address range 2F82FFh. Port COM2Base+0 Transmit Receive Buffer Serial Data Port COM2Base+1 Interrupt Enable Undefined .always read Interrupt Handshake Input State Change Intr Parity, Overrun, Framing Error Break Interrupt Transmit Buffer Empty Interrupt Receive Data Ready Port COM2Base+1-0 Baud Rate Generator Divisor.RW 15-0 Divisor Value Baud Rate Generator Baud Rate 115,200 Divisor (e.g., setting this register selects 115.2 Kbaud) Port COM2Base+2 Interrupt Status Undefined .always read Interrupt (0=highest priority) Priority (Handshake Input Changed State) Priority (Transmit Buffer Empty) Priority (Data Received) Priority (Serialization Error Break) Interrupt Pending Interrupt Pending Interrupt Pending Port COM2Base+2 FIFO Con
Other recent searches
TSOP11 - TSOP11 TSOP11 Datasheet
TSOP1130TB1 - TSOP1130TB1 TSOP1130TB1 Datasheet
TSOP1136TB1 - TSOP1136TB1 TSOP1136TB1 Datasheet
TSOP1138TB1 - TSOP1138TB1 TSOP1138TB1 Datasheet
TSOP1156TB1 - TSOP1156TB1 TSOP1156TB1 Datasheet
TSOP1133TB1 - TSOP1133TB1 TSOP1133TB1 Datasheet
TSOP1137TB1 - TSOP1137TB1 TSOP1137TB1 Datasheet
TSOP1140TB1 - TSOP1140TB1 TSOP1140TB1 Datasheet
TLV2354 - TLV2354 TLV2354 Datasheet
TLV2354Y - TLV2354Y TLV2354Y Datasheet
SMP100-xxx - SMP100-xxx SMP100-xxx Datasheet
SMP100-xxxH225 - SMP100-xxxH225 SMP100-xxxH225 Datasheet
VDE0433 - VDE0433 VDE0433 Datasheet
VDE0878 - VDE0878 VDE0878 Datasheet
NJU28001 - NJU28001 NJU28001 Datasheet
NJU3200 - NJU3200 NJU3200 Datasheet
NJU3300 - NJU3300 NJU3300 Datasheet
NJU501 - NJU501 NJU501 Datasheet
NJU502 - NJU502 NJU502 Datasheet
NJU503Series - NJU503Series NJU503Series Datasheet
NJU511Series - NJU511Series NJU511Series Datasheet
NJU512Series - NJU512Series NJU512Series Datasheet
NJU5201 - NJU5201 NJU5201 Datasheet
NJU5202 - NJU5202 NJU5202 Datasheet
NJU5502Series - NJU5502Series NJU5502Series Datasheet
NJU5503Series - NJU5503Series NJU5503Series Datasheet
NJU5504Series - NJU5504Series NJU5504Series Datasheet
NJU5505Series - NJU5505Series NJU5505Series Datasheet
NJU5506Series - NJU5506Series NJU5506Series Datasheet
NJU5507Series - NJU5507Series NJU5507Series Datasheet
NJU5508Series - NJU5508Series NJU5508Series Datasheet
NJU5510Series - NJU5510Series NJU5510Series Datasheet
NJU5511Series - NJU5511Series NJU5511Series Datasheet
NJU5601 - NJU5601 NJU5601 Datasheet
NJU6014 - NJU6014 NJU6014 Datasheet
NJU6103 - NJU6103 NJU6103 Datasheet
NJU6104 - NJU6104 NJU6104 Datasheet
NFSL036BT - NFSL036BT NFSL036BT Datasheet
M36P0R9060N0 - M36P0R9060N0 M36P0R9060N0 Datasheet
GB20RF60K - GB20RF60K GB20RF60K Datasheet
AQV414 - AQV414 AQV414 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
