Preliminary Data Sheet September, 2008 FEATURES 25ns maximum volt
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UT9Q512K32E Megabit SRAM
Preliminary Data Sheet September, 2008
FEATURES 25ns maximum volt supply) address access time Asynchronous operation compatible with industry standard 512K SRAMs compatible inputs output levels, three-state bidirectional data Operational environment: Total dose: krads(Si) Immune >110 MeV-cm2/mg LETTH(0.25) MeV-cm2/mg Saturated Cross Section (cm2) bit, 2.8E-8 <1.1E-9 errors/bit-day, Adams geosynchronous heavy Packaging: 68-lead dual cavity ceramic quad flatpack (CQFP) (11.0 grams) Standard Microcircuit Drawing 5962-01511 compliant part
INTRODUCTION UT9Q512K32E RadTol product high-performance byte (16Mbit) CMOS static multi-chip module (MCM), organized four individual 524,288 SRAMs with common output enable. Memory expansion provided active chip enable (En), active output enable (G), three-state drivers. This device power-down feature that reduces power consumption more than when deselected. Writing each memory accomplished taking chip enable (En) input write enable (Wn) inputs LOW. Data eight pins (DQ0 through DQ7) then written into location specified address pins through A18). Reading from device accomplished taking chip enable (En) output enable while forcing write enable (Wn) HIGH. Under these conditions, contents memory location specified address pins will appear pins. input/output pins placed high impedance state when device deselected HIGH), outputs disabled HIGH), during write operation LOW). Perform accesses making along with common input combination discrete memory die.
A(18:0)
512K
512K
512K
512K
DQ(31:24) DQ3(7:0)
DQ(23:16) DQ2(7:0)
DQ(15:8) DQ1(7:0)
DQ(7:0) DQ0(7:0)
Figure UT9Q512K32E SRAM Block Diagram
DEVICE OPERATION UT9Q512K32E three control inputs called Enable (En), Write Enable (Wn), Output Enable (G); address inputs, A(18:0); eight bidirectional data lines, DQ(7:0). Device Enable controls device selection, active, standby modes. Asserting enables device, causes rise active value, decodes address inputs select 524,288 words memory. controls read write operations. During read cycle, must asserted enable outputs. Table Device Operation Truth Table Figure 25ns SRAM Pinout (68) Data Mode 3-state Data 3-state Mode Standby Write Read2 Read
DQ0(0) DQ1(0) DQ2(0) DQ3(0) DQ4(0) DQ5(0) DQ6(0) DQ7(0) DQ0(1) DQ1(1) DQ2(1) DQ3(1) DQ4(1) DQ5(1) DQ6(1) DQ7(1) View DQ0(2) DQ1(2) DQ2(2) DQ3(2) DQ4(2) DQ5(2) DQ6(2) DQ7(2) DQ0(3) DQ1(3) DQ2(3) DQ3(3) DQ4(3) DQ5(3) DQ6(3) DQ7(3)
NAMES A(18:0) DQn(7:0) Address Data Input/Output Enable Write Enable Output Enable Power Ground
Notes: defined "don't care" condition. Device active; outputs disabled.
READ CYCLE combination greater than (min) less than (max) defines read cycle. Read access time measured from latter Device Enable, Output Enable, valid address valid data output. SRAM Read Cycle Address Access figure initiated change address inputs while chip enabled with asserted deasserted. Valid data appears data outputs DQ(7:0) after specified tAVQV satisfied. Outputs remain active throughout entire cycle. long Device Enable Output Enable active, address inputs change rate equal minimum read cycle time (tAVAV). SRAM read Cycle Chip Enable Controlled Access figure initiated going active while remains asserted, remains deasserted, addresses remain stable entire cycle. After specified tETQV satisfied, eight-bit word addressed A(18:0) accessed appears data outputs DQ(7:0). SRAM read Cycle Output Enable Controlled Access figure initiated going active while asserted, deasserted, addresses stable. Read access time tGLQV unless tAVQV tETQV have been satisfied.
WRITE CYCLE combination less than VIL(max) less than VIL(max) defines write cycle. state "don't care" write cycle. outputs placed high-impedance state when either greater than VIH(min), when less than VIL(max). Write Cycle Write Enable-controlled Access defined write terminated going high, with still active. write pulse width defined tWLWH when write initiated tETWH when write initiated Unless outputs have been previously placed high-impedance state user must wait tWLQZ before applying data nine bidirectional pins DQ(7:0) avoid contention. Write Cycle Chip Enable-controlled Access defined write terminated latter going inactive. write pulse width defined tWLEF when write initiated tETEF when write initiated going active. initiated write, unless outputs have been previously placed high-impedance state user must wait tWLQZ before applying data eight bidirectional pins DQ(7:0) avoid contention.
OPERATIONAL ENVIRONMENT UT9Q512K32E SRAM incorporates features which allows operation limited environment. Table Operational Environment Design Specifications1 Total Dose Heavy Error Rate2 <1.1E-9 krad(Si) Errors/Bit-Day
Notes: SRAM will latchup during radiation exposure under recommended operating conditions. worst case particle environment, Geosynchronous orbit, mils Aluminum.
ABSOLUTE MAXIMUM RATINGS1 (Referenced VSS) SYMBOL VI/O TSTG PARAMETER supply voltage Voltage Storage temperature Maximum power dissipation Maximum junction temperature2 Thermal resistance, junction-to-case3 input current LIMITS -0.5 7.0V -0.5 7.0V +150°C 1.0W (per byte) +150°C 10°C/W
Notes: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections this specification recommended. Exposure absolute maximum rating conditions extended periods affect device reliability performance. Maximum junction temperature increased +175°C during burn-in steady-static life. Test MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Positive supply voltage Case temperature range input voltage LIMITS 5.5V Screen 40°C 105°C
ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* -40°C +105°C (VDD 5.0V screening) SYMBOL VOL1 VOL2 VOH1 VOH2 CIN1 CIO1 PARAMETER High-level input voltage Low-level input voltage Low-level output voltage Low-level output voltage High-level output voltage High-level output voltage Input capacitance Bidirectional capacitance Input leakage current Three-state output leakage current (TTL) (TTL) 8mA, =4.5V (TTL) 200A,VDD =4.5V (CMOS) -4mA,VDD =4.5V (TTL) 200A,VDD =4.5V (CMOS) 1MHz 1MHz VSS, (max) (max) (max) IOS2, IDD(OP) Short-circuit output current (max), (max), Inputs: 0.8V, 2.0V IOUT (max) Inputs: 0.8V, 2.0V IOUT (max) -40°C Inputs: 25°C IOUT 0.5, (max) 105°C 0.5V CONDITION 0.08 UNIT
Supply current operating 1MHz (per byte)
IDD1(OP)
Supply current operating @40MHz (per byte)
IDD2(SB)
Supply current standby @0MHz (per byte)
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method 1019. Measured only initial qualification after process design changes that could affect input/output capacitance. Supplied design limit guaranteed tested. more than output shorted time maximum duration second.
CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* -40°C +105°C (VDD 5.0V screening) SYMBOL tAVAV1 tAVQV tAXQX2 tGLQX2 tGLQV tGHQZ2 tETQX2,3 tETQV3 tEFQZ1,2,4 Read cycle time Read access time Output hold time G-controlled Output Enable time G-controlled Output Enable time (Read Cycle G-controlled output three-state time En-controlled Output Enable time En-controlled access time En-controlled output three-state time PARAMETER UNIT
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method 1019. Functional test. Three-state defined 500mV change from steady-state output voltage. (enable true) notation refers falling edge immunity does affect read parameters. (enable false) notation refers rising edge immunity does affect read parameters.
High Active Levels
Active High Levels
VLOAD 500mV VLOAD VLOAD 500mV
500mV
500mV
Figure 5-Volt SRAM Loading
tAVAV A(18:0)
DQn(7:0)
Previous Valid Data
Valid Data tAVQV
Assumptions: (max) (min)
tAXQX Figure SRAM Read Cycle Address Access
A(18:0) tETQV DQn(7:0) tETQX tEFQZ
DATA VALID
Assumptions: (max) (min)
Figure SRAM Read Cycle Chip Enable-Controlled Access
tAVQV A(18:0)
tGLQX Qn(7:0) tGLQV
ssumptions: (max) (min)
tGHQZ
DATA VALID
Figure SRAM Read Cycle Output Enable-Controlled Access
CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* -40°C +105°C (VDD 5.0V screening) SYMBOL tAVAV1 tETWH tAVET tAVWL tWLWH tWHAX tEFAX tWLQZ2 tWHQX2 tETEF tDVWH tWHDX tWLEF tDVEF tEFDX tAVWH tWHWL1 Write cycle time Device Enable write Address setup time write controlled) Address setup time write controlled) Write pulse width Address hold time write controlled) Address hold time Device Enable controlled) controlled three-state time controlled Output Enable time Device Enable pulse width controlled) Data setup time Data hold time Device Enable controlled write pulse width Data setup time Data hold time Address valid write Write disable time PARAMETER UNIT
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method 1019. Functional test performed with outputs disabled high). Three-state defined 500mV change from steady-state output voltage.
A(18:0) tAVAV2 tAVWH tETWH tAVWL Qn(7:0) tWLQZ Dn(7:0)
Assumptions: (max). (min) then Qn(7:0) will three-state entire cycle. high tAVAV cycle. APPLIED DATA
tWHWL tWHAX
tWLWH
tWHQX
tDVWH
tWHDX
Figure SRAM Write Cycle Write Enable Controlled Access
tAVAV3 A(18:0) tAVET tETEF tEFAX
tAVET tWLEF
APPLIED DATA
tETEF tEFAX
Dn(7:0)
tWLQZ Qn(7:0)
tDVEF
tEFDX
Assumptions Notes: (max). (min) then Qn(7:0) will three-state entire cycle. Either scenario above occur. high tAVAV cycle.
Figure SRAM Write Cycle Chip Enable Controlled Access
CMOS VDD-0.05V ohms VLOAD 1.55V 0.5V
50pF Notes: 50pF including scope probe test socket capacitance. Measurement data output occurs high high transition mid-point (i.e., CMOS input VDD/2). Input Pulses
Figure Test Loads Input Waveforms
DATA RETENTION MODE 2.5V 4.5V tEFR 4.5V
Figure Data Retention Waveform
DATA RETENTION CHARACTERISTICS (Pre-Radiation) *(VDD2 VDD2 (min), Pulse) SYMBOL PARAMETER TEMP MINIMUM IDDR VDD1 data retention Data retention current (per byte) -40oC 25oC 105oC tEFR1 Chip deselect data retention time Operation recovery time -2.5 tAVAV
MAXIMUM
UNIT
Notes: *Post-radiation performance guaranteed 25oC MILSTD-883 Method 1019. other inputs
PACKAGING
Notes: exposed metallized areas gold plated over nickel MIL-PRF-38535. electrically connected VSS. Packages shipped with repaired leads shown. Coplanarity requirements apply repaired area. Letter designations cross reference MIL-STD-1835. Lead true position tolerances coplanarity measured. Capacitor pads sized CDR32 (1206) capacitors.
Figure 68-Lead Ceramic Quad Flatpack
ORDERING INFORMATION 512K32 16Megabit SRAM MCM:
UT9Q512K32E
Lead Finish: Gold
Screening: Prototype flow -40oC +105oC
Package Type: 68-lead dual cavity CQFP
Device Type: =25ns access time, 5.0V operation Aeroflex UTMC Core Part Number
Notes: Prototype flow Aeroflex Colorado Springs Manufacturing Flows Document. Devices tested 25oC. Radiation neither tested guaranteed. Gold lead finish only. Extended Industrial Temperature Range flow Aeroflex Colorado Springs Manufacturing Flows Document. Devices tested -40°C +105°C. Radiation neither tested guaranteed. Gold Lead Finish Only.
512K32 16Megabit SRAM MCM:
5962 01511
Lead Finish: Gold
Case Outline: 68-lead dual cavity CQFP Class Designator: Class
Device Type (NOTE access time, 5.0V operation, (-40oC +105oC)
Drawing Number: 01511 Total Dose none (10krad(Si)) (30krad(Si)) (contact factory) (50krad(Si)) (contact factory) Federal Stock Class Designator: Options Notes: Total dose radiation must specified when ordering. Gold finish only. Aeroflex's assembly flow, defined section 4.2.2.d SMD, provides QML-Q product through that that manufac tured with Aeroflex's standard QML-V flow.
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Aeroflex Colorado Springs, Inc., reserves right make changes products services herein time without notice. Consult Aeroflex authorized sales representative verify that information this data sheet current before using this product. Aeroflex does assume responsibility liability arising application product service described herein, except expressly agreed writing Aeroflex; does purchase, lease, product service from Aeroflex convey license under patent rights, copyrights, trademark rights, other intellectual rights Aeroflex third parties.
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