Data Sheet March 2008 www.aeroflex.com/RadHardASIC FEATURES 3,500

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Data Sheet March 2008 www.aeroflex.com/RadHardASIC FEATURES 3,500

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UT0.25HBD Hardened-by-Design Standard Cell
Data Sheet March 2008 www.aeroflex.com/RadHardASIC
FEATURES 3,500,000 usable equivalent gates 2.5V Core 3,000,000 3.3V core using standard cell architecture Toggle rates Advanced 0.25 silicon gate CMOS processed commercial Operating voltage 100% 3.3V 3.3V 2.5V Input buffers 5-volt compliant Multiple product assurance levels available, military, industrial Radiation hardened from 100Krads(Si) Megarad total dose available using Aeroflex Colorado Springs's (Aeroflex) RadHard techniques SEU-immune less than 1.0E-10 errors/bits-day available using special library cells Robust Aeroflex Design Library cells macros Design support Mentor Graphics®, SynopsysTM, Verilog VHDL design languages Linux workstations Full complement industry standard cores Configurable compilers Supports cold sparing power down applications Power dissipation 0.04W/MHz/gate VDDCORE 2.5V duty cycle 0.06W/MHz/gate VDDCORE 3.3V duty cycle External chip capacitor attachment option available space quality levels (for improved response)
PRODUCT DESCRIPTION high-performance UT0.25 Hardened-by-Design ASIC standard cell family features densities 3,500,000 equivalent gates available multiple quality assurance levels such MIL-PRF-38535, military industrial grades non-RadHard versions. those designs requiring stringent radiation hardness, Aeroflex's 0.25 deep sub-micron process employs special technique that enhances total dose radiation hardness from 100Krads(Si) Megarad while maintaining circuit density reliability. addition, both greater transient radiation hardness latch-up immunity, deep submicron process built epitaxial wafers. Developed from Aeroflex's patented architectures, deep submicron ASIC family uses highly efficient standard cell architecture internal cell instantiation. Combined with state-of-the-art placement routing tools, area utilization signal interconnect transistors maximized using five levels metal interconnect. UT0.25HBD ASIC family supported extensive cell library that includes SSI, MSI, 54XX equivalent functions, well configurable cores. Aeroflex's core library includes following functions: Intel 80C31® equivalent Intel 80C196® equivalent MIL-STD-1553 functions (BRCTM, RTI, RTMP) MIL-STD-1750 microprocessor RISC microcontroller Configurable
Table Gate Densities SIZE (Mils estimate) EQUIVALENT USABLE GATES1 SIGNAL I/O2 276,890 501,760 757,350 1,024,000 1,524,122 2,007,040 2,524,058 3,029,402 POWER GROUND PADS
Notes: Based NAND2 equivalents plus routing overhead. Actual usable gate count design-dependent. Includes five pins that reserved JTAG boundary-scan, depending user requirements.
Low-noise Device Package Solutions Separate on-chip power ground buses provided internal cells output drivers which further isolate internal design circuitry from switching noise. addition, Aeroflex offers advanced low-noise package technology with multi-layer, co-fired ceramic construction featuring built-in isolated power ground planes (see Table These planes provide lower overall resistance/inductance through power ground paths which minimize voltage drops during periods heavy switching. These isolated planes also help sustain supply
voltage during dose rate events, thus preventing rail span collapse. Flatpacks available with leads; PGAs available with pins LGAs/CCGAs pins. Aeroflex's flatpacks feature non-conductive that helps maintain lead integrity through test handling operations. addition packages listed Table Aeroflex offers custom package development package tooling modification services individual requirements.
Table Packages Type Flatpack LGA/CCGA Package 132, 172, 196, 256, 304, 340, 281,
Notes: number device pads available restricted selected package. packages have additional non-connected index (i.e., index total package pins PGA). Contact Aeroflex specific package drawings. External chip capacitor attachment option available space quality levels (for improved response).
Extensive Cell Library UT0.25HBD family gate arrays supported extensive cell library that includes SSI, MSI, 54XX-equivalent functions, well other library functions. User-selectable options cell configurations include scan register elements, well output drive strength. Aeroflex's core library includes following functions: Intel® 80C31 equivalent Intel® 80C196 equivalent MIL-STD-1553 functions (BCRTM, RTI, RTMP) MIL-STD-1750 microprocessor Standard microprocessor peripheral functions Configurable (SRAM, DPsRAM) RISC Microcontroller USART (82C51) EDAC
Clock Driver Distribution Aeroflex design tools provide methods balanced clock distribution that maximize drive capability minimize relative clock skew between clocked devices. Speed Performance Aeroflex specializes high-performance circuits designed operate harsh military radiation environments. Table presents sampling typical cell delays. Note that propagation delay CMOS device function fanout loading, input slew, supply voltage, operating temperature, processing radiation tolerance. radiation environment, additional performance variances must considered. UT0.25HBD array family simulation models account these effects accurately determine circuit performance particular conditions. Power Dissipation Each internal gate driver average power consumption based switching frequency capacitive loading. Radiation-tolerant processes exhibit power dissipation that typical CMOS processes. rigorous power estimating methodology, refer Aeroflex UT0.25HBD Design Manual consult with Aeroflex Applications Engineer. Typical Power Dissipation 0.04W/Gate-MHz@2.5V 0.06W/Gate-MHz@3.3V duty cycle duty cycle
Refer Aeroflex's UT0.25HBD Design Manual complete cell listing details. Buffers UT0.25HBD gate array family offers signal locations (note: device signal availability affected package selection pinout.) cells configured user serve input, output, bidirectional, three-state, additional power ground pads. Output drive options range from 24mA. drive larger off-chip loads, output drivers combined parallel provide additional drive 48mA. Other buffer features options include: Pull-up pull-down resistors Schmitt trigger LVDS Cold Sparing
JTAG Boundary-Scan UT0.25HBD arrays provide test access port boundary-scan that conforms IEEE Standard 1149.1 (JTAG). Some benefits this capability are: Easy test complex assembled printed circuit boards Gain access control internal scan paths Initiation Built-In Self Test
Table Typical Cell Delays CELL Internal Gates INV1, Inverter INV4, Inverter NAND2, 2-Input NAND NOR2, 2-Input Output Buffers OC3325N4_C, CMOS OC3325N12_C, CMOS Input Buffers IC3325_C, CMOS .605 .455 .512 .601 4.302 6.080 3.025 3.726 4.263 5.790 2.961 3.425 OUTPUT TRANSITION PROPAGATION DELAY 2.5V .126 .123 .074 .081 .162 .124 .128 .178 .473 .474 .542 .416 PROPAGATION DELAY 3.3V .172 .195 .114 .144 .218 .193 .173 .257 .681 .648 .725 .630
Note: specifications (typical). Output load capacitance 50pF. Fanout loading input buffers gates equivalent gate input loads. core cells output buffers input slew ~.2ns. input buffer, input slew 0.4ns (slew measured from VDD).
ASIC DESIGN SOFTWARE Using combination state-of-the-art third-party proprietary design tools, Aeroflex delivers support capability handle complex, high-performance ASIC designs from design concept through design verification test. Aeroflex's flexible circuit creation methodology supports high level design providing UT0.25HBD libraries Mentor Graphics Synopsys synthesis tools. Design verification performed VHDL Verilog simulator Mentor Graphics environment, using Aeroflex's robust libraries. Aeroflex also supports Automatic Test Program Generation improve design testing. Aeroflex DESIGN SYSTEMS Aeroflex offers Hardware Description Language (HDL) design system supporting VHDL Verilog. Both VHDL Verilog libraries provide sign-off quality models robust tools. High Level Design Activities
ADVANTAGES AEROFLEX DESIGN SYSTEMS Aeroflex Design System gives freedom tools from Synopsys, Mentor Graphics, Cadence, Viewlogic, other vendors help synthesize verify design. Aeroflex's Logic Rules Checker Tester Rules Checker allow verify partial complete designs compliance with Aeroflex design rules. Aeroflex Design System accepts back-annotation timing information through SDF. Your design stays entirely within language which started (VHDL Verilog) preventing conversion headaches.
XDTsm (eXternal Design Translation) Through Aeroflex's services, customers convert existing non-Aeroflex design Aeroflex's processes. tool particularly useful converting FPGA Aeroflex radiation-tolerant gate array. translation tools convert industry standard netlist formats vendor libraries Aeroflex formats libraries. Industry standard netlist formats supported Aeroflex include: VHDL Verilog HDLFPGA source files (Actel, Altera, Xilinx) EDIF Third-party netlists supported Synopsys
Synopsys VSS/VCS
Tool Supplier
Mentor ModelSim
Viewlogic SpeedWave/
Cadence Leapfrog/ Verilog
Aeroflex Design System
Completed ASIC Design
Aeroflex Springs Design Flow VHDL libraries VITAL compliant, Verilog libraries compliant.With library capabilities Aeroflex provides, High Level Design methods synthesize your design simulation. Aeroflex also provides tools verify that your design will result working ASIC devices. Either Aeroflex's design system lets easily access Aeroflex's RadHard capabilities.
AEROFLEX MENTOR GRAPHICS DESIGN SYSTEM Aeroflex Mentor Graphics Design System software fully integrated into Mentor Graphics design environment, making familiar easy use. Aeroflex tools support Mentor functions such cross-highlighting, graphical menus, design navigation.
Design Idea
Convert FPGA
Schematic Entry Translate External Design
ADVANTAGES AEROFLEX MENTOR DESIGN SYSTEM Aeroflex customers have successfully used Aeroflex Mentor Graphics Design System over decade. Aeroflex's Logic Tester Rules Checker tools allow verify partial complete designs compliance with Aeroflex manufacturing practices procedures. Design System accepts pre-and post-layout timing information ensure your design results devices that meet your specifications. Design System supports Leonardo, database transfer between Synopsys Mentor. Design System supports powerful Mentor Graphics ATPG capabilities. TOOLS SUPPORTED AEROFLEX
Synthesis
Aeroflex supports libraries for: Mentor Graphics ModelSim Synopsys Design Compiler PrimeTime Formality TetraMax VITAL-compliant VHDL Tools OVI-compliant Verilog Tools
Aeroflex Mentor Design System
Design Manufacturing Aeroflex Mentor Graphics Design Flow After creating design Mentor Graphics environment, easily verify design electrical rules compliance with Aeroflex Logic Rules Checker. Testability verified with Aeroflex Tester Rules Checker. Both these tools fully integrated into Mentor Graphics Environment. When have completed design activities, Aeroflex's Design Transfer tool captures required files prepares them easy transfer Aeroflex. Aeroflex uses this data convert your design into packaged tested device.
TRAINING SUPPORT Aeroflex personnel conduct training classes tailored meet individual needs. These classes address wide engineering backgrounds specific customer concerns. Applications assistance also available through phases ASIC Design.
PHYSICAL DESIGN Using five layers metal interconnect, Aeroflex achieves optimized layouts that maximize speed critical nets, overall chip performance, design density 3,500,000 equivalent gates. Test Capability Aeroflex supports phases test development from test stimulus generation through high-speed production test. This support includes ATPG, fault simulation, fault grading. Scan design options available UT0.25HBD storage elements. Automatic test program development capabilities handle large vector sets with Aeroflex's LTX/Trillium MicroMasters, supporting high-speed testing 80MHz with multiplexing), Teradyne Tiger 1.2GHz). Unparalleled Quality Reliability Aeroflex dedicated meeting stringent performance requirements aerospace defense systems suppliers. Aeroflex maintains highest level quality reliability through Quality Management Program under MIL-PRF-38535 ISO9001. 1988, were first gate array manufacturer achieve certification qualification technology families. product assurance program kept pace with demands certification qualification. quality management plan includes following activities initiatives. Quality improvement plan Failure analysis program plan Corrective action plan Change control program Standard Evaluation Circuit (SEC) Technology Characterization Vehicle (TCV) assessment program Certification qualification program Because numerous product variations permitted with customer specific designs, much reliability testing performed using Standard Evaluation Circuit (SEC) Technology Characterization Vehicle (TCV). Aeroflex utilizes wafer foundry's data from test structures evaluate carrier aging, electromigration, time dependent test samples reliability testing. Data from wafer-level testing provide rapid feedback fabrication process, well establish reliability performance product before packaged shipped. Radiation Tolerance Aeroflex incorporates radiation-tolerance techniques process design, design rules, array design, power distribution, library element design. radiation-tolerance process parameters controlled monitored using statistical methods in-line testing. PARAMETER Total Ionizing Dose (TID) Dose Rate Upset (DRU) Dose Rate Survivability (DRS) RADIATION HARDNESS ASSURANCE 3.0E5 rad(SiO2) 1.0E6 rad(SiO2) >6.6E9 rad(Si)/sec latchup observed maximum dose rate equipment configuration >5.0E11 rad(Si)/sec NOTES
Single Event <2.0E-12 errors cell-day (SEU) Single Event Latchup (SEL) Latchup-immune over worst case 125oC, 2.75V 3.6V core, 3.6V VDD, >110MeV/cm2/mg Projected neutron fluence 1.0E14 n/sq
Notes: Total dose Co-60 testing accordance with MIL-STD-883, Method 1019. Data sheet electrical characteristics guaranteed 3.0E5 rads(SiO2). postradiation values measured 25°C. Datasheet electrical characteristics guaranteed 1.0E6 (SiO2). postradiation values measured 25°C. Short pulse 20ns FWHM (full width, half maximum) 25°C, 2.25V core/3.0V VDD. Short pulse 35ns FWHM (full width, half maximum) 125°C, 2.75V core/3.6V VDD. limit based standard evaluation circuit 2.25V 3.6V core/3.0V 25oC condition. SEU-hard flip-flop cell. Non-hard flip-flop typical 8E-9.
ABSOLUTE MAXIMUM RATINGS (Referenced VSS) SYMBOL VDDCORE VDDCORE TSTG PARAMETER Supply Voltage Core Supply Voltage Voltage Difference (2.5V core) Storage temperature Maximum junction temperature Latchup immunity input current Lead temperature (solder sec) LIMITS -0.3V 4.0V -0.3 2.8V -0.3 4.0V 1.35V +150°C +150°C
+150mA +10mA
+300°C
Note: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections this specification recommended. Exposure absolute maximum rating conditions extended periods affect device reliability. recommended "power-on" sequence VDDCORE voltage supply applied first, followed voltage supply. recommended "power-off" sequence reverse. Remove voltage supply, followed removing VDDCORE voltage supply.
RECOMMENDED OPERATING CONDITIONS SYMBOL VDDCORE PARAMETER Supply Voltage Core Supply Voltage LIMITS 0.3V 0.25V 0.3V
Note: must maintained voltage greater than VDDCORE 0.25V 2.5V core option.
ELECTRICAL CHARACTERISTICS (VDD 3.3V +0.3; VDDCORE 2.5V +0.25 3.3V +0.3V; -55°C +125°C) SYMBOL PARAMETER Low-level input voltage CMOS, inputs LVTLL High-level input voltage CMOS inputs inputs LVTLL Schmitt Trigger, positive going threshold1 CONDITION -55oC +125oC 3.3V 0.3V VDDCORE 2.5V 0.25V -55oC +125oC 3.3V VDDCORE 2.5V 0.25 -55oC +125oC 3.3V VDDCORE 2.5V 0.25 VTSchmitt Trigger, negative going threshold1 -55oC +125oC 3.3V VDDCORE 2.5V 0.25 Schmitt Trigger, typical range hysterisis2 Input leakage current Inputs with pull-down resistors Inputs with pull-down resistors Inputs with pull-up resistors Inputs with pull-up resistors Cold Spare Inputs Cold Spare Inputs Operating Mode VDDC 3.6V 5.5V 3.0V 4.0mA 5.0mA 8.0mA 12.0mA 24.0mA 1.0A 100.0A 1500.0A -120 0.05 0.05 0.3VDD 0.7VDD 0.5VDD 0.7VDD 0.3VDD UNIT
Low-level output voltage LVTTL buffer LVTTL buffer LVTTL buffer LVTTL buffer LVTTL buffer CMOS outputs CMOS outputs outputs
SYMBOL
PARAMETER High-level output voltage3 LVTTL buffer LVTTL buffer LVTTL buffer LVTTL buffer LVTTL buffer CMOS outputs CMOS outputs outputs
CONDITION 3.0V -4.0mA -5.0mA -8.0mA -12.0mA -24.0mA -1.0A -100.0A -500.0A Operating mode 3.6V VDDC
UNIT
VDD-0.05 VDD-0.35
Three-state output leakage current Bidirect with pull-up resistor Bidirect with pull-up resistor Bidirect with pull-down resistor Bidirect with pull-down resistor Cold Spare bidirect Cold Spare bidirect
-120
Short-circuit output current CMOS, buffer CMOS, buffer CMOS, buffer -130
COUT
Input capacitance CMOS LVTTL output capacitance 3.0mA buffer 5.0mA buffer 9.0mA buffer 12.0mA buffer CMOS output capacitance 3.0mA buffer 5.0mA buffer 9.0mA buffer 12.0mA buffer
1MHz 1MHz
1MHz
IDDQ
Quiescent Supply Current6 Group subgroups
3.6V 200K gates 400K gates 600K gates 800K gates 1000K gates 1500K gates 2000K gates 2500K gates 3000K gates 3.6V 200K gates 400K gates 600K gates 800K gates 1000K gates 1500K gates 2000K gates 2500K gates 3000K gates 12.5
Group subgroup
Group subgroup Designator:
3.6V 200K gates 400K gates 600K gates 800K gates 1000K gates 1500K gates 2000K gates 2500K gates 3000K gates
Notes: Contact Aeroflex refer prior usage. Functional tests conducted accordance with MIL-STD-883 with following input test conditions: VIH(min) 20%, VIL(max) 50%, specified herein, TTL, CMOS, Schmitt compatible inputs. Devices tested using input voltage within above specified range, guaranteed VIH(min) VIL(max). Supplied design limit guaranteed tested. MIL-PRF-38535, current density 5.0E5 amps/cm2, maximum product load capacitance (per output buffer) times frequency should exceed 3,765pF*MHz. Aeroflex specification maximum second output shorted ground maximum output voltage supply exceeding this specification will reduce current lifetime because potential joule heating. Capacitance measured initial qualification when design changes affect value. Capacitance measured between designated terminal frequency 1MHz signal amplitude <50mV RMS. inputs with internal pull-ups should left floating. other inputs should tied high low.
HP/Apollo HP-UX registered trademarks Hewlett-Packard, Inc. Intel registered trademark Intel Corporation Mentor, Mentor Graphics, AutoLogic QuickSim QuickFault QuickHDL, QuickGrade FastScan, FlexTest Advisor registered trademarks Mentor Graphics Corporation registered trademark Microsystems, Inc. Verilog Leapfrog registered trademarks Cadence Design Systems, Inc. Synopsys, Design Compiler, Test Compiler Plus, VHDL Compiler, Verilog Compiler, TestSim trademarks Synopsys, Inc.
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Aeroflex UTMC Microelectronic Systems Inc. (Aeroflex) reserves right make changes products services herein time without notice. Consult Aeroflex authorized sales representative verify that information this data sheet current before using this product. Aeroflex does assume responsibility liability arising application product service described herein, except expressly agreed writing Aeroflex; does purchase, lease, product service from Aeroflex convey license under patent rights, copyrights, trademark rights, other intellectual rights Aeroflex third parties.
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Data Sheet March 2008 www.aeroflex.com/RadHardASIC FEATURES 3,500

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