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Revision History
following table shows revision history this document.
Date 01/16/07 01/17/07 05/07/07 07/24/07 09/25/07 04/04/08 05/19/08 06/27/08 Version 1.0.1 3.0.1 Initial Xilinx release. Minor typographical edit. Added support ML506 boards. Updated "EDK Design" section. Added "Memory Interface Generator (MIG) Design" section updated "References" section. Removed SGMII design. Added lwIP demonstration. Added support ML507 boards. Updated links "References." Revision
ML505/ML506/ML507 Reference Design
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UG349 (v3.0.1) June 2008
Table Contents
Preface: About This Guide
Additional Documentation Additional Support Resources Typographical Conventions
Online Document
ML505/ML506/ML507 Reference Design
Introduction Reference Designs
Design MicroBlaze Processor PowerPC Processor. Stand-Alone Software Applications Operating System Software Applications ChipScope Serial Toolkit IBERT Design Memory Interface Generator (MIG) Design LogiCORE Endpoint Block Plus Express (x1) Design System Generator Design (ML506)
References
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
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ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
Preface
About This Guide
This user guide introduces several designs that demonstrate Virtex®-5 FPGA features using ML505 (LXT), ML506 (SXT), ML507 (FXT) Evaluation Platforms (referred collectively ML50x boards this guide). provided designs include processing systems based embedded PowerPC® processor block, MicroBlazesoft processor, integrated Tri-mode Ethernet MAC, RocketIOGTP transceiver.
Additional Documentation
following documents also available download http://www.xilinx.com/virtex5. Virtex-5 Family Overview features product selection Virtex-5 family outlined this overview. Virtex-5 FPGA Data Sheet: Switching Characteristics This data sheet contains Switching Characteristic specifications Virtex-5 family. Virtex-5 FPGA User Guide Chapters this user guide cover following topics:
Clocking Resources Clock Management Technology (CMT) Phase-Locked Loops (PLLs) Block Configurable Logic Blocks (CLBs) SelectIOResources SelectIO Logic Resources Advanced SelectIO Logic Resources
Virtex-5 FPGA RocketIO Transceiver User Guide This guide describes RocketIO transceivers available Virtex-5 platforms.
Virtex-5 FPGA RocketIO Transceiver User Guide This guide describes RocketIO transceivers available Virtex-5 platform.
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
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Preface: About This Guide
Embedded Processor Block Virtex-5 FPGAs Reference Guide This reference guide description embedded processor block available Virtex-5 platform.
Virtex-5 FPGA Tri-Mode Ethernet Media Access Controller This guide describes dedicated Tri-Mode Ethernet Media Access Controller available Virtex-5 LXT, SXT, platforms.
Virtex-5 FPGA Integrated Endpoint Block User Guide Express Designs This guide describes integrated Endpoint blocks Virtex-5 LXT, SXT, platforms used Express® designs.
XtremeDSP Design Considerations This guide describes XtremeDSPslice includes reference designs using DSP48E slice.
Virtex-5 FPGA Configuration Guide This all-encompassing configuration guide includes chapters configuration interfaces (serial SelectMAP), bitstream encryption, Boundary-Scan JTAG configuration, reconfiguration techniques, readback through SelectMAP JTAG interfaces.
Virtex-5 FPGA Packaging Pinout Specifications This specification includes tables device/package combinations maximum I/Os, definitions, pinout tables, pinout diagrams, mechanical drawings, thermal specifications.
Virtex-5 Designer's Guide This guide provides information design Virtex-5 devices, with focus strategies making design decisions interface level.
Additional Support Resources
search database silicon software questions answers, create technical support case WebCase, Xilinx website http://www.xilinx.com/support.
Typographical Conventions
This document uses following typographical conventions. example illustrates each convention.
Convention Meaning Example
Italic font
Virtex-5 FPGA References other documents Configuration Guide more information. Emphasis text address asserted after clock event http://www.xilinx.com/virtex5
Underlined Text
Indicates link page.
www.xilinx.com
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
Typographical Conventions
Online Document
following conventions used this document:
Convention Meaning Cross-reference link location current document Cross-reference link location another document Hyperlink website (URL) Example section "Additional Documentation" details. Refer "System Monitor Primitive" details. Figure Virtex-5 Data Sheet http://www.xilinx.com latest documentation.
Blue text
text Blue, underlined text
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
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Preface: About This Guide
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ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
ML505/ML506/ML507 Reference Design
Introduction
Virtex-5 family FPGAs [Ref offers designers multiple platforms with optimized balance high-performance logic, serial connectivity, signal processing, embedded processing resources. members Virtex-5 family built using second generation Advanced Silicon Modular Block (ASMBLTM) technology state-ofthe-art copper process produce industry's highest performance FPGAs. addition embedded PowerPC processor block, integrated system-level hard-IP blocks Express® (PCIe®), Tri-mode Ethernet, advanced high-speed RocketIO serial transceivers also provided through Virtex-5 FPGA family. Along with capabilities offered directly through integrated block implemented silicon, Xilinx LogiCOREIP catalog embedded processing catalog available system level designers. designers utilizing RocketIO GTP/GTX transceivers, ChipscopePro Serial Toolkit offers fastest setup begin using high speed serial channels. design using Xilinx Memory Interface Generator (MIG) tool also provided show easy design, implement, verify external memory interfaces. [Ref Offered general purpose development boards, ML505, ML506, ML507 platforms useful exercising architectural features Virtex-5 FPGAs platforms create user designs. Sharing common printed circuit board (PCB) only difference between boards FPGA: ML505 populated with Virtex-5 XC5VLX50T device ML506 populated with Virtex-5 XC5VSX50T device ML507 populated with Virtex-5 XC5VFX70T device
Virtex-5 platform contains embedded PowerPC processor block with integrated engines multi-port crossbar switch that offers designers unparalleled FPGA processing power through ML507. addressing common features ML505, ML506, ML507, this guide refers boards ML50x. Users obtain quick understanding features offered ML50x boards running demonstration content provided CompactFlash (CF) card included with each board. ML505/ML506/ML507 Getting Started Tutorial [Ref shows configure ML50x from files pre-loaded card describes what observe expected output.
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
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Reference Designs
Reference Designs
Design
ML50x platforms utilize Embedded Development (EDK) Base System Builder (BSB) wizard create embedded processing systems. wizard helps designers quickly create working embedded system using point-and-click graphical user interface (GUI) select Xilinx processor associated peripherals. Processing systems using either MicroBlaze soft processor embedded PowerPC block generated BSB. designs further customized within Xilinx Platform Studio (XPS) environment leveraging extensive peripherals offered through catalog. generated designs ML50x boards available
MicroBlaze Processor
ML50x platforms support common software applications hardware designs that utilize MicroBlaze soft processor. design page lists multiple MicroBlaze reference designs along with documentation wizard create these designs. ML505 base design (ml505_bsb_design.zip) base design out-of-the-box design which demonstrates many features offered board. ML505 design with standard addition (ml505_bsb_std_ip.zip) This design derived from base design using standard supported peripherals. additional peripherals used access more GPIO devices board. ML505 standard design with addition (ml505_bsb_std_ip_usb.zip) This design also derived from base design using standard supported peripherals. additional peripherals used provide capabilities. ML505 standard design with pcores addition (ml505_std_ip_pcores.zip) This design adds frame-buffer-based video output port base design. v4.6 DVI/VGA pcore that drives video port created using EDK's Create Import Peripheral wizard template. application demonstrating port open source Lightweight (lwIP) networking library also provided. Xilinx Ethernet xps_ll_temac used demonstrate GMII SGMII interfaces with lwIP's sockets modes Application Program Interface (API). Previous designs used LogiCORE demonstrate SGMII capability that available through peripheral. Libraries Document Collection provides additional details using lwIP networking library. [Ref
www.xilinx.com
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
Reference Designs
PowerPC Processor
addition supporting MicroBlaze soft processor designs, ML507 supports PowerPC processor designs. ML507 reference designs that Virtex-5 integrated PowerPC processor block labeled with _ppc440 suffix their names. These designs functionally equivalent MicroBlaze designs same PLBv46 peripherals offered catalog. descriptions same those listed "MicroBlaze Processor," page ML507 base design (ml507_bsb_design_ppc440.zip) ML507 design with standard addition (ml507_bsb_std_ip_ppc440.zip) ML507 standard design with addition ML505 standard design with pcores addition
strategy beginning with known good design deriving designs with additional capabilities offers quick generate variety designs ability debug designs using incremental changes.
Stand-Alone Software Applications
Stand-alone software applications (Table provided verify board functionality. These applications compiled within downloaded ML50x over JTAG download cable. Pre-built bitstreams, files, readme.txt files that explain each applications ML50x boards available Software Applications (ML505 Example)
ML505 Designs Description Complete collection stand-alone applications board test BIT, ELF, files. each application individually, select files below replace system_my_ace.ace configuration address production ML505 card. Designs ML505 Design ml505_bsb_bootloop.bit ml505_bsb_testapp_mem.elf ml505_bsb_testapp_mem.ace testapp_memory_readme.txt Design source files tutorials.
Table
Tests SRAM DDR2 memory.
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
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Reference Designs
Table
Software Applications (ML505 Example) (Cont'd)
ML505 Designs
Description Tests following peripherals:
RS232_Uart_2 LEDs_8Bit LEDs_Positions Push_Buttons_5Bit DIP_Switches_8Bit IIC_EEPROM Ethernet_MAC SysACE_CompactFlash debug_module
ml505_bsb_bootloop.bit ml505_bsb_testapp_periph.elf ml505_bsb_testapp_periph.ace testapp_peripheral_readme.txt
Plus Standard Designs ML505 Design Addition ml505_std_ip_bootloop.bit bootload_lcd.elf bootload_lcd.ace bootload_lcd_readme.txt ml505_std_ip_bootloop.bit button_led_test.elf button_led_test.ace button_led_test_readme.txt ml505_std_ip_bootloop.bit xflash.elf xflash.ace xflash_readme.txt ml505_std_ip_bootloop.bit hello.elf hello.ace hello_readme.txt ml505_std_ip_bootloop.bit hello_uart.elf hello_uart.ace hello_uart_readme.txt ml505_std_ip_bootloop.bit hello_uart_1.elf hello_uart_1.ace hello_uart_1_readme.txt ml505_std_ip_bootloop.bit iic_clock.elf iic_clock.ace iic_clock_readme.txt ml505_std_ip_bootloop.bit iic_ddr2.elf iic_ddr2.ace iic_ddr2_readme.txt Design source files tutorials. Main menu load launch file demonstrations.
Verifies functionality GPIO switches, GPIO LEDs, N-E-S-W buttons, LEDs.
Tests linear flash memory.
Exercises serial port output input functionality using libc routines.
Exercises serial port output input functionality using low-level UART driver routines UART Exercises serial port output input functionality using low-level UART driver routines UART Uses Xilinx peripheral dynamic mode along with low-level driver access clock generator chip. Uses Xilinx peripheral dynamic mode along with low-level driver access DDR2 EEPROM.
www.xilinx.com
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
Reference Designs
Table
Software Applications (ML505 Example) (Cont'd)
ML505 Designs Description Uses Xilinx peripheral dynamic mode along with low-level driver access connector's pins. Uses Xilinx peripheral dynamic mode along with low-level driver access controller.
ml505_std_ip_bootloop.bit iic_dvi_connector.elf iic_dvi_connector.ace iic_dvi_connector_readme.txt ml505_std_ip_bootloop.bit iic_dvi_controller.elf iic_dvi_controller.ace iic_dvi_controller_readme.txt ml505_std_ip_bootloop.bit iic_eeprom.elf iic_eeprom.ace iic_eeprom_readme.txt ml505_std_ip_bootloop.bit iic_fan.elf iic_fan.ace iic_fan_readme.txt ml505_std_ip_bootloop.bit iic_sfp.elf iic_sfp.ace iic_sfp_readme.txt ml505_std_ip_bootloop.bit iic_vga_in_controller.elf iic_vga_in_controller.ace ml505_std_ip_bootloop.bit piezo.elf piezo.ace ringtones.zip piezo_readme.txt ml505_std_ip_bootloop.bit testfatfs.elf testfatfs.ace testfatfs.zip testfatfs_readme.txt ml505_std_ip_bootloop.bit sysace_rebooter.elf sysace_rebooter.ace sysace_rebooter_readme.txt
Dynamic mode EEPROM access example.
Uses Xilinx peripheral dynamic mode along with low-level driver access controller. Uses Xilinx peripheral dynamic mode along with low-level driver access user-supplied module. Uses Xilinx peripheral dynamic mode along with low-level driver access input controller.
Demonstrates audio output onboard piezo speaker using ringtone RTTTL files.
Write read test file system CompactFlash card.
User-selectable loading files utilizing System controller.
Plus Standard Plus Designs ML505 Design Addition ml505_std_ip_usb_bootloop.bit usb_hpi_test.elf usb_hpi_test.ace demo.bin usb_hpi_test_readme.txt Design source files tutorials.
Tests host interface utilizing keyboard.
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
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Reference Designs
Table
Software Applications (ML505 Example) (Cont'd)
ML505 Designs Description
Plus Standard Plus PCORE Designs ML505 Design Pcore Addition ml505_pcores_bootloop.bit bootload_video.elf bootload_video.ace bootload_video_readme.txt ml505_pcores_bootloop.bit flash_hello.elf flash_hello_readme.txt ml505_pcores_bootloop.bit my_ace.elf my_ace.ace my_ace_readme.txt ml505_pcores_bootloop.bit my_plat_flash.elf my_plat_flash_readme.txt ml505_pcores_bootloop.bit slideshow.elf slideshow.ace slides.zip slideshow_readme.txt ml505_pcores_bootloop.bit simon.elf simon.ace simon_readme.txt ml505_pcores_bootloop.bit spi_hello.elf spi_hello_readme.txt ml505_pcores_bootloop.bit test_ac97.elf test_ac97.ace test_ac97_readme.txt ml505_pcores_bootloop.bit xrom.elf xrom.ace xrom_readme.txt ml505_pcores_bootloop.bit lwipdemo.elf lwipdemo.ace lwipdemo_readme.txt ml505_pcores_bootloop.bit webserver.elf webserver.ace webserver_readme.txt Design source files tutorials.
Video bootload application.
Placeholder application user-generated Linear Flash design. Loaded from Linear Flash. Placeholder application user-generated file. Loaded from CompactFlash. Placeholder application user-generated Platform Flash design. Loaded from Platform Flash. self-running audio video presentation highlighting features ML505 Virtex5 FPGA technology.
Interactive game using N-E-S-W buttons, LEDs, panel.
Placeholder application user-generated Flash design. Loaded from Flash.
Records plays back audio using AC97 controller.
Board tests/diagnostics.
Demonstrates networking functionality using lwIP sockets mode. browser based control GPIO LEDs display GPIO switch status over Ethernet. Uses LWIP mode webserver.
www.xilinx.com
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
Reference Designs
Table
Software Applications (ML505 Example) (Cont'd)
ML505 Designs Description
Plus Standard Plus PCORE Plus SGMII Designs ML505 Pcores Design SGMII Addition Design source files tutorials. ml505_pcores_sgmii_bootloop.bit lwipdemo_sgmii.elf lwipdemo_sgmii.ace lwipdemo_sgmii_readme.txt ml505_pcores_sgmii_bootloop.bit webserver_sgmii.elf webserver_sgmii.ace webserver_sgmii_readme.txt
Uses LWIP sockets mode webserver.
Uses LWIP mode webserver.
Operating System Software Applications
Along with ability stand-alone software applications, ML507 demonstrate embedded operating system (OS) based applications. using board support package (BSP) generation process described Libraries Document Collection [Ref 16], software developer create supported thirdparty After generated, customer-provided third-party tools used create based software application that runs embedded development platform. link tutorial example design generating VxWorks system image provided ML507 reference designs page. ML507 referernce design page:
ML507 VxWorks example:
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
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Reference Designs
ChipScope Serial Toolkit IBERT Design
ChipScope Serial Toolkit [Ref provides ability generate hardware design exercise Virtex-5 RocketIO GTP/GTX transceivers. Refer respective RocketIO transceiver user guides further information [Ref [Ref After querying user device part package, location system clock pin, dedicated RocketIO GTP/GTX clock pins, expected transceiver line rates, ChipScope software generates bitstream that implements Integrated Error Ratio Tester (IBERT). IBERT design easily scalable user board designs. pre-built IBERT design tutorial available ML50x boards
Figure shows overview IBERT core ML50x system.
Host Computer with ChipScope Software
ChipScope
Virtex-5 FPGA
IBERT Core
ICON Core
Parallel Cable
JTAG Connections
ML50x Board
Figure
UG349_01_040408
IBERT Core Generated Using ChipScope Software
IBERT design (ml505_ibert_4gtps.zip, ml506_ibert_4gtps.zip, ml507_ibert_4gtxs.zip) (Figure page verifies loopback connections over following interfaces that GTP/GTX transceivers: SATA Ethernet SGMII PCIe Onboard Loopback
SATA cross-over cable included with ML50x platform. Refer posted tutorials description equipment available from third-party vendors test these interfaces.
www.xilinx.com
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
Reference Designs
ML505/ML506
GTP_DUAL_X0Y4
ML507
GTX_DUAL_X0Y5
GTP_DUAL_X0Y3
SGMII SGMII LOOPBACK LOOPBACK
GTX_DUAL_X0Y4
SGMII SGMII LOOPBACK LOOPBACK
GTP_DUAL_X0Y2
SATA1 SATA1
GTX_DUAL_X0Y3
SATA1 SATA1
SATA2 SATA2
SATA2 SATA2
GTP_DUAL_X0Y1
PCIe PCIe LOOPBACK LOOPBACK
GTX_DUAL_X0Y2
PCIe PCIe LOOPBACK LOOPBACK
UG349_02_051208
Figure
IBERT Design
Note: internal RocketIO GTP/GTX loopback used with SGMII interface.
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
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Reference Designs
Memory Interface Generator (MIG) Design
tool generate SDRAM, DDR2 SDRAM, QDRII SRAM interfaces Virtex-5 FPGAs. tool takes inputs such memory interface type, FPGA family, FPGA devices, frequencies, data width, memory mode register values, forth, from user through GUI. tool generates RTL, SDC, UCF, document files output. EDIF (EDIF created after running script file, where script file tool output) files integrated with other design files. Refer Xilinx Memory Interface Generator User Guide [Ref information download tool, tool, implement memory controllers. user guide also contains information recommended constraints, trace matching, terminations schemes, clock capable rules, bank recommendations, suggestions, loopback trace signals, more. Consult this guide before implementing with external memory interface. pages ML50x design located
Figure page shows example view user interface. "References" section additional resources.
UG349_03_050908
Figure
Memory Interface Generator
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ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
Reference Designs
LogiCORE Endpoint Block Plus Express (x1) Design
LogiCORE provides designers access standard supported FPGA cores that scaled across user board designs. ML50x reference design pages contain tutorials example pre-built Endpoint Block Plus wrapper that implements single-lane Endpoint block PCIe. pages ML50x PCIe design located
tutorials describe verify Programmed Input Output (PIO) example design included with generated PCIe core using host with PCIe capability shareware PCIe software utility. Details example design available LogiCORE Endpoint Block Plus Express User Guide [Ref 26]. Endpoint Block Plus wrapper automatically connects block RAMs, GTP/GTX transceivers, reset clock modules. user customize generate wrapper using simple menu options CORE Generator GUI. options available determine correct attribute settings unneeded ports. Endpoint Block Plus solution offers most common, easy-to-use features simplify design process: Pre-implemented optimal buffering high-bandwidth applications LocalLink User Interface easy bridging other Xilinx Pre-implemented PCIe Endpoint spec required features:
Memory checking, filtering, indication user Non-memory checking Error message generation misrouted non-memory Error message generation memory miss Message Signaling Interrupt (MSI) controller
Figure page illustrates sub-systems instantiated within Endpoint block used example design. Refer Endpoint Block Plus Wrapper Express product page additional information Endpoint solution.
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
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Reference Designs
Block (Tx)
Block (Rx) Block Interface
Block (Retry)
Lane Transaction Layer Interface Transaction Layer Data Link Layer Physical Layer Lane Lane Lane Lane Lane Lane User Application Management Interface Configuration Capabilities Module Lane Transceiver Interface Transceiver(s)
Virtex-5 Endpoint Block
Power Management Interface
Configuration Status Interface
Clock Reset Interface
Miscellaneous Logic (Optional)
Clock Reset Block
UG349_04_040408
Figure
Virtex-5 Endpoint Block Plus PCIe Diagram
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ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
Reference Designs
System Generator Design (ML506)
Xilinx System Generatorfor User Guide [Ref comprehensive document that presents designers with methodology performing signal processing algorithm exploration, design prototyping, model analysis from within high-level Simulink simulation environment. System Generator extends Simulink allowing designs translated into FPGA hardware. addition, hardware co-simulation capability System Generator provides ability designs hardware development platform under control Simulink, while offering access data analysis visualization tools within MATLAB. Numerous example designs shown Xilinx System Generator User Guide available System Generator. example hardware co-simulation filter design (Figure that available System Generator presented ML506 reference design page
UG349_05_040408
Figure
System Generator Example Design ML506 Platform
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
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References
References
This section provides references documentation supporting Virtex-5 devices, tools, additional information, Documents supporting Virtex-5 FPGAs:
DS100, Virtex-5 Family Overview. DS202, Virtex-5 Data Sheet: Switching Characteristics. UG190, Virtex-5 User Guide. UG200, Embedded Processor Block Virtex-5 FPGAs Reference Guide. UG196, Virtex-5 FPGA RocketIO Transceiver User Guide. UG198, Virtex-5 FPGA RocketIO Transceiver User Guide. UG194, Virtex-5 Tri-Mode Ethernet Media Access Controller User Guide. UG197, Virtex-5 Integrated Endpoint Block User Guide Express Designs. UG193, XtremeDSP Design Considerations.
UG191, Virtex-5 Configuration User Guide. UG192, Virtex-5 System Monitor User Guide. UG195, Virtex-5 Packaging Pinout Specification.
Documents supporting Xilinx Platform Studio (XPS):
UG111, Embedded System Tools Reference Manual XTP013, Concepts, Tools, Techniques. UG081, MicroBlaze Processor Reference Guide. Libraries Document Collection.
Documents specific ML50x Evaluation Platform:
UG348, ML505/ML506/ML507 Getting Started Tutorial. UG347, ML505/ML506/ML507 Evaluation Platform User Guide.
Documents supporting IBERT: UG213, ChipScope Serial Toolkit. UG029, ChipScope Software Cores User Guide. Xilinx Memory Solutions page offers following material supporting Memory Interface Generator (MIG) tool:
WP260, Memory Interfaces Made Easy with Xilinx FPGAs Memory Interface Generator. UG086, Xilinx Memory Interface Generator (MIG) User Guide (for registered users). Demos Demand, Memory Interface Solutions with Xilinx FPGAs. Xilinx Support Memory Interface Resources (for registered users).
Documents supporting LogiCORE Endpoint block PCIe solutions:
DS551, LogiCORE Endpoint Block Plus Express Data Sheet. UG341, LogiCORE Endpoint Block Plus Express User Guide. UG343, LogiCORE Endpoint Block Plus Express Getting Started Guide.
Documents supporting LogiCORE SGMII solution: DS550, LogiCORE Virtex-5 Embedded Tri-Mode Ethernet Wrapper Data Sheet. UG340, LogiCORE Virtex-5 Embedded Tri-Mode Ethernet Wrapper Getting Started Guide.
www.xilinx.com
ML505/ML506/ML507 Reference Design UG349 (v3.0.1) June 2008
References
Xilinx Resources page includes documents supporting System Generator DSP:
System Generator Getting Started Guide, System Generator User Guide, System Generator Reference Guide,
Documents supporting additional embedded processor LogiCORE cores:
DS537, XPS_LL_TEMAC (v1.00a) Data Sheet.
XAPP1026, LightWeight (lwIP) Application Examples Application Note.
XAPP925, Reference System: Using with Cypress CY7C67300 Controller Application Note.
DS581, External Peripheral Controller (EPC) (v1.00a) Data Sheet.
DS531, Processor Local (PLB) v4.6 (v1.00a) Data Sheet. DS402, Device Control Register (DCR) v2.9 (v1.00a) Data Sheet. DS577, 16550 UART (v1.00a) Data Sheet. DS606, Interface (v1.00a) Data Sheet. DS578, PLBV46 Bridge (v1.00a) Data Sheet. DS444, Block Block Data Sheet. DS445, Local Memory (LMB) v1.0 (v1.00a) Data Sheet. DS641, Microprocessor Debug Module (MDM) (v1.00a) Data Sheet. DS452, Block Interface Controller Data Sheet. DS583, System Interface Controller (v1.00a) Data Sheet. DS573, Timer/Counter (v1.00a) Data Sheet. DS569, General Purpose Input/Output (GPIO) (v1.00a) Data Sheet. DS572, Interrupt Controller (v1.00a) Data Sheet.
XAPP778, Using Creating Interrupt-Based Systems Application Note.
DS481, Util Vector Logic Data Sheet. DS484, Util Split Operation Data Sheet. DS575, Multi-CHannel External Memory Controller (XPS EMC) (v1.00a) Data Sheet. UG081, MicroBlaze Processor Reference Guide: MicroBlaze (v7.00a). DS614, Clock Generator (v1.00a) Data Sheet. DS406, Processor System Reset Module (v2.00a) Data Sheet. DS616, PLBV46 Full Bridge (v1.00a) Data Sheet. DS643, Multi-Port Memory Controller (MPMC) Data Sheet.
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