Preliminary Version Last Updated 2/6/03 SM731 Databook
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Mobile Computer Display Controller
Preliminary Version
Last Updated 2/6/03
SM731 Databook
Silicon Motion®, Inc.
SM731 DataBook
Silicon Motion Inc.
SM731 DataBook
Notice Silicon Motion®, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice. responsibility assumed Silicon Motion, Inc. this information, infringements patents other rights third parties. Copyright Notice Copyright, 2003 Silicon Motion, Inc. rights reserved. part this publication reproduced, photocopied, transmitted form, without prior written consent Silicon Motion, Inc. Silicon Motion, Inc. reserves right make changes product specification without reservation without notice users Microsoft®, Windows®, Windows NT®, Direct3D® registered trademarks trademarks Microsoft Corporation. Macrovision®: This product incorporates copyright protection technology that protected U.S. patents other intellectual property rights. this copyright protection technology must authorized Macrovision, intended home other limited pay-per-view uses only unless otherwise authorized Macrovision. Reverse engineering disassembly prohibited
Version Number
Date
Note
registers same Lynx3DM except registers. registers other than registers have been included single chapter. Document includes 385-ball schematics ball-diagram. Several sections have been temporarily removed until final details completed. Updated headers footers. Added numerical ball list. Added panel registers 100h 119h. Completed ball diagram signal definitions. Added LVDS registers. Changed Video Registers Updated Changed Clock control, VGA, Power down control, Memory control registers. Updated section, added 2D3D registers, made changes engineering specifications. Updated Flat Panel Registers Updated Drawing Engine Registers Chapter 2D3D Registers Chapter Updated databook engineering specifications Updated databook engineering specifications Updated databook engineering specifications Added definitions MA[6:0] Power-on Configuration Table
10/10/00
11/1/00 1/16/01 2/23/01 3/29/01 5/1/01 8/15/01 9/25/01 11/20/01 1/16/02 2/25/02 4/1/02
Silicon Motion Inc.
SM731 DataBook Date
Version Number
Note
Changed SM730 SM731 Updated power configuation table Changed from ~PME VPVDD Updated NAND Tree Scan Test Order Deleted RAMDAC Block Diagram Added description Activity Output (P22) Changed following registers: CCR65_[4], CRT9E_[6], SVR4A_[6], SVR4C_[7:0], FPR100_[25:24], FPR100_[17:15], FPR100_[10:9], FPR120_[15:0] Added LVDS Transmitter Device Transition Times Diagram LVDS Specification Table Remove external memory support, 0/32 support, support. Changed register CPR00, reserved
7/11/02
2/6/03
Silicon Motion®, Inc. CONFIDENTIAL
SM731 Databook
Table Contents
Chapter Overview Chapter Initialization
SM731 Power-On Configurations
Chapter PCI/AGP Interface
Configuration Registers
Chapter Signal Descriptions
SM731 Ball Descriptions. SM731 NAND Tree Scan Testing. 4-10 General Information 4-10 NAND Tree Simulation 4-10
Chapter Display Memory Interface
Memory Configuration Page Break Look Ahead. Memory Timing Control
Chapter Drawing Engine Chapter Display Processors Chapter Zoom Video Port Video Capture Unit
Zoom Video Port. Video Capture Unit Functional Description Theory Operation
Chapter Flat Panel Interface
Digital Interface. LVDS Interfaces
Chapter Miscellaneous Functions 10-1
Video BIOS Interface. 10-1 VESA DPMS Interface 10-2 VESA DDC2B Interface 10-2 Linear tile address conversion access 10-3
Chapter Clock Synthesizers 11-1 Chapter Power Management 12-1
ACPI 12-1 ACPI Mode Sequence 12-1 Dynamic Power Management Control (DPMC) 12-4 Activity output (P22) 12-6 Deep Sleep Mode 12-6
Chapter Motion Compensation Specification 13-1
Overview. 13-1 Data Flow External System Responsibilities 13-1 Level Architecture 13-1 Instruction Format Operation 13-3
Chapter Drawing Engine 14-1
Command Interpreter 14-3 Setup Engine 14-3 Rasterizer Engine 14-3 Texture Engine 14-3 Pixel Engine 14-4 Engine 14-4
Chapter Encoder 15-1
Function Descriptions 15-3 Macrovision Antitaping Process 15-3 Closed Captioning 15-4 Synchronization 15-5
Table Contents
Silicon Motion®, Inc. CONFIDENTIAL
SM731 Databook
Sub-carrier Generation .15-5 Parallel I/F. .15-5
Chapter Power Configuration 16-1
SM731 Power-On Configurations .16-1
Chapter Register Overview Usage 17-1
Register Types .17-1 Configuration Registers .17-1 Memory Mapped Registers .17-1 Memory Mapped Registers .17-1 MMIO Write .17-2 MMIO Read .17-2 Linear Memory Write .17-3 Linear Memory Read .17-3 Mapped Register Mapped Summary .17-4
Chapter Configuration Space Registers 18-1
Configuration Space Registers. .18-2 Extended Registers .18-11
Chapter Standard Registers 19-1
Standard Registers .19-4 General Registers .19-4 Sequencer Register. .19-6 CRTC Controller Registers .19-9 Graphics Controller Registers .19-21 Attribute Controller Registers .19-26 RAMDAC Registers. .19-30
Chapter Extended Mapped Registers 20-1
Extended Registers .20-5 System Control Registers .20-5 Power Down Control Registers .20-14 Memory Control Registers. .20-18 Clock Control Registers. .20-21 General Purpose Registers .20-33 Pop-up Icon Hardware Cursor Registers .20-36 Pop-up Icon Registers .20-37 Hardware Cursor Registers .20-40 Extended Control Registers .20-42 Shadow Registers. .20-52
Chapter Flat Panel Processor Registers 21-1
Video Processor Control Registers .21-4 Flat Panel Registers .21-31
Chapter Processor Registers 22-1
Video Processor Control Registers .22-3
Chapter Drawing Engine Registers 23-1
Drawing Engine Control Registers .23-3
Chapter Video Capture Control Registers 24-1
Capture Processor Control Registers .24-2 Linear Tile Address Conversion Access .24-7
Chapter PCI/AGP Control Registers 25-1
Motion Comp Master Control Registers .25-3 Motion Compensation ICMD Control Registers. .25-6 Motion Compensation IDCT Control Registers .25-8 Host Master Control Registers .25-10 Texture Master Control Registers. .25-13
Chapter Encoder Registers 26-1
Decoder Register Descriptions .26-2 Common Register .26-2 Closed Captioning Registers .26-2
Chapter Registers 27-1 Chapter 2D3D Registers 28-1
Data Header Specification .28-6
Table Contents
Silicon Motion®, Inc. CONFIDENTIAL
SM731 Databook
Chapter Electrical Specifications 29-1
Absolute Maximum Ratings 29-1 Specifications 29-1 Specifications 29-2 Timing Specifications 29-3 Power Reset 29-3 Panel On/Off Sequence 29-5 Cycles. 29-6 Cycles 29-7 Synchronous DRAM (SDRAM) SGRAM Cycles 29-9 Flat Panel Interface Cycle Timing. 29-10
Chapter Mechanical Dimensions 30-1 Appendix Video Modes
Standard Compatible Modes VESA Super Modes Resolution Modes Resolution Modes Resolution Modes 1024 Resolution Modes 1280 1024 Resolution Modes
Appendix Popup Icon Consideration
Introduction Popup Icon Icon Pattern Memory Location Icon Pattern Icon Control Backend Icon Control backend. Video BIOS Function Call Enable/Disable Popup Icon Select Size Popup Icon. Popup Icon Location. Popup Icon Foreground Color Popup Icon Background Color Popup Icon Bitmap
Appendix Handler Programming Consideration
Introduction Background. System BIOS Consideration Int10 Vector Entry Alternate INT10 Entry
Appendix Programming [3:0] Pins
Application Notes control [3:0] Pins
Appendix Monitor Detect
Monitor Detect Detect
Appendix Timing Register Summary
Timing Register Summary
Index .I-1
Table Contents
Silicon Motion®, Inc. CONFIDENTIAL
SM731 Databook
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure System Block Diagram SM731 SGRAM Power-Up Initialization Sequence. SM731 Video BIOS Initialization Flow SM731 Diagram Package NAND Tree Connection 4-10 NAND Tree Simulation Timing Diagram 4-10 Display Data Source Video Encoder Interface Video Port Video Capture Block Diagram. Video Capture Data Flow. Capture Buffer Structure Interlaced Mode Video BIOS Configuration Interface 10-1 SM731 Protocol Flow Chart 10-3 Clocks Generator Block Diagram. 11-1 Level Architecture 13-2 Control Block Diagram 13-2 Block Diagram. 13-3 Stream Instruction 13-4 Instruction Format 13-4 Engine 14-2 Encoder Block Diagram. 15-2 Port 17-4 Port 3?4. 17-4 Memory Mapped Address Diagram 17-5 Frame Buffer Memory Space. 17-6 Power-on Reset Reset Configuration Timing. 29-3 LVDS Transmitter Device Transition Times. 29-4 Panel Power 29-5 Panel Power Off. 29-5 Timing Diagram 29-6 Timing Diagram. 29-7 Read Request with Return Data (4Qw) 29-8 SDRAM/SGRAM Read Write Cycles 29-9 Interface Timing. 29-10 Mechanical Dimensions 30-1 Hardware Cursor Popup Icon Memory Location.B-1
List Figures
Silicon Motion®, Inc. CONFIDENTIAL
SM731 Databook
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Power Configuration Ball Functions Signal Descriptions. SM731 GROUND Connections. NAND Tree Scan Test Order 4-11 SM731 Video Port Interface Compliance Setting Summary Video Capture Digital Interface Pinout FPDATA Definition DPMS Summary. 10-2 Recommended values common VCLK settings 11-2 Interface Signals Sleep Mode States 12-2 Gated Clock Trees 12-4 Instruction Flags Parameters. 13-4 Encoder Block Interface Description. 15-2 Encoder Sampling Rates 15-3 Closed Captioning Lines. 15-4 Closed Captioning Field Output Data 15-5 Closed Captioning Even Field Output Data 15-5 Power Configuration 16-1 Configuration Registers Quick Reference 18-1 Standard Registers Quick Reference 19-1 Extended Mapped Registers Quick Reference 20-1 Extended Registers Quick Reference 21-1 Memory Mapped Video Registers Quick Reference 22-1 Drawing Engine Capture Control Registers Quick Reference 23-1 Capture Control Registers Quick Reference 24-1 Motion Comp Video Registers Quick Reference 25-1 Encoder Registers Quick Reference. 26-1 Registers. 27-1 Vertex Registers 27-2 Global Look Table (700-7FF) 27-3 Registers Quick Reference 27-3 Summary Registers 28-3 Absolute Maximum Ratings 29-1 Digital Specification 29-1 RAMDAC Characteristics 29-2 RAMDAC/Clock Synthesizer Specifications 29-2 RAMDAC Specifications. 29-2 Power-on Reset Configuration Reset Timing 29-3 Switching Characteristics 29-4 LVDS Specifications 29-4 Timing MHz). 29-6 mode Timing 29-7 Timing Parameters 29-7 AGP4X Timing Parameters 29-8 SDRAM/SGRAM Memory Read Timing 29-9 Color Interface Timing. 29-10
List Tables
Silicon Motion®, CONFIDENTIAL Table Table Table Table Table Table Table Table Table
SM731 Databook
Standard Compatible Modes VESA Super Modes Resolution Modes Extended Modes 800x600 Extended Modes 1024x768 Extended Modes 1280x1024 Extended Modes 1600x1200 Extended Modes Timing Register Summary
List Tables
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Chapter Overview
SM731 power managed, low-power display controller portable devices including notebooks Tablet PCs. This device delivers full featured unique memory architecture designed enhance 3D/2D performance, enhanced multi-display capabilities, Motion Compensation DVD. ReduceONis technology that enables systems lower power consumptions, provides mechanism intelligently manage chip's internal clock core voltage each major functional block graphics chip. turning clock block that used, power consumption significantly reduced during normal operation. Thus ReduceON provides method further reducing overall system power resulting longer battery life. SM731 incorporates IEEE Floating Point Setup engine well full featured rendering engine. engine pipeline designed operate balanced manner, allowing setup million triangles second (125MHz core frequency) rasterization million pixels second. dual pipe Texture engine output million Texels second. Among other features, SM731 natively supports mapping, Alpha blend, Specular highlights Fog, Stencil planes, buffer fog, Bump Mapping, engine. SM731 integrates Mbytes on-board SGRAM (SDR) over 64-bit memory operating MHz. total maximum peak bandwidth available (1.2 Gbytes/sec) allows concurrent support large displays other processing functions optimum performance. SM731 continues support Dual Application/Dual View capabilities predecessors. addition, SM731 drive independent digital displays (dual-digital), well simultaneously drive LCD, displays (DualMon). SM731 also incorporates clock LVDS channels that drive separate panels single high resolution panel UXGA). above capabilities available under Windows 98/ME, Windows 2000, Windows future Microsoft operating systems. robust 128-bit Drawing Engine provides compromise performance. Drawing Engine supports ROPs, BitBLT, transparent BLT, pattern BLT, color expansion, line draw Alpha blending. Host interface Unit allows support with signals over 1.5V 3.3V interface. Support ACPI power states provided. high quality encoder, Core, Backend Controller RAMDAC incorporated well. SM731's Motion Compensation block, Video Processor block, Video Capture Unit provide superior video quality real-time video playback capture. When combined with performance CPUs, Motion Compensation block allows full frame playback video content without need additional hardware. Video Processor supports multiple independent full screen, full motion video windows with overlay. Each motion video window uses hardware YUV-to-RGB conversion, scaling, color interpolation. When combined with multi-view capabilities chip, these independent video streams output each display devices bilinear scaled support applications such full screen display local remote images video conferencing. SM731 designed with 0.25m, 5LM, 2.5V CMOS process technology. hierarchical layout approach provides enhanced internal timing control. addition built-in test modes signature analyzer, SM731 incorporates test which used simultaneously monitor internal signals through Zoom Video (ZV) Port Interface. capability
Overview
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
used increase fault coverage, reduce silicon validation debugging time. SM731 available 385-pin packages.
LaserDisc Tuner NTSC/PAL Camera
NTSC/PAL Decoder
Port
PCI/AGP2X/4X
SM731 16/32MB
Monitor
Flat Panel
Figure System Block Diagram SM731
Overview
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Features
High performance, power managed Motion Compensation DualMon support
Benefits
Desktop level performance within power budget notebook system Allows full frame playback content software Applications available same time across multiple display devices Single chip implementation ideal mobile systems
Dual View support Dual-Digital support Hardware support landscape/portrait rotation Tabview support Adaptive Power Management Dynamic functional block shut-down, clock control Multiple independent hardware video windows
rectangular portion primary display zoomed display multiple secondary displays Independent display support external digital monitor projector Portrait view desktop publishing, word processing applications Tablet PCs. with different orientations which Tablet PCs. (LCD portrait landscape) Reduce average power consumption when operation mode Independent full screen, motion video separate displays. Complete dual view support video
128-bit, single clock cycle Drawing Engine High performance memory interface 2X/4X sideband support panel support 1600x1200 with independent built-in LVDS transceiver channels Integrated Encoder with Macrovision 235MHz 24-bit RAMDAC Zoom Video Port PC99, PC2001 Compliant, ACPI Compliant support Microsoft Windows Windows 2000, Windows Linux (xfree86.org)
compromise graphics performance mobile systems Delivers over 1.2GB/s bandwidth support graphics, Provides interface capability today's most popular graphics busses Supports panel requirements mobile systems Graphics/video display with external support logic Supports resolutions 1600x1200 Provides support camera, tuner input, output Meets WHQL certification requirements Complete software support
Microsoft, Windows, Direct3D registered trademarks trademarks Microsoft Corporation. Regarding Macrovision: This product incorporates copyright protection technology that protected U.S. patents other intellectual property rights. this copyright protection technology must authorized Macrovision, intended home other limited pay-per-view uses only unless otherwise authorized Macrovision. Reverse engineering disassembly prohibited.
Overview
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Chapter Initialization
SM731 generates internal power-on reset during system power-on. After receiving system ~RESET signal, SM731 will release internal power-on reset circuit enter RESET period until host de-asserts ~RESET signal. During RESET period, SM731 resets internal state machines registers power-on default states. During power-on, SM731 configured based configuration lines [37:0]. Table provides detailed description each configuration line. (memory data) lines have internal pull-up resistors pads which latched into corresponding register logic rising edge (trailing edge) ~RESET. specific logic during power-on reset, external pull-down resistor must added corresponding line. addition power-on configuration, SM731 performs initialization sequence integrated memory. After memory initialization been completed, SM731's video BIOS ready service system BIOS requests. System BIOS passes pointer SM731 video BIOS start video BIOS initialization sequence.
SDCK
SDCKEN
COMMAND
PRECHARGE
LOAD MODE REGISTER
AUTO REFRESH
AUTO REFRESH
ACTIVE
High-Z
T=200us
BOTH BANKS
CODE
BANK
tMTC
POWER-UP SDCLK stable
PRECHARGE
Program Mode Register
AUTO REFRESH Cycle
AUTO REFRESH Cycle
Figure SGRAM Power-Up Initialization Sequence
Figure illustrates SM731 Video BIOS initialization flow. initialization sequence consists following stages: Load configuration table panel Initialize INT10 function Initialize hardware Query system BIOS calls initial mode Enable display
Initialization
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Start
Load default settings (Including: MCLK, AGP/PCI, Panel)
Read MD/MA line settings
AX=7500 Subsystem Subvendor
AX=7501 Primary Panel Info.
AX=7502 Secondary Panel Info.
AX=7503 Initial mode number
AX=7504 Info.
AX=7505 Expansion/ Centering Info.
AX=7506 Banner Status
AX=7507 Display Status
Memory Size
Mode
POST done
Figure SM731 Video BIOS Initialization Flow
Initialization
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
SM731 Power-On Configurations
MD[63:0], MA[11:0], MBA[1:0] have internal pull-up resistors pads external pull-down resistor external pull-down resistor
Table Power Configuration
Signal Name
MD[37]
Read/Write
Config Only
Register Address
Address
Description
selection. This hardware test feature which used debug purpose only) Definition: pllvck new,high performance pllvrck existing from SM731 pllmck existing from SM731 pllmck2 new,high performance MD[37] config (default) Vclk(video clock) pllvck VrClk(LCD Panel clock) pllvrck Mclk(Engine clock) pllmck Mclk2(memory controller clock) pllmck2 else Vclk(video clock) pllvrck VrClk(LCD Panel clock) pllvrck Mclk(Engine clock) pllmck Mclk2(memory controller clock) pllmck also definition CCR67[3:2]
MD[36:35]
Config Only
Size Base Memory selection 00=4MB 01=8MB 10=16MB 11=32MB Being used when only Endian selected 0=Small Endian 1=Big Endian 0=Only Endian 1=Both Endian Reserved
MD[34]
Config Only
MD[33] MD[32] MD[31] MD[30:25] MD[24] MD[23]
Config Only
MCR76[7]
3c5.76
0=Reserved 1=Normal (default) Reserved
MCR76[0]
3c5.76
0=SDRAM interface 1=Reserved 0=AND with RESETN reset free running clock divider simulation testing 1=Normal (default) Reserved
MD[22} MBA[1] MBA[0] Config Only Config Only
0=Enable C0000 EPROM access 1=Disable C0000 EPROM access 0=>PCI Config Reg54[2]=1=>AGP4X capable 1=>PCI Config Reg54[2]=0=>Not AGP4X capable
Initialization
Silicon Motion®, Inc. CONFIDENTIAL Signal Name
MA[11:8]
SM731 DataBook Register Address
GPR70[3:0]
Read/Write
Address
3c5.70
Description
Panel 0000 640x480 0001 800x600 0010 1024x768 0011 1280x1024 0100 1600x1200 configuration 0=For 1.5V 1=For 3.3V LVDS interface LVDS Panel R,G,B TX3-+. bits LVDS R,G,B Tx3-+. bits LVSDS (Hitachi type) Panel Sequence Software panel on/off sequence Hardware panel on/off sequence LVDS Configuration double LVDS configuration (two LVDS chips panel side) single LVDS configuration (only single LVDS receiver panel) 00=Reserved 01=Select non-LVDS panel primary panel display 10=Select LVDS1 primary panel display 11=Both LVDS1 non-LVDS panel primary panel display Reserved software purposes Reserved
MA[7]
MA[6]
MA[5]
MA[4]
MA[3]
MA[2:1]
MA[0] MD[21:0]
Note:
Windows Windows Windows Windows setting [36:35, should [111]. However, Windows setting [36:35, should [1,0,0].
Initialization
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Chapter PCI/AGP Interface
SM731 provides glue-less interface system bus. device fully compliant with Version 2.2. SM731's Host Interface Unit supports both slave master mode. maximize performance, Host Interface Unit also supports burst write, burst read with Read Look Ahead. When connected interface, SM731 supports 2X/4X with sideband. PCI/AGP Host Interface Unit manages data transfer between external PCI/AGP internal Host Interface (HIF) bus. functional blocks, with exception Drawing Engine, tied through proprietary protocol. Separate decode logic dedicated FIFO used Drawing Engine. addition Configuration Space Registers, PCI/AGP Host Interface Unit contains Power Down Control Registers (PDR20-PDR23) System Control Registers (SCR10-SCR1A). These Registers accessed even while internal PLLs turned off.
Configuration Registers
configuration registers designated CSR00 CSR3D. brief description elements register follows: Vendor register (CSR00) hardwired 126Fh identify Silicon Motion, Inc. chip vendor. Device register (CSR02) hardwired 0730h identify SM731 device. Status register (CSR06) hardwired 01b, which indicates medium speed ~DEVSEL. Class Code register (CSR08) hardwired 030000h specify SM731 compatible device. [7:0] used identify revision SM731. Memory Base Address register (CSR10) specifies configuration space address relocation. After poweron, register defaults 00h, which indicates base register located anywhere 32-bit address space that base register located memory space. Subsystem Vendor Subsystem (addressable CSR2C CSR2E respectively) 32-bit read only registers. These registers used differentiate between multiple graphics adapters within same system.
PCI/AGP Interface
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Chapter Signal Descriptions
SM731 packaged package. Table lists each ball associated signal. Figure illustrates pinout diagram SM731 package. Figure illustrates mechanical dimensions package.
SM731 Ball Descriptions
following table, Table provides listing numerical order each ball associated signal. Table offers brief description each signal used SM731 sorted functional block. Signal names with preceding active "LOW" signals, whereas signal names without preceding active "HIGH" signals. Also, following abbreviations used Type. INPUT SIGNAL Output Signal Input Output Signal `Note: Outputs signals tri-stated. Internal pull-up 100K resistor. Internal pull-down 100K resistor.
Table Ball Functions
Ball
Function
VDD2 MD31 MD30 ~SIP_AGP VDD3 VDD2 AD12 AD14 ~BE0 ~FRAME ~BE2 AD16 AD18 AD21 VDD2
Ball
Function
VDD2 VDD3 MD28 MD29 VPVDD ~AGP_BUSY AD10 AD13 ~BE1 ~TRDY ~STOP AD17 AD20 AD23
Ball
Function
VDD2 MD25 MD26 MD27 ~RBF ~PIPE AD11 AD15 ~DEVSEL ~IRDY AD19 AD22 ~BE3
Ball
Function
IDSEL AD24 AD25 MD16 MD12 MD13 MD14 DQS0 MD15 MD24 SBA7 SBA6 SBA5 SBA4 SBA3 SBA2 SBA1 SBA0 HVREF ~SB_STB SB_STB
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL Ball
SM731 DataBook Ball
Function
~AD_STB1 AD26 AD27 AD28 MD18 MD17 MD10 MD11 VDD2 VDD3 VDD2 HVDD HVDD VDD1 HVDD VDD2 AD_STB1 AD29 AD30 AD31 MD19 MD20 VDD3 HVDD AD_STB0 ~REQ ~GNT MD22 MD21 ~DQM3 MVREF ~AD_STB0 ~RST ~INTA ~DQM0 MD23 SDCKE ~DQM1 VDD2
Function
VDD2 ~DQM2 PCLK ~CAS ~RAS MA11 VDD3 VDD3 VDD3 VDD1 HVDD VDD3 VDD3 VDD1 HREF VDD2 VDD2 VDD3 VDD2
Ball
Function
VDD1 VPVDD BLANK PALCLK VDD3 VDD2 VDD2 VDD1 EXCKEN ~PDOWN MCKIN VREF SDCK ~SDCK VDD3 VDD2 VDD2 VDD1 VDD2 CRTHSYNC CRTVSYNC ~CLKRUN ACON ~DQM7 ~DQM5 ~DQM4 MA10 USR3 USR2 USR1 USR0 MD41 MD40 MD55 ~DQM6
Ball
Function
VDD2 VDD1 TEST0 TEST1 CKIN MD43 MD42 MD54 MD53 TVSS1 CVDD CVSS IREF2 MD45 MD44 MD52 MD51 VDD3 VDD1 TVDD CVBS MD47 MD46 MD50 MD49 VDD2 FPVDD FPVDD FPVDD LVDD2 LVSS2 PLLVDD PLLVSS LVSS1 LVDD1 TVSS2 AVDD AVSS2 MD56 MD57 MD38
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL Ball
AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23
SM731 DataBook Ball
AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23
Function
MD39 VDD3 MD48 ~ROM FPDE FPSCLK FPVSYNC FD11 FD14 FD15 FD19 TX7TXCLK2+ TX6TX5TX1TX2RS0 IREF GREEN MD58 MD59 MD60 MD35 MD36 MD37 FPHSYNC FPVDDEN1 FD12 FD16 FD18 TX7+ TXCLK2TX6+ TX5+ TX1+ TX2+ AVSS AVSS1 BLUE VDD2 VDD3 MD61 MD32 MD33 MD34
Function
FPVBIASEN1
FD13 FD17 FD22 FPVDDEN2 FPEN2 TX4TX0TXCLK1+ TX3SPNLCKI VDD1 VDD2 MD62 MD63 DSQ1 FPEN1 FD10 VDD2 VDD1 FD20 FD21
FPVBIASEN2
FD23 TX4+ TX0+ TXCLK1TX3+ SPNLCKO VDD1
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Table Signal Descriptions
Signal Name Type Pull-up/ Max. Pull-Down (mA) Load (pF)
Description
Host Interface (PCI AGP)
[31:0] Multiplexed Address Data Bus. transaction consists address cycle followed more data cycles. Command Byte Enables. These signals carry command during address cycle byte enable during data cycles. Parity. SM731 asserts this signal verify even parity across [31:0] C/~BE [3:0]. Cycle Frame. SM731 asserts this signal indicate beginning duration transaction. deasserted during final data cycle transaction. Target Ready. data cycle completed when both ~IRDY ~TRDY asserted same cycle. Initiator Ready. data cycle completed when both ~IRDY ~TRDY asserted same cycle. Stop. SM731 asserts this signal indicate that current target requesting master stop current transaction. Device Select. SM731 asserts this signal when decodes addresses target current transaction. Select. This input used during configuration read/write cycles. System Clock, 33MHz. 66MHz System Reset. SM731 asserts this signal force registers state machines initial default values Request (bus master mode) Grant (bus master mode) Interrupt Pipe signal. Initiates pipelined request. Signal indicates beginning duration pipelined access. Read Buffer Full. Indicates graphics device accept previously priority read data Address Strobes transfer support Inverted Address Strobes Status support Sideband address bits Sideband strobe inverted sideband strobe Power management signal bus. Power management signal bus. Host Voltage reference (AGP Voltage)
[3:0]
~FRAME
~TRDY ~IRDY ~STOP ~DEVSEL IDSEL ~RST ~REQ ~GNT ~INTA ~PIPE ~RBF AD_STB[1:0] ~AD_STB[1:0] ST[2:0] SBA[7:0] SB_STB ~SB_STB ~AGP_BUSY ~STP_AGP HVREF
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL Signal Name Type Pull-up/ Max. Pull-Down (mA) Load (pF)
pull-up
SM731 DataBook Description
Power Down Interface
~PDOWN Deep power down mode enable. When PDOWN PLLs shut down AGP/PCI pads except pads power down When deep power down mode SM731 will respond host cycle PDOWN (default) normal setting ~CLKRUN SM731 Memory activity detection depending SCR18 select ~CLKRUN select ACTIVITY power supply connected
~CLKRUN/ ACTIVITY
pull-up
ACON
pull-up
Clock Interface
PALCLK CKIN MCKIN/ TMDSCLK pull-up pull-up pull-up 27MHz clock source 14.318MHz clock (~EXCKEN Video Clock (~EXCKEN Memory Clock (~EXCKEN TMDSCLK (~EXCKEN TMDSCLK free running clock which used drive TMDS transmitter interface implementation. Note: this used secondary clock source dual panel configuration. this case configure TMDSCLK. External Clock Enable. Select external VCLK from CKIN MCLK from MCKIN. Vrclk clock used input optional, external Spread Spectrum inducer Vrclk clock tree input, connected optional, external Spread Spectrum inducer
~EXCKEN SPNLCLKO SPNLCLKI
pull-up pull-down
Flat Panel Interface
FDATA [23:0] pull-down Flat Panel Data Bits direct connection panel external TMDS transceiver. These lines programmed convey information from Panel Controller (primary display source) controller (secondary display source). Single Pixel clock mode support only. FDATA[23:22], FDATA[14:15] FDATA[6:7] driven panel type bpp. Horizontal Sync signal from Panel Controller (primary display source) Controller (secondary source). Vertical Sync signal from Panel Controller (primary display source) Controller (secondary source). Display Enable signal from Panel Controller (primary display source) Controller (secondary source). This signal used indicate active horizontal display time. Flat Panel Shift Clock. This pixel clock Flat Panel Data.
FPHSYNC FPVSYNC FPDE
pull-down pull-down pull-down
FPSCLK
pull-down
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL Signal Name
FPEN2
SM731 DataBook Pull-up/ Max. Pull-Down (mA) Load (pF)
pull-down
Type
Description
Flat Panel Enable. This signal needs become active after panel voltages, clocks, data stable. This signal also needs become inactive before panel voltages control signals removed. FPEN part VESA FPDI-1B specification. Panel Controller Controller timing source. Flat Panel Enable. This signal used control Panel power. Panel Controller Controller timing source. Flat Panel Voltage Bias Enable. This signal used control Bias power. Panel Controller Controller timing source.
FPVDDEN2
pull-down
FPVBIASEN2
pull-down
LVDS1 Interface
TX[3:0]+, TX[3:0]TXCLK1+, TXCLK1FPEN1 LVDS1 transmitter encoded data differential pairs. Data source always from Panel Controller (primary display). LVDS1 transmitter encoded clock differential pair. Source always Virtual_Clock, from Panel Controller (primary display). Flat Panel Enable. This signal needs become active after panel voltages, clocks, data stable. This signal also needs become inactive before panel voltages control signals removed. Timing source always from Panel Controller Flat Panel Enable. This signal used control Panel power. Timing source always from Panel Controller. Flat Panel Voltage Bias Enable. This signal used control Bias power. Timing source always from Panel Controller.
FPVDDEN1
FPVBIASEN1
LVDS2 Interface
TX[7:4]+, TX[7:4]TXCLK2+, TXCLK2O LVDS2 transmitter encoded data differential pairs. Data source Panel Controller (primary display) Controller (secondary display). LVDS2 transmitter encoded clock differential pair. Source Virtual_Clock, from Panel Controller (primary display) Video Clock, from Controller (secondary display).
Interface
GREEN BLUE IREF CRTVSYNC CRTHSYNC pull-down pull-down Analog Current Output Analog Green Current Output Analog Blue Current Output Current Reference Input Vertical Sync Horizontal Sync
Interface
CVBS Luminance Output Chrominance Output Composite Video Output
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL Signal Name
IREF2
SM731 DataBook Pull-up/ Max. Pull-Down (mA) Load (pF) Description
Current Reference Input
Type
Video Port Interface
[15:0] PCLK VREF HREF BLANK pull-down pull-up pull-up pull-up pull-up input/ digital output Pixel Clock VSYNC input from Card video decoder HSYNC input from Card video decoder Blank output BLANK output
General Purpose Registers
USR3 USR2 USR1 USR0 pull-up pull-up pull-up pull-up General Purpose General Purpose General Purpose I/O. USR1/ DDC2/ Data CRT. used select different test modes. General Purpose I/O. USR0/ DDC2/ Clock CRT. used select different test modes.
Test Mode Pins
TEST [1:0] pull-down Test mode selects
Reserved
RS[6:0] Reserved connect
Signal Descriptions
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SM731 DataBook
VDD2
~AGP_ BUSY
AD12
AD14
~BE0
~FRA
~BE2
AD16
AD18
AD21
VDD2
~SIP_ MD31 MD30 MD28 MD29 VPVDD
VDD3 VDD2
VDD2 VDD3
AD10
AD13
~BE1 ~TRDY ~STOP AD17 ~DEV ~IRDY AD19 SBA0 HVREF
AD20
AD23
VDD2
MD25 MD26 MD27
~RBF ~PIPE
AD11
AD15
AD22
~BE3 IDSEL AD24
AD25
MD16
MD12 MD13 MD14 DQS0 MD15 MD24
SBA7
SBA6
SBA5
SBA4
SBA3
SBA2
SBA1
~SB_S SB_ST ~AD_S AD26
AD27
AD28
MD18 MD17 MD10 MD11
VDD2
VDD3
VDD2
HVDD
HVDD
VDD1 HVDD VDD2
AD_S
AD29
AD30
AD31
MD19 MD20
VDD3
HVDD
AD_S ~REQ ~GNT ~AD_S ~RST ~INTA
MD22 MD21 ~DQM3 MVREF
SM731 Pinout
~DQM0 MD23 SDCKE ~DQM1 VDD2
VDD2
~DQM2
PCLK
~CAS ~RAS
MA11
VDD3
VDD3 VDD3
VDD1
HVDD
VDD3 VDD3
VDD1
HREF
VDD2
VDD2
VDD3 VDD2
VDD1
VPVDD BLANK PALCLK
VDD3
VDD2 VDD2
VDD1
EXCK ~PDO MCKIN VREF
SDCK ~SDCK
VDD3
VDD2 VDD2
VDD1
CRTH CRTV ~CLK ACON VDD2 SYNC SYNC USR3 USR2 USR1 USR0
~DQM7 ~DQM5 ~DQM4 MA10
MD41 MD40 MD55 ~DQM6 VDD2
VIEW
VDD1
TEST0 TEST1 CKIN
MD43 MD42 MD54 MD53
TVSS1 CVDD CVSS IREF2
MD45 MD44 MD52 MD51 VDD3
VDD1 TVDD
CVBS
MD47 MD46 MD50 MD49
VDD2
FPVDD
FPVDD
FPVDD LVDD2 LVSS2 PLLVDD PLLVSS LVSS1 LVDD1 TXCLK TXCLK
TVSS2 AVDD AVSS2
MD56 MD57 MD38 MD39 VDD3 MD48 ~ROM FPDE
FPSC
FPVS
FD11
FD14
FD15
FD19
TX7-
TX6-
TX5-
TX1-
TX2-
IREF
GREEN
MD58 MD59 MD60 MD35 MD36 MD37
FPHS FPVD DEN1
FPVBIA SEN1
FD12
FD16
FD18
TX7+
TX6+
TX5+
TX1+ TXCL TXCL
TX2+
AVSS AVSS1 BLUE SPNL SPNL
VDD2 VDD3 MD61 MD32 MD33 MD34 FPEN
FD13
FD17
FD22
FPVDD FPEN2 FPVBIA FD23 SEN2
TX4-
TX0-
TX3-
VDD1
VDD2 MD62 MD63 DQS1
FD10
VDD2 VDD1
FD20
FD21
TX4+
TX0+
TX3+
VDD1
Figure SM731 Diagram Package
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Table SM731 GROUND Connections
AVDD CVDD FPVDD HVDD LVDD1 LVDD2 PLLVDD TVDD VPVDD VDD1 VDD2
Location
W10, E12,E14,E17,F19,K19 M19, E16, K14, L14, M14, N14, P14, T19, V19, AB22, AC12, AC22 A12, A22, B23, E10, E18, H19, M11, N10, N11, P10, P11, P19, AB1, AC2, AC11 A11, K10, K11, L10, L11, M10,
Supply Voltage
3.3V 2.5V 3.3V 3.3V/1.5V AGP4x 2.5V 2.5V 2.5V 3.3V 3.3V 2.5V 2.5V/3.3V*
Description
analog power Clock analog power Flat panel interface Host interface LVDS core LVDS core LVDS analog power power port interface Core Memory power
VDD3
2.5V/3.3V*
Memory core power
GROUND AVSS AVSS1 AVSS2 CVSS LVSS1 LVSS2 PLLVSS TVSS1 TVSS2
Location
Supply Voltage
Description
AA21 AA22 A23, E11, E13, E15, E19, G19, J19, K12, K13, L12, L13, L19, M12, M13, N12, N13, N19, P12, P13, R19, U19, W11, W19, AC1, AC23
analog ground analog ground analog ground Clock analog ground LVDS core ground LVDS core ground LVDS analog ground Ground Ground Digital Ground
Signal Descriptions
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SM731 NAND Tree Scan Testing
SM731 NAND Tree scan test circuit designed verifying device being properly soldered board (NAND support SM721 only). detects opened/shorted traces signal with simple test pattern which, this particular case, only ~243 vectors length. Since NAND Tree scan test circuit uses Combination logic; therefore, clock pulses required during testing.
General Information
SM731 NAND Tree scan test circuit long chain 2-input NAND gates. first NAND chain input (signal "~ROMEN"), last chain output (signal "BLANK"). order setup SM731 NAND Tree testing, USR[3:0] pins programmed 0010h Test[1:0] pins 10h. VDD's, VSS's, Analog pins RED, GREEN, BLUE, IREF, CVBS, IREF2 included scan chain.
NandTree_out CAPTURE block) TestMode pad_input pad_input pad_input pad_input
Figure NAND Tree Connection
NAND Tree Simulation
order setup SM731 NAND Tree scan test mode, USR[3:0] Test[1:0] pins programmed 0010h respectively. NAND Tree mode, internal signal TestMode6 (active "High" signal). beginning simulation, inputs forced "1". Then, follow NAND Tree sequence change each input every 400ns, starting with input_0 (signal "~ROMEN"). Output (signal "BLANK") should clock waveform that toggles every 400ns 2.5MHz square waveform) (See Figure mismatch waveform would mean device properly soldered board.
TestMode6
Input (~ROMEN)
Input #2(MD31)
Input (MD0)
Input #4(MD30)
Input (MD1)
Input #6(MD29)
Input (MD2)
Input #8(MD28)
Output (BLANK)
Figure NAND Tree Simulation Timing Diagram
Signal Descriptions
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SM731 DataBook
Table NAND Tree Scan Test Order
NAND TREE SCAN ORDER#
Name
STOPAGP RBFN AGPBUSYN PIPEN SBA_[7] SBA_[6] SBA_[5] SBA_[4] SBA_[3] SBA_[2] SBA_[1] SBA_[0] PCIAD_[0] PCIAD_[1] PCIAD_[2] PCIAD_[3] PCIAD_[4] PCIAD_[5] PCIAD_[6] PCIAD_[7] PCIAD_[8] PCIAD_[9] PCIAD_[10] PCIAD_[11] PCIAD_[12] PCIAD_[13] PCIAD_[14] PCIAD_[15] CBE_[3] CBE_[2] CBE_[1] CBE_[0] DEVSEL IRDYN TRDYN PCIPAR STOPN FRAMEN
In/Out
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL NAND TREE SCAN ORDER#
SM731 DataBook Name
PCICLK ADSTBN_1 ADSTB_1 ADSTBN_0 ADSTB_1 SBSTBN SBSTB IDSEL PCIAD_16 PCIAD_17 PCIAD_18 PCIAD_19 PCIAD_20 PCIAD_21 PCIAD_22 PCIAD_23 PCIAD_24 PCIAD_25 PCIAD_26 PCIAD_27 PCIAD_28 PCIAD_29 PCIAD_30 PCIAD_31 PCIREQN PCIGNTN PCIRSTN INTAN ACTIVITY VPDATA_0 VPDATA_1 VPDATA_2 VPDATA_3 VPDATA_4 VPDATA_5 VPDATA_6 VPDATA_7 VPDATA_8 VPDATA_9 VPDATA_10 VPDATA_11 VPDATA_12
In/Out
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL NAND TREE SCAN ORDER#
SM731 DataBook Name
VPDATA_13 VPDATA_14 VPDATA_15 VPHSYNC VPVSYNC VPCLK PALCLK XMCK ACON ENXCLK CRTHSYNC CRTVSYNC SPNLCKI SPNLCK0 XVCK VBIASEN2 FPVDDEN2 FPEN2 FPDATA_23 FPDATA_22 FPDATA_21 FPDATA_20 FPDATA_19 FPDATA_18 FPDATA_17 FPDATA_16 FPDATA_15 FPDATA_14 FPDATA_13 FPDATA_12 VBIASEN FPVDDEN FPEN FPDE FPSCLK FPVSYNC FPHSYNC FPDATA_11 FPDATA_10 FPDATA_9 FPDATA_8 FPDATA_7
In/Out
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL NAND TREE SCAN ORDER#
SM731 DataBook Name
FPDATA_6 FPDATA_5 FPDATA_4 FPDATA_3 FPDATA_2 FPDATA_1 FPDATA_0 MEMROM EXTMEMDATA_63 EXTMEMDATA_62 EXTMEMDATA_61 EXTMEMDATA_60 EXTMEMDATA_59 EXTMEMDATA_58 EXTMEMDATA_57 EXTMEMDATA_56 EXTMEMDATA_55 EXTMEMDATA_54 EXTMEMDATA_53 EXTMEMDATA_52 EXTMEMDATA_51 EXTMEMDATA_50 EXTMEMDATA_49 EXTMEMDATA_48 EXTMEMDQS1 EXTMEMDATA_47 EXTMEMDATA_46 EXTMEMDATA_45 EXTMEMDATA_44 EXTMEMDATA_43 EXTMEMDATA_42 EXTMEMDATA_41 EXTMEMDATA_40 EXTMEMDATA_39 EXTMEMDATA_38 EXTMEMDATA_37 EXTMEMDATA_36 EXTMEMDATA_35 EXTMEMDATA_34 EXTMEMDATA_33 EXTMEMDATA_32 EXTMEMDQM_7
In/Out
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL NAND TREE SCAN ORDER#
SM731 DataBook Name
EXTMEMDQM_6 EXTMEMDQM_5 EXTMEMDQM_4 EXTMEMDSF EXTMEMWEN EXTMEMCASN EXTMEMRASN EXTMEMCSN EXTMEMCKE EXTMEMBA_1 EXTMEMBA_0 EXTMEMSCLKN EXTMEMSCKP EXTMEMMA_11 EXTMEMMA_10 EXTMEMMA_9 EXTMEMMA_8 EXTMEMMA_7 EXTMEMMA_6 EXTMEMMA_5 EXTMEMMA_4 EXTMEMMA_3 EXTMEMMA_2 EXTMEMMA_1 EXTMEMMA_0 EXTMEMDQM_3 EXTMEMDQM_2 EXTMEMDQM_1 EXTMEMDQM_0 EXTMEMDATA_31 EXTMEMDATA_30 EXTMEMDATA_29 EXTMEMDATA_28 EXTMEMDATA_27 EXTMEMDATA_26 EXTMEMDATA_25 EXTMEMDATA_24 EXTMEMDATA_23 EXTMEMDATA_22 EXTMEMDATA_21 EXTMEMDATA_20 EXTMEMDATA_19
In/Out
Signal Descriptions
Silicon Motion®, Inc. CONFIDENTIAL NAND TREE SCAN ORDER#
SM731 DataBook Name
EXTMEMDATA_18 EXTMEMDATA_17 EXTMEMDATA_16 EXTMEMDQS_0 EXTMEMDATA_15 EXTMEMDATA_14 EXTMEMDATA_13 EXTMEMDATA_12 EXTMEMDATA_11 EXTMEMDATA_10 EXTMEMDATA_9 EXTMEMDATA_8 EXTMEMDATA_7 EXTMEMDATA_6 EXTMEMDATA_5 EXTMEMDATA_4 EXTMEMDATA_3 EXTMEMDATA_2 EXTMEMDATA_1 EXTMEMDATA_0
In/Out
Signal Descriptions
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SM731 DataBook
Chapter Display Memory Interface
Memory Configuration
SM731 memory interface 64-bits wide clocked MHz, total bandwidth 1.2GB/s peak. SM731 supports both single double data rate SGRAM.
Page Break Look Ahead
standard architectures, memory controller will break cycle when agent changes. SM731 allow Wait Cycle" during agent changes preceding current agents same page.
Memory Timing Control
Memory timing control configured [7:0] [31:24] during power-on reset. They should always same. Reference Table Initialization section complete description these memory configuration bits. Note: MD[32-0] pull-up resistors pads. default configuration therefore logical during power-on reset. line external pull-down resistor needs added. After power-on initialization, software used overwrite initial setting writing MCR62 bits [7:0] correspond [7:0], MCR76 bits [7:0] correspond [31:24].
Display Memory Interface
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Chapter Drawing Engine
SM731's 128-bit Drawing Engine designed accelerate Microsoft's DirectDraw Direct3D applications. engine contains 3-operand with raster operations, source destination FIFOs, well host data FIFO. drawing engine pipeline allows single cycle operations runs memory clock speed. SM731's Drawing Engine includes several functions achieve high performance. device supports color expansion with packed mono font, color pattern fill, host BLT, stretch BLT, short stroke, line draw, others. Dedicated pathways designed transfer data between host interface (HIF) Drawing Engine, memory interface (MIF) Drawing Engine. addition, drawing engine supports rotation BIBLT block size. This feature allows conversion between landscape portrait display without need special software drivers. Drawing Engine offers several assist features. Drawing Engine supports low-resolution modes hardware arithmetic stretching allow rendered smaller back buffer scaled front buffer. SM731 also supports fast BLT, source clear during BLT, transparent BLT, programmable blter stride, page flip, alpha blending bitblt.
Drawing Engine
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Chapter Display Processors
SM731 fully independent Display Processors, which graphics data with overlaid video windows. Each processor output combined image separate display device (LCDOUT, TV). implementing processors controllers), SM731 allows Dual View/ DualMon implementations, where independent display devices used simultaneously, each with timing, resolution content. primary display processor, also referred Panel Controller, more complex than secondary processor (referred "Video processor" controller) because back-end specifically designed drive panels. built controls registers that specific those display devices. Section "Flat Panel Registers" details registers primary display processor while section "CRT Controller registers" details registers secondary display processor. order accommodate wider range applications, some SM731 display interfaces display data from either processor, according diagram below. interface data path controlled register FPR100.
Display Processor
Panel Controller
LVDS1
LVDS2
Display Processor
Controller Digital
Encoder
Figure Display Data Source
Each display processor it's support index mode well gamma correction. size list 256x24. Each display processor also it's hardware cursor (32x32) icon generator.
Display Processors
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Chapter Zoom Video Port Video Capture Unit
Zoom Video Port
SM731's Zoom Video Port Port) designed interface with video solutions implemented PCMCIA CardBus) cards: examples NTSC/PAL decoders, MPEG-2 decoders, JPEG Codecs. Port also directly interface with NTSC/PAL decoder, such Phillips 7111 BT819. Figure illustrates example Phillips video encoder interface Port. Incoming video data from Port interface format. data interlaced non-interlaced. Port configured output video capture function disabled. 18-bit graphics video data format sent when Port configured output mode. Port also configured test port. signals from each logic blocks within SM731 brought internal test Bus) connected Port. System designers silicon validation engineers access these signals setting TEST0, TEST1, USR0, USR1, USR2 pins. This approach bring total internal signals primary pins. test port capability used enhance fault coverage, well reduce silicon validation debugging time. Table lists signal definitions following Port interface configurations: input mode, input mode, graphics/video (output mode).
Philips SAA7110/ SAA7111
SM731
[7:0] [7:0]
Video NTSC/PAL Signal
[7:0] [7:0] HREF VREF PCLK
HREF
Figure Video Encoder Interface Video Port
Zoom Video Port Video Capture Unit
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Table SM731 Video Port Interface Compliance
Video Port Interface
VREF HREF BLANK PCLK
Port (Input mode)
HREF (note1) PCLK
NTSC/PAL Decoder (Input mode)
HREF (note1) PCLK
Graphics/Video (Output mode)
BLANK PCLK G3/Vindex_[7] G2/Vindex_[6] G7/Vindex_[5] G6/Vindex_[4] G5/Vindex_[3] G4/Vindex_[2] G3/Vindex_[1] G2/Vindex_[0]
Note BLANK used TVCLK output, which independent port. Note Vindex [7:0] indexed video Note test internal only
Video Capture Unit
Video Capture Unit captures incoming video data from Port then stores data into frame buffer. Video Capture Unit support several features maintain display quality, balance capture rate: 2-tap, 3-tap, 4-tap horizontal filtering reduction horizontal vertical frame size 4:2:2, 4:2:2 with byte swap, 5:5:5, 5:6:5 Multiple frame skipping methods Interlaced data non-interlaced data capture Single buffer double buffer capture Cropping
SM731 uses Video Processor block display captured data LCD, display. captured data displayed through Video Window Video Window stretching, color interpolation, YUV-to-RGB conversion, color functions performed Video Processor. SM731's Video Processor simultaneously process captured video data perform CD-ROM playback independent video windows. SM731 also supports real-time video capture hard drive system memory through master mode slave mode. master mode, SM731 uses Drawing Engine's Host Host functions maximize performance.
Zoom Video Port Video Capture Unit
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Functional Description
SM731's Video Capture Unit supports Video Port Extension (VPE) specification video stream processing. This capture unit includes CLIP block, FILTER block, SHRINK block, FIFO control block. Figure Figure illustrate SM731 Video Capture Block Diagram Data Flow. CLIP functional block used select desired rectangles from video stream captured. VPR40 register (Video Source Clipping Control) used define upper left corner rectangle from video source. VPR44 register (Video Source Capture Size Control) used define height width rectangle from video source.
Video Stream from Port Display Memory CLIP Screen Graphics
FILTER Drawing Engine Interface Block
SHRINK
Capture Buffer
VPR1C
Video Window
VPR48 FIFO
Capture Buffer
VPR30
Video Window
VPR4C
Figure Video Capture Block Diagram
FILTER functional block controls horizontal filtering logic. CPR00 (Capture Port Control) used select tap, tap, filtering. SHRINK functional block used only reduce storage area both display memory hard drive, also increase performance video capture video playback. CPR00 used enable vertical reduction, used enable horizontal reduction. With filter shrink functions, SM731 able achieve high video capture performance maintain optimal video playback quality. CPR00 select different frame skipping options event capture rate less than incoming video stream. CPR00 used support interlaced capture double buffer capture. CPR00 used control/status bits Buffer Buffer captured data displayed either Video Window Video Window video capture driver needs program VPR1C VPR30), Video Window Source Start Address, with same address value from Capture Port Buffer Start Address register. VPR00 (Miscellaneous Graphics Video Control) used automatically display capture data Video Window without programming VPR1C register. This feature independent single buffer double buffer mode.
Zoom Video Port Video Capture Unit
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From
Vide
Supp lier
VPR40 [25:16] VPR44 [10:0]
VPR40 [9:0]
cropping
VPR44 [26:16]
filtering scaling
capture data
capture buffer
Figure Video Capture Data Flow
Theory Operation
Initialization Enable Video Capture (CPR00 Preset Buffer Buffer Status/Control bits (CPR00 [2:1] 11b) Enable Drawing Engine (DPR0E Select Host Read Command function (DPR0E [3:0] =9h) Enable master mode (SCR17 Select Field Detection, VREF/HREF polarity, Vertical/Horizontal Reduction, Horizontal Filtering, Video Capture Input Data Format, Frame Skip, Interlaced/non-interlaced other miscellaneous settings (CPR00, Capture Port Control Register)
Zoom Video Port Video Capture Unit
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Table Setting Summary Video Capture
Continuous Capture Conditional Capture Single Buffer Double Buffer Non-interlaced Mode Interlaced Mode
Buffer Status/Control (CPR00
Buffer Status/Control (CPR00
Video Capture Unit supports following types capture modes: Single Buffer Mode with Continuous Capture Single Buffer Mode with Conditional Capture Double Buffer Mode with Continuous Capture Double Buffer Mode with Conditional Capture Interlace Non-Interlaced Mode
summary each video capture modes follows: Single Buffer Mode with Continuous Capture Video Capture Unit (VCU)
Continuously capture incoming video data capture buffer Independent bits
Drawing Engine (DE)
recommended Drawing Engine transfer captured data from display memory hard drive system memory this mode. This mode used view captured data only.
Video Processor (VP)
VPR00 Captured data displayed either Video Window Video Window setting video window start address register. VPR00 Captured data automatically displayed Video Window
Single Buffer Mode with Conditional Capture Video Capture Unit (VCU) Drawing Engine (DE)
Test will activate transfer captured data from capture buffer hard drive system memory will after completes frame step
Video Processor (VP)
VPR00 Captured data displayed either Video Window Video Window setting video window start address register. VPR00 Captured data automatically displayed Video Window
monitors start capture will reset after completes frame step
Zoom Video Port Video Capture Unit
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Continuously capture incoming video data into capture buffer buffer Automatically switch from buffer other when completes frame Independent bits
SM731 DataBook
Drawing Engine (DE)
recommended transfer captured data from display memory hard drive system memory this mode. This mode used view captured data only.
Video Processor (VP)
VPR00 Captured data displayed either Video Window Video Window setting video window start address register. VPR00 Captured data automatically displayed Video Window capture buffer used VCU, Video Window will display captured data from capture buffer
Double Buffer Mode with Conditional Capture Video Capture Unit (VCU) Drawing Engine (DE)
monitors B2S) will activate transfer captured data from capture buffer 1(or buffer hard drive system memory will B2S) after completes frame will continuously transfer Data from capture buffer step both bits
Video Processor (VP)
VPR00 Captured data displayed either Video Window Video Window setting video window start address register. VPR00 Captured data automatically displayed Video Window capture buffer used VCU, Video Window will display captured data from capture buffer
monitors bits B2S) start video capture store into capture buffer buffer will reset B2S) after completes frame will continue video capture step both bits
Interlaced Capture
CPR00 bits used select interlaced capture mode. most video capture applications, interlaced video stream will treated non-interlaced video stream dropping even frames (CPR00[13:11] 010b), dropping frames (CPR00[13:11] 011). This approach will reduce artifacts when playing back captured data. However, some video capture applications, de-interlacing needed handle incoming interlaced video stream. de-interlacing case, CPR00 needs enable interlaced capture incoming interlaced video stream. double buffer mode (CPR00 needs turned same time. Capture Buffer Capture Buffer combined together single buffer with line offset. Figure illustrates capture buffer structure. video capture driver will preset bits initialize buffer status/control bits. Video Capture Unit will start video capture After fills capture buffer both bits VCU. video capture driver will activate Drawing Engine transfer captured data capture buffer system memory hard drive when both "0". After completion transfer, Drawing Engine will both "1". Video Capture Unit then continues video capture repeats same protocol. During video playback, captured data displayed either Video Window Video Window recommended display both even frame frame video playback. video captured driver program Video Window Source Start Address Register Video Window Source Width Offset Register such that frame even frame) captured data will dropped during video playback. scaling, color interpolation, YUV-to-RGB conversion functions also enabled same time.
Zoom Video Port Video Capture Unit
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Even Field From Video Capture Unit Drawing Engine Video Processor
Field
Even Field
Capture Buffer
Capture Buffer
Even Field
Field
Even Field
Figure Capture Buffer Structure Interlaced Mode
Zoom Video Port Video Capture Unit
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SM731 DataBook
Chapter Flat Panel Interface
SM731 directly drive panels equipped with CMOS digital interface and/or panels with LVDS interface. There independent display controllers inside SM731: Panel controller also referenced Primary Controller Controller also referred Secondary Controller. Because this, SM731 able drive screens with different images, from separate frame buffers independently programmable timing resolution. Furthermore, panels programmed display images from either controller, with some restrictions. Section Display Processors. Digital Interface drive data from either Panel Controller controller, just like LVDS2 interface. LVDS1 interface hardwired drive data from Panel controller (primary display). digital interface LVDS2 interface both turned drive single pixel panels, their data source same either from Panel controller controller. There will restriction only interface single pixel panel LVDS2 used double pixel panel.
Digital Interface
digital interface wide programmed drive 18bpp displays. image source, along with corresponding control signals (syncs, shift clock power control), selectable between Primary (FP) Secondary (CRT) controllers through control FPR100[5]. FPR100[5] interface drives data control signals from Panel controller (Primary). FPR100[5] Interface drives data control signals from controller (Secondary).
Table Digital Interface Pinout
Digital Interface Pinout
FDATA [23:0] Flat Panel Data Bits direct connection panel external TMDS transceiver. These lines programmed convey information from Panel controller (primary display source) controller (secondary display source). Single Pixel clock mode support only. FDATA[23:22], FDATA[15:14] FDATA[7:6] driven panel type bpp. Horizontal Sync signal from Panel controller (primary display source) controller (secondary source). Vertical Sync signal from Panel controller (primary display source) controller (secondary source). Display Enable signal from Panel controller (primary display source) controller (secondary source). This signal used indicate active horizontal display time. Flat Panel Shift Clock. This pixel clock Flat Panel Data. Flat Panel Enable. This signal needs become active after panel voltages, clocks, data stable. This signal also needs become inactive before panel voltages control signals removed. FPEN part VESA FPDI-1B specification. Panel controller controller timing source. Flat Panel Enable. This signal used control Panel power. Panel controller controller timing source.
FPHSYNC FPVSYNC FPSCLK FPEN2
FPVDDEN2
Flat Panel Interface
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FPVBIASEN2
SM731 DataBook
Flat Panel Voltage Bias Enable. This signal used control Bias power. Panel Controller Controller timing source.
Table FPDATA Definition
FPDATA Definition
FPDATA23 FPDATA22 FPDATA21 FPDATA20 FPDATA19 FPDATA18 FPDATA17 FPDATA16 18bpp, single pix/clk panel Drive Drive 24bpp, single pix/clk panel
FPDATA15 FPDATA14 FPDATA13 FPDATA12 FPDATA11 FPDATA10 FPDATA9 FPDATA8
Drive Drive
FPDATA7 FPDATA6 FPDATA5 FPDATA4 FPDATA3 FPDATA2 FPDATA1 FPDATA0
Drive Drive
LVDS Interfaces
LVDS interfaces used drive independent panels, displaying data from Primary controller other displaying data from Secondary controller. They also combined drive single, pixels clock, high resolution panel. Each LVDS block compresses bits data bits timing into four differential
Flat Panel Interface
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SM731 DataBook
wire pairs, MBytes second maximum clock rate MHz. fifth differential pair transmits interface clock. This way, each LVDS block drive SXGA+ panel (1400x1050x24 @60Hz). LVDS1 Interface hardwired Panel Controller (Primary). programmed drive panels, and, used conjunction with LVDS2 Interface, used drive channel, pixels clock panel QXGA size (2048x1536). Associated with LVDS1 interface following control signals, whose timing source always Primary Controller: FPEN1, FPVDDEN1 FPVBIASEN1.
Flat Panel Interface
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Chapter Miscellaneous Functions
This chapter describes functions SM731 such Video BIOS interface, VESA DPMS, VESA DDC2B.
Video BIOS Interface
Video BIOS contains code chip power-on initialization, graphics mode setup, various read/write routines frame buffer. Video BIOS burned into separate video BIOS EPROM (this typical case add-in cards) integrated into system BIOS (this typical case motherboard graphics implementation). support separate video BIOS access, BIOS address decode must enabled setting CSR30 (Expansion Enable Base Address Register) implementations where video BIOS integrated into system BIOS ROM, BIOS address decode access must disabled clearing CSR30 Figure shows external video BIOS configuration interface SM731. ~ROMEN (ROM Enable) signal from SM731 connects signals BIOS ROM. Since video BIOS address data shared with video memory data (MD) lines, programmers must ensure that memory inactive when reading from Video BIOS ROM. this case, Video BIOS must read shadowed (typically system memory C0000) immediately after reset. Direct physical access Video BIOS must then disabled prevent interference with ensuing graphics operations.
64Kx8 SM731
[7:0] [47:32] ~ROMEN
BIOS
[7:0] [15:0]
Figure Video BIOS Configuration Interface
Miscellaneous Functions
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SM731 DataBook
VESA DPMS Interface
SM731 supports VESA Display Power Management Signaling (DPMS) direct programming PDR22 (LCD Panel Control Select Register) bits through implementation chip's power down states. Table shows VESA DPMS states methods entering each DPMS states.
Table DPMS Summary
DPMS State
Standby Suspend
HSYNC State
Pulses pulses Pulses pulses
VSYNC State
Pulses Pulses pulses pulses
State
Active Blank Blank Blank
Direct Programming Method
PDR22 [5:4] PDR22 [5:4] PDR22 [5:4] PDR22 [5:4]
Power Down State Method
Automatic Standby DPMS when enter Standby mode state
CCR69[2]=0 selects Suspend DPMS state when Sleep mode CCR69[2]=1 selects DPMS state when Sleep mode
VESA DDC2B Interface
SM731 provides dual ports I2C-Bus through [3:0] pins various applications such VESA's DDC2B monitor interface. recommended USR1 USR0 primary port signals Bus. USR3 USR2 reserved secondary port. GPR72 (User Defined Register GPR73 (User Defined Register defined support I2C/DDC2 protocol. SM731, master controller only, designed initiate transfer, generate clock signal, terminate transfer slave component. SM731's I2C-Bus interface designed interface with NTSC/PAL decoders, EEPROMs, audio decoders, others. operation voltage [3:0] pins controlled VPVDD, which configured 3.3V. Each [3:0] pins internal pull-up resistor. enable data (SDA) clock (SCL) from SM731's primary port, GPR72 (3C5h index 72h) must "11". drive logic line (USR1) line (USR0), program GPR72 "0". read back from GPR72. Figure shows basic I2C-Bus protocol SM731 master transmitter.
Miscellaneous Functions
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Yes, Check GPR72 [3:2]
Busy?
Initiate Start
Send 7-bit Slave Address with R/~W
Check GPR72[3]
from slave?
Time Out?
optional
Send Byte Slave Address
Abort Transfer
Check GPR72[3]
from slave?
Time Out?
Send Byte Slave Address
Abort Transfer
Check GPR72[3]
from slave?
Time Out?
Last Byte?
Abort Transfer
Stop Transfer
Figure SM731 Protocol Flow Chart
Linear tile address conversion access
order access frame buffer tile mode during time application (software idea about tile format memory), internal hardware make address conversion address right tile location. additional information Chapter Video Capture Control Registers.
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Chapter Clock Synthesizers
SM731 integrates three programmable clock synthesizers memory clock (MCLK), Video Clock (VCLK), Video Clock 2(VCLK2). VCLK1 utilized standard only, only, CRT/LCD display modes which refresh rate both devices same. VCLK2 utilized when Virtual Refresh mode implemented this case, VCLK1 utilized panel timing clock panel display block within SM731. VCLK2 utilized clock interface independently LCD/CRT display modes independently clock various functional blocks within device save power under only display mode. Please Virtual Refresh discussion under Power Management section additional details regarding power saving capabilities under Virtual Refresh architecture. Figure illustrates control logic MCLK, VCLK, VCLK2. figure also shows clock generator module WFIFO (WFIFOCLK), RFIFO (RFIFOCLK), (RAMCLK), Video Capture (VCMCLK), Drawing Engine (DPMCLK), Video Processor (VPCLK). TVCLK used external analog encoder (this clock either derived from 14.318MHz base clock NTSC, from separate 17.734480MHz clock source connected input signal PALCLK PAL).
SLEEP STANDBY CCR68_6 CCR68_7 ~EXCKEN PD20_5 VCLK2 CKIN PLL1 1/16 CKIN PLL3 ~EXCKEN 1/16 MCLK VCLK PD20_4 CCR69_0 CCR69_1 FPR31_7
VRCLK
VCLK
VCLK
VCLK2
WFIFOCLK RFIFOCLK RAMCLK
VCLK2
VCLK MCLK PDR21[5:0] STANDBY
MCKIN PLL2
CLOCK GENERATOR
VCMCLK DPMCLK VPCLK TVCLK
1/16 SLEEP AUTO_OFF
MCLK
Figure Clocks Generator Block Diagram
VCLK programmed using VCLK Numerator Register (VNR), CCR6C, VCLK Denominator (VDR) Post Scalar (PS) register, CCR6D. VCLK frequency based following equation:
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VCLK 14.31818
post scalar used support VCLK frequencies which need large number. With enabled, number original number. This helps reduce jitter maintain accuracy. VCLK2 programmed using VCLK2 Numerator Register (VCLK2NR), CCR6E, VCLK Denominator (VCLK2DR) register CCR6F. VCLK2 frequency based following equation:
VCLK2NR VCLK2 14.31818 VCLK2DR
Table Recommended values common VCLK settings
Resolution Mode
640x480 640x480 640x480 800x600 800x600 800x600 1024x768 1024x768 1024x768 1280x1024 1280x1024 1280x1024 1400x1050 1400x1050 1400x1050 1600x1200 1600x1200 1600x1200
Ref. Rate
60Hz 75Hz 85Hz 60Hz 75Hz 85Hz 60Hz 75Hz 85Hz 60Hz 75Hz 85Hz 60Hz 75Hz 85Hz 60Hz 75Hz 85Hz
VCLK (MHz)
25Mhz 31Mhz 36Mhz 40Mhz 49Mhz 56Mhz 65Mhz 78Mhz 94.5Mhz 104Mhz 134Mhz 157Mhz 122Mhz 149MHz 181Mhz 161Mhz 202Mhz 229Mhz
Notes: numbers hard coded modes. Post scalar enabled.
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MCLK programmed using MCLK Numerator Register (MNR), CCR6A, MCLK Denominator Register (MDR), CCR6B. MCLK frequency based following equation:
MCLK 14.31818
Clock Synthesizers
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Chapter Power Management
SM731 supports three type power management:
ACPI ACPI requirements defined Management Interface Specification (PPMI v1.0) Display device Class Power Management Specification v1.0a. Dynamic Power Management Control Silicon Motion's proprietary pattern pending scheme control clock rate under different operational modes. control mechanism provides control external voltage regulator achieve power saving under normal operations. Deep Sleep pads turned off.
ACPI
SM731 supports D0-D3 modes operation software programming Power Management Control/Status Register PMSCR[1:0]. required Management Interface Specification; Configuration Space Status Register (offset 06h) indicate capabilities have been defined SM731. offset 34h, Cap_Ptr register, stores offset capabilities (this register hardwired 40h). first byte offset value 01h, which indicates Power Management capability (supports states addition required power states). second byte value indicating additional capability features. (Note: SM731 does offer support optional ~PME capabilities defined PPMI v1.0. Please refer Power Management Interface Specification Display Device Class Power Management Reference Specification v1.0a additional details). SCR24_[0] enable ACPI function. ACPI state (stand mode), most clocks shut down only maintain minimum operational modes such screen refresh. ACPI states (suspend sleep modes), clocks shut down. DRAM enters self refresh mode, PDR20_[7] need enable these states. Display driver support ACPI under Windows future versions Windows will provided Silicon Motion accordance with PC97 PC98 requirements. power management controlled ACPI states according standards. power management power sequencing controlled FPEN, FPVDD, VBIAS control pins. Please refer flat panel register FPR100 details.
ACPI Mode Sequence
PDR24_[0] (ACPI enable) PDR20_[7]=1 (Enable Sleep Mode) PDR20_[6] (self DRAM refresh) SCR25_[1] power down AGP4xpll. PDR21_[4] Shut pixel shift clock PDR20_[1] Turn panel data pains FPR100_[13:12] Power LVDS module Clock divider
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PDR20_[5:4] Enable clock divider Sleep mode CCR9E_[7:0] Memory clock divide, other clocks divide Activate ACPI mode
Table Interface Signals Sleep Mode States
Signal Name
Host Interface [31:0] [3:0] ~FRAME ~TRDY ~IRDY ~STOP ~DEVSEL IDSEL ~RST ~REQ ~GNT ~INTA Power Down Interface ~PDOWN ~CLKRUN Clock Interface REFCLK/PALCLK CKIN LVDSCLK ~EXCKEN Memory Interface [11:0] [63:0] ~RAS ~CAS [1:0] ~DQM [7:0] (note tri-state open-collector tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state
Sleep Mode
Power Management
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SDCKEN ~ROMEN Flat Panel Interface FDATA [23:0] FPSCLK FPEN FPVDDEN VBIASEN LP/FHSYNC FP/FVSYNC Interface CRTVSYNC CRTHSYNC Video Port Interface [15:0] PCLK VREF HREF BLANK/TVCLK General Purpose Registers/I USR3 USR2 USR1/SDA USR0/SCL Test Mode Pins TEST [1:0]
SM731 DataBook Sleep Mode
(self-refresh), (CAS-b-RAS) depends
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Table Gated Clock Trees
Clock Tree name
Video Capture Video Video Wfifo Engine Motion Comp Engine CLUT CLUT Encoder SVHS pix.Shift PwrDown
Control Register (1=disable unless noted)
PDR21_[2] PDR21_[0] PDR21_[4] PDR21_[5] PDR21_[1] CCR66_[1] CCR66_[0] PDR21_[7] CCR66_[6] CCR6_[7] CCR65_[5](1=enable) CCR65_[6](1=enable) CCR65_[7](1=enable) PDR21_[3] PDR21_[6]
Sleep
effect effect
Standby
effect effect effect
Dynamic Power Management Control (DPMC)
DPMC different from ACPI power-down mode, used minimize power usage under normal operation without going "sleep" mode. major functional blocks have their gated clock tree which shut down independently software control. DPMC also dynamically control engine clock memory clock rate achieve power savings, clock rate adjustment controlled look table (register CCR94 CCR9D). Depending state DPMC, clock rate adjusted automatically. DPMC three states normal, save, idle. These states depend power on/off, activity, engine on/off.
enable dynamic power management control
PDR23_[7] disable DPMC enable DPMC
DPMC interrupt
"ACON" system provided input status control signal. "ACON" means power off. Saving battery power) becomes important. "ACON" means power Once DPMC enabled(PDR23_[7]=1) SM731 generate interrupt monitoring ACON pin. When ACON input status changes from 0->1 from 1->0 interrupt will software generated control DPMC.
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DPMC interrupt control register bits
SCR1C_[1] DPMC interrupt status SCR1F_[5] DPMC interrupt enable Disable DPMC interrupt Enable DPMC interrupt SCR1F_[1] DPMC interrupt mask bit: interrupt mask Mask DPMC interrupt
DPMC States
Once DPMC enabled, there states: Normal state: "ACON" status DPMC will stay power "Normal" state. DPMC will always stay this state PDR23_[7] engine clock rate determined CCR6A/CCR6B engine (CCR6A CCR98)/CCR6B engine memory clock rate determined CCR63/CCR64 (CCR63 CCR99)/CCR64 PowerSave state: "activity detection" detect power off) activities, DPMC will "PowerIdle" state. Otherwise DPMC will stay "PowerSave" state. engine clock rate determined (CCR6A CCR94)/CCR6B engine (CCR6A CCR9A)/CCR6B engine memory clock rate determined (CCR63 CCR95)/CCR64 (CCR63 CCR9B)/CCR64 PowerIdle state: "activity detection" detected (Bus idle) activity DPMC return "PowerSave" state. Otherwise stay "PowerIdle" state. engine clock rate determined (CCR6A CCR96)/CCR6B engine (CCR6A CCR9C)/CCR6B engine memory clock rate determined (CCR63 CCR97)/CCR64 (CCR63 CCR9D)/CCR64
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SM731 control logic monitor host activities. DPMC programmed define long takes wake from idle states what kind activity detection should monitored DPMC wake following. PDR23_[6:5] detect Memory write/read write/read capture enable detect memory write write capture enable detect memory write/read capture enable detect write/read capture enable PDR23_[3:0] Timer control count number VSYNC (CRT timing). there activities specified period, power management will enter "idle" mode. 0000 Disable activity detection 0001 VSYNC 0010 VSYNC 0011 VSYNC 0100 VSYNC 0101 VSYNC 0110 VSYNC 0111 VSYNC 1000 VSYNC 1001 VSYNC 1010 VSYNC 1011 VSYNC 1100 128K VSYNC 1101 192K VSYNC 1110 256K VSYNC 1111 384K VSYNC
Activity output (P22)
There Activity output which used control external power regulator adjust core achieve power savings. SCR18_[7] Select ~CLKRUN input P22. There Activity output this case. This mode considered alternative implementing ReduceOn. Activity available, appropriate note further details). Select Activity output P22. This Activity will always "ACON" input high; otherwise, output will controlled CCR65_[4]: Output status Output high status Note: Silicon Motion software implements this ReduceOn control which will control external power regulator. Activity low, then will 2.5V. Activity high, then will dropped.
Deep Sleep Mode
Power Management
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After SM731 ACPI mode activated, "deep sleep mode" used further reduce static current chip shutting down internal PLLs AGP/PCI pads. sequence entering this mode should ACPI Deep Sleep Mode. Before exiting from ACPI mode, "deep sleep mode" must first disengaged. enter this mode, pull "PWDOWN" (normally high internal pull up). PDR21_[6] before pull PWDOWN low.
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Chapter Motion Compensation Specification
Overview
Motion Compensation block (MC) executes series instructions pipelined fashion. There actually only type instruction with several flags that control instruction execution. instruction similar arithmetic instruction with three sources (imm IMMediate operand, Memory ReaD ACCumulator) destination (mwr Memory WRite). main difference between standard instructions those used that instruction works rectangular blocks data instead 64-bit integers. rectangular blocks data (rectangles) used 2-dimensional arrays containing 8-bit values. current implementation, horizontal vertical sizes (hsize vsize) limited following ranges: hsize vsize requires 128x16 SRAM temporary storage input output array values. acts accumulator. throughput pipeline pixels cycle. Under worst case assumptions MPEG-2 MP@ML picture will thus require Mcycles/second.
Data Flow External System Responsibilities
instructions motion compensation generated software front-end graphics controller standard software API. instructions specify different types operations: Memory accesses used reading prediction data writing reconstructed pels, Data processing operations used combine predictions with error terms generated IDCT operation. core handles data processing operations required motion compensation. graphics memory controller handles memory access operations. memory controller must read instructions generated software, fetch prediction data, feed data block write final reconstructed pels into proper location.
Level Architecture
level architecture core shown Figure consists simplified quadrilinear filer (mc_qlf this data path), 128x16 dual port SRAM, controller (mc_ctl). four data busses: command (cmd), immediate operand (imm), memory read (mrd) memory write (mwr).
Motion Compensation Specification
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Motion Compensation Commands
IDCT Data Prediction Data (From Memory)
mc_ctl
mc_qlf
SRAM 128x16
Memory
Figure Level Architecture
current architecture input output busses kept separate offer maximum processing throughput. Except command bus, busses operate continuously 16-bit 18-bit value cycle (two pixels/cycle). busses rdy-ack protocol stalled cycle. MPEG IDCT output through prediction through bus. bidirectionally interpolated macroblocks, first forward prediction read, half-pel interpolated, stored 128x16 memory (block ACCumulator). Next, backward prediction read, half-pel interpolated, added both (forward prediction) (immediate IDCT) data.
Motion Compensation Commands
demux
flags
flags
Figure Control Block Diagram
Words from loaded directly into 16-bit register command pipeline advances. flags0 flags1 registers each hold exactly instruction each together form instruction FIFO. instruction encoded more 16-bit words, which means that will take more pipeline advances before flags register accepted entire instruction. Having instructions queued time allows prepare idle pipeline with data ahead time before current instruction completed.
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Prediction Data (From Memory) IDCT Data
pipeline
SRAM read data
pipeline
recon
SRAM write data
Figure Block Diagram
Quadrilinear Filter consists three pipelines, namely acc, mrd, pipelines. pipeline shown block diagram because consists stages external first stage synchronous SRAM read port while second stage register that accepts SRAM read data. width this register matches width reconstruction memory write back (mwr) data application dependent. pipeline accepts prediction data from memory 16-bit wide format (2-pels). alignment, horizontal half interpolation, vertical half interpolation handled pipeline. pipeline accepts IDCT data 18-bit (9-bit pel) 16-bit (8-bit pel) format. data reformatted based flags current instruction. Data from three pipelines combined held reconstruction register. data added together, then saturated values between 255. From this register data written local SRAM 16-bits pels) time.
Instruction Format Operation
Figure shows instruction format. flags parameters instructions summarized Table commands have most significant (MSB) word set=1. Commands that have cleared=0, intended memory controller other control logic external Currently, only command with MSB=0 used indicate stream:
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10000
00000
Figure Stream Instruction
This Stream command occur anywhere command stream should trigger command stream transfer. After this instruction encountered hardware, communication would then take place between hardware driver determine what step take next. This command intended logic external should also passed will Flush command required order results from last valid command written memory. following table defines format instructions. Notice that word set=1, indicating that this instruction.
hsize [4:0]
vsize [4:0]
mrd_slot[1:0] mrd_plane[1:0] mrd_slot[1:0] mrd_plane[1:0]
mrd_hadder [11:0] mrd_hadder [11:0] mrd_hadder [11:0] mrd_hadder [11:0]
Figure Instruction Format
Table Instruction Flags Parameters
Flag
hsize [4:0]
Parameter
Meaning
Immediate Shift Left sign extend left IMmediate data 8-bits pixel Memory ReaD IMMediate ACCumulate Memory WRite Horizontal Blocks interLeaved Horizontal Blocks Immediate operand Horizontal block Immediate operand Horizontal block Vertical Blocks interLeaved Vertical Blocks Immediate operand Vertical block Immediate operand Vertical block Horizontal SIZE Horizontal Half interpolation
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vsize [4:0] mrd_slot [1:0] mrd_plane [1:0] mrd_haddr [11:0] mrd_vaddr [11:0] mrd_vstep mwr_slot [1:0] mwr_plane [1:0] mwr_haddr [11:0] mwr_vaddr [11:0] mwr_vstep
SM731 DataBook Meaning
Vertical SIZE Vertical Half interpolation Memory ReaD SLOT Memory ReaD PLANE Memory ReaD Horizontal ADDRess Memory ReaD Vertical ADDRess Memory ReaD Vertical STEP Memory WRite SLOT Memory WRite PLANE Memory WRite Horizontal ADDRess Memory WRite Vertical ADDRess Memory ReaD Vertical STEP
Each instruction consists two, four 16-bit words. first instruction, instruction Figure contains instruction flags. second instruction contains rectangle size. Depending flags first instruction, remaining four instructions present. instruction most important flags MRD, IMM, ACC, MWR. These flags indicate what source operands used result should stored memory accumulator (the 128x16 memory). none these four flags set. none source flags set, generates rectangle zeros. (Memory ReaD) flag set, instructions must present. These instructions specify address from which prediction data should fetched. memory slot (prediction slot) from which read data given mrd_slot [1:0]. slot contains frame video which broken down into three color planes: Cb/Cr interleaved). Each color plane broken down into fields. field located even lines while bottom field located lines frame. offset slot (frame) from which fetch data given mrd_haddr [11:0} mrd_vaddr [11:0]. vertical step, mrd_vstep, indicates whether every line every other line should read from slot. frame prediction every line read (mrd_vstep field prediction every other line read (mrd_vstep first line rectangle prediction data indicated mrd_vaddr [11:0]. field prediction (mrd_vstep which field data must come from depends location first line prediction rectangle. that line field, then data comes from field. Otherwise comes from bottom field. parameter mrd_plane (Memory ReaD PLANE) indicates which video plane being processed (0=Y, 1=Cb, 2=Cr, 3=CbCr). MPEG decompression memory read plane, mrd_plane [1:0] memorywrite plane, mwr_plane [1:0], always equal. (Note: they provided different values offer increased flexibility other applications (read from plane write different plane). set, instruction must present. These instructions specify address which final computed pels should written. Similar data read instructions, write slot indicated mwr_slot [1:0]. offset indicated mwr_haddr [11:0] mdr_vaddr [11:0]. mwr_vstep specifies whether skip line between successive rows written same that mrd_vstep does prediction data. MPEG-2 decode, mwr_vstep setting reflects motion type macroblock being processed.
Motion Compensation Specification
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instruction set, Horizontal Half interpolation performed horizontal size shall hsize pixels plus one. set, Vertical Half interpolation performed vertical size shall vsize rows plus one. flag set, adds content ACCumulator (the 128x16 memory memory read data present). flag set, adds immediate data, supplied bus, interpolated data, (mrd acc)/2. immediate data error term calculated IDCT. other nine flags have meaning only set. indicates immediate data only bits wide. IM8=0 will accept IDCT data 9-bit pixel format. MPEG-2 defines range IDCT data from -256 =255 which covered 9-bit two's complement number. setting IM8=1 indicates that data 8-bit pixel format which approximates full range. flag used conjunction with differentiates between 8-bit modes. ignored when IM8=0. 8-bit approximations allow data packed more efficiently into standard word widths. issue sign bit. Intra-coded macroblocks never sign since values restricted range +255, while predicted bidirectional IDCT values take range -256 +255. this reason, commands separated into different categories: intracoded intra-coded. IM8=1 ISL=0, first determines type command currently being executed, then generates sign based category. Intra-coded values zero extended, while intra-coded values sign extended full bits. Software that decodes IDCT data must remove sign intra-coded case while saturating lower bits removing intra-coded case. Non-intra coded data retains sign since saturation process results 8-bit twos complement number whose most significant represents sign. IM8=1/ISL=0 setting will upper limit amount correction that made prediction data though. After correction IDCT error terms greater than =127 less than -128. mentioned before, MPEG-2 specifies range between +255 -256. Under normal conditions values rarely exceed smaller range since motion relatively slow from picture picture. When they will almost impossible observer notice since corrupted pels will located area where great deal motion occurring. some rare cases though this range clipping cause visible artifacts. They corrected though, with second data "pass". Instructions with settings MRD=1, ACC=1 IMM=1 calculate results follows: (mrd+acc) Instructions with settings MRD=0, ACC=1 IMM=1 calculate results differently: This allows correction data terms that were saturated range [-128, +127]. first pass would correct this smaller range while second pass would allow correction range [-256 +254]. reach correction +255, third pass generated would required very often. IM8=1 ISL=1, shifts 8-bit data left before performing calculations with Intra coded non-intra coded commands both treat data this way. Software must drop least significant original 9bit terms convert format data required this mode. This fastest generate 8-bit data will result lower quality video. Images that contain large areas single color will suffer contour lines. remaining eight flags needed accommodate possible combinations coded_block_pattern dct_type. immediate data present only indicated these flags. term "reconstruction plane" following paragraphs refers data that written block's local SRAM result given command. Each reconstructed horizontal vertical component that make position plane.
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indicate that coded_block_pattern flag (IDCT data present) horizontal blocks that processed. used left most pels while used right most. locations reconstruction plane assigned coded block pattern (cbp) bits, namely IH0, IH1, IV1. IDCT data only used reconstruction calculation given location when Otherwise, IDCT data either masked missing from immediate data stream. bits used when vertical blocks present. MPEG terms, thought indicating that block coded. thought indicating whether coded. IDCT data re-ordered combined with prediction data (MRD bus). this reason, bits apply evenly adjacent blocks they MPEG bitstream. Their assignment locations reconstruction plane reflect change order IDCT data. indicates that Vertical Block processed same time. high, used half rows while used bottom half. half, whether used will dependent horizontal reconstruction position, LHB. same true bottom half. indicator number vertical rows command. vsize [3:0] bits indicate this. Although high, vsize [3:0] bits indicate this. Although high, vsize [3:0] used determine vertical half-way point command. indicates that Blocks Vertically interLeaved. This needed when frame prediction field type data used frame picture. When high, even rows reconstruction plane assigned while rows assigned IV1. MPEG related applications, will never both high. command generator that sets them both will cause failure though. result will union modes. half rows will interleaved while bottom half will not. bottom rows will assigned bits. indicates that Horizontal Blocks processed same time. When high, either will assigned left most half reconstruction row, while will used right most half. left half, whether used will dependent number, LVB. same true right half. indicator number horizontal pels row. hsize [4:0] bits indicate this. Although high, hsize [4:0] used determine half-way point row. indicates that Blocks Horizontally interLeaved. This needed when chroma stored single plane save memory bandwidth. When high, upper bits [17:0] interpreted IDCT used mask while lower bits interpreted with mask. When coded block pattern corresponding immediate data masked before being used reconstruction calculations. Unlike non-interleaved cases, data pels masked must present immediate data stream even though their values thrown out. When high, ignored. Setting both bits high same effect setting high low.
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Chapter Drawing Engine
SM731 incorporates high drawing engine capable rendering million triangles million Texels second. engine itself along with several pipelines incorporates have been completely redesigned from Silicon Motion's previous engine built inside Lynx3DM (SM720). Architectural Delta from SM720 Fast engine 20-cycle setup engine Dual texel pipelines Tile based rasterization Enable single cycle tri-linear mip-map anisotropic filtering color destination cache 32-bit frame z/stencil buffer Reduce page break penalty Functionality Delta from SM720 clear value Single cycle multitexture Bump mapping buffer based Stencil planes planes)
Drawing Engine
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Setup
Rasterizer
Engine
Pixel Engine
Texture Engine
Final Pixel
Figure Engine
Drawing Engine
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Command Interpreter
SM731 incorporates sophisticated command interpreter engine through which data from engine flows. software driver builds buffer structures memory containing triangle data commands Engine. From there SM731 hardware gathers these buffers, processes, conveys status information back driver. Feature Fast engine Vertex buffer entries Supports flexible vertex format Supports vertex buffer Supports memory memory blit Supports tiled memory memory blit Accumulates sends state changes entire pipeline
Setup Engine
Setup Engine completes triangle parameter setup every cycles. This gives million triangles second performance MHz. This performance full featured triangle, i.e. triangle with parameters: Feature Primitive types supported: Triangle list Triangle strip Triangle Functionality features: Cull, cull cull sets color components diffused specular colors registers flat shading sets texture coordinates Texture coordinate wrapping. Wrapping independent each texture coordinate Screen space Homogeneous space
Rasterizer Engine
improve memory interface performance, SM731 supports tile based rasterization. Feature Tiled rasterization Supports clipping window Supports Supports specular diffuse lighting Supports textures
Texture Engine
texture pipeline computes single pixel with textures each clock cycle. pipeline gives Mtexels/second performance Mhz. Feature Dual Texture pipeline Floating point computation Supports point sample, bi-linear, tri-linear mip-map Supports Bump mapping
Drawing Engine
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Supports texture compression
Supported texture formats: ARGB8888 ARGB4444 ARGB1555 RGB565 DXT1,
Pixel Engine
Pixel Engine includes Texture Blending stages Feature Efficient pixel pipeline Supports both diffuse specular color components Supports 16-bit 32-bit frame buffer formats Supports multi-texture blend functions Supports color function Supports both vertex table based Supports alpha test function Supports source destination blend modes Supports dithering 16-bit frame buffer format
Engine
SM731 Engine supports Stencil Fog. z/stencil/fog pipeline computes stencil values pixels cycle. This gives MP/s. Feature Zero cycle buffer clear Supports either screen space Supported formats: fixed point format Supported formats: 16-bit fixed point format 24-bit floating point format Supports stencil planes Supports table based with table size stencil cache
Drawing Engine
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Chapter Encoder
Encoder NTSC/PAL Composite Video/S-video Encoder. receives inputs converts digital video signals based CCIR format. input video signal Encoder 8-bit each. sampling rate corresponding CCIR 601, Square pixel 4Fsc (NTSC only). output video signals Encoder Composite video signal S-video signals 10-bit each. These output signals over-sampled double frequency clock called CLKX2. This feature helps simplify external analog filtering. Encoder video timing controlled vertical sync horizontal sync input signals. blank signal input optional. blank signal input signal pulled internal blanking control will performed. Macrovision 7.1.4 closed captioning functions included.
Feature Summary
NTSC/PAL interlace mode digital video encoder Composite Video S-Video digital output CCIR 601, Square pixel 4Fsc (NTSC only) resolution input Slave timing operation Interlace mode operation over-sampling data output simplify external analog filtering Selectable pedestal level OIRE/7.5IRE NTSC Macrovision function (version 7.1.4) Closed captioning function
Encoder
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CLKX2
R[7:0] Converter
Blank Pedestal
Closed Caption Encoder
YD[9:0]
G[7:0]
Antitaping Process Control
OverSampling
CVBS[9:0]
B[7.0]
Color Burst Generator
CD[9:0] Subcarrier Generator
VSYNC_L HSYNC_L BLANK_L CLKX1 Timing Controller Parallel Interface
DI[7:0] DO[7:0] MODE[2:0] RESET_L
Figure Encoder Block Diagram
Table Encoder Block Interface Description
Excore-TV Encoder list
name
VSYNC_L HSYNC_L BLANK_L CLKX1
Width
Description
4:4:4 sampled data This data should synchronized CLKX1. 4:4:4 sampled Green data This data should synchronized CLKX1. 4:4:4 sampled Blue data This data should synchronized CLKX1. Vertical sync input, active This goes during vertical sync intervals. Horizontal sync input, active This goes during horizontal sync intervals. Composite blanking input, active low. This goes during composite blanking intervals. this signal low, input data will masked. Pixel rate clock input This clock should free-running, will synchronized CLKX2.
Encoder
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CLKX2 MODE
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Width
Description
Pixel rate clock input This clock should free-running. Mode select When MR[7] mode controlled these input pins, otherwise mode register (MR) setting will taken. 000: NTSC CCIR 100: CCIR 001: NTSC Square Pixel 101: Square pixel 010: NTSC 4Fsc Reset input, active Macrovision function Enable Parallel data input Parallel data output Parallel index strobe Parallel data strobe S-video Luminance data output Composite video data output S-video Chrominance data output
RESET_l MV_EN CVBS
Function Descriptions
Video data input sampling rate video input data RGB. Each data 8-bit value. range data respectively. data latched positive edge CLKX1. Encoder supports following sampling rates:
Table Encoder Sampling Rates
Video Mode
CCIR NTSC Square pixel 4Fsc CCIR Square pixel 14.75
Frequency
13.5 12.27 14.32 13.5
Total pixel/line
Total lines/frame
Macrovision Antitaping Process
Encoder supports Macrovision Antitaping process function (U7.01). Macrovision involves functions which colorstripe process, Pseudo Sync/AGC pulses with sync pulse amplitude reduction back porch pulses. same line assigned closed captioning Macrovision process, Macrovision functions line disabled closed captioning function.
Encoder
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
color stripe process function applied composite video output Chrominance signal output. This activated MCR0[3] controlled MCR1 MCR7 MCR16 MCR21. This function controls color burst length polarity. When this process invoked during burst blanking lines, color burst signal put. When color burst length assigned beyond active video time, color burst completes blanking time. Active video data then starts. blanking time controlled BLANK-L input internal blanking. Pseudo Sync/AGC pulse function applied composite video output S-video Luminance output. Pseudo Sync pulse applied Luminance signal. pulses super-white positive going pulse. Both these pulses output after color burst signal. Sync Pulse amplitude reduction changes synchronizing level. This function activated MCR0[5] MCR0[1:0], controlled MCR0[2], MCR8 MCRI4. back porch pulse function generates high level signal immediately after trailing edge H-sync pulse. value 100IRE NTSC mode 7OOmV mode. This function activated MCR0[4], controlled MCR[15].
Closed Captioning
closed captioning function applied Luminance data, shown composite video output Svideo Luminance output follows. level timing corresponds standard EIA-608.
This function controlled closed captioning registers. closed captioned line controlled follows.
Table Closed Captioning Lines
Video Mode
NTSC
field
Even field
When closed captioning function enabled CCEN register, captioning data will placed assigned line. When there data, Encoder outputs data. When there data, null code (80h) will output.
Encoder
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
field even field controlled separately. When (even) data registers written, Encoder recognizes data (even) field. status OST(EST) normal usage, data written when status
Table Closed Captioning Field Output Data
Enable
CCE[0] CCE[0] CCE[0]
Status
Output Data
data CO_DT0 (hex)
Output Data
data CO_DT1 (hex)
Table Closed Captioning Even Field Output Data
Enable
CCE[0] CCE[0] CCE[0]
Status
Output Data
data CO_DT0 (hex)
Output Data
data CE_DT1 (hex)
Video data output Over-sampling Encoder outputs composite video, Luminance Chrorninance signals. These outputs have 10-bit each, over-sampled double frequency clock designated CLKX2. This over-sampling simplifies external analog filtering. output level timing depend mode selected.
Synchronization
This Encoder operates slave mode. This means that vertical sync horizontal sync required operation. blanking signal optional. Encoder will calculate composite blanking time using sync information. blank signal BLANK-L pulled input data blanking time will masked internal blanking signal. When blanking signal controlled, it's possible shorten active time input data. Encoder will mask input data when BLANK-L low. Encoder automatically detects Odd/Even field sync information.
Sub-carrier Generation
sub-carrier internally generated using CLKX1. Depending sampling rate, Encoder will automatically calculate exact frequency. sub-carrier phase reset under following conditions: RESET-L low. first field changes field after RESET- goes high. first field changes field after Encoder detects mode change. When genlock control this case, sub-carrier phase will reset every fields NTSC mode fields mode.
Parallel
internal register access, parallel used. When write index signal designated high, register address latched. When write data signal designated high, data will written latched address.
Encoder
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Chapter Power Configuration
SM731 Power-On Configurations
MD[63:0] MA[11:0] have internal pull-up resistors pads external pull-down resistor external pull-down resistor
Table Power Configuration
Signal Name
MD[37]
Read/Write
Config Only
Register Address
Address
Description
selection. This hardware test feature which used debug purpose only) Definition: pllvck new,high performance pllvrck existing from SM731 pllmck existing from SM731 pllmck2 new,high performance MD[37] config (default) Vclk(video clock) pllvck VrClk(LCD Panel clock) pllvrck Mclk(Engine clock) pllmck Mclk2(memory controller clock) pllmck2 else Vclk(video clock) pllvrck VrClk(LCD Panel clock) pllvrck Mclk(Engine clock) pllmck Mclk2(memory controller clock) pllmck also definition CCR67[3:2]
MD[36:35]
Config Only
Size Base Memory selection 00=4MB 01=8MB 10=16MB 11=32MB Being used when only Endian selected 0=Small Endian 1=Big Endian 0=Only Endian 1=Both Endian Reserved
MD[34]
Config Only
MD[33] MD[32] MD[31] MD[30:25] MD[24]
Config Only
MCR76[7]
3c5.76
0=Reserved 1=Normal (default) Reserved
MCR76[0]
3c5.76
0=SDRAM interface 1=Reserved
Power Configuration
Silicon Motion®, Inc. CONFIDENTIAL Signal Name
MD[23]
SM731 DataBook Register Address Address Description
0=AND with RESETN reset free running clock divider simulation testing 1=Normal (default) Reserved
Read/Write
MD[22} MBA[1] MBA[0] Config Only Config Only
0=Enable C0000 EPROM access 1=Disable C0000 EPROM access 0=>PCI Config Reg54[2]=1=>AGP4X capable 1=>PCI Config Reg54[2]=0=>Not AGP4X capable GPR70[3:0] 3c5.70 Panel 0000 640x480 0001 800x600 0010 1024x768 0011 1280x1024 0100 1600x1200 configuration 0=For 1.5V 1=For 3.3V LVDS interface LVDS Panel R,G,B TX3-+. bits LVDS R,G,B Tx3-+. bits LVSDS (Hitachi type) Panel Sequence Software panel on/off sequence Hardware panel on/off sequence LVDS Configuration double LVDS configuration (two LVDS chips panel side) single LVDS configuration (only single LVDS receiver panel) 00=Reserved 01=Select non-LVDS panel primary panel display 10=Select LVDS1 primary panel display 11=Both LVDS1 non-LVDS panel primary panel display Reserved software purposes Reserved
MA[11:8]
MA[7]
MA[6]
MA[5]
MA[4]
MA[3]
MA[2:1]
MA[0] MD[21:0]
Note:
Windows Windows Windows Windows setting [36:35, should [111]. However, Windows setting [36:35, should [1,0,0].
Power Configuration
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Chapter Register Overview Usage
Register Types
There three general types registers used SM731:
Configuration Registers
Configuration registers listed Chapter Configuration Space Registers accessed standard read/write protocols specified specification.
Memory Mapped Registers
mapped registers within SM731 have been designed memory mapped well. They listed Chapter Standard Registers Chapter Extended Mapped Registers. "I/O" "Memory" Mapping selected through configuration registers CSR04 Access "I/O" space done first writing index value into register 3C4. Thereafter, indexed register accessed read/write address
Example: Register with Index write read/write to/from
procedure access these registers "Memory" Mapped space similar "I/O" space; with index register being moved memory address 6C03C4 access register 6C03C5.
Example: Register with Index Memory write 6C03C4 Memory read/write to/from 6C03C5
Memory Mapped Registers
advanced functions SM731 controlled through Memory Mapped registers. Such motion compensation video registers, master control registers, encoder registers registers. following diagram illustrates Memory Mapped register address assignment. memory mapped registers accessed though port 3cf. described following table.
Address[7:0] Address[15:8] Address[23:16] Address[31:24] Data[7:0]
Register Overview Usage
Silicon Motion®, Inc. CONFIDENTIAL
28-2F 3cf[7:4] 3cf[3:0] Data[15:8] Data[23:16] Data[31:24] Activate Write/Read IOAccess Command Reserved Byte Enable
SM731 DataBook
Address [31:30] Represent Different Ways access [31:30] 2'b00: Linear Memory Access [31:30] 2'b01: Linear Memory Access
MMIO Write
write 20-27 fill address data. Write Example: MMIO Address 32'h00002800; Data 32'haabbccdd; Byte Enable 4'b0000
iowr_w(32'h3ce,32'h00000020); iowr_w(32'h3ce,32'h00002821); iowr_w(32'h3ce,32'h00000022); iowr_w(32'h3ce,32'h00000023); iowr_w(32'h3ce,32'h0000dd24); iowr_w(32'h3ce,32'h0000cc25); iowr_w(32'h3ce,32'h0000bb26); iowr_w(32'h3ce,32'h0000aa27); iowr_w(32'h3ce,32'h00000028); MMIO word write MMIO word write MMIO word write MMIO word write MMIO word write MMIO word write MMIO word write MMIO word write MMIO with Byte Enable 4'b0000
MMIO Read
write 20-23 fill address. Read with index 3ce=28 activate read 24-27 data. Example: MMIO Address 32'h00002800
iowr_w(32'h3ce,32'h00000020); iowr_w(32'h3ce,32'h00002821); iowr_w(32'h3ce,32'h00000022); iowr_w(32'h3ce,32'h00000023); iowr_b(32'h3ce,32'h00000028); iord_b(32'h3cf,data); iowr_b(32'h3ce,32'h00000024); iord_b(32'h3cf,data); iowr_b(32'h3ce,32'h00000025); iord_b(32'h3cf,data); iowr_b(32'h3ce,32'h00000026); MMIO word write MMIO word write MMIO word write MMIO word write update index Execute Read. Don't care data MMIO index write MMIO Read Data[7:0] MMIO index write MMIO Read Data[15:8] MMIO index write
Register Overview Usage
Silicon Motion®, Inc. CONFIDENTIAL
iord_b(32'h3cf,data); iowr_b(32'h3ce,32'h00000027); iord_b(32'h3cf,data); MMIO Read Data[23:16] MMIO index write MMIO Read Data[31:24]
SM731 DataBook
Linear Memory Write
write 20-27 fill address data. Write Example: Lmem Address 32'h40002800; Data 32'haabbccdd; Byte Enable 4'b0000
iowr_w(32'h3ce,32'h00000020); iowr_w(32'h3ce,32'h00002821); iowr_w(32'h3ce,32'h00000022); iowr_w(32'h3ce,32'h00004023); iowr_w(32'h3ce,32'h0000dd24); iowr_w(32'h3ce,32'h0000cc25); iowr_w(32'h3ce,32'h0000bb26); iowr_w(32'h3ce,32'h0000aa27); iowr_w(32'h3ce,32'h00000028); MMIO word write MMIO word write MMIO word write MMIO word write MMIO word write MMIO word write MMIO word write MMIO word write MMIO with Byte Enable 4'b0000
Linear Memory Read
write 20-23 fill address. Read with index 3ce=28 activate read 24-27 data. Example: Lmem Address 32'h40002800
iowr_w(32'h3ce,32'h00000020); iowr_w(32'h3ce,32'h00002821); iowr_w(32'h3ce,32'h00000022); iowr_w(32'h3ce,32'h00004023); iowr_b(32'h3ce,32'h00000028); iord_b(32'h3cf,data); iowr_b(32'h3ce,32'h00000024); iord_b(32'h3cf,data); iowr_b(32'h3ce,32'h00000025); iord_b(32'h3cf,data); iowr_b(32'h3ce,32'h00000026); iord_b(32'h3cf,data); iowr_b(32'h3ce,32'h00000027); iord_b(32'h3cf,data); MMIO word write MMIO word write MMIO word write MMIO word write update index Execute Read. Don't care data MMIO index write MMIO Read Data[7:0] MMIO index write MMIO Read Data[15:8] MMIO index write MMIO Read Data[23:16 MMIO index write MMIO Read Data[31:24]
Register Overview Usage
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Mapped Register Mapped Summary
Sequencer Registers System Control Registers Power Down Control Registers Memory Control Registers Clock Power Down Control Registers Block USR0-3 Ports Control Registers General Purpose Control Registers Scratch Registers Memory Control Registers Monitor Detect CRT/TV Test Registers Icon Registers Icon Registers
Index Index 10-1F Index 20-24 Index 60-63 Index Index Index 70-73 Index 74-75 Index Index 7A-7D Index 80-8D Index 90-93
Figure Port
CRTC Registers Extended CRTC Control Registers Scratch Registers Shadow Registers Encoder Control Registers Screen Centering Expansion Control
Index 0-26 Index 30-3C Index 3D-3F Index 40-4D Index 6X-8X Index 90-9F; Index A0-AD
Figure Port
Register Overview Usage
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
MMIO_Base (cfg14) MMIO_Base 2D3D Ports Video Port Vidcap Port ICMD Port IDCT Port Port 2D3D Master Port Core Port ICMD Data Port IDCT Data Port Data Port Panel Control Registers Data Port 2D3D Data Port Memory Space Additional Data Port 0000_0000-0000_07ff 0000_0800-0000_0fff 0000_1000-0000_17ff 0000_1800-0000_1fff 0000_2000-0000_27ff 0000_2800-0000_2fff 0000_3000-0000_37ff 0000_3800-0000_3fff 0000_4000-0000_47ff 0000_4800-0000_4fff 0000_5000-0000_57ff 0000_5800-0000_5fff 0000_6000_0000_7fff 0001_0000-0008_ffff 000c_0000-000f_ffff 01_00000-00_01_fffff 512K 256K
Figure Memory Mapped Address Diagram
Register Overview Usage
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
FB_Base (cfg10)
Frame Buffer
Configurationable Memory Size 64MB
Figure Frame Buffer Memory Space (32MB single endian, 64MB bi-endian)
Register Overview Usage
Silicon Motion®, Inc. CONFIDENTIAL
SM731 DataBook
Chapter Configuration Space Registers
Table Configuration Registers Quick Reference
Summary Registers
CSR00: Vendor Device CSR04: Command Status CSR06: Status CSR08: Revision Class Code CSR0C: Latency Timer CSR10: Linear Frame Buffer Base Address Register CSR2C: Subsystem Subsystem Vendor CSR30: Expansion
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