PowerPC 440SPe Embedded Processor PowerPC® processor core operati
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Part Number 440SPe Revision 1.26 June 2008
PowerPC 440SPe Embedded Processor
PowerPC® processor core operating with 32KB D-caches (with parity checking) On-chip 256KB SRAM configurable Cache Ethernet Packet/Code store memory Selectable Processor clock ratios (Refer Clocking chapter PPC440SPe Embedded Processor User's Manual details) Support Chip Selects) 64-bit/32bit SDRAM with 266-333-400 400-533-667 Three PCI-Express serial interfaces: lanes lanes 2.5Gb/s lane Root Endpoint support. Opaque bridge 64-bit PCI-X interfaces (DDR 266) with support conventional Optional: High throughput RAID hardware acceleration, performs Galois Field parity computations, supports drives Optional:16 Programmable Galois Field polynomials including Accelerator with controller messaging with controllers External Peripheral (16-bit Data, 27-bit Address) three devices; Bank0=16 Bank1 Bank2=128 each Ethernet 10/100/1000Mbps half- fullduplex interface. Operational modes supported GMII. Programmable Interrupt Controller supports interrupts from variety sources. Programmable General Purpose Timers (GPT) Three serial ports (16750 compatible UART) interfaces General Purpose (GPIO) interface available JTAG interface board level testing Processor boot from memory
Description
Designed specifically address high-end embedded applications storage, PowerPC 440SPe (PPC440SPe) provides high-performance, power solution that interfaces wide range peripherals incorporating on-chip power management features lower power dissipation. This chip contains high-performance RISC processor core, DDR1/DDR2 SDRAM controller, configurable 256KB SRAM used cache software-controlled on-chip memory, three PCIExpress interfaces, PCI-X interface, 1Gbps Ethernet interface, I2O/DMA controller, control external peripherals, optional RAID acceleration, unit, serial ports, interfaces, general purpose I/O. Technology: CMOS Cu-11, 0.13mm Package: 27mm, 675-ball, pitch, Flip ChipPlastic Ball Grid Array (FC-PBGA) Power (estimated): Less than @533MHz Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V
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PowerPC 440SPe Embedded Processor
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Contents
Ordering Information PPC440SPe Functional Block Diagram Address Maps PowerPC Processor Core Internal Buses On-Chip SRAM/L2 Cache Express PCI-X Interface DDR1/DDR2 SDRAM Memory Controller External Peripheral Controller (EBC) Ethernet Controller Interface I2O/DMA Controller Optional RAID RAID Acceleration Hardware XOR/DMA2 Controller Serial Port Interface General Purpose Timers (GPT) General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) JTAG 27mm, 675-Ball FC-PBGA Core Package Signal Lists Signal Description Clock Test Conditions Clock Timing Waveform Spread Spectrum Clocking Specifications Input/Output Timing Input Setup Hold Waveform Output Delay Hold Timing Waveform SDRAM Specifications SDRAM Write Operation SDRAM Read Operation Initialization Strapping Serial Bootstrap Revision
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PowerPC 440SPe Embedded Processor
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Figures
Figure Order Part Number Figure PPC440SPe Functional Block Diagram Figure 27mm, 675-Ball FC-PBGA Core Package Figure Clock Timing Waveform Figure Input Setup Hold Waveform Figure Output Delay Hold Timing Waveform Figure SDRAM Signal Termination Figure SDRAM Write Cycle Timing Figure SDRAM Read Data Path Figure SDRAM Memory Data Figure SDRAM Read Cycle Timing-Example
Tables
Table System Memory Address Table Address (4KB Device Configuration Registers) Table Signals Listed Alphabetically Table Signals Listed Ball Assignment Table Summary Table Signal Functional Description Table Absolute Maximum Ratings Table Package Thermal Specifications Table Recommended Operating Conditions Table Input Capacitance Table Power Supply Loads Table Clocking Specifications Table Peripheral Interface Clock Timings Table Specifications-All Speeds Table Specifications-667MHz Table SDRAM Output Driver Specifications Table SDRAM Read Write Timing-TSA Table SDRAM Clock Write Timing-TDS Table SDRAM Write Data Timing-TSD Table SDRAM Read Timing-TSD Table Strapping Assignments
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PowerPC 440SPe Embedded Processor
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Ordering Information
information about availability following parts, contact your local sales office. most current version 440SPe Revision part numbers 440SPe Revision shown following figures.
Product Name PPC440SPe Notes: Product Feature RAID6 enabled (Rev Level only) RAID6 enabled (Rev Level only) Module Package Type leaded FC-PBGA lead free FC-PGBA (RoHS compliant) Chip Revision Level (2.0) Processor Frequency 533MHz 667=667 =800MHz Case Temperature Range +95°C Order Part Number (see Notes 1-5) PPC440SPe-xpBfffC Package 27mm, FC-PBGA Level Value 0x53421891 JTAG 0x14538049
Each part number contains revision code. This mask revision number included part number identification purposes only. (Processor Version Register) JTAG register software accessible (read-only) contain information that uniquely identifies part. PPC440SPe Embedded Processor User's Manual details about accessing these registers. Note: Raid-enabled versions (Product Feature require RAID license. Figure Order Part Number
PPC440SPe-RNB667C
AMCC Part Number Product Feature Package Case Temperature Range Processor Speed Revision Level Note: example part number above RAID6-enabled, lead-free package, Chip Revision Level Express core revision level 1.1, capable running MHz, shipped tray packaging.
part numbers 440SPe Revision shown following figure.
Product Name PPC440SPe PPC440SPe Order Part Number PPC440SPe-3GA533C PPC440SPe-3GA667C Processor Frequency 533MHz 667MHz Package 27mm, FC-PBGA 27mm, FC-PBGA Level Value 0x53421890 0x53421890 JTAG 0x14538049 0x14538049
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PowerPC 440SPe Embedded Processor
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PPC440SPe Functional Block Diagram
Figure PPC440SPe Functional Block Diagram
IRQs Clock, Control, Reset Timers DCRs Registers Timers GPIO UART
Power Mgmt
Universal Interrupt Controller
PPC440
Processor Core JTAG 32KB D-Cache
Trace 32KB I-Cache PCI-E Handler On-chip Peripheral (OPB)
Cache/SRAM
Bridge Ethernet 10/100/ 1000 MII, GMII External Controller (EBC)
Processor Local (PLB)
Latency (LL) Segment
High Bandwidth (HB) Segment
I2O/DMA Controller (DMA0 DMA1)
Memory Queue SDRAM Cntl 64+8
XOR/DMA Accelerator Unit (DMA2)
PCI-Express PCI-E0 PCI-E1 PCI-E2
PCI-X
64-bit
lanes lanes lanes
PPC440SPe System Chip (SOC) designed around CoreConnect BusArchitecture. Implemented with Crossbar option, CoreConnect buses provide: Master 128-bit Data 64-bit Address interfaces 166.66MHz, 2.6GB/s both Read Write data path (10.6 GB/s total) 32-bit interfaces 83.33MHz maximum throughput 333MB/s
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PowerPC 440SPe Embedded Processor
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Address Maps
PPC440SPe incorporates address maps. first fixed processor system memory address map. This address defines possible contents various processor accessible address regions. second address identifies system Device Configuration Registers (DCRs). DCRs accessed software running PPC440SPe processor through mtdcr mfdcr instructions.
Table System Memory Address (Sheet
Function Function SDRAM Local Memory (LL)1 SRAM Reserved Registers Registers Registers I20/DMA Buffers Internal Interfaces (LL) Reserved XOR/DMA2 Reserved Express Interrupt Handler Reserved Internal Peripherals (LL) Memory Reserved UART0 Reserved UART1 Reserved IIC0 Reserved IIC1 Reserved UART2 Reserved GPIO Controller Registers Reserved Ethernet Controller Registers Reserved
Start Address 0000 0000 0000 0000 0000 0004 0000 0000 0000 0004 0004 0000 0000 0004 0010 0000 0000 0004 0010 0100 0000 0004 0010 0200 0000 0004 0010 0300 0000 0004 0010 1000 0000 0004 0020 0000 0000 0004 0020 0400 0000 0004 0030 0000 0000 0004 0030 0100 0000 0004 E000 0000 0000 0004 F000 0000 0000 0004 F000 0200 0000 0004 F000 0208 0000 0004 F000 0300 0000 0004 F000 0308 0000 0004 F000 0400 0000 0004 F000 0420 0000 0004 F000 0500 0000 0004 F000 0520 0000 0004 F000 0600 0000 0004 F000 0608 0000 0004 F000 0700 0000 0004 F000 0780 0000 0004 F000 0800 0000 0004 F000 0900
Address 0000 0003 FFFF FFFF 0000 0004 0003 FFFF 0000 0004 000F FFFF 0000 0004 0010 00FF 0000 0004 0010 01FF 0000 0004 0010 02FF 0000 0004 0010 0FFF 0000 0004 001F FFFF 0000 0004 0020 03FF 0000 0004 002F FFFF 0000 0004 0030 00FF 0000 0004 DFFF FFFF 0000 0004 EFFF FFFF 0000 0004 F000 01FF 0000 0004 F000 0207 0000 0004 F000 02FF 0000 0004 F000 0307 0000 0004 F000 03FF 0000 0004 F000 041F 0000 0004 F000 04FF 0000 0004 F000 051F 0000 0004 F000 05FF 0000 0004 F000 0607 0000 0004 F000 06FF 0000 0004 F000 077F 0000 0004 F000 07FF 0000 0004 F000 08FF 0000 0004 F000 09FF
Size 16GB 256KB
256B 256B 256B 3.25K
256B
256MB
248B 128B
256B
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PowerPC 440SPe Embedded Processor
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Table System Memory Address (Sheet
Function Function General Purpose Timers Reserved Boot ROM2, Reserved Local Memory Alias (HB) Aliased SDRAM Reserved PCIX0 Reserved PCIX0 Addressing configuration Regs Reserved PCIX0 Core Configuration Regs Space (HB) Reserved PCIX0 Simple Message Passing Reserved PCIX0 Special Cycle Reserved Memory (PCI-Express PCI-X) PCI-X boot (PCI memory Memory (PCI-Express PCI-X) Reserved4 Reserved5 Core Space (HB) Notes: SDRAM on-chip SRAM located anywhere Local Memory area memory map. Boot Expansion areas memory intended Flash-type devices. While locating volatile SDRAM SRAM this region supported, these regions this purpose recommended. When optional boot from PCI-X memory selected, PCI-X Boot address space begins FF00 0000 MB). Never decoded. Unpredictable results Read Write operations. Accessed means Peripheral Bank Configuration Registers. Memory (PCI-Express PCI-X) Bank0 Start Address 0000 0004 F000 0A00 0000 0004 F000 0B40 0000 0004 FF00 0000 0000 0005 0000 0000 0000 0008 0000 0000 0000 000C 0000 0000 0000 000C 0800 0000 0000 000C 0801 0000 0000 000C 0EC0 0000 0000 000C 0EC0 0008 0000 000C 0EC8 0000 0000 000C 0EC8 1000 0000 000C 0EC8 1100 0000 000C 0EC8 1200 0000 000C 0ED0 0000 0000 000C 0EE0 0000 0000 000C 1000 0000 0000 000C FF00 0000 0000 000D 0000 0000 0000 0010 0000 0000 1000 0000 0000 0000 2000 0000 0000 0000 Address 0000 0004 F000 0B3F 0000 0004 FEFF FFFF 0000 0004 FFFF FFFF 0000 0007 FFFF FFFF 0000 000B FFFF FFFF 0000 000C 07FF FFFF 0000 000C 0800 FFFF 0000 000C 0EBF FFFF 0000 000C 0EC0 0007 0000 000C 0EC7 FFFF 0000 000C 0EC8 0FFF 0000 000C 0EC8 10FF 0000 000C 0EC8 11FF 0000 000C 0ECF FFFF 0000 000C 0EDF FFFF 0000 000C 0FFF FFFF 0000 000C FEFF FFFF 0000 000C FFFF FFFF 0000 000F FFFF FFFF 0FFF FFFF FFFF FFFF 1FFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 3.8GB 16MB 12GB 256B 64KB 16GB 16MB Size 320B
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PowerPC 440SPe Embedded Processor
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Table Address (4KB Device Configuration Registers)
Function Total Address Space1 function: Reserved Clocking Power Reset System DCRs Memory Controller External Controller Reserved SRAM Controller Memory Queue I2O, DMA0 DMA1 Bridge Reserved Reserved Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller PCI-Express PCI-Express PCI-Express Power Management Reserved Ethernet Reserved Notes: address space addressable with bits (1024 unique addresses). Each unique address represents single 32-bit (word) register. (1024W) equals (4096 bytes). 128W 512W Start Address Address Size (4KB)1
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PowerPC 440SPe Embedded Processor
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PowerPC Processor Core
PowerPC processor core designed high-end applications such RAID controllers, SAN, ISCSI, routers, switches, printers, set-top boxes, first processor core implement Book PowerPC embedded architecture uses 128-bit version IBM's on-chip CoreConnect Architecture. Features include: operation PowerPC Book architecture 32KB I-cache, 32KB D-cache parity data address Checking parity with error injection Three logical regions D-cache: Locked, Transient, Normal D-cache full-line flush capability 41-bit virtual address, 36-bit (64GB) physical address Superscalar, out-of-order execution Seven-stage pipeline Three execution pipelines Dynamic branch prediction Memory management unit 64-entry, full associative, unified with parity Separate instruction data micro-TLBs Storage attributes write-through, cache-inhibited, guarded, little endian Debug facilities Multiple instruction data range breakpoints Data value compare Single step, branch, trap events Non-invasive real-time trace interface instructions Single cycle multiply multiply-accumulate integer multiply
Internal Buses
PowerPC 440SPe features three standard on-chip buses: Processor Local (PLB), On-Chip Peripheral (OPB), Device Control Register (DCR). high performance, high bandwidth cores such PowerPC processor core, SDRAM memory controller, Express PCI-X bridges connect PLB. hosts lower data rate peripherals. daisy-chained provides lower bandwidth path passing status control information between processor core other on-chip cores. Crossbar arbiter that supports data transfer between master slave segments identified Latency (LL) High Bandwidth (HB) segments. segment allows masters I2O, that adversely affected latency, communicate with slave devices with minimal latency. segment allows masters DMA, XOR, Express exchange large blocks data with SDRAM, Express without interfering with latency masters. features include: 128-bit implementation architecture Separate simultaneous read write data paths 64-bit address Simultaneous control, address, data phases Four levels pipelining Byte enable capability supporting unaligned transfers 64-byte burst transfers
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PowerPC 440SPe Embedded Processor
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166MHz, maximum 5.2GB/s (simultaneous read write) Processor clock ratios Dynamic sizing: 8-bit data path 32-bit address 83.33MHz, maximum 333MB/s Register control 32-bit data path 10-bit address
On-Chip SRAM/L2 Cache
Features include: Four banks 64KB each total 256KB Configurable either cache SRAM Memory cycles supported: Single beat read write, bytes Quadword Read Write burst 12-bit master Guarded memory accesses boundaries Sustainable 2.6GB/s peak bandwidth 166MHz cache improves processor performance reduces load Cache coherency maintained hardware snoop mechanism Latency (LL) software Data Array Array parity Unified data instruction cache Four-way associative 36-bit addressing Full replacement algorithm Write through, look aside Ethernet packet store allows Ethernet packets held processing Ethernet core
Express
Features include: Three independent Express interfaces lanes lanes GB/sec full duplex lane Compliant with Express base specification 1.0a Each Express port Point Root Complex. (Upstream Downstream) Applications compliant with rules limited Point port PPC440SPe PCI-Express PCI-Express opaque (Non-Transparent) bridge Power Management Supports virtual channel (VC0) Traffic Class (TC) filtering Maximum Payload block size Bytes Supports 1024 byte maximum Read request size Requests supported: posted outbound Write requests (memory messages) posted inbound Write requests outbound Read requests outstanding Express inbound Read requests outstanding Express Outbound request Express Root Port Inbound request Express Point
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Buffering each Express Port following transaction types: byte Replay buffer: flight transactions bytes Outbound posted Writes bytes Outbound Reads completion prefetch request from first I2O/DMA Master prefetch request from I2O/DMA Master prefetch request from first PCIE links prefetch request from PCIE links byte from PPC440 bytes Inbound posted Writes bytes Inbound Reads completion Parity checking each buffer Programmable Outbound Memory Regions: Memory, I/O, Message, config, Internal Regs Programmable Inbound Memory Regions: Memory, I/O, Expansion INTx Interrupts support (PCI legacy): INTx Termination Root Ports. A/B/C/D interrupts wired A/B/C/D INTx types Generation Endpoints Message Signaled Interrupts Generation Point Termination Root Ports MSI_X Termination Root Ports
PCI-X Interface
PCI-X interface allows connection PCI-X devices PowerPC processor local memory. PCI-X interface supports 64-bit PCI-X mode configured either host adapter mode. 32/64-bit legacy mode, compatible with Version 2.3, also supported. Features include: PCI-X Split transactions Frequency 266MHz 64-bit address/data supported 266MHz Mode only backward compatibility Frequency 66MHz 64-bit Host Bridge Adapter Device interface Optional arbitration function with PCI-X mode supporting four external devices, that disabled with external arbiter Support PLB-based (external PLB-PCI-X bridge) Support Message Signaled Interrupts (MSI) both out-bound interrupts Simple message passing capability Asynchronous Power Management Version arbitration function with PCI-X Mode support (optional) register addressable both from on-chip processor device sides Ability boot from PCI-X memory Error tracking/status Supports initiation transfer following address spaces: Single beat reads writes Single beat burst memory reads writes Single beat configuration reads writes (Type Type Single beat special cycles
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PowerPC 440SPe Embedded Processor
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PCI-X initialization sequence support (frequency mode determination) Support unexpected split completions Outbound transaction split discard timers Vital Product Data (VPD) support PCI-X PCI-Express opaque bridge
DDR1/DDR2 SDRAM Memory Controller
DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, other discrete devices. Global memory timings, address bank sizes, memory addressing modes programmable. DDR2 SDRAM controller interfaces through Memory Queue (MQ) function that includes highspeed FIFO buffers. Features include: Registered non-registered industry standard DIMMs DDR2 400/667 support 64-and 32-bit memory interfaces with optional 8-bit (SEC/DED) 5.32GB/s peak bandwidth 64-bit interface 2.66GB/s peak bandwidth 32-bit interface Four chip (bank) select signals supporting external banks latencies supported Page mode accesses open pages) with configurable paging policy Look-ahead request queue with programmable depth four commands. Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing current bank) 16GB four external banks MemClkout signals high loading unbuffered DIMMS. Programmable address mapping timing Hardware software initiated self-refresh Sync DRAM configuration means mode register extended mode register commands Power management (self-refresh, suspend, sleep) Latency High Bandwidth ports Selectable read response (immediate deferred) Programmable Latency High Bandwidth arbitration schemes High Bandwidth port four read buffers write buffers Latency port four 128B read buffers 128B write buffers
External Peripheral Controller (EBC)
Features include: Support Boot Bank programmable size 8,16 three ROM, EPROM, SRAM, Flash memory, slave peripherals supported Burst non-burst devices 8-bit data 27-bit address, 128MB address space Banks Peripheral Device pacing with external "Ready" Latch data Ready, synchronous asynchronous Programmable access timing device Wait States non-burst Burst Wait States first access Wait States subsequent accesses Programmable CSon, CSoff relative address Programmable OEon, WEon, WEoff clock cycles) relative Programmable address mapping
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Ethernet Controller Interface
Ethernet support interfaces physical layer, included chip. Features include: 10/100/1000 interface running full- half-duplex modes full Media Independent Interface (MII) with 4-bit parallel data transfer Gigabit Media Independent Interface (GMII)
I2O/DMA Controller
I20/DMA controller provides support messaging controllers (DMA0 DMA1). manages Message Frame Address (MFA) FIFOs queues memory response register reads writes transfers message frames. DMAs provide normal memory access support ease burden. features include: pull- push-messaging methods Dynamic message frame size Programmable FIFO size (4096 64-bit MFAs maximum) 64-bit 32-bit sizes Three interrupt gathering methods Registered prefetch posting 32-bit inbound outbound doorbell registers Four 32-bit scratch registers features include: Programmable Command Pointer FIFO Completion FIFO size 2048 operations queued) 512-byte buffering Simultaneous fill drain (PLB read/write pipelining) source address destination address memory alignment restrictions source destination 32-byte command descriptor block Maximum transfer size 16MB 64-bit addressing buffering (DMA1 only) Prefetch indicators PCI-X buffer management (DMA1 only)
Optional RAID RAID Acceleration Hardware
440SPe provides integrated acceleration hardware that implements high throughput RAID RAID algorithms compute single parity RAID dual parity RAID RAID used recover data case single disk drive failure, RAID provides data recovery disk drives fail. 440SPe offers choice engines computing parity. first choice available with XOR/DMA2 acceleration unit used RAID second choice parity computation, along with RAID Galois Field GF(28)-based polynomial computations, resides inside Memory Queue functional block Memory Controller unit. Galois Field polynomial used with 440SPe programmable sixteen available irreducible polynomials, including 11d. RAID RAID parity computations performed Memory Queue assisted two-channel engine I2O/DMA controller unit, designated DMA0 DMA1. RAID acceleration hardware also provides various alternatives balancing load performance, depending customer-specific application firmware. two-way crossbar architecture perform data read write operations simultaneously, resulting extremely high throughput. RAID capability available only with RAID-enabled part numbers (PPC440SPe-RpBfffC) indicated ordering information section this data sheet.
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PowerPC 440SPe Embedded Processor
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more information about RAID implementation, description, configuration acceleration hardware, refer following AMCC documents: PowerPC 440SP/440SPe RAID Support Application Note PowerPC 440SPe RAID Addendum User's Manual
XOR/DMA2 Controller
XOR/DMA2 controller performs functions needed support RAID applications including parity generation check functions used across data stripes RAID system. Computes bit-wise data streams with result stored designated target Performs check data streams Driven linked list Command Block structure specifying control information, source operands, target operand, status information, link Source target streams reside anywhere address space. Provides completion status Command Block handled software later time 96-byte 160-byte Command Block formats supported memory alignment restrictions operands target Internal register arrays data buffers parity protected used controller (DMA2) with single source target addresses Master interface Slave port used control interface reading writing control status information
Serial Port
serial port compatible with 16570 UART interface. Features include: 8-pin, 4-pin, 2-pin interfaces provided Selectable internal external serial clock allow wide range baud rates Register compatibility with 16750 register Complete status reporting capability Fully programmable serial-interface characteristics
Interface
Features include: interfaces provided Support Philips, Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters Supports fixed interface independent byte data buffers Twelve memory-mapped, fully programmable configuration registers programmable interrupt request signal Full management protocols Programmable error recovery Port supports serial Bootstrap with default override parameters initialization
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PowerPC 440SPe Embedded Processor
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General Purpose Timers (GPT)
Provides time base counter system timers additional those defined processor core. 32-bit time base counter driven clock Seven 32-bit compare timers
General Purpose (GPIO) Controller
Controller functions GPIO registers programmed accessed means memory-mapped master accesses. GPIOs pin-shared with other functions. DCRs control whether particular that GPIO capabilities acts GPIO used another purpose. Each GPIO output separately programmable tri-state driver (pull-up, pull-down, open-drain).
Universal Interrupt Controller (UIC)
Four cascaded Universal Interrupt Controllers (UIC) process internal on-chip external processor interrupts. Note: Processor specific interrupts (for example, page faults) resources. Features include: external interrupts internal interrupts Edge-triggered level-sensitive Positive- negative-active Non-critical critical interrupt on-chip processor core Programmable interrupt priority ordering Programmable critical interrupt vector faster vector processing
JTAG
Features include: IEEE 1149.1 Test Access Port RISCWatch Debugger support JTAG Boundary Scan Description Language (BSDL)
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PowerPC 440SPe Embedded Processor
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Figure 27mm, 675-Ball FC-PBGA Core Package
View
Corner
PPC440SPe
xpBfffC
Part Number
Number
AAAAAAAA
Note: dimensions
Bottom View
27.0
27.0
SOLDERBALL
1.00
3.22
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PowerPC 440SPe Embedded Processor
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Signal Lists
This section contains tables that list external signals. Table lists external signals alphabetical order shows ball (pin) number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signal(s) brackets. Table multiplexed pins that have internal signal connected after reset marked High Multiplexed signals appear alphabetically multiple times list-once each signal name ball. page number listed gives page "Signal Functional Description" page where signals indicated interface group begin. Table page lists external signals order ball (pin) number. Signal List-Alphabetic Order
Table Signals Listed Alphabetically (Sheet
Signal Name BankSel0 BankSel1 BankSel2 BankSel3 ClkEn0 ClkEn1 ClkEn2 ClkEn3 Ball AE22 AD21 AE21 AD20 SDRAM AB22 AA22 AE25 AF25 AD25 SDRAM Interface Group Page
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Table Signals Listed Alphabetically (Sheet
Signal Name DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 Ball AA23 AA24 SDRAM Interface Group Page
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Table Signals Listed Alphabetically (Sheet
Signal Name EMCCD EMCCrS EMCGTxClk EMCMDClk EMCMDIO EMCRefClk EMCRxClk EMCRxD0 EMCRxD1 EMCRxD2 EMCRxD3 EMCRxD4 EMCRxD5 EMCRxD6 EMCRxD7 EMCRxDV EMCRxErr EMCTxClk EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxD4 EMCTxD5 EMCTxD6 EMCTxD7 EMCTxEn EMCTxErr ExtReset Ball Ethernet System Power Interface Group Page
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Table Signals Listed Alphabetically (Sheet
Signal Name Ball Interface Group Page
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Table Signals Listed Alphabetically (Sheet
Signal Name Ball Power Interface Group Page
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PowerPC 440SPe Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name [GPIO00] [TRCCLK] High [GPIO01] [TRCBS0] High [GPIO02] [TRCBS1] High [GPIO03] [TRCBS2] High [GPIO04] [TRCES0] High [GPIO05] [TRCES1] High [GPIO06] [TRCES2] High [GPIO07] [TRCES3] High [GPIO08] [TECES4] High [GPIO09] [TRCTS0] High [GPIO10] [TRCTS1] High Ball AC01 AC07 AC13 AC14 AC20 AC26 AF04 AF10 AF17 AF23 GPIO Peripherals Note: Trace enabled reset setting SDR0_SDSTP1[DBG] (bit serial bootstrap ROM. Power Interface Group Page
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PowerPC 440SPe Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name [GPIO11] [TRCTS2] High [GPIO12] [TRCTS3] High [GPIO13] [TRCTS4] High [GPIO14] [TRCTS5] High [GPIO15] [TRCTS6] High [GPIO16] IRQ0 [GPIO17] IRQ1 [GPIO18] IRQ2 [GPIO19] IRQ3 [GPIO20] IRQ4 [GPIO21] IRQ5 [GPIO22] IRQ6 [GPIO23] IRQ7 [GPIO24] IRQ8 [GPIO25] IRQ9 [GPIO26] IRQ10 [GPIO27] IRQ11 [GPIO28] IRQ12 [GPIO29] IRQ13 [GPIO30] IRQ14 [GPIO31] IRQ15 Halt HISRRst IIC0SClk IIC0SDA IIC1SClk IIC1SDA Ball System AD17 Peripheral GPIO Peripherals Interface Group Page
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PowerPC 440SPe Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name IRQ0 [GPIO16] IRQ1 [GPIO17] IRQ2 [GPIO18] IRQ3 [GPIO19] IRQ4 [GPIO20] IRQ5 [GPIO21] IRQ6 [GPIO22] IRQ7 [GPIO23] IRQ8 [GPIO24] IRQ9 [GPIO25] IRQ10 [GPIO26] IRQ11 [GPIO27] IRQ12 [GPIO28] IRQ13 [GPIO29] IRQ14 [GPIO30] IRQ15 [GPIO31] MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemAddr13 MemAddr14 Ball Interrupts AF22 AF19 AD22 AF18 AB24 AF21 AE18 AE20 AD19 AB26 AB17 AE19 SDRAM Interface Group Page
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PowerPC 440SPe Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name MemClkOut0 MemClkOut0 MemClkOut1 MemClkOut1 MemClkOut2 MemClkOut2 MemClkOut3 MemClkOut3 MemClkOut4 MemClkOut4 MemClkOut5 MemClkOut5 MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 Ball AA21 AA20 AB21 AC21 AB19 AC19 AA19 AB20 AA18 AB18 AC18 AD18 AC25 AA26 AC24 AA25 SDRAM AD24 AD23 AB25 AB23 Interface Group Page
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PowerPC 440SPe Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 Ball SDRAM Interface Group Page
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PowerPC 440SPe Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 MemData60 MemData61 MemData62 MemData63 MemDCFdbkD MemDCFdbkR MemODT0 MemODT1 MemODT2 MemODT3 MemVRef0 MemVRef1 ball Ball SDRAM AE24 AF24 Interface Group Page
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Table Signals Listed Alphabetically (Sheet
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball Power Interface Group Page
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Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name PCIE_PLLGNDA PCIE_PLLGNDB PCIE_PLLVDD2 PCIE_PLLVDDA PCIE_PLLVDDB PCIE_REFCLK PCIE_REFCLK PCIE0_RX0 PCIE0_RX0 PCIE0_RX1 PCIE0_RX1 PCIE0_RX2 PCIE0_RX2 PCIE0_RX3 PCIE0_RX3 PCIE0_RX4 PCIE0_RX4 PCIE0_RX5 PCIE0_RX5 PCIE0_RX6 PCIE0_RX6 PCIE0_RX7 PCIE0_RX7 PCIE0_TX0 PCIE0_TX0 PCIE0_TX1 PCIE0_TX1 PCIE0_TX2 PCIE0_TX2 PCIE0_TX3 PCIE0_TX3 Ball AB11 AC11 AD12 AD13 AF15 AF16 AE16 PCI-Express AD15 AA11 AF11 AE11 AB12 AA12 AE13 AF12 Power Interface Group Page
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PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name PCIE0_TX4 PCIE0_TX4 PCIE0_TX5 PCIE0_TX5 PCIE0_TX6 PCIE0_TX6 PCIE0_TX7 PCIE0_TX7 PCIE0AV25 PCIE0AVREG PCIE1_RX0 PCIE1_RX0 PCIE1_RX1 PCIE1_RX1 PCIE1_RX2 PCIE1_RX2 PCIE1_RX3 PCIE1_RX3 PCIE1_TX0 PCIE1_TX0 PCIE1_TX1 PCIE1_TX1 PCIE1_TX2 PCIE1_TX2 PCIE1_TX3 PCIE1_TX3 PCIE1AV25 PCIE1AVREG Ball AE14 AD14 AB16 AC16 AA15 AA16 PCI-Express Interface Group Page
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name PCIE2_RX0 PCIE2_RX0 PCIE2_RX1 PCIE2_RX1 PCIE2_RX2 PCIE2_RX2 PCIE2_RX3 PCIE2_RX3 PCIE2_TX0 PCIE2_TX0 PCIE2_TX1 PCIE2_TX1 PCIE2_TX2 PCIE2_TX2 PCIE2_TX3 PCIE2_TX3 PCIE2AV25 PCIE2AVREG PCIECalRN PCIECalRP PCIEPLLTSTON Ball PCI-Express Interface Group Page
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name PCIX0Ack64 PCIX0AD0 PCIX0AD1 PCIX0AD10 PCIX0AD11 PCIX0AD12 PCIX0AD13 PCIX0AD14 PCIX0AD15 PCIX0AD16 PCIX0AD17 PCIX0AD18 PCIX0AD19 PCIX0AD2 PCIX0AD20 PCIX0AD21 PCIX0AD22 PCIX0AD23 PCIX0AD24 PCIX0AD25 PCIX0AD26 PCIX0AD27 PCIX0AD28 PCIX0AD29 PCIX0AD3 PCIX0AD30 PCIX0AD31 PCIX0AD32 Ball AD02 AB04 AA05 AB02 AA03 AA02 AA01 PCI-X0 AD10 Interface Group Page
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name PCIX0AD33 PCIX0AD34 PCIX0AD35 PCIX0AD36 PCIX0AD37 PCIX0AD38 PCIX0AD39 PCIX0AD4 PCIX0AD40 PCIX0AD41 PCIX0AD42 PCIX0AD43 PCIX0AD44 PCIX0AD45 PCIX0AD46 PCIX0AD47 PCIX0AD48 PCIX0AD49 PCIX0AD5 PCIX0AD50 PCIX0AD51 PCIX0AD52 PCIX0AD53 PCIX0AD54 PCIX0AD55 PCIX0AD56 PCIX0AD57 PCIX0AD58 PCIX0AD59 PCIX0AD6 PCIX0AD60 Ball AA10 AF09 AF08 AD09 AF06 AD08 AC09 AE06 AD07 AC08 AB09 AE05 AD06 AB08 AA09 AC02 AF03 AE04 AA08 AB07 AF02 AE03 AD04 AC05 AE07 AA04 PCI-X0 Interface Group Page
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name PCIX0AD61 PCIX0AD62 PCIX0AD63 PCIX0AD7 PCIX0AD8 PCIX0AD9 PCIX0BE0 PCIX0BE1 PCIX0BE2 PCIX0BE3 PCIX0BE4 PCIX0BE5 PCIX0BE6 PCIX0BE7 PCIX0CalG0 PCIX0CalR0 PCIX0Cap PCIX0Clk PCIX0DevSel PCIX0ECC2 PCIX0ECC3 PCIX0ECC4 PCIX0ECC5 PCIX0Frame PCIX0Gnt0 PCIX0Gnt1 PCIX0Gnt2 PCIX0Gnt3 PCIX0IDSel Ball AA07 AE02 AB05 AA06 AC06 AB06 AE09 AE08 PCI-X0 Interface Group Page
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PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name PCIX0INTA PCIX0IRDY PCIX0M66En PCIX0Par PCIX0Par64 PCIX0PErr PCIX0PLLG PCIX0PLLV PCIX0Req0 PCIX0Req1 PCIX0Req2 PCIX0Req3 PCIX0Req64 PCIX0Reset PCIX0Serr PCIX0Stop PCIX0TRDY PCIX0VC PCIX0VRef0 PCIX0VRef1 PerAddr0 PerAddr1 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 Ball AB01 AD03 AE01 AD01 PCI-X0 AC03 AF05 AD05 AB03 External Slave Peripheral (EBC) Interface Group Page
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PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr2 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerBE0 PerBE1 PerBLast PerClk PerCS0 PerCS1 PerCS2 PerData00 PerData01 PerData02 PerData03 PerData04 Ball External Slave Peripheral (EBC) Interface Group Page
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PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerErr PerOE PerPar0 PerPar1 PerR/W PerReady PerWE PSRO1 PxVDD PxVDD PxVDD PxVDD PxVDD PxVDD PxVDD PxVDD PxVDD PxVDD PxVDD Ball External Slave Peripheral (EBC) Power Miscellaneous Interface Group Page
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PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name PxVDD PxVDD PxVDD SCANOUT00 SCANOUT07 SCANOUT08 SCANOUT14 SCANOUT15 SCANOUT16 SCANOUT17 SCANOUT18 SCANOUT19 SCANOUT20 SCANOUT21 SCANOUT25 SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD Ball AF01 AF07 AF13 AE23 AB10 AE10 AD11 Tests AC12 AE12 AB13 AB14 AE15 Power AF14 AF20 AF26 SDRAM Power Interface Group Page
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PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name SYS2PLLG SYS2PLLV SYSClk SYSErr SysPartSel SYSPLLG SYSPLLV SysReset TESTEN THERMALDA THERMALDB TMR_CLK [TRCCLK] [GPIO00] High [TRCBS0] [GPIO01] High [TRCBS1] [GPIO02] High [TRCBS2] [GPIO03] High [TRCES0] [GPIO04] High [TRCES1] [GPIO05] High [TRCES2] [GPIO06] High [TRCES3] [GPIO07] High [TRCES4] [GPIO08] High [TRCTS0] [GPIO09] High [TRCTS1] [GPIO10] High [TRCTS2] [GPIO11] High [TRCTS3] [GPIO12] High [TRCTS4] [GPIO13] High [TRCTS5] [GPIO14] High [TRCTS6] [GPIO15] High TRST Ball AD26 AE26 AA17 AB15 JTAG AD16 AA13 Miscellaneous AA14 AC15 AE17 JTAG Note: Trace enabled reset setting SDR0_SDSTP1[DBG] (bit serial bootstrap ROM. Trace System JTAG System Power Interface Group Page
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PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name UARTSerClk UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_DSR/CTS UART1_DTR/RTS UART1_Rx UART1_Tx UART2_Rx UART2_Tx Ball UART Peripheral Interface Group Page
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Alphabetically (Sheet
Signal Name Ball Power AC04 AC10 AC17 AC23 AC22 SDRAM Interface Group Page
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Signal List-Ball Assignment Order following table, only primary (default) signal name shown each pin. Multiplexed pins marked with asterisk (*). determine other signals that share pin, look primary signal name Table page Table Signals Listed Ball Assignment (Sheet
Ball Signal name ball IRQ9* PerPar1 EMCTxD3 PerAddr22 OVDD PerAddr17 PCIX0M66En SysPartSel UART1_Rx OVDD OVDD PerAddr8 PerWE PCIE1_TX3 PCIE1_RX3 OVDD PCIE1_TX1 PerAddr24 MemData59 MemData62 OVDD Ball Signal name EMCRxClk EMCMDIO PerData13 PerBE1 PerData02 PerPar0 PerAddr18 UART0_CTS PerAddr15 EMCTxD7 ExtReset UART1_Tx SYSPLLV SYSPLLG PerAddr2 PerAddr10 PerAddr26 PCIE1_TX3 PCIE1_RX3 PCIE1_TX1 PCIE1_RX1 MemData63 MemData61 MemData58 DQS7 MemData60 Ball Signal name EMCTxEn EMCTxClk EMCTxD0 PerData11 EMCTxD5 PerData04 PerBE0 PerAddr21 PerAddr16 PerAddr14 PerCS1 UART0_DSR UART0_DTR UART0_RI PerCS0 SYSCLK PerClk PCIE1_TX2 PCIE1_RX2 PCIE1_RX1 PCIE1_TX0 GPIO28_IRQ12 MemData56 DQS7 MemData57 Ball Signal name EMCTxErr EMCCrS PerData10 PerData15 PerAddr23 UART0_Tx PerAddr13 UART0_Rx PerAddr3 PerBLast PCIE1_TX2 PCIE1_RX2 PCIE1_TX0 MemData54 MemData55 MemData53
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PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Ball Assignment (Sheet
Ball Signal name EMCTxD6 GPIO19_IRQ3 EMCTxD4 IRQ4* PerOE PerData09 PerData14 PerData06 PerAddr20 PCIX0Gnt1 PerAddr19 TESTEN PerAddr0 PerAddr1 PerAddr11 PerReady PerAddr25 PCIE1AVREG PCIE1AV25 PCIE1_RX0 PCIE1_RX0 DQS6 MemData51 IRQ11* MemData52 IRQ10* Ball Signal name TRCBS1* TRCES3* EMCMDClk EMCRxErr EMCRxD7 IRQ7* PerData07 PerData12 PerData08 UART1_DSR/CTS PerAddr12 UART2_Tx UART2_Rx PerAddr9 PerR/W Reserved Reserved PCIE2_RX3 PCIE2_RX3 PCIE2_RX2 PCIE2_RX2 DQS6 MemData49 MemData50 MemData48 Ball Signal name OVDD TRCES1* EMCRxD2 TRCTS2* EMCTxD1 OVDD PerData00 UART0_RTS UART1_DTR/RTS PerCS2 OVDD OVDD PerErr Reserved Reserved PCIE2_TX3 OVDD PCIE2_TX2 MemData43 DQS5 OVDD Ball Signal name TRCBS0* EMCRxD3 EMCRxD4 TRCTS0* EMCCD TRCTS6* EMCRefClk IRQ8* IRQ5* PerData01 PerData03 UARTSerClk UART0_DCD PerAddr5 IIC1SDA PerAddr4 IIC0SClk IIC1SClk PCIE2_TX3 PCIE2_TX1 PCIE2_TX2 MemData45 MemData42 MemData44 DQS5 MemData41
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PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Ball Assignment (Sheet
Ball Signal name PCIEPLLTSTON EMCRxD1 TRCES4* TRCTS4* TRCTS1* EMCRxDV EMCTxD2 EMCGTxClk PerData05 PerAddr7 PerAddr6 IIC0SDA PCIE2_RX1 PCIE2_TX1 PCIE2_RX0 MemData47 MemData40 MemData46 MemData37 Ball Signal name PCIX0Req1 TRCES0* PCIX0Req2 TRCTS5* TMR_CLK OVDD OVDD OVDD OVDD PCIE2_RX1 PCIE2_RX0 IRQ15* MemData33 IRQ14* Ball Signal name TRCCLK* TRCBS2* PCIX0Reset EMCRxD5 TRCTS3* EMCRxD0 IRQ6* IRQ0* SysReset OVDD OVDD PCIE2AV25 PCIE2AVREG PCIE2_TX0 PCIE2_TX0 DQS4 MemData35 IRQ13* MemData36 MemData34 Ball Signal name PCIX0VC PCIX0Req3 PCIX0Cap PCIX0Gnt2 TRCES2* IRQ1* EMCRxD6 IRQ2* OVDD OVDD ECC2 MemData38 DQS4 SCANOUT25 MemData39 SYSERR MemData32
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Ball Assignment (Sheet
Ball Signal name OVDD PCIE_PLLGNDB PCIE_PLLVDDB PCIX0Clk PCIX0Frame OVDD PCIX0DevSel PCIX0PErr OVDD OVDD OVDD OVDD ECC7 ECC5 OVDD ECC6 Halt MemData31 MemData29 OVDD Ball Signal name PxVDD PCIE_PLLGNDA PCIE_PLLVDDA PCIE_REFCLK PCIE_REFCLK PxVDD PCIX0ECC5 PCIE_PLLVDD2 PxVDD PxVDD SVDD SVDD ECC3 ECC4 SVDD DQS8 SCANOUT08 DQS3 DQS3 SVDD Ball Signal name PCIX0ECC4 PCIX0Req0 PCIX0ECC3 PCIX0Gnt3 PCIX0ECC2 PCIX0AD31 PCIX0AD30 PCIECalRP PxVDD SVDD ECC0 ECC1 DQS8 MemData27 MemAddr12 MemData25 MemAddr08 MemData30 Ball Signal name PCIX0AD29 PCIX0AD28 PCIX0Gnt0 PCIX0AD27 PCIX0AD26 PCIX0AD25 PCIX0AD24 PCIECalRN PCIX0VRef1 PxVDD SVDD MemData14 DQS1 MemData11 MemData09 MemData24 MemData26 MemAddr03 MemData28
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Ball Assignment (Sheet
Ball Signal name PCIX0INTA PCIX0BE3 PCIX0IDSel PCIX0AD23 PCIX0AD61 PSRO1 PxVDD PxVDD SVDD SVDD MemData08 DQS1 SCANOUT07 MemData16 SCANOUT00 Ball Signal name PCIX0AD22 PCIX0AD21 PCIX0AD20 PCIX0AD19 PCIX0AD18 PCIX0AD13 PCIX0AD9 PCIX0AD3 PCIE0_RX0 PCIE0AV25 PCIE0_RX6 MemVRef1 MemData10 MemData12 MemData13 MemData18 MemData19 MemData21 Ball Signal name PCIX0Par PCIX0BE2 PCIX0AD16 PCIX0AD17 PCIX0AD12 PCIX0AD8 PCIX0AD4 PCIX0AD53 PCIX0AD60 PCIX0AD34 PCIE0_RX0 PCIE0_RX2 PCIE0AVREG PCIE0_RX6 PCIE0_RX7 PCIE0_RX7 BankSel3 MemVRef0 MemODT3 MemODT2 MemODT0 MemData15 DQS2 DQS2 MemData17 MemData23 Ball Signal name PxVDD PCIX0BE1 PCIX0BE0 PCIX0AD7 PCIX0AD2 PxVDD PCIX0VRef0 PCIX0AD49 PCIE0_TX0 PCIE0_RX2 PxVDD SVDD PCIE0_TX6 PCIE0_TX7 BankSel1 BankSel2 SVDD ClkEn0 MemODT1 MemData20 MemData22 SVDD
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Ball Assignment (Sheet
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 Signal name PCIX0AD15 PCIX0AD14 PCIX0AD11 PCIX0AD6 PCIX0AD1 PCIX0BE5 PCIX0AD62 PCIX0AD52 PCIX0AD48 PCIX0AD33 PCIE0_TX0 PCIE0_TX2 THERMALDA THERMALDB PCIE0_TX6 PCIE0_TX7 MemClkOut4 MemClkOut3 MemClkOut0 MemClkOut0 ClkEn1 DQS0 DQS0 MemData03 MemData01 Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 Signal name PCIX0IRDY PCIX0AD10 PCIX0TRDY PCIX0AD0 PCIX0BE4 PCIX0BE7 PCIX0AD54 PCIX0AD47 PCIX0AD44 SCANOUT14 PCIE0_RX1 PCIE0_TX2 SCANOUT19 SCANOUT20 PCIE0_TX5 MemAddr13 MemClkOut4 MemClkOut2 MemClkOut3 MemClkOut1 MemData07 MemAddr05 MemData06 MemAddr11 Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 PCIX0AD5 PCIX0Req64 PCIX0AD58 PCIX0BE6 PCIX0AD43 PCIX0AD40 PCIE0_RX1 SCANOUT17 PCIE0_TX5 MemClkOut5 MemClkOut2 MemClkOut1 MemData02 MemData00 Signal name Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 Signal name PCIX0PLLV PCIX0Ack64 PCIX0Par64 PCIX0AD57 PCIX0Stop PCIX0AD46 PCIX0AD42 PCIX0AD39 PCIX0AD37 PCIX0AD32 SCANOUT16 PCIE0_RX3 PCIE0_RX3 PCIE0_TX4 PCIE0_RX5 HISRRst MemClkOut5 MemAddr10 BankSel0 MemAddr02 MemData05 MemData04 SYS2PLLG
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signals Listed Ball Assignment (Sheet
Ball AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 Signal name PCIX0PLLG PCIX0AD63 PCIX0AD56 PCIX0AD51 PCIX0AD45 PCIX0AD41 PCIX0AD59 PCIX0CalR0 PCIX0CalG0 SCANOUT15 PCIE0_TX1 SCANOUT18 PCIE0_TX3 PCIE0_TX4 SCANOUT21 PCIE0_RX5 TRST MemAddr07 MemAddr14 MemAddr09 MemDCFdbkD ClkEn2 SYS2PLLV Ball AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal name PxVDD PCIX0AD55 PCIX0AD50 PCIX0Serr PCIX0AD38 PxVDD PCIX0AD36 PCIX0AD35 PCIE0_TX1 PCIE0_TX3 PxVDD SVDD PCIE0_RX4 PCIE0_RX4 MemAddr04 MemAddr01 SVDD MemAddr06 MemAddr00 MemDCFdbkR ClkEn3 SVDD Ball Signal name Ball Signal name
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PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Signal Description
PPC440SPe embedded controller packaged 27mm Flip-Chip Plastic Ball Grid Array (FC-PBGA). following tables describe package level pinout. Table Summary
Group Total Signal Pins AxVDD (1.5V) AxVDD (2.5V HSS) AxGND OVDD (3.3V I/Os) PxVDD (3.3/1.5V PCI) SVDD (2.5/1.8V SDRAM) (1.5V logic) Total Power Pins Reserved Total Pins Pins
table "Signal Functional Description" page each signal listed along with short description function. Active-low signals (for example, RAS) marked with overline. "Signals Listed Alphabetically" page (ball) number which each signal assigned. Multiplexed Signals Some signals multiplexed same that used different functions. signal names shown Table page accompanied signal names that might multiplexed same pin. expected that single application particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. Strapping Pins group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Strapping" page 77). Note that these multiplexed pins since function pins programmable. Multipurpose Signals addition multiplexing, some pins also multi-purpose. example, PCIX0Ack function instead PCIX0ECC1 depending interface mode operation.
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name PCI-Express Interfaces Express Reference Clock: differential clock pair. Input type controlled PESDR0_PLLLCT1[MCENT] register. 2.5V CMOS LVDS 2.5V LVPECL (recommended) Express Serial Data Transmit differential signals Mode: PCIE0Tx[7:0]/PCIE0Tx[7:0] used. Mode: Only PCIE0Tx[3:0]/PCIE0Tx[3:0] used. Express Serial Data Receive differential signals Mode: PCIE0Rx[7:0]/PCIE0Rx[7:0] used. Mode: Only PCIE0Rx[3:0]/PCIE0Rx[3:0] used Express Analog Observation point internal voltage regulator Positive negative inputs Kohm Express External calibration resistor Enable Express test modes. Description Type
Notes
PCIE_REFCLK PCIE_REFCLK
Diff PECL
PCIE0Tx[7:0] PCIE0Tx[7:0] PCIE1:2Tx[3:0] PCIE1:2Tx[3:0] PCIE0Rx[7:0] PCIE0Rx[7:0] PCIE1:2Rx[3:0] PCIE1:2Rx[3:0] PCIE0:2AVREG PCIECalRP PCIECalRN PCIEPLLTSTON PCI-X0 Interfaces
LVDS
VDD=1.5V
LVDS
VDD=1.5V
PCIX0Ack64/PCIX0ECC1
Ack64 ECC1. Normally used Ack64 indicating that target transfer data using bits. Used ECC1 PCIX mode Address/Data (bidirectional) PCI-X0
3.3V 1.5V mode 3.3V 1.5V mode 3.3V 1.5V mode
PCIX0AD63:00
PCIX0BE7:0
PCI-X Byte Enables PCI-X0 Balls External calibration resistor. Used control PCI-X Impedance Ohm. Capable PCI-X operation. This analog input sampled configure determine state PCIX0VC output signal: 0.00VDD (0.0V) Conventional PCIX0VC
PCIX0CalG0 PCIX0CalR0
PCIX0Cap
0.49VDD (1.0V) PCI-X Mode PCIX0VC 0.75VDD (2.5V) PCI-X PCIX0VC 1.00VDD (3.3V) PCI-X PCIX0VC
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Description Input PCI-X Clock. PCIX0Clk Type
Notes
Note: PCI-X interface being used, drive this
with 3.3V clock signal frequency between 66MHz Indicates driving device decoded address target current access. check bits 5-2. bits valid only PCIX mode
3.3V
PCIX0DevSel
3.3V
PCIX0ECC5:2
Note: PCIXPar ECC0.
PCIXAck64 ECC1. PCIXReq64 ECC6. PCIXPar64 ECC7. Driven current master indicate beginning duration access. Indicates that specified agent granted access PCI-X bus. When Arbitration internal PPC440SPe, GRANTS Gnt0:3 outputs. When arbitration external, only used Input. Used chip select during configuration read write transactions. PCI-X Host, during Configuration ISDSEL Output that duplicates AD17. ISDSEL always 3.3V even Mode Level sensitive interrupt. Indicates initiating agent's ability complete current data phase transaction. Capable 66MHz operation. Even parity indicator ECC0. Normally used indicate even parity across PCIAD31:00 BE3:0. Used ECC0 PCIX0 mode Even parity indicator ECC7. Normally used indicate even parity across PCIXAD63:32 BE7:4 PCIX0 Used ECC7 PCIX0 mode Reports data parity errors during transactions except Special Cycle. indication PCI-X arbiter that specified agent wishes bus. When Arbitration internal PPC440SPe, REQS Req0:3 Inputs. When arbitration external, only used output.
3.3V 1.5V mode
PCIX0Frame
3.3V
PCIX0Gnt0 PCIX0Gnt1:3
3.3V
PCIX0IDSel
3.3V
PCIX0INTA PCIX0IRDY
3.3V 3.3V 3.3V 1.5V mode 3.3V 1.5V mode
PCIX0M66En
PCIX0Par/PCIX0ECC0
PCIX0Par64/PCIX0ECC7
3.3V 1.5V mode
PCIX0PErr
3.3V
PCIX0Req0 PCIX0Req1:3
3.3V
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Description Request 64-bit transfer ECC6. Normally used current master indicate 64-bit transfer. Used ECC6 PCIX0 mode Sets device registers logic consistent state. Reports address parity errors, data parity errors Special Cycle command, other catastrophic system errors. Indicates current target requesting master stop current transaction. Type 3.3V 1.5V mode 3.3V 3.3V
Notes
PCIX0Req64/PCIX0ECC6
PCIX0Reset PCIX0SErr
PCIX0Stop PCIX0TRDY
3.3V 3.3V
Indicates target agent's ability complete current data phase transaction.
Voltage control output. Used control voltage regulator supplying voltage. PCIX0Cap signal. 3.3V (PCI I/O) =1.5V (PCI-X DDR) Voltage reference input PCI-X mode 2/PCI-X (1.5V) I/O. used PCI-X mode
PCIX0VC
3.3(1.5)V
PCIX0VRef0:1 SDRAM Interface BA0:2 BankSel0:3 ClkEn0:3 DM0:8 DQS0:8 DQS0:8 ECC0:7 MemAddr14:00
VPCIXDDR
Bank Address supporting internal banks. Selects four external SDRAM banks. Column Address Strobe. Clock Enable. each external bank. Memory write data byte lane masks. MEMDM8 byte lane mask byte lane. Byte lane data strobe. DQS8 data strobe byte lane. These signals differential pairs. check bits 0:7. Memory address bus.
2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM DIFF 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM
Note: MemAddr14 most significant (msb).
Subsystem clocks. Clock signal (differential pair) duplicated times support high loading: clocks used unbuffered DIMMS. Each individual clock signal enabled programming SDR0_DDRCLKSET register. Memory data bus.
MemClkOut0:5 MemClkOut0:5
2.5(1.8)V SDRAM DIFF
MemData63:00
Note: MemData63 most significant (msb).
2.5(1.8)V SDRAM
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name MemDCFdbkD MemDCFdbkR MemODT0:3 Description Feedback driver, timing measurements. Feedback receiver. Connect externally MemDCFdbkD. Memory on-die termination control Type 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM Volt 2.5(1.8)V SDRAM Volt 2.5(1.8)V SDRAM 2.5(1.8)V SDRAM
Notes
MemVRef0
Memory reference voltage (SVREF) input.
MemVRef1
Memory reference voltage (SVREF) supplemental input.
Ethernet Interface EMCCD EMCCrS EMCMDClk EMCMDIO EMCRxD0:7 EMCRxDV EMCRxErr EMCRxClk EMCRefClk EMCTxClk EMCGTxClk EMCTxD0:7 EMCTxEn EMCTxErr
Address Strobe. Write Enable.
Collision detection. Carrier sense. Management data clock. Transfer command status information between PHY. Receive data. Receive data valid. Receive error. Receive clock. Reference clock.Typical use: GMII Gigabit interface Transmit clock 10/100 Mb/s. Ethernet gigabit transmit clock. 125MHz Transmit data. Transmit data enabled. Transmit error.
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
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Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name External Slave Peripheral Interface PerAddr00:26 PerBE0:1 PerBLast PerCS0:2 PerData00:15 Peripheral address bus. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Description Type
Notes
Note: PerAddr00 most significant (msb).
External peripheral data byte enable. Used peripheral controller indicates last transfer memory access. External peripheral device select. Peripheral data bus.
Note: PerData0 most significant (msb).
Used peripheral controller controller depending upon type transfer involved. When PPC440SPe master, enables selected device drive bus. External peripheral data byte parity. Used peripheral slave indicate ready transfer data. peripheral controller this signal High Read from external memory, Write. Write Enable. Peripheral clock used synchronous peripheral slaves. External error used input record external slave peripheral errors.
PerOE
3.3V LVTTL
PerPar0:1 PerReady PerR/W PerWE PerClk PerErr Peripheral Interface IIC0SClk IIC0SDA IIC1SClk IIC1SDA
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
IIC0 Serial Clock. IIC0 Serial Data. IIC1 Serial Clock. IIC1 Serial Data.
3.3V 3.3V 3.3V 3.3V
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Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name UART Peripheral Interface Serial clock input that provides alternative internally generated serial clock. Used cases where allowable internally generated clock rates satisfactory. UART0 Receive data. UART0 Transmit data. UART0 Data Carrier Detect. UART0 Data Ready. UART0 Clear Send. UART0 Data Terminal Ready. UART0 Request Send. UART0 Ring Indicator. UART1 Receive data. UART1 Transmit data. UART1 Data Ready Clear Send. choice determined register setting. UART1 Request Send Data Terminal Ready. choice determined register setting. UART2 Receive data. UART2 Transmit data. Description Type
Notes
UARTSerClk
3.3V LVTTL
UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RTS UART0_RI UART1_Rx UART1_Tx UART1_DSR/CTS UART1_DTR/RTS UART2_Rx UART2_Tx Interrupts Interface IRQ0:15 System Interface Halt GPIO00:31 SysClk SysErr SysPartSel SysReset
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
External interrupt Requests through These pins multiplexed with GPIO16:31
3.3V LVTTL
Halt from external debugger. General purpose through GPIOs multiplexed with IRQs, Trace signal Setting done with register bits. Main system clock input. when machine check generated. used. Main system reset. External logic drive this (minimum cycles) initiate system reset. reset PPC440SPe also initiated software. External Reset. During PPC440SPe's reset phase this signal down level.
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
ExtReset
3.3V LVTTL
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Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name HISRRst TESTEN TMR_CLK JTAG Interface Test Clock. Test Data Test Data Out. Test Mode Select. Test Reset. During chip power-up, this signal must from start ramp-up until least SysClk cycles after stable order initialize JTAG controller. 3.3V LVTTL 3.3V LVTTL w/pull-down 3.3V LVTTL 3.3V LVTTL with pull-up 3.3V LVTTL with pull-up Description Hardware initiated system reset with initial SDRAM self-refresh phase save data Memory. Test Enable. Processor timer external input clock. Type 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Notes
TRST
Trace Interface TrcClk TRCBS0:2 TrcES0:4 TrcTS0:6 Tests SCANOUT[00][07:08] [14:21] [25] Power PCIE0:2AV25 PCIE_PLLVDD2 PCIE_PLLVDDA PCIE_PLLVDDB PCIE_PLLGNDA PCIE_PLLGNDB PCIX0PLLG PCIX0PLLV 2.5V supply voltage serial link Express 2.5V supply voltage Express Reference clock Input receiver front Analog 2.5V filtered supply voltage Express Analog 2.5V filtered supply voltage Express GNDA Express GNDB Express Ground PCI-X0 Analog 1.5V Filtered Supply voltages input PCI-X0 separate filter analog voltages recommended. 36mA 20mA 20mA Test scan Manufacturing test signals: need termination Trace data capture clock, runs frequency processor. Trace branch execution status. Trace Execution Status presented every fourth processor clock cycle. Additional information trace execution branch status. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
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Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name SYSPLLG SYSPLLV SYS2PLLG SYS2PLLV OVDD PxVDD Description Ground SYS_PLL Analog 1.5V Filtered Supply voltages input SYS_PLL separate filter analog voltages recommended. Ground DDR_PLL (SDRAM) Analog 1.5V Filtered Supply voltages input DDR_PLL (SDRAM) separate filter analog voltages recommended. Logic voltage ground. 3.3V supply (except SDRAM PCI-X). PCI-X voltage supply. PCI-X PCI-X Mode SDRAM voltage supply. 2.5V DDR1 SDRAM 1.8V DDR2 SDRAM Voltage supply for: 1.5V internal logic 1.5V I/Os Express ports Type
Notes
SVDD
Miscellaneous PSRO1 THERMALDA THERMALDB Reserved
Performance Screen Ring Oscillator. chip Diode thermal monitoring. diffusion (In), (out) connect voltage, ground, signals these pins.
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Device Characteristics
Table Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device. None performance specification contained this document guaranteed when operating these maximum ratings.
Characteristic Supply Voltage (Internal logic) Supply Voltage (I/O interface, except SDRAM) Supply Voltage (PCI-X I/O) Supply Voltage (PCI-X I/O) Supply Voltages (System PLLs) Supply Voltages (PCI-X PLLs) Supply Voltage (DDR SDRAM logic) Supply Voltage (DDR2 SDRAM logic) Input Voltage (3.3V LVTTL receivers) Storage temperature range Case temperature under bias Notes: analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440SPe. separate filter, shown below, recommended each voltage: AxVDD, APxVDD PCIE_PLLVDDA Express Murata BLM15AG102SN1 ceramic Symbol OVDD PxVDD PxVDD AxVDD APxVDD SVDD SVDD TSTG Value +1.6 +3.6 +3.6 +1.6 +1.6 +1.6 +2.7 +1.95 +3.6 +150 +120 Unit Notes
ferrite bead chip, Murata BLM31A700S ceramic
This value specification operational temperature range, stress rating only 800MHz voltage range 1.5V 1.6V
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Table Package Thermal Specifications
Thermal resistance values PPC440SPe package convection environment follows:
Airflow ft/min (m/sec) Parameter Symbol Junction-to-case thermal resistance Case-to-ambient thermal resistance (w/o heat sink) (0.51) 13.1 Range Minimum Junction-to-ball (typical) Notes: Case temperature, measured center case surface with device soldered circuit board. this part junction temperature case temperature essentially identical. case-to-ambient thermal resistance measured JEDEC JESD51-6 standard environment; accurately predict thermal performance production equipment environments. operational case temperature must maintained. °C/W theoretical using infinite heat sink. larger number applies module mounted 1.8mm thick, card using 1oz. copper power planes, with effective heat transfer area 75mm2. Maximum °C/W (1.02) 11.9 °C/W °C/W Unit Notes
15.5
Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Logic Supply Voltage Supply Voltage PCI-X Supply Voltage PCI-X mode Voltage Reference Input PCI-X Mode DDR1 SDRAM Supply Voltage (DDR400) DDR2 SDRAM Analog System Supply Voltages Analog Express Supply voltage Analog PCI-X Supply Voltages DDR1 SDRAM Reference Voltage DDR2 SDRAM Reference Voltage
Symbol OVDD PxVDD PCIX0VRef0:1 SVDD AxVDD APExVDD APxVDD SVREF SVREF
Minimum +1.425 +3.0 +3.0 +1.425 +1.425 +2.3 +1.7 +1.4 1.65 +1.4 +1.15 0.49 SVDD
Typical +1.5 +3.3 +3.3 +1.5 +1.5 +2.5 (2.6) +1.8 +1.5 +2.5 +1.5 +1.25 0.50 SVDD
Maximum +1.575 +3.6 +3.6 +1.575 +1.575 +2.7 +1.9 +1.6 +2.75 +1.6 +1.35 0.51 SVDD
Unit
Notes
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Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Input Logic High (2.5V SDRAM) Input Logic High (1.8V DDR2 SDRAM) Input Logic High (2.5V CMOS, 3.3V tolerant receiver) Input Logic High (3.3V PCI-X) Input Logic High (1.5V PCI-X DDR) Input Logic High (3.3V LVTTL) Input Logic (2.5V SDRAM) Input Logic (1.8V DDR2 SDRAM) Input Logic (2.5V CMOS, 3.3V tolerant receiver) Input Logic (3.3V PCI-X) Input Logic (1.5V PCI-X DDR) Input Logic (3.3V LVTTL) Output Logic High (2.5V SDRAM) Output Logic High (1.8V DDR2 SDRAM) Output Logic High (2.5V CMOS, 3.3V tolerant receiver) Output Logic High (3.3V PCI-X) Output Logic High (1.5V PCI-X DDR) Output Logic High (3.3V LVTTL) Output Logic (2.5V SDRAM) Output Logic (1.8V DDR2 SDRAM) Output Logic (2.5V CMOS, 3.3V tolerant receiver) Output Logic (3.3V PCI-X) Output Logic (1.5V PCI-X DDR) Output Logic (3.3V LVTTL) Input Leakage Current (with internal pull-up pull-down) Input Leakage Current (with internal pull-down) Input Leakage Current (with internal pull-up)
Symbol
Minimum SVREF+0.18 SVREF+0.125
Typical
Maximum SVDD+0.3 SVDD+0.3
Unit
Notes
0.5OVDD +2.0 -0.3 -0.3 OVDD+0.5 +3.6 SVREF-0.18 SVREF-0.125 -0.5 +1.95 SVDD-0.45 0.9OVDD +2.4 OVDD OVDD 0.45 0.45 0.1OVDD IIL1 IIL2 IIL3 (LPDL) -150 (LPDL) +0.4 (MPUL) (MPUL) 0.35OVDD +0.8 SVDD SVDD
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Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Input Allowable Overshoot (3.3V LVTTL) Input Allowable Undershoot (3.3V LVTTL) Output Allowable Overshoot (3.3V LVTTL) Output Allowable Undershoot (3.3V LVTTL) Case Temperature Notes:
Symbol VIMAO VIMAU VOMAO VOMAU3
Minimum
Typical
Maximum +3.9
Unit
Notes
-0.6 +3.9 -0.6
PCI-X drivers meet PCI-X specifications. SVREF SVDD/2 analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440SPe. "Absolute Maximum Ratings" page During chip power-up, OVDD should begin ramp before VDD. External voltage should applied chip pins before OVDD applied chip. power-down cycle should complete (OVDD should both below 0.4V) before power cycle started. LPDL least positive down level; MPUL most positive level. Case temperature, measured center case surface with device soldered circuit board.
Table Input Capacitance
Parameter Group (2.5V SSTL I/O) Group (3.3V LVTTL I/O) Group (PCI-X I/O) Group (Receivers) Group (3.3V tolerant CMOS I/O) Group (1.5V Express) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 Maximum Unit Notes
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Table Power Supply Loads
Parameter (1.5V) active operating current OVDD (3.3V) active operating current PxVDD (3.3V) active operating current PxVDD (1.5V) active operating current SVDD (2.5V) active operating current SVDD (1.8V) active operating current AxVDD (1.5V) input current APxVDD (1.5V) input current Symbol IODD IPDD IPDD ISDD ISDD IADD IAPDD Minimum Typical Maximum 5400 1200 Unit Notes
Notes: "Absolute Maximum Ratings" page filter recommendations. Valid only CPU/PLB/OPB 533.33/133.33/66.66 MHz.
Clock Test Conditions
Clock timing switching characteristics specified accordance with operating conditions shown table "Recommended Operating Conditions." specifications characterized with 1.5V, 10pF test load shown figure right. Note: 800MHz voltage range 1.5V 1.6V.
Output
10pF
Table Clocking Specifications
Symbol SysClk Input Frequency Period Edge stability (cycle-to-cycle jitter) High time time 33.33 nominal period nominal period 83.33 ±0.15 nominal period nominal period Parameter Units
Note: Input slew rate 1V/ns
Frequency Period 0.75 1333.33 1.66
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Table Clocking Specifications
Symbol Processor Clock (CPU Clock) MemClkOut Frequency Period High time nominal period 333.33 nominal period Frequency Period 800* Parameter Units
Clock PerClk Clock Frequency Period 83.33 22.2 Frequency Period 83.33
Figure Clock Timing Waveform
Spread Spectrum Clocking
Care must taken when using spread spectrum clock generator (SSCG) with PPC440SPe. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with PPC440SPe following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC440SPe with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -1%, modulation frequency cannot exceed 40kHz. some cases, on-board PPC440SPe peripherals impose more stringent requirements. Peripheral Clock logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClkOut since also tracks modulation.
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PCI-X maximum spread spectrum modulated between 30kHz 33kHz. Express, maximum spread spectrum -0.5%, modulated between 30kHz 33kHz. ports ends link must transmit data rate that within parts million (ppm) each other times. This specified allow rate clock sources with tolerance. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. Ethernet operation unaffected. operation unaffected. Important: system designer ensure that SSCG used with PPC440SPe meets above requirements does adversely affect other aspects system.
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Specifications
Table Peripheral Interface Clock Timings
Parameter PCIX0Clk input frequency (asynchronous mode) PCIX0Clk period (asynchronous mode) PCIX0Clk input high time PCIX0Clk input time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output time EMCTxClk input frequency EMCTxClk period EMCTxClk input high time EMCTxClk input time EMCRxClk input frequency EMCRxClk period EMCRxClk input high time EMCRxClk input time PerClk output frequency (for sync. slaves) PerClk period PerClk output high time PerClk output time UARTSerClk input frequency UARTSerClk period UARTSerClk input high time UARTSerClk input time TmrClk input frequency TmrClk period TmrClk input high time TmrClk input time Notes: TOPB period clock. internal clock runs integral divisor ratio frequency clock. maximum clock frequency 83.33 MHz. Refer Clocking chapter PPC440SPe Embedded Processor User's Manual details. When PCI-X interface used support legacy interface, maximum PCIXClk frequency 66.66MHz. nominal period nominal period nominal period nominal period nominal period nominal period nominal period nominal period 2TOPB+2 TOPB+1 TOPB+1 nominal period nominal period 133.33 nominal period nominal period 83.33 nominal period nominal period 1000/(2TOPB1+2ns) nominal period nominal period Units Notes
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Input/Output Timing
These timing diagrams illustrate relationship timing parameters defined Specification tables that follow. Figure Input Setup Hold Waveform
Clock
Inputs Valid
Figure Output Delay Hold Timing Waveform
Clock
TOVmax Outputs TOHmin
TOVmax TOHmin
TOVmax TOHmin
High (Drive) Float (High-Z) (Drive) Valid Valid
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Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133.33MHz. PCI-X input setup time requirement 1.2ns 133.33MHz 1.7ns 66.66MHz. timings parentheses) asynchronous operation 66.66MHz. output hold time requirement 66.66MHz 33.33MHz. These signals that change both positive negative clock transitions.
Input (ns) Signal PCI-X Interface PCIX0Ack64 PCIX0AD63:00 PCIX0BE7:0 PCIX0CalG0:1 PCIX0CalR0:1 PCIX0Cap PCIX0Clk PCIX0DevSel PCIX0ECC5:2 PCIX0Frame PCIX0Gnt0 PCIX0Gnt1 PCIX0Gnt2:3 PCIX0IDSel PCIX0INTA PCIX0IRDY PCIX0M66En PCIXPar PCIXPar64 PCIX0PErr PCIX0Req0 PCIX0Req1:3 PCIX0Req64 PCIX0Reset PCIX0SErr PCIX0Stop PCIX0TRDY PCIX0VC Ethernet Interface EMCCD EMCCrS EMCMDClk EMCMDIO EMCRxD0:7 EMCRxDV EMCRxErr EMCRxClk EMCRefClk EMCTxClk EMCGTxClk EMCTxD0:7 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 EMCTxClk async async EMCMDClk EMCRxClk EMCRxClk EMCRxClk async async async async Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 0.5(0) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) 3.5(6) (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk PCIX0Clk async Setup Time Hold Time (TIS min) (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
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Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133.33MHz. PCI-X input setup time requirement 1.2ns 133.33MHz 1.7ns 66.66MHz. timings parentheses) asynchronous operation 66.66MHz. output hold time requirement 66.66MHz 33.33MHz. These signals that change both positive negative clock transitions.
Input (ns) Signal EMCTxEn EMCTxErr IIC0SClk IIC0SDA IIC1SClk IIC1SDA UARTSerClk UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RI UART0_RTS UART1_Rx UART1_Tx UART1_DSR/CTS UART1_DTR/RTS UART2_Rx UART2_Tx Interrupts Interface IRQ0:15 JTAG Interface TRST System Interface Halt GPIO00:31 SysClk SysErr SysReset HISRRst TESTEN TmrClk Trace Interface TrcClk TRCBS0:2 TrcES0:4 TrcTS0:6 19.1 19.1 19.1 19.1 19.1 19.1 19.1 async async async async async async 19.1 async async async async async async Setup Time Hold Time (TIS min) (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 19.1 19.1 15.3 15.3 15.3 15.3 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 (minimum) 10.2 10.2 10.2 10.2 UARTSerClk UARTSerClk async async async async async async UARTSerClk UARTSerClk async async UARTSerClk UARTSerClk IIC0SClk IIC0SClk Clock EMCTxClk EMCTxClk Notes
Internal Peripheral Interface
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Table Specifications-667MHz
Notes: PerClk rising edge package with 10pF load trails internal clock approximately 1.3ns.
Input (ns) Signal Setup Time Hold Time (TIS min) (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 19.1 27.7 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 (minimum) 12.8 Clock Notes
External Slave Peripheral Interface PerAddr00:26 PerBE0:1 PerBLast PerCS0:2 PerData0:15 PerOE PerPar0:1 PerReady PerR/W PerWE ExtReset PerClk PerErr PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
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SDRAM Specifications
SDRAM controller times operation with internal clock signals generates MemClkOut0 from clock. clock internal signal that cannot directly observed. However MemClkOut0 same frequency clock signal phase with clock signal. Note: MemClkOut0 advanced with respect clock means SDRAM0_CLKTR programming register. typical system, users advance MemClkOut 90°. This depends specific application requires thorough understanding memory system general (refer SDRAM controller chapter PPC440SPe Embedded Processor User's Manual). following sections, label MemClkOut0(0) refers MemClkOut0 when been phase-shifted, MemClkOut0(90) refers MemClkOut0 when been phase-advanced 90°. Advancing MemClkOut0 creates cycle setup time cycle hold time address control signals relation MemClkOut0(90). rising edge MemClkOut0(90) aligns with first rising edge signal. following data generated means simulation includes logic, driver, package RLC, lengths. used circuit design recommendation. Values calculated over best case worst case processes with speed, temperature, voltage follows: Best Case Fast process, 0°C, +1.6V Worst Case Slow process, +95°C, +1.4V Note: following tables timing diagrams, minimum values measured under best case conditions maximum values measured under worst case conditions. signals terminated indicated figure below timing data following sections. Figure SDRAM Signal Termination
MemClkOut0 10pF 10pF
MemClkOut0
PPC440SPe
SVDD/2
Addr/Ctrl/Data/DQS
30pF
Note: This diagram illustrates model SDRAM interface used when generating simulation timing data. recommended physical circuit design this interface. actual interface design will depend many factors, including type memory used board layout.
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Table SDRAM Output Driver Specifications
Signal Path Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 DQS0:8 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 Output Current (mA) (maximum) (minimum)
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SDRAM Write Operation
following timing chart shows relationship between signals involved write operation. Figure SDRAM Write Cycle Timing
MemClkOut Addr/Cmd
MemData
Setup time address command signals MemClkOut Hold time address command signals from MemClkOut Setup time data signals (minimum time data valid before rising/falling edge DSQ) Hold time data signals (minimum time data valid after rising/falling edge DSQ) Delay from rising/falling edge clock rising/falling edge
SDRAM Read Write Timing-TSA
Note Clock speed MHz. referenced MemClkOut. Note Memory clock signal shifted from internal clock. Table SDRAM Read Write Timing-TSA
(ns) Signal Name Minimum MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 1.32 1.15 1.12 1.29 1.24 1.29 1.35 Minimum 1.49 1.52 1.45 1.14 1.48 1.43 (ns)
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SDRAM Clock Write Timing-TDS
Note signals referenced MemClkOut. Note Clock speed MHz. Note values table include cycle ns). Note obtain adjusted values lower clock frequencies, subtract from values following table cycle time lower clock frequency (TDS TCYC).
Table SDRAM Clock Write Timing-TDS
(ns) Signal Name Minimum DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 4.76 4.78 4.78 4.76 4.79 4.80 4.81 4.79 4.77 Maximum 5.07 5.09 5.10 5.07 5.11 5.13 5.11 5.11 5.07
SDRAM Write Data Timing-TSD
Note measured under worst-case conditions. Note Clock speed values following table MHz.
Table SDRAM Write Data Timing-TSD
Signal Name MemData00:07, MemData08:15, MemData16:23, MemData24:31, MemData32:39, MemData40:47, MemData48:55, MemData56:63, ECC0:7, Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 (ns) 0.58 0.62 0.62 0.63 0.68 0.67 0.62 0.65 0.63 (ns) 0.64 0.55 0.60 0.57 0.54 0.52 0.61 0.55 0.61
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
SDRAM Read Operation
Read incoming Data from SDRAM done rising falling edges differential signal. Data must centered these edges correct operation. PPC440SPe delay with very fine granularity through programming MCIF0_RODC[RQFD] register field. SDRAM MemClkOut0 Read Clock Delay order accommodate timing variations introduced system designs using this chip, three-stage data path shown below used eliminate metastability allow data sampling adjusted minimum latency. data stored Flip Flops Stage such that transferred later within period. Figure SDRAM Read Data Path
FeedBack Signals
Clock
Flip-Flop
MemDCFdbkD Driver
Coarse Delay
FeedBack Signal
Delay
Read Start Read Latency adjust circuit
MCIF0_RFDC[RFFD]
Fine Delay
Clock
Stage Store Oversampling Fine Delay
MemDCFdbkR
Feedback Data Capture Window
aligned signal
Cycles Delay
MCIF0_RFDC[RFOS]
MCIF0_RDCC[RDSS]
adjust Oversampling Clock
Q2_Ovs
Package pins
Compare
(x64)
Read FIFO Upper
[0:63]
Data (x64)
Rising Edge Sync Stage
Stage (x64)
Lower
Stage
[64:127]
(Diff)
Programmed Read Delay
Falling Edge Sync Clock Clock
MCIF0_RQDC[RQFD]
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Table SDRAM Read Timing-TSD
Notes: measured under worst case conditions. Clock speed values table 333.33MHz. time values table include cycle 166MHz (3ns 0.25 0.75 ns). obtain adjusted values lower clock frequencies, subtract 0.75 from values table cycle time lower clock frequency (e.g., 0.75 0.25TCYC).
Signal Names MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 Read Data (ns) 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 Read Data Hold (ns) 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00
following examples, data strobes (DQS) data shown coincident. There actually slight skew specified SDRAM specifications, there additional skew loading signal routing. recommended that signal length eight signals matched.
Figure SDRAM Memory Data
MemData
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
following example shows timing relationship between SDRAM Data input store Data stage Figure SDRAM Read Cycle Timing-Example
Oversampling Guard Band Clock Clock Memclk (Diff.) MemCntl Data
Feedback Output cycle Delayed
Store Data Stage
Data Stage
Data Stage
Data Stage Valid High Data Stage
Clock
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Initialization
PPC440SPe provides option setting initial parameters based default values reading them from serial "bootstrap" attached IIC0 bus. These options defined strapping three external pins (see "Strapping" below).
Strapping
While SysReset input (system reset), state certain pins read enable certain default initial conditions prior PPC440SPe start-up. actual capture instant nearest SysClk edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. They used strap functions only during reset. Following reset they used normal functions. following table lists strapping pins along with their functions strapping options:
Table Strapping Assignments
Strapping Function Option (UART0_DCD) (UART0_DSR) Bit2 (UART0_CTS)
Serial Bootstrap disabled (Bit off). Refer Bootstrap Controller chapter PPC440SPe Embedded Processor User's Manual details. Serial Bootstrap enabled (Bit on). options being selected IIC0 slave address that responds with strapping data reading bits from Bootstrap ROM. Serial Bootstrap enabled (Bit on). options being selected IIC0 slave address that responds with strapping data reading bits from Bootstrap ROM.
Boot from Boot from 0x54 0x50 0x54 0x50
Serial Bootstrap
During reset, serial device enabled, initial conditions read from connected IIC0 port. this case, de-assertion SysReset, PPC440SPe sequentially reads bytes from device IIC0 port sets SDR0_SDSTP0 SDR0_SDSTP7 registers accordingly. initialization settings their default values covered detail PPC440SPe Embedded Processor User's Manual Note: 800MHz, clock ratio must 5:1, this means that will 160MHz memory DDR640.
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
Revision
Revision
1.26 1.25
Date
June 2008 October 2007
Description
Deleted word "Preliminary" Data Sheet heading. Changed technical support telephone number, changed from 667MHz 800MHz. Updated sheets Signal Functional Description table, Input Capacitance table, Power Supply Loads table, PCIX0VRef0:1 signal Signal Functional Description table PCI-X mode Updated Recommended Operating Conditions table. Updated Processor Clock values Clocking Specifications table. Updated Recommended Conditions Signal Functional Description tables PCIX mode Updated signal lists. Corrected reference PCIX0Cap Signal Functional Description table. Added reference Note UART0_CTS register Signal Functional Description table. Fixed issue PEROE signal Signal Functional Description table. Fixed issue UARTSerClk signal throughout document. Fixed issue PSRO1 signal Signal Functional Description table. Updated Clocking Specifications table Serial Bootstrap paragraph. Updated ordering information, core package graphic Figure Added RAID acceleration section Features, Description, functional details sections. Additional update ordering information. Updated ordering information, part number list, package diagram. Removed statement from Serial Port feature statement. Removed reference notes from PERBLAST entry signal functional description table. Updated description On-Chip SRAM/L2 Cache Introduction. Updated Signal Function Description table updated mailing address copyright date disclaimer. Clarified information about SDRAM specifications. Corrected upper limit allowable case temperature, documented reserved signal pins, added bookmarks signal lists. Restored multiplexed signal information "Signals Listed Alphabetically" table. Applied corrections table from Updated leakage current info, case temp range, SDRAM Signal Termination graphic. Update Write timing diagrams. Updated system memory address map. Corrected functional block diagram. Removed text unsupported COLA component. Removed references unsupported COLA serial interface. Reformatted LOF, comply with AMCC style. Update case temp Recommended Conditions table match Ordering Information table. Update Ordering info, Express features info, SDRAM read data path read cycle timing example, memory map.
1.24 1.23 1.22 1.21
October 2006 Sept. 2006 Sept. 2006 June 2006
1.20
June 2006
1.19
2006
1.18 1.17 1.16 1.15 1.14 1.13 1.12 1.11 1.10 1.09 1.08 1.07 1.06 1.05 1.04 1.03
2006 April 2006 March 2006 March 2006 March 2006 January 2006 November 2005 October 2005 October 2005 July 2005 2005 2005 2005 Feb. 2005 Dec. 2004 Dec. 2004
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
1.02 1.01 Sept. 2004 Sept. 2004 Sept. 2004 Aug. 2004 July 2004 June 2004 June 2004 PCI-Express assignment changes. Converted AMCC format, corrected tables, graphics needed. Renamed 440SPe, added table, VDDA 2.5V PROGRESS) Miscellaneous technical additions, corrections from Support. Correct TOC, LOF, LOT, broken cross-references. alphabetic list, update address map. Create initial data sheet.
AMCC Proprietary
PowerPC 440SPe Embedded Processor
Revision 1.26 June 2008
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