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PNX15xx/952x Series Data Book
Volume
Connected Media Processor
Rev. December 2007
Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
Chapter Integrated Circuit Data
2.3.1 2.3.2
Introduction. Description
Boundary Scan Notice Circuit Summary Signal List Power List Reference Voltage
IIC3M4SDAT5V IIC3M4SCLT5V type circuit58 PCIT5V type circuit
7.10 7.11 7.12 7.13
Timing Specification
Absolute Maximum Ratings PNX15xx/952x Series Operating Conditions
PNX1500 Device PNX1501 Device PNX1502 Device PNX1520 Device PNX9520 Device PNX9525 Device
5.4.1 5.4.2
Power Considerations
Power Supply Sequencing Leakage current Power Consumption Standby Power Consumption Power Consumption Typical Power Consumption Typical Applications50 Expected Maximum Currents
Reset DRAM Interface Interface QVCP, FGPO Interfaces FGPI Interfaces 10/100 Mode 10/100 RMII Mode Audio Input Interface Audio Output Interface SPDIF Interface Interface GPIO Interface JTAG Interface.
10.1 10.2 10.2.1 10.2.2 10.3 10.3.1 10.3.2 10.4
Package Outline Ball Assignment Board Design Guidelines
Power Supplies Decoupling Analog Supplies. Analog Supply Core, VDDA, Analog Supply SDRAM interface Devices Require Termination? What really want termination PNX1500?77 Package Handling, Soldering Thermal Properties78
DC/AC Characteristics
Input Clock Specification SSTL_2 type Circuit BPX2T14MCP Type Circuit BPTS1CHP BPTS1CP Type Circuit BPTS3CHP BPTS3CP Type Circuit IPCHP IPCP Type Circuit BPT3MCHDT5V BPT3MCHT5V Type Circuit57
Miscellaneous Soft Errors Radiation Ordering Information.
Chapter Overview
Introduction.
PNX15xx/952x Series Functional Overview PNX15xx/952x Series Features Summary
De-scrambler
7.5.1
Image Processing
Pixel Format Video Input Processor Memory Based Scaler Drawing Engine Quality Video Composition Processor External Video Improvement Post Processing
PNX15xx/952x Series Functional Block Diagram85 System Resources.
System Reset System Booting Clock System Power Management Semaphores Interface
Audio processing Input/Output
Audio Processing Audio Inputs Outputs
System Memory
General Purpose Interfaces
Main Memory Interface Flash
TM3260 VLIW Media Processor Core MPEG Decoding
Video/Data Input Router Video/Data Output Router Fast General Purpose Input Fast General Purpose Output
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Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.2
Peripheral Interface
GPIO General Purpose Software Flexible Serial Interface101 Software Timestamping Event sequence monitoring signal generation
10.3 10.3.1 10.3.2 10.3.3 10.4
PCI-2.2 XIO-16 Interface Unit Capabilities Simple Peripheral Capabilities (`XIO-8/16') Drive Interface 10/100 Ethernet
GPIO reset value Remote Control Receiver Blaster
Endian Modes System Debug
Chapter System Chip Resources
2.4.1
Introduction. System Memory
View View. View System View Programmable Apertures DRAM Aperture Control MMIO Registers
Master Semaphore Usage Notes Semaphore MMIO Registers.
6.3.1
System Related Information TM3260
Interrupts Timers System Parameters TM3260 TM3260 System Parameters MMIO Registers
Aperture Boundaries
Video Input Output Routers
System Principles
Module Powerdown bit. System Module MMIO registers
MMIO Registers Input/Output Video/Data Router125
Miscellaneous System Registers Summary Simplified Internal Infrastructure MMIO Memory References
Miscellaneous System MMIO registers
System Endian Mode
System Endian Mode MMIO registers
System Semaphores
Semaphore Specification Construction 12-bit
Chapter Reset
2.2.1 2.2.2
Introduction. Functional Description
RESET_IN_N POR_IN_N? watchdog Timer Interrupt Mode Interrupt Mode Software Reset
External Software Reset
Timing Description
Hardware Timing Software Timing
Register Definitions References
Chapter Clock Module
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5
Introduction. Functional Description
Modules their Clocks Clock Sources PNX15xx/952x Series Specification Clock Dividers Clocks Assignment Summary External Clocks Clock Control Logic Bypass Clock Sources Power-up Reset sequence
2.8.1 2.10 2.11 2.11.1 2.11.2 2.12 2.12.1 2.12.2
Clock Stretching Clock Frequency Determination Power Down Wake-Up from Power Down Clock Detection Clocks GPIO Clocks Setting GPIO[14:12]/GCLOCK[2:0] Clock Outputs170 GPIO[6:4]/CLOCK[6:4] Clock Outputs Clock Block Diagrams TM3260, QVCP clocks Clock Dividers
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
2.12.3 2.12.4 2.12.5 2.12.6
Internal PNX15xx/952x Series Clock from Dividers174 GPIO Clocks External Clocks SPDO
Registers Definition
Registers Summary Registers Description
Chapter Boot Module
2.2.1 2.2.2 2.2.3
Introduction. Functional Description
Boot Modes Boot Module Operation MMIO Interface Master Boot Control/State Machine Boot Command Language
3.1.1 3.2.1
Binary Sequence Common Boot Script Specifics Boot From Flash Memory Devices212 Binary Sequence Section Flash Boot
Specifics Host-Assisted Mode
Boot From EEPROM
PNX15xx/952x Series Boot Scripts Content
External Boot EEPROM Types Boot Commands Endian Mode Details Operation
Common Behavior
References
Chapter PCI-XIO Module
Introduction. Functional Description
PCI-XIO Block Level Diagram Architecture
4.3.1 4.3.2 4.3.3 4.3.4
Application Notes
Interface System Memory Interface, Interface Motorola Interface NAND-Flash Interface Flash Interface Interface Endian Support General Notes
3.1.1 3.1.2 3.1.3 3.1.4
Operation
Overview NAND-Flash Interface Operation Motorola Style Interface Flash Interface Description Interrupt Enable Register
Register Descriptions
Register Summary
Chapter General Purpose Input Output Pins
2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.3.1 2.3.2 2.4.1
Introduction. Functional Description
GPIO: Basic Behavior GPIO Mode settings GPIO Data Settings MMIO Registers GPIO Status Reading GPIO: Event Monitoring Mode Timestamp Reference clock Timestamp format. GPIO: Signal Monitoring Pattern Generation Modes273 Signal Monitoring Mode. Signal Pattern Generation Mode GPIO Error Behaviour GPIO Frequency Restrictions. GPIO Clock Pins GPIO Interrupts Timer Sources Wake-up Interrupt
External Watchdog
Applications
Duty-cycle programming Spike Filtering
4.10
MMIO Registers
GPIO Mode Control Registers GPIO Data Control Readable Internal PNX15xx/952x Series Signals
Sampling Pattern Generation Control Registers FIFO Queues293 Signal Event Monitoring Control Registers Timestamp Units300 Timestamp Unit Registers GPIO Time Counter GPIO TM3260 Timer Input Select GPIO Interrupt Status Clock Select
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Product data sheet
Rev. December 2007
Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
4.11 4.12
GPIO Interrupt Registers FIFO Queues (One each FIFO Queue)303 GPIO Module Status Register Timestamp Units304
4.13 4.14 4.15
GPIO POWERDOWN GPIO Module GPIO IO_SEL Selection Values
Chapter Controller
2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.3.1 2.3.2 2.5.1 2.5.2 2.5.3 2.5.4
Introduction. Functional Description
Start Warm Start Start Mode Warm Start Observing Start State Arbitration First Level Arbitration: Between CPU315 Second Level Arbitration. Dynamic Ratios Pre-Emption Back Buffer (BLB) PMAN (Hub) versus Controller Interaction.
2.5.5
Sequence Actions
Application Notes
Memory Configurations Error Signaling Latency Data Coherency. Programming Internal Arbiter Controller Memory Devices332
4.0.1
Timing Diagrams Tables.
Tcas Timing Parameter Trrd Timing Parameters Trfc Timing Parameter Timing Parameter Tras Timing Parameter Timing Parameter Trcd_rd Timing Parameter. Trcd_wr Timing Parameter
Addressing Memory Region Mapping Scheme Memory Rank Locations Clock Programming Power Management Halting Unhalting MMIO Directed Halt Auto Halt Observing Halt Mode
Register Descriptions
Register Summary Register Table
References
Chapter Controller
Introduction.
Controller Features
Functional Description
Overview Power Sequencing
Operation
Overview Power Sequencing State Machine
3.2.1 3.2.2 3.2.3 3.2.4
IDLE state DCEN state BLEN state PEPED state Counter Gating Logic
Register Descriptions
MMIO Registers
Chapter QVCP
Introduction.
Features
2.3.6 2.3.7 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6
2.3.1 2.3.2 2.3.3 2.3.4 2.3.5
Functional Description
QVCP Block Diagram Architecture Layer Resources Functions Memory Access Control (DMA CTRL) Pixel Formatter Unit (PFU) Chroma Undither (CKEY/UDTH) Unit359 Chroma Upsample Filter (CUPS) Linear Interpolator (LINT)
Video/Graphics Contrast Brightness Matrix (VCBM)363 Layer Fetch Control Pool Resources Functions CLUT (Color Look Table) DCTI (Digital Chroma/Color Transient Improvement)365 HSRU (Horizontal Sample Rate Upconverter) HIST (Histogram Modification) Unit LSHR (Luminance/Luma Sharpening) Unit Color Features (CFTR) Unit
B.V. 2007. rights reserved.
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Product data sheet
Rev. December 2007
Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
2.4.7 2.6.1 2.6.2 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.7.6
PLAN (Semi Planar DMA) Unit Screen Timing Generator Mixer Structure Generation Alpha Blending Output Pipeline Structure Supported Output Formats Layer Selection Chrominance Downsampling (CDNS) Gamma Correction Noise Shaping (GNSH& ONSH)372 Output Interface Modes Auxiliary Pins
3.4.1
Changing Timing Programming QVCP Different Output Formats
4.1.1 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.10
Application Notes
Special Features Signature Analysis Programming Help LINT Parameters HSRU Parameters LSHR Parameters DCTI Parameters CFTR Parameters Underflow Behavior Layer Underflow Underflow Symptom Underflow Recovery Underflow Trouble-shooting Underflow Handling Setting QVCP External VSYNC Clock Calculations.
3.2.1 3.2.2 3.3.1 3.3.2 3.3.3 3.3.4
Programming Resource Assignment
MMIO Task Based Programming Setup Order QVCP Shadow Registers Fast Access Registers Programming Layer Pool Resources Resource Assignment Selection Aperture Assignment Data Flow Selection Pool Resource Assignment Example Programming
Register Descriptions
Register Summary Register Tables
Chapter Video Input Processor
Introduction.
Features
2.2.1 2.2.2 2.5.1
Functional Description
Block Level Diagram Chip Connections Data Routing Video Modes Input Timing Test Pattern Generator Input Formats Video Data Path Video Data Flow
2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.5.8
Video Data Acquisition Internal Timing Field Identifier Generation Horizontal Video Filters (Sampling, Scaling, Color Space Conversion)439 Video Data Write Memory Auxiliary Data Path Interrupt Generation
Register Descriptions
Register Summary Register Table
Chapter FGPO: Fast General Purpose Output
Introduction.
FGPO Overview FGPO mapping MMIO Interface Header Initiator Data Initiator Record Output Mode Message Passing Mode
2.7.1 2.7.2 2.7.3 2.7.4 2.10 2.11 2.12 2.13
Functional Description
Reset. Base Addresses Sample (data) Size Record Message Size Records Messages Buffer
Stride Interrupt Events BUF1DONE BUF2DONE Interrupts. THRESH1_REACHED THRESH2_REACHED Interrupts468 UNDERRUN Interrupt Interrupt Record Message Counters Timestamp Variable Length Output Time Registers Double Buffer Operation Single Buffer Operation
Operation
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Product data sheet
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Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5
Both Operating Modes Setup. Interrupt Service Routines Optimized Transfers. Terminating Transfers Signal Edge Definitions Message Passing Mode PNX1300 Series Message Passing Mode
3.4.1 3.4.2
Record Output Mode Record Synchronization Events Buffer Synchronization Events
Register Descriptions
Mode Register Setup Status Registers
Chapter FGPI: Fast General Purpose Interface
1.4.1 1.4.2 1.4.3
Introduction.
FGPI Overview FGPI mapping MMIO Interface Data Packer 8-Bit Sample Packing Mode 16-bit Sample Packing Mode 32-bit Sample Mode Record Capture Mode Message Passing Mode
2.10 2.11 2.12 2.13
Record Message Counters Timestamp Variable Length Double Buffer Operation Single Buffer Operation Buffer Synchronization
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2.1 3.4.1 3.4.2 3.4.3
Operation
2.7.1 2.7.2 2.7.3 2.7.4 2.7.5
Functional Description
Reset. Base Addresses Sample (data) Size Record Message Size Records Messages Buffer Stride. Interrupt Events. BUF1FULL BUF2FULL Interrupts THRESH1_REACHED THRESH2_REACHED Interrupts491 OVERRUN Interrupt Interrupt OVERFLOW Interrupt (Message Passing Mode Only)492
Both Operating Modes Setup Interrupt Service Routines Optimized Transfers Terminating Transfers Signal Edge Definitions Message Passing Mode. Minimum Message/Record Size PNX1300 Series Message Passing Mode Record Capture Mode Record Synchronization Buffer Synchronization Setup Operation with Input Router VDI_MODE[7] 1499
Register Descriptions
Mode Registers Status Registers
Chapter Audio Output
Introduction.
Features
2.2.1 2.3.1 2.4.1 2.6.1 2.6.2
Functional Description
External Interface Memory Data Formats Endian Control Audio Data Operation TRANS_ENABLE Interrupts Interrupt Latency Timestamp Events Serial Data Framing Serial Frame Limitations Characteristics
2.6.3
Serial Framing Example Codec Control Data Latency HBE. Error Behavior
3.1.1 3.1.2
Operation
Clock Programming Sample Clock Generator Clock System Operation Reset-Related Issues Register Programming Guidelines Power Management
Register Descriptions
Register Summary Register Table
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
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Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
Chapter Audio Input
Introduction.
Features
Functional Description
Chip Level External Interface General Operations
3.1.1
Operation
Clock Programming Clock System Operation Reset-Related Issues Register Programming Guidelines Serial Data Framing Memory Data Formats
3.5.1 3.10 3.11 3.12 3.13
Endian Control Memory Buffers Capture Data Latency HBE. Error Behavior Interrupts Timestamp Events Diagnostic Mode Software Reset Mode
Register Descriptions
Register Table
Chapter SPDIF Output
Introduction.
Features
Functional Description
Architecture General Operations
3.1.1 3.3.1 3.3.2
Operation
Clock Programming Sample Rate Programming Register Programming Guidelines Data Formatting IEC-60958 Serial Format Transparent Mode
3.4.1 3.4.2 3.4.3 3.4.4
Errors Interrupts Error Conditions Latency Interrupts Timestamp Events Endian Mode
Signal Description
External Interface
Register Descriptions
Register Summary Register Table
Chapter SPDIF Input
Introduction.
Features
2.2.1 2.3.1 2.3.2 2.3.3 2.3.4
Functional Description
SPDIF Input Block Level Diagram Architecture Functional Modes General Operations Received Serial Format Memory Formats. SPDIF Input Endian Mode Bandwidth Latency Requirements
3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.2.12
SPDI_STATUS Register Functions LOCK UNLOCK State Behavior UNLOCK Error Behavior SPDI_CTL Functions SPDI_CBITSx Channel Status Bits SPDI_UBITSx User Bits SPDI_BASEx SPDI_SIZE Registers Memory Buffers568 SPDI_SMPMASK Sample Size Masking SPDI_BPTR Start IEC60958 Block
3.1.1 3.1.2 3.1.3 3.1.4 3.2.1
Operation
Clock Programming SPDIF Input Clock Domains SPDIF Receiver Sample Rate Tolerance IEC60958562 SPDIF Input Receiver Jitter Tolerance SPDIF Input Oversampling Clock Register Programming Guidelines SPDIF Input Register
Interrupts Event Timestamping
4.1.1
Signal Descriptions
External Interface Pins System Interface Requirements
5.1.1
Register Descriptions
Register Summary SPDIF Input Interrupt Registers Register Table
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
Chapter Memory Based Scaler
2.2.1 2.2.2 2.4.1 2.4.2 2.4.3
Introduction. Functional Description
Block Level Diagram Data Flow Horizontal Processing Pipeline Vertical Processing Pipeline Data Processing General Operations Task Control Video Source Controls Horizontal Video Filters
2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11
Vertical Video Filters De-Interlacing Color-Key Processing Alpha Processing Video Data Output. Address Generation Interrupt Generation Measurement Functions
Register Descriptions
Register Summary Register Table
Chapter Drawing Engine
Introduction.
Features
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14
Functional Description
Drawing Engine Block Level Diagram Architecture Registers Host Interface Color Expand. Rotator Source FIFO Pattern FIFO Destination FIFO. Write Datapath Source State Destination State Address Stepper Engine Vector Engine Memory Interface
2.2.15 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6
Byte Masking General Operations Raster Operations Alpha Blending. Source Data Location Type Patterns Transparency Block Writes
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6
Operation
Register Programming Guidelines Alpha Blending. Mono Expand Mono Register Setup Solid Fill Setup Color Setup PatRam
Register Descriptions
Register Summary Register Tables
Chapter MPEG-1 MPEG-2 Variable Length Decoder
Introduction.
Features
3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.2.12 3.2.13 3.3.1 3.3.2 3.3.3 3.4.1 3.4.2 3.4.3
Functional Description
Block Level Diagram
3.2.1 3.2.2 3.2.3 3.2.4
Operation
Reset-Related Issues MMIO Registers Status (VLD_MC_STATUS) Interrupt Enable (VLD_IE) Control (VLD_CTL) Current Read Address (VLD_INP_ADR) Read Count (VLD_INP_CNT)654 Macroblock Header Current Write Address (VLD_MBH_ADR)654 Macroblock Header Current Write Count654
3.2.5 3.2.6
Run-Level Current Write Address (VLD_RL_ADR)655 Run-Level Current Write Count Command (VLD_COMMAND) Shift Register (VLD_SR) Quantizer Scale (VLD_QS) Picture Info (VLD_PI). Count (VLD_BIT_CNT) Operation Input Output Restart Parsing Error Handling Unexpected Start Code Overflow Flush
Application Notes
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
4.0.1
PNX1300 Series versus PNX15xx/952x Series VLD663
Register Descriptions
PNX1300 Series PNX15xx/952x Series Register Differences663 Register Summary Register Table
Chapter Digital Video Disc Descrambler
Introduction.
Functional Description
Introduction
Chapter LAN100 Ethernet Media Access Controller
Features
Functional Description
Chip System Interconnections Functional Block Diagram Description
Register Descriptions
Register Summary Register Definitions Pattern Matching Join Register
Descriptor Status Formats
Receive Descriptors Status Transmit Descriptors Status
5.1.1 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8
LAN100 Functions
MMIO Interface Overview Direct Memory Access Descriptor FIFOs Ownership Descriptors Sequential Order with Wrap-around Full Empty State FIFOs Interrupt Packet Fragments Initialization Transmit process Overview Device Driver Sets Descriptors Data Tx(Rt) Manager Reads Tx(Rt) Descriptor Arrays708 Tx(Rt) manager transmits data Update ConsumeIndex Write Transmission Status Transmission Error Handling Transmit Triggers Interrupts Transmit example Receive process Device Driver Sets Descriptors Manager Reads Descriptor Arrays
5.5.9 5.8.1 5.8.2 5.8.3 5.10 5.10.1 5.10.2 5.10.3 5.11 5.12 5.12.1 5.12.2 5.12.3 5.12.4 5.12.5 5.12.6 5.12.7 5.13 5.13.1 5.13.2 5.13.3 5.14 5.14.1 5.14.2 5.15 5.16 5.17 5.18 5.19 5.19.1 5.19.2
Receive example Transmission Retry time-stamps Transmission modes Overview Real-time/non-real-time transmission mode Quality-of-service Transmission Mode Duplex Modes IEEE 802.3/Clause Flow Control Overview Receive Flow Control Transmit Flow Control Half-duplex Mode Back Pressure Receive filtering Overview Unicast, Broadcast Multicast Perfect Address Match Imperfect Hash Filtering Pattern Match Filtering Logic Functions Enabling Disabling Filtering Runt Frames Wake-up Overview Filtering Magic Packet Enabling Disabling Receive Transmit Enabling Disabling Reception Enabling Disabling Transmission Transmission Padding Huge Frames Frame Length Checking Statistics Counters Status Vectors Reset Hard Reset Soft Reset
6.2.1 6.2.2
System Integration
Interface Power Management Sleep Mode Coma Mode Disabling LAN100 Little/big Endian Interrupts Errors Aborts Cache coherency
Manager Receives Data Update ProduceIndex Write Reception Status Reception Error Handling Receive Triggers Interrupts Device Driver Processes Receive Data
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
Chapter TM3260 Debug
Introduction.
Features
3.1.1
Operation
2.1.1 2.1.2 2.1.3
Functional Description
General Operations Test Access Port (TAP) Controller. PNX15xx/952x Series JTAG Instruction
Register Programming Guidelines Handshaking Communication Protocol Debug Settings
Register Descriptions
Register Summary
Chapter Interface
Introduction.
Features
2.1.1 2.1.2 2.1.3 2.1.4
Functional Description
General Operations Arbitration Control Logic Serial Clock Generator Counter Control Register
2.1.5 2.1.6 2.1.7 2.1.8 2.1.9 2.1.10
Status Decoder Register Input Filter Address Register Comparator Data Shift Register Related Interrupts Modes Operation
Register Descriptions
Register Tables
Chapter Memory Arbiter
Introduction.
Features
2.3.1
Arbiter Startup Behavior.
Operation
2.2.1
Functional Description
Arbiter Features Mapping Gate Arbitration Algorithm
Clock Programming Register Programming Guidelines
Register Descriptions
Register Table
Chapter Power Management
1.1.1
Power Management Mechanisms.
Clock Management Essential Operating Infrastructure During Powerdown785
1.1.2 1.1.3 1.1.4 1.1.5
Module Powerdown Sequence Peripheral Module Wakeup Sequence TM3260 Powerdown Modes SDRAM Controller.
Chapter Pixel Formats
3.5.1
Introduction. Summary Native Pixel Formats Native Pixel Format Representation
Indexed Formats 16-Bit Pixel-Packed Formats 32-Bit Pixel-Packed Formats Packed 4:2:2 Formats Planar 4:2:0 4:2:2 Formats Planar Variants
3.5.2 3.5.3
Semi-Planar 10-Bit 4:2:2 4:2:0 Formats
Packed 10-bit 4:2:2 format
Universal Converter Alpha Value Pixel Transparency Values Image Storage Format System Endian Mode
Chapter Endian Mode
Introduction.
Features
Endian Mode System Block Diagram
Endian Mode Theory
Functional Description
"CPU Rule"
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Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
"DMA Convention Rule"
PNX15xx/952x Series Endian Mode Architecture Details807
Global Endian Mode Module Control Module SIMD Programming Issues Optional Endian Mode Override
6.2.1 6.2.2
PMAN Network Endian Block Diagram Across Interface Data Ordering Rules Address Invariant Data Ordering Rules Data Transfers Across Network Across DTL-to-MTL Adapters Interface
Example: Audio In-Programmer's View Implementation Details
Detailed Example Introduction
Chapter Network
2.3.1
Functional Description
Endian Mode
Error Generation Interrupt Generation Programmable Timeout Arbitration
Register Descriptions
Register Summary Register Tables
Chapter TM3260 VLIW
Introduction. Data sheet status Definitions Disclaimers Licenses Trademarks Contact information
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
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Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
Chapter Integrated Circuit Data
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Application Diagram Crystal Oscillator
SSTL_2 Test Load Condition SSTL_2 Receiver Signal Conditions. BPX2T14MCP Test Load Condition BPTS1CHP BPTS1CP Test Load Condition55 BPTS3CHP BPTS3CP Test Load Condition56 BPT3MCHDT5V BPT3MCHT5V Test Load Condition57 Tval(min) Slew Rate Test Load Condition58 Reset Timing Output Input Timing Measurement Conditions61 Tval(max) Rising Falling Edge QVCP FGPO Timing FGPI Timing
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
10/100 Timing Mode 10/100 Timing RMII Mode Audio Input Timing Audio Output Timing SPDIF Timing Timing Timing Audio Output Timing JTAG Timing BGA456 Plastic Ball grid Array; Balls; body 1.75 mm71 Bottom View Assignment View Assignment Digital VCCP Power Supply Analog VCCA/ VSSA Power Supply Filter75 Digital Power Supply Analog VDDA/ VSSA_1.2 Power Supply Filter76 Digital Power Supply Analog VDDA/ VSSA_1.2 Power Supply Filter76
Chapter Overview
Figure Block Diagram PNX15xx/952x Series Figure PNX15xx/952x Series Functional Block Diagram85
Chapter System Chip Resources
Figure Figure Operating Modes PNX15xx/952x Series109 PNX15xx/952x Series System Memory
Figure
Simplified Internal Infrastructure
Chapter Reset
Figure Figure Reset Module Block Diagram Watchdog Interrupt Mode Figure Figure Watchdog Interrupt Mode POR_IN_N Timing Reset Sequence
Chapter Clock Module
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Clock Module Block Diagram Block Diagram Block Diagram Clock Control Logic Waveforms Blocking Logic Clock Stretcher Clock Detection Circuit TM3260, QVCP clocks QVCP_PROC Clock QVCP_PIX Clock Clock Dividers Internal PNX15xx/952x Series Clock from Dividers174 Internal PNX15xx/952x Series Clock from Dividers: PCI, SPDI, I2C175 Internal PNX15xx/952x Series Clock from Dividers: Timestamp175 GPIO Clocks VDI_CLK1 Block Diagram VDI_CLK2 Block Diagram VDO_CLK1 Block Diagram VDO_CLK2 Block Diagram Clocks Clocks Clock Block Diagram Receive Transmit Clocks SPDO Clock
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Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. December 2007
-xiv
Semiconductors
Volume
PNX15xx/952x Series
Connected Media Processor
Chapter Boot Module
Figure Figure Boot Block Diagram System Memory Block Diagram Configuration PNX15xx/952x Series Standalone Mode212 Figure System Memory Block Diagram Configuration PNX15xx/952x Series Hostassisted Mode215
Chapter PCI-XIO Module
Figure Figure Figure Figure Figure Figure Figure Figure PCI-XIO Block Diagram Read Status. Read Data Write Data Block Erase Motorola Write With DSACK Motorola Write Without DSACK Motorola Read Figure Figure Figure Figure Figure Figure Figure Flash Write Flash Read Interface Isolation Translation Logic Register Transfer/PIO Data Transfer
Timings Transaction, Flow Controlled Device IORDY236
Chapter General Purpose Input Output Pins
Figure Figure Figure Figure Figure Figure GPIO Module Block Diagram Functional Block Diagram GPIO 32-bit Timestamp Format 1-bit Signal Sampling. 4-bit Signal Sampling 1-bit Pattern Generation Figure Figure Figure Figure Figure 4-bit Samples FIFO Pattern Generation Mode280 Example Signals with without Sub-Carrier285 IrDA Control with Sub-Carrier Enabled Sub-Carrier Multiplexing Examples Duty Cycles Signals
Chapter Controller
Figure Figure Figure Figure Figure Figure Figure Figure Ports SDRAM Controller315 Arbitration Controller account Arbitration when priority. account using dynamic ratios Address Mapping: Interleaved Mode SDRAM Controller Start Halt State Machine327 Examples Supported Memory Configurations329 Tcas Timing Parameter Trrd Timing Parameters Trfc Timing Parameter Timing Parameter Tras Timing Parameter Timing Parameter Trcd_rd Timing Parameter Trcd_wr Timing Parameter
Figure Figure Figure Figure Figure Figure Figure Figure
Chapter Controller
Figure Figure Block diagram Controller Generic Power Sequence Panels
Figure Figure
Power Sequencing State Machine Block Diagram348 Clock Gating Logic
Chapter QVCP
Figure Figure Figure QVCP Level Diagram QVCP BLock Diagram. Undithering Pedestal Manipulation Figure Figure Figure 4:2:2 4:4:4 Formats. Mixer Block Diagram-Pixel Selection Mixer Block Diagram-Pixel Processing
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Figure Figure Figure Figure
VBI/Programming Data Packet Formats Shadow Mechanism Shadowing Registers Resource Layer
Figure Figure Figure Figure
Resource Layer 2-Layer Resource Elements Scenario Pool Aperture Reassignments Video Frame Screen Timing
Chapter Video Input Processor
Figure Figure Figure Figure Figure Figure Figure Simplified Block Diagram Module Interface Digital Video Input Port Timing Relationships Mode431 Test Pattern Data Stream Dual Data Stream Video Data Flow Figure Figure Figure Figure Figure Figure Figure Source Target Window Parameters Acquisition Window Counter Reference Field Identifier Timing Double Buffer Mode Auxiliary Data Flow Data Structure Masked Checking.
Chapter FGPO: Fast General Purpose Output
Figure Figure Figure Level Block Diagram FGPO Module Block Diagram Back-to-back Message Passing Example Figure Figure Figure Double Buffer Major States Signal Edge Definition Back-to-back Message Passing Example
Chapter FGPI: Fast General Purpose Interface
Figure Figure Figure Level Block Diagram FGPI Module Block Diagram Input data width equal sample size setting490 Figure Figure Figure Figure Double Buffer Major States Buffer Sync Actions Signal Edge Definition Back-to-back Message Passing Example
Chapter Audio Output
Figure Figure Figure Audio Block Diagram Examples Audio Memory Formats
Figure Figure Figure
Definition Serial Frame Positions (POLARITY CLOCK_EDGE 0)514
Serial Frame Bits) 18-Bit Precision Converter515 Example Codec Frame Layout Crystal Semiconductor CS4218517 Audio Clock System Interface
Chapter Audio Input
Figure Figure Figure Audio Block Diagram. Audio Clock System Interface Audio Serial Frame Position Definition (POLARITY CLOCK_EDGE EARLYMODE 0)534 Figure Audio Serial Frame Position Definition (POLARITY CLOCK_EDGE EARLYMODE 1)534 Serial Frame SAA7366 18-Bit Converter (Format SWS)535 Audio Memory Formats
Figure Figure
Chapter SPDIF Output
Figure Figure Serial Format IEC-60958 Block Bi-Phase Mark Data Transmission Figure Suggested External SPDIF Output Interface Circuitry553
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Chapter SPDIF Input
Figure Figure Figure Figure Figure SPDIF Input Block Diagram Serial Format IEC60958 Block SPDIF Input: Mode Format SPDIF Input Sample Order View Memory
Figure Figure Figure Figure Figure
SPDIF Input Oversampling Clock Generation
Endian Mode Byte Address Memory Format
Lock/Unlock Processing SPDIF Input SPDIF Input Consumer interface SPDIF Input MMIO Registers SPDIF Input MMIO Registers
Chapter Memory Based Scaler
Figure Figure Figure Block Diagram Level Horizontal Processing Pipeline Figure Figure Figure Vertical Processing Pipeline Task FIFO Linked List Measurement
Chapter Drawing Engine
Figure Drawing Engine Block Diagram.
Chapter MPEG-1 MPEG-2 Variable Length Decoder
Figure Figure Block Diagram MPEG-2 Macro Block Header Output Format
Figure
MPEG-1 Macro Block Header Output Format
Chapter Digital Video Disc Descrambler
Chapter LAN100 Ethernet Media Access Controller
Figure Figure Figure Figure Figure Figure Figure Figure Simplified LAN100 Block Diagram LAN100 Functional Block Diagram Pattern matching join function Receive descriptor memory layout Transmit Descriptor Memory Layout. Transmit example memory registers Transmit example waves Receive example memory registers Figure Figure Figure Figure Figure Figure Figure Receive example waves Real-time/non-real-time transmit example transmission example Transmit flow control Receive filter block diagram Receive Active/Inactive state machine Transmit Active/Inactive state machine
Chapter TM3260 Debug
Figure Figure State Diagram Controller System with JTAG Access Figure Additional JTAG Data Control Registers
Chapter Interface
Figure First Transmitted Byte
Chapter Memory Arbiter
Figure Arbitration Scheme
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Chapter Power Management
Chapter Pixel Formats
Figure Figure Figure Figure Figure Figure Figure Native Pixel Format Unit Layout Indexed Formats 16-Bit Pixel-Packed Formats 32-Bit/Pixel Packed Formats UYVY Packed 4:2:2 Format YUY2/2vuy Packed 4:2:2 Format Spatial Sampling Structure Packed Planar 4:2:2 Data793 Figure Figure Figure Figure Figure Figure Spatial Sampling Structure 4:2:0 Data
Planar 4:2:0 4:2:2 Formats Semi-Planar 4:2:0 4:2:2 Formats795 Semi-Planar 10-bit 4:2:0 4:2:2 Formats796 Packed 10-bit 4:2:2 Format Image Storage Format
Chapter Endian Mode
Figure Figure Figure Figure System Block Diagram: Endian-Related Blocks803 Big-Endian Layout DMA_Descriptor Little-Endian Layout DMA_Descriptor Memory Content Created Program.
Figure Figure Figure
Audio Memory Data Structure (Programmer's View)809 Audio Control/Status MMIO Registers Big-Endian External Drawing RGB565 Pixels816
Chapter Network
Chapter TM3260 VLIW
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Chapter Integrated Circuit Data
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table PNX1500 Types PNX1500 Modes PNX1500 Special I/Os. PNX1500 Interface Power List Reference Voltage Absolute Maximum Ratings PNX1500 Operating Range Thermal Characteristics45 PNX1500 Maximum Operating Speeds PNX1501 Operating Range Thermal Characteristics46 PNX1501 Maximum Operating Speeds PNX1502 Operating Range Thermal Characteristics47 PNX1502 Maximum Operating Speeds PNX1520 Operating Range Thermal Characteristics47 PNX1520 Maximum Operating Speeds PNX9520 Operating Range Thermal Characteristics48 PNX9520 Maximum Operating Speeds PNX9525 Operating Range Thermal Characteristics48 PNX9525 Maximum Operating Speeds MPEG-2 Decoding with 720x480P Output PNX150250 Estimated PNX15xx/952x Series Maximum Peak current50 Specification HC-49U 27.00000 Crystal52 Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Specification Oscillator Mode SSTL_2 AC/DC Characteristics BPX2T14MCP Characteristics BPTS1CHP BPTS1CP Characteristics BPTS3CHP BPTS3CP Characteristics IPCHP IPCP Characteristics BPT3MCHDT5V BPT3MCHT5V Characteristics57 IIC3M4SDAT5V IIC3M4SCLT5V Characteristics58 PCIT5V Characteristics Reset Timing DRAM Interface Timing Timing QVCP, FGPO Timing With Internal Clock Generation62 QVCP, FGPO Timing With External Clock Generation62 FGPI Timing 10/100 Timing 10/100 RMII Timing Audio Input Timing Audio Output Timing. SPDIF Timing Timing GPIO Timing JTAG Timing Recommended Trance Length Ordering Information
Chapter Overview
Table Table Table Table Partitioning Functions Resources PNX15xx/952x Series Boot Options Footprints 32-bit 16-bit Interface
TM3260 Characteristics
Table Table Table Table Table
Native Pixel Format Summary Video/Data Input Operating Modes Video/Data Output Operating Modes PNX15xx/952x Series capabilities PCI/XIO-16 Interface Unit Capabilities105
Chapter System Chip Resources
Table Table Table Table Table Table SYSTEM Registers SYSTEM Registers SYSTEM Registers Semaphore MMIO Registers Interrupt Source Assignments TM3260 Timer Source Selection Table Table Table Table Table TM3260 System Parameters MMIO Registers
Global Registers Miscellaneous System MMIO registers System Registers Summary MMIO Memory
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Chapter Reset
Table RESET Module
Chapter Clock Module
Table Table Table Table Table Table PNX15xx/952x Series Module Clocks
Current Adjustment Values Based Settings Characteristics Internal Clock Dividers Clock Assignment.
Table Table Table Table Table
External Clocks Bypass Clock Sources Advantages Centralized Clock Gating Control167 Registers Summar CLOCK MODULE REGISTERS.
Chapter Boot Module
Table Table Table Table Table Boot Modes Boot Commands. Default SDRAM Timing Parameters Latency Related SDRAM Timing Parameters209 Setup Command register Content210 Table Table Table Table Table Binary Sequence Common Boot Script
Flash TIming Parameters Used Default Boot Scripts213 Binary Sequence Section Flash Boot214 Host Configuration Sequence Examples EEPROM Devices
Chapter PCI-XIO Module
Table Table Table Table Table Supported Commands Multiplexing Recommended Settings NAND GPXIO Address Configuration Timing Table Table Table Table PCI-XIO Register Summary Configuration Register Summary Registers Description Configuration Registers
Chapter General Purpose Input Output Pins
Table Table Table Table Table Table Table Table Table Table Table GPIO List GPIO Mode Select Settings MASK[xx] IOD[xx] Bits GPIO clock sources Example Characteristics Register Summary GPIO Mode Control Registers GPIO Data Control Readable Internal PNX1500 Signals Sampling Pattern Generation Control Registers FIFO Queues293 Signal Event Monitoring Control Registers Timestamp Units300 Table Table Table Table Table Table Table Table Table Table Timestamp Unit Registers GPIO Time Counter GPIO TM3260 Timer Input Select GPIO Interrupt Status. Clock Select GPIO Interrupt Registers FIFO Queues (One each FIFO Queue)303 GPIO Module Status Register Timestamp Units304 GPIO POWERDOWN GPIO Module GPIO IO_SEL Selection Values
Chapter Controller
Table Table Preemption Field. 32-Byte Interleaving, Columns Table Table 32-Byte Interleaving, Columns Mapping scheme: 1024-Byte Interleaving,
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Table Table
Columns323 1024-Byte Interleaving, Columns Timing Parameters
Table Table Table
Commands Register Summary Register Description
Chapter Controller
Table Controller Register Summary Table CONTROLLER Registers
Chapter QVCP
Table Table Table Table Table Table Table Table Table Table Table Summary Native Pixel Formats. Color Combining ROPs Chroma Examples Table Invert/Select/Alpha/KeyPass/ AlphaPass ROPs369 Data Packet Descriptor Shadow Registers Fast Access Registers. Resource Assignment Register Space Allocation. Association Resource-Layer Assignment Pool Resource384 Programming Values Supported PNX15xx/ 952x Series Output Formats389 LINT programming HSRU programming LSHR Programming Parameters DCTI Programming Parameters. CFTR Programming Parameters Interface Characteristics Some Target Resolutions394 Register Module Association QVCP Registers
Table Table Table Table Table Table Table Table Table
Chapter Video Input Processor
Table Table Table Table Table Submodule Descriptions Test Pattern Generator Setup Video Input Formats Relationship Between Input Formats Video Data Capture435 Field Identifier Generation Modes Table Table Table Table Table Output Pixel Formats Relationship Between Input Formats Data Capture442 Relationship Between Input Formats Data Capture446 MMIO Register Summary Video Input Processor (VIP) Registers
Chapter FGPO: Fast General Purpose Output
Table Table Module signal pins Register Summary Table Table Fast general purpose output (FGPO) Status Registers
Chapter FGPI: Fast General Purpose Interface
Table Table Module signal pins Register Summary Table Table Fast general purpose INput (FGPI) Status Registers
Chapter Audio Output
Table Table Table Table Audio Unit External Signals Operating Modes Memory Formats Bits Transmitted Each Memory Data Item
Minimum Serial Frame Length Bits
Table Table Table Table Table
Example Setup 64-Bit Framing Audio Latency Tolerance Examples Clock System Setting Register Summary Audio Output Port Registers
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Chapter Audio Input
Table Table Table Table Table Table Table Audio-In Related Ports Sample Rate Settings Positions Assigned Each Data Item Example Setup SAA7366 Operating Modes Memory Formats Endian Ordering Audio Data Main Memory536 Audio Data Arbiter Latency Requirement Examples 16-Bit Data Examples538 Audio Data Arbiter Latency Requirement Examples 32-Bit Data Examples538 Mode Format Input Data Word Select541 Register Summary Audio (I2S) Input Ports Registers
Table
Table Table Table
Chapter SPDIF Output
Table Table Table SPDIF Sample Rates Jitter SPDIF Subframe Descriptor Word SPDO Block Latency Requirements Table Table Table SPDIF External Signals SPDIF Output Module Register Summary SPDO Registers
Chapter SPDIF Input
Table Table Table SPDIF Input Oversampling Clock Value Settings562 Input Jitter Different Sample Rates SPDI_CBITS1 Channel Status Meaning Table Table Table SPDI_CBITS2 Channel Status Meaning SPDIF Input Summary SPDIF Input Registers
Chapter Memory Based Scaler
Table Table Table Pipeline Processing (Horizontal First Mode)
Pipeline Processing (Vertical First Mode) De-Interlacing Mode Maximum Filter Lengths
Table Table Table Table Table
Task Descriptor Opcode Table Input Pixel Formats Output Pixel Formats Register Summary Memory Based Scaler (MBS) Registers
Chapter Drawing Engine
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Source Destination Data Mono Bitmap Text Data Parameters Solid Color Fill Parameters Color Parameters. Memory Space Addresses Command Registers Real Time Drawing Registers Registers Description Destination Address Base Pixel Size Pixel Format Assignments Dithering Source Linear Destination Linear Source Stride Destination Stride Color Compare Mono Host Color SurfAlpha Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Mono Host Color HAlpha Color Control. Source Address, Coordinates Destination Address, Coordinates Size Destination Address, Coordinates Vector Constant Vector Count Control TransMask MonoPatFColor MonoPatBColor EngineStatus PanicControl EngineConfig HostFIFOStatus POWERDOWN Module Drawing Engine Data Registers
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Chapter MPEG-1 MPEG-2 Variable Length Decoder
Table Table Table Table Table Table Software Reset Procedure STATUS Control Commands Command Register References MPEG-2 Macroblock Header Data659 References MPEG-1 Macroblock Header Data661 Error Handling Register Summary Registers
Table Table Table Table
Chapter Digital Video Disc Descrambler
Chapter LAN100 Ethernet Media Access Controller
Table Table Table Table Table Table LAN100 MMIO Register LAN100 Registers PatternMatchJoin Register Nibble Functions
Receive Descriptor Structure Receive Descriptor Control Word Receive Status Structure
Table Table Table Table Table Table
Receive Status Information Word Transmit Descriptor Fields Transmit Descriptor Control Word Transmit Status Structure Transmit Status Information Word LAN100 Interface external
Chapter TM3260 Debug
Table Table Table JTAG TM3260 Instruction Encoding JTAG Instruction Encoding Transfer Data JTAG Table Table Register Summary TM_DBG Registers
Chapter Interface
Table Table Table Table Register Summary Registers Registers Registers Table Table Table Status Codes Registers Registers
Chapter Memory Arbiter
Table Table Peripheral Sub-Arbitration Register Summary Table PMAN (Hub) Arbiter Registers
Chapter Power Management
Chapter Pixel Formats
Table Native Pixel Format Summary Table Alpha Code Value Pixel Transparency
Chapter Endian Mode
Table Table Memory Result Store Address Instruction805 Register Result (Unsigned) Load Instruction805 Register Result (Signed) Load Instruction
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Table Table Table Table
Precise Mapping Audio Sample Time Bits Memory Bytes809 Interface Rules Interface Byte Address Interface Rules
Table Table Table Table
Network Data Transfer Rules Bits ata-time Transfer)812 Memory Byte Address Memory Item Rules Interface Byte Address
Chapter Network
Table Controller_TriMedia Configuration Register Summary819 Table Controller_TriMedia Configuration Registers (Rev 0.32)820
Chapter TM3260 VLIW
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Introduction
PNX1500 Media Processor Series complete Audio/Video/Graphics system chip that contains high-performance 32-bit VLIW processor, TriMediaTM3260, capable high quality software video (multi-video standard digital decoder/ encoder image improvement), audio signal processing, well general purpose control processing. either used standalone, accelerator general purpose processor. PNX1500 processes input signals utilizing several Audio/Video co-processor modules before send them external peripherals. These modules provide additional video data processing bandwidth without taking away precious cycles. combination co-processor modules makes PNX1500 System On-Chip (SoC) suitable most applications, especially those requiring high level processing power/ throughput reduced cost. Refer Section page 1-79 ordering information well different PNX1500 derivatives available. Throughout this document PNX1500 PNX15xx/ 952x Series will used refer derivatives PNX1500 devices unless otherwise specified.
Description
Boundary Scan Notice
PNX1500 implements full IEEE1149.1 boundary scan. designated `IN' only (from functionality point view) function output during boundary scan.
Circuit Summary
PNX1500 total functional pins, reserved pin, power pins. regular I/Os powered power supply. DDR-I interface supports supports power supply depending PNX15xx/952x Series device. PNX1500 supports input tolerant pins some specific interfaces such I2C. Refer Section 2.3.2 page 1-44 summary list voltage reference each pin.
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Chapter Integrated Circuit Data
PNX1500 uses different I/Os depending type interface, e.g. PCI, electrical characteristics needed functionality, e.g. clock signal requires sharper edges than regular signal. following table summarizes types a.k.a. pads, used PNX1500.
Table PNX1500 Types Type PCIT5V IIC3M4SDAT5V IIC3M4SCLT5V BPX2T14MCP BPTS1CP BPTS1CHP BPTS3CP BPTS3CHP BPT3MCHT5V 3.3-V impedance output, with fast rise/fall time, combined with 3.3-V input only. Used Clock signals requires board level 27-33 series terminator resistor match trace. 3.3-V regular impedance output, with fast rise/fall time, combined with 3.3-V input only. 3.3-V regular impedance output, with fast rise/fall time, combined with 3.3-V input only with hysteresis. 3.3-V regular impedance output, with slow rise/fall time, combined with 3.3-V input only. 3.3-V regular impedance output, with slow rise/fall time, combined with 3.3-V input only with hysteresis. 3.3-V regular impedance output, with slow rise/fall time, combined with tolerant input with hysteresis. Description compliant using 3.3- signaling conventions. Open drain 3.3- I/Os.
BPT3MCHDT5V 3.3-V regular impedance output, with slow rise/fall time, combined with tolerant input with hysteresis internal pull-down. Note: pull-down strong enough actually pull down input. Instead input sees `1'. IPCP IPCHP SSTLCLKIO SSTLADDIO SSTLDATIO 3.3-V input only. 3.3-V input only with hysteresis. SSTL_2 impedance, e.g. SDRAM clocks. Requires board level series terminator resistor match trace. SSTL_2 impedance output signals, e.g. SDRAM address control signals. Requires board level matched trace. SSTL_2 impedance SDRAM data signals. Requires board level matched trace.
above types used modes listed following table
Table PNX1500 Modes Modes I/OD I/O/D Description Input only, except during boundary scan GPIO mode. Output only, except when used GPIO pin. Open drain output active pull low, active drive high, requires external pull-up. Input Output. Input open drain output active pull low, active drive high, requires external pull-up. Input output open drain output with input active pull low, active drive high, requires external pullup when operated open drain mode. Output floating.
Unused pins remain unconnected, i.e. floating they contain internal pull-up pull-down. More specifically,
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PCI_FRAME_N, PCI_TDRY_N, PCI_IRDY_N, PCI_DEVSEL_N, PCI_STOP_N,
PCI_SERR_N, PCI_PERR_N PCI_INTA_N require external pull-up. Refer Section 4.3.3 specification more details.
I/OD signal must pulled-up they used. GPIO[11:8] must pulled-up down.
following Section contains table that specifies contains pull-up, pull-down none (column `P'). Remark: pull-down BPT3MCHDT5V pads strong enough actually pull down input. Instead input sees `1'. Speciality pads, e.g. power supply, described following table.
Table PNX1500 Special I/Os Name APIO1V2 APIO3V3 APOD SSTLREFGEN VDDE3V3 Description Analog core logic. Analog 3.3-V logic. Generic Analog signal. Reference voltage SDRAM interface. power supply peripherals I/Os. power supply memory SDRAM I/Os. These I/Os 3.3-V capable Automated Test Equipment (ATE), functional mode. VDDI VSSE VSSIS core power supply. Common ground I/Os. Common ground core.
Signal List
following table details interface PNX1500. types, refer tables presented Section 2.2. type indicates functional mode (i.e. dedicated GPIO always I/O/D type). column indicates signal pulled down, `D', pulled neither `-'. Active signals suffixed `_N'.
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Remark: pull-down BPT3MCHDT5V pads strong enough actually pull down input. Instead input sees `1'.
Table PNX1500 Interface Name System Clock XTAL_IN APIO1V2 PNX1500 main input clock. internal clocks derived from this input reference clock. crystal should placed close possible package. Refer Figure Figure board level connections. This input follows operating range VDD. XTAL_OUT APIO1V2 Crystal oscillator output. Connect external crystal between this XTAL_IN. Refer Figure Figure board level connections. This clock intended clock simple PNX1500 configurations. outputs 33.23 clock. board level 27-33 series resistor recommended reduce ringing. Ball Type Type GPIO Description
PCI_SYS_CLK
BPX2T14MCP
Miscellaneous System Interface POR_IN_N BPT3MCHT5V PNX1500 Power Reset input. Asserting this input triggers hardware reset function PNX1500 (including JTAG state machine). This typically connected on-board reset upon voltage drop. active low. Upon asserting this reset input, PNX1500 asserts SYS_RST_OUT_N reset attached peripheral chips. This also tied PCI_RST signal systems. This tolerant input. PNX1500 reset input. Asserting this input triggers hardware reset function PNX1500 (This does reset JTAG state machine). Upon asserting this reset input, PNX1500 asserts SYS_RST_OUT_N reset attached peripheral chips. This also tied PCI_RST signal systems. With respect POR_IN_N reset pin, this used warm reset. most applications, both reset pins tied together. active low. This tolerant input. SYS_RST_OUT_N BPX2T14MCP Active peripheral reset output. This output asserted upon PNX1500 reset (hardware, watchdog timer software), de-asserted PNX1500 system software. intended used reset external peripherals. Reserved future expansion. left unconnected board level normal operation.
RESET_IN_N
BPT3MCHT5V
RESERVED
AB23 BPT3MCHDT5V
Main Memory Interface (DDR SDRAM controller) Refer Section 10.3 page 1-76 board design guidelines
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Chapter Integrated Circuit Data
Table PNX1500 Interface Name MM_CLK MM_CLK_N MM_CS1_N MM_CS0_N MM_RAS_N MM_CAS_N MM_WE_N MM_CKE AVREF MM_BA1 MM_BA0 MM_ADDR12 MM_ADDR11 MM_ADDR10 MM_ADDR09 MM_ADDR08 MM_ADDR07 MM_ADDR06 MM_ADDR05 MM_ADDR04 MM_ADDR03 MM_ADDR02 MM_ADDR01 MM_ADDR00 MM_DQM3 MM_DQM2 MM_DQM1 MM_DQM0 MM_DQS3 MM_DQS2 MM_DQS1 MM_DQS0 Ball Type SSTLCLKIO SSTLCLKIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLREFGEN SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLADDIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO Type GPIO Description SDRAM Output Clock. Refer Section 10.3 page 1-76 board level connections. Chip select SDRAM. active low. address strobe. active low. Column address strobe. active low. Write enable. active Clock enable output SDRAMs. Voltage reference. SDRAM bank address. supports 4-bank types SDRAMs. SDRAM address bus. used column addresses. Byte write enable signals: MM_DQM0 attached byte MM_DATA[7:0] MM_DQM1 attached byte MM_DATA[15:8] MM_DQM2 attached byte MM_DATA[23:16] MM_DQM3 attached byte MM_DATA[31:24] Byte strobe signals: MM_DQS0 attached byte MM_DATA[7:0] MM_DQS1 attached byte MM_DATA[15:8] MM_DQS2 attached byte MM_DATA[23:16] MM_DQS3 attached byte MM_DATA[31:24]
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Table PNX1500 Interface Name MM_DATA31 MM_DATA30 MM_DATA29 MM_DATA28 MM_DATA27 MM_DATA26 MM_DATA25 MM_DATA24 MM_DATA23 MM_DATA22 MM_DATA21 MM_DATA20 MM_DATA19 MM_DATA18 MM_DATA17 MM_DATA16 MM_DATA15 MM_DATA14 MM_DATA13 MM_DATA12 MM_DATA11 MM_DATA10 MM_DATA09 MM_DATA08 MM_DATA07 MM_DATA06 MM_DATA05 MM_DATA04 MM_DATA03 MM_DATA02 MM_DATA01 MM_DATA00 Ball Type SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO SSTLDATIO Type GPIO Description SDRAM data bus.
MHz, 32-bit Interface 8-bit Interface (Flash, M68K system bus) (note: buffer design allows drive/receive from either bus) PCI_CLK PCIT5V input signals sampled with respect rising edge this clock. outputs generated based this clock. small configurations, PCI_SYS_CLK used provide this clock.
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Chapter Integrated Circuit Data
Table PNX1500 Interface Name PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD09 PCI_AD08 PCI_AD07 PCI_AD06 PCI_AD05 PCI_AD04 PCI_AD03 PCI_AD02 PCI_AD01 PCI_AD00 PCI_C/BE3_N PCI_C/BE2_N PCI_C/BE1_N PCI_C/BE0_N PCI_PAR PCI_FRAME_N PCI_IRDY_N Ball Type PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V Type GPIO Description Multiplexed address data bus. Multiplexed Commands Byte Enables. Even Parity across AD[31:0] C/BE[3:0]_N lines. Sustained Tri-state. Frame driven master indicate beginning duration access. Sustained Tri-state. Initiator Ready indicates that master ready complete current data phase.
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PNX15xx/952x Series
Chapter Integrated Circuit Data
Table PNX1500 Interface Name PCI_TRDY_N Ball Type PCIT5V Type GPIO Description Sustained Tri-state. Target Ready indicates that target ready complete current data phase. Sustained Tri-state. indicates that target requesting that master stop current transaction. Used Chip Select during configuration read/write cycles. Sustained Tri-state. indicates whether device been selected. PNX1500 arbiter bus, this acts request input external device, otherwise driven PNX1500 master request bus. PNX1500 arbiter bus, this acts output grant requester, otherwise Indicates PNX1500 that access been granted. PNX1500 arbiter bus, this acts request input external device. This also used input external interrupt line TM3260. PCI_GNT_A_N PCIT5V PNX1500 arbiter bus, this acts output grant requester. internal arbiter used, this used input external interrupt line TM3260. PNX1500 arbiter bus, this acts request input external device. This used input external interrupt line TM3260. This pins also used DSACK signal when using M68K system PCI-XIO interface. PCI_GNT_B_N PCIT5V PNX1500 arbiter bus, this acts output grant requester. internal arbiter used, this used input external interrupt line TM3260. Sustained Tri-state. Parity errors generated/ received PNX1500 through this pin. System Error. This signal asserted when operating target when detects address parity error.
PCI_STOP_N
PCIT5V
PCI_IDSEL PCI_DEVSEL_N PCI_REQ_N
PCIT5V PCIT5V PCIT5V
PCI_GNT_N
PCIT5V
PCI_REQ_A_N
PCIT5V
PCI_REQ_B_N
PCIT5V
PCI_PERR_N PCI_SERR_N
PCIT5V PCIT5V
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Table PNX1500 Interface Name PCI_INTA_N Ball Type PCIT5V Type I/OD GPIO Description specifically intended used INTA pin, that software requires less board specific information. should configured used interrupt output case when external host exists. Interrupts asserted software running TM3260. standalone systems where PNX1500 host, this should configured input allowing external devices request interrupt service from TM3260 CPU.
Additional signals regular signals implement Flash, drive interface M68k System Buses. XIO_D15 XIO_D14 XIO_D13 XIO_D12 XIO_D11 XIO_D10 XIO_D09 XIO_D08 XIO_SEL4 XIO_SEL3 XIO_SEL2 XIO_SEL1 XIO_SEL0 XIO_ACK XIO_AD Video/Data Group This group provides ITU656 20-bit inputs, 32-bit data streaming input. Refer Section page 3-125 detailed definition operating modes this group. VDI_D33 VDI_D32 BPTS3CHP BPTS3CHP Control streaming data mode. AA25 AA26 AD25 AC19 AE26 AC22 AB24 AC23 AD26 AB25 AB26 AC20 AA24 PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V PCIT5V extended 8-bit data signals 16-bit NAND/NOR flash support well M68K system buses with 16-bit wide data path. Chip Selects. required component glue-less connections. Flash/EEPROM acknowledge. Same XIO_A[25] defined module.
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Chapter Integrated Circuit Data
Table PNX1500 Interface Name VDI_D31 VDI_D30 VDI_D29 VDI_D28 VDI_D27 VDI_D26 VDI_D25 VDI_D24 VDI_D23 VDI_D22 VDI_D21 VDI_D20 VDI_D19 VDI_D18 VDI_D17 VDI_D16 VDI_D15 VDI_D14 VDI_D13 VDI_D12 VDI_D11 VDI_D10 VDI_D09 VDI_D08 VDI_D07 VDI_D06 VDI_D05 VDI_D04 VDI_D03 VDI_D02 VDI_D01 VDI_D00 VDI_CLK1 Ball AC14 AF12 AE12 AF11 AC13 AD11 AF10 AE10 AC12 AD10 AC11 AC10 Type BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPX2T14MCP Type GPIO Description Video Streaming Parallel Data control Inputs. positive edge this internally externally generated clock samples video data. When generated internally, clock software adjusted with Hertz accuracy allow generation precisely timed sequence samples locked arbitrary reference, such broadcast transport stream source. board level 27-33 series resistor recommended reduce ringing. Data Valid clock qualifier associated with VDI_CLK1.
VDI_V1
AF13
BPTS3CHP
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Table PNX1500 Interface Name VDI_CLK2 Ball Type BPX2T14MCP Type GPIO Description positive edge this internally externally generated clock samples streaming data. When generated internally, clock software adjusted with Hertz accuracy allow generation precisely timed sequence samples locked arbitrary reference, such broadcast transport stream source. board level 27-33 series resistor recommended reduce ringing. Data Valid clock qualifier associated with VDI_CLK2.
VDI_V2 Video/Data Group
BPTS3CHP
video mode provides ITU656 16-bit outputs, digital 24-/30-bit outputs, digital 24-/30-bit RGB/VGA outputs. data streaming mode provides 16-bit 32-bit data streaming output. Refer Section page 3-125 detailed definition operating modes this group. VDO_D34 VDO_D33 VDO_D32 BPTS1CHP BPTS1CHP BPTS1CHP FGPO data extended mode. Control Streaming Parallel Data Outputs. FGPO data bits [4:3] extended mode.
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Chapter Integrated Circuit Data
Table PNX1500 Interface Name VDO_D31 VDO_D30 VDO_D29 VDO_D28 VDO_D27 VDO_D26 VDO_D25 VDO_D24 VDO_D23 VDO_D22 VDO_D21 VDO_D20 VDO_D19 VDO_D18 VDO_D17 VDO_D16 VDO_D15 VDO_D14 VDO_D13 VDO_D12 VDO_D11 VDO_D10 VDO_D09 VDO_D08 VDO_D07 VDO_D06 VDO_D05 VDO_D04 VDO_D03 VDO_D02 VDO_D01 VDO_D00 VDO_CLK1 Ball Type BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPTS1CHP BPX2T14MCP Type GPIO Description Video and/or Streaming Parallel Data Outputs. VDO_D29 used input when QVCP used VSYNC slave mode. positive negative edge this internally externally generated clock causes transitions video samples. When generated internally clock software adjusted with Hertz accuracy, allow generation precisely timed sequence samples locked arbitrary reference, such broadcast transport stream source. board level 27-33 series resistor recommended reduce ringing.
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Chapter Integrated Circuit Data
Table PNX1500 Interface Name VDO_CLK2 Ball Type BPX2T14MCP Type GPIO Description positive edge this internally externally generated clock causes transitions streaming data samples. When generated internally, clock software adjusted with Hertz accuracy allow generation precisely timed sequence samples locked arbitrary reference, such broadcast transport stream source. board level 27-33 series resistor recommended reduce ringing. VDO_AUX programmed output, CBLANK signal, Field indicator video/ graphics detector. Synchronization signal Streaming Parallel Data Outputs. FGPO data intended extended mode. Synchronization signal Streaming Parallel Data Outputs. FGPO data intended extended mode.
VDO_AUX
BPTS1CHP
FGPO_REC_SYNC
BPTS1CHP
FGPO_BUF_SYNC
BPTS1CHP
Octal Audio (audio always acts receiver, master slave timing) AI_OSCLK AF23 BPX2T14MCP Over-Sampling Clock. This output programmed emit frequency with Hertz resolution. intended used over sampling clock external subsystem. board level 27-33 series resistor recommended reduce ringing. operate either master slave mode. When Audio-In programmed serialinterface timing slave (power-up default), AI_SCK input. AI_SCK receives serial clock from external subsystem. This clock treated fully asynchronous PNX1500 main clock. When Audio programmed serialinterface timing master, AI_SCK output. AI_SCK drives serial clock external subsystem. frequency programmable integral divide AI_OSCLK frequency. AI_SCK limited MHz. sample rate valid samples embedded variable. used output, board level 27-33 series resistor recommended reduce ringing.
AI_SCK
AD20
BPX2T14MCP
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Table PNX1500 Interface Name AI_WS Ball AD21 Type BPTS3CHP Type GPIO Description operate either master slave mode. When Audio programmed serialinterface timing slave (power-up default), AI_WS acts input. AI_WS sampled same edge selected AI_SD[3:0]. When Audio programmed serialinterface timing master, AI_WS acts output. asserted opposite edge AI_SD[3:0] sampling edge. AI_WS word-select frame-synchronization signal from/to external subsystem. AI_SD3 AI_SD2 AI_SD1 AI_SD0 AD22 BPT3MCHDT5V AC17 BPT3MCHDT5V AF24 BPT3MCHDT5V AE23 BPT3MCHDT5V Serial Data from external subsystem. Data this sampled positive negative edge AI_SCK determined CLOCK_EDGE AI_SERIAL register. These pins tolerant input.
Octal Audio (audio always acts sender, master slave timing) AO_OSCLK AD19 BPX2T14MCP Over Sampling Clock. This output programmed emit frequency MHz, with Hertz resolution. intended used over sampling clock external conversion subsystem. board level 27-33 series resistor recommended reduce ringing. operate either master slave mode. When Audio programmed serial interface timing slave (power default), AO_SCK acts input. receives Serial Clock from external audio subsystem. clock treated fully asynchronous PNX1500 main clock. When Audio programmed serial interface timing master, AO_SCK acts output. drives Serial Clock external audio subsystem. clock frequency programmable integral divide AO_OSCLK frequency. AO_SCK limited MHz. sample rate valid samples variable. used output, board level 27-33 series resistor recommended reduce ringing.
AO_SCK
AE18
BPX2T14MCP
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Table PNX1500 Interface Name AO_WS Ball AE20 Type BPTS3CHP Type GPIO Description operate either master slave mode. When Audio-Out programmed serialinterface timing slave (power-up default), AO_WS acts input. AO_WS sampled opposite AO_SCK edge which AO_SD[3:0] asserted. When Audio programmed serialinterface timing master, AO_WS acts output. AO_WS asserted same AO_SCK edge AO_SD[3:0]. AO_WS word-select framesynchronization signal from/to external subsystem. Each audio channel receives sample every period. AO_SD3 AO_SD2 AO_SD1 AO_SD0 SPDIF interface SPDI BPT3MCHDT5V Input SPDIF (Sony/Philips Digital Audio Interface, a.k.a. Dolby DigitalTM), self clocking audio data stream IEC958 with 1937 extensions. This tolerant input. Output SPDIF. Note that this low-impedance driver requires 27-33 resistor close PNX1500 match board line impedance. This resistor becomes part voltage divider necessary drive IEC958 isolation transformer. AF21 AF20 AE19 AF19 BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP Serial Data external audio subsystem first channels. timing transitions these outputs determined CLOCK_EDGE AO_SERIAL register, positive negative AO_SCK edge.
SPDO
AF22
BPX2T14MCP
10/100 interface (MII) LAN_CLK LAN_TX_CLK/ LAN_REF_CLK AF18 AF14 BPTS1CP BPTS3CP Clock feed external PHY, usually MHz. Transmit clock RMII reference clock. Both LAN_TX_CLK LAN_RX_CLK have connected RMII reference clock RMII mode. RMII Transmit Enable Transmit Data Transmit Data RMII Transmit Data RMII Transmit Data Transmit Error Carrier Sense RMII Carrier Sene Receive Data Valid. This tolerant input. Collision Detect. This tolerant input.
LAN_TX_EN LAN_TXD3 LAN_TXD2 LAN_TXD1 LAN_TXD0 LAN_TX_ER LAN_CRS/ LAN_CRS_DV LAN_COL
AD13 AF15 AD14 AC15 AE14 AE13
BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP
AC24 BPT3MCHDT5V AA23 BPT3MCHDT5V
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Chapter Integrated Circuit Data
Table PNX1500 Interface Name LAN_RX_CLK/ LAN_REF_CLK LAN_RXD3 LAN_RXD2 LAN_RXD1 LAN_RXD0 LAN_RX_DV LAN_RX_ER LAN_MDIO LAN_MDC Interface IIC3M4SDAT5V IIC3M4SCLT5V I/OD I/OD serial data. This tolerant input. clock. This tolerant input. Ball AF16 Type BPTS3CP Type GPIO Description Receive Clock. Both LAN_TX_CLK LAN_RX_CLK have connected RMII reference clock RMII mode. Receive Data Receive Data RMII Receive Data RMII Receive Data Receive Data Valid. RMII Receive Error. Management data I/O. Management Data clock.
AD17 AD16 AF17 AE16 AE15 AD15 AC26 AC25
BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP BPTS3CHP
IIC_SDA IIC_SCL
GPIO Multi-function flexible software universal serial interface Each GPIO individually set/read software, connected engine that makes function serial pattern generator serial observer, that software implement complex serial protocols. Typically, used receiver, blaster, switches, lights serial communications protocols. addition, with entry GPIO column this list (individually) GPIO instead primary function. After power-on reset, every GPIO input mode avoid potential electrical conflict board. GPIO15/WAKEUP AC21 BPT3MCHDT5V I/O/D Used GPIO pin. This also used wake-up event once PNX1500 been sent into deep power down mode. This tolerant input. Used GPIO pins. These pins also used output internally generated clocks external components present board (Section 2.11.1 page 5-170). GPIO12/GCLOCK00 requires board level 27-33 series resistor reduce ringing. After power boot sequence, these pins used GPIO[11:8] pins. These GPIO pins must strapped with resistors determine PNX1500 boot mode upon reset. GPIO[11:10] pins also used input external interrupt lines TM3260. software assert regular intervals WDOG_OUT output prevent external watchdog device reset entire system. Other GPIO pins used that feature. These pins tolerant input. Used GPIO pin. This tolerant input.
GPIO14/GCLOCK02 GPIO13/GCLOCK01 GPIO12/GCLOCK00
AE22 AE21 AC16
BPTS1CHP BPTS1CHP BPX2T14MCP
I/O/D I/O/D I/O/D
GPIO11/ BOOT_MODE07 GPIO10/ BOOT_MODE06 GPIO09/ BOOT_MODE05 GPIO08/ BOOT_MODE04/ WDOG_OUT
AC18 AD23 AF26 AF25
BPT3MCHT5V BPT3MCHT5V BPT3MCHT5V BPT3MCHT5V
I/O/D I/O/D I/O/D I/O/D
GPIO7
AE24 BPT3MCHDT5V I/O/D
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Table PNX1500 Interface Name GPIO06/CLOCK06 GPIO05/CLOCK05 GPIO04/CLOCK04 Ball Type BPTS1CHP BPX2T14MCP BPTS1CHP Type I/O/D I/O/D I/O/D GPIO Description Used GPIO pins. These pins also used output internally generated clocks external components present board. These GPIO pins also used clocks sampling pattern generation GPIO module (Section 2.11.2 page 5-170). GPIO05/ GCLOCK05 requires board level 27-33 series resistor reduce ringing. After power boot sequence, this functions GPIO[3] pin. This also used clock sampling pattern generation GPIO module. This GPIO strapped with resistor determine PNX1500 boot mode upon reset. After power boot sequence, these pins configured GPIO[2:0] pins. These pins also used clocks sampling pattern generation GPIO module. These GPIO pins strapped with resistors determine PNX1500 boot mode upon reset.
GPIO03/CLOCK03/ BOOT_MODE03
BPTS1CHP
I/O/D
GPIO02/CLOCK02/ BOOT_MODE02 GPIO01/CLOCK01/ BOOT_MODE01 GPIO00/CLOCK00/ BOOT_MODE00
BPTS1CHP BPTS1CHP BPTS1CHP
I/O/D I/O/D I/O/D
JTAG Interface (debug access port 1149.1 boundary scan port) JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TMS IPCHP BPTS3CHP IPCP IPCHP JTAG Test Data Input. JTAG Test Data Output. This either output, float. never input. JTAG Test Clock Input. JTAG Test Mode Select Input.
Power Supplies Ground Refer Section page 1-74 board level connection decoupling associated with these pins. VDDA VSSA_1.2 APOD APOD Analog, quiescent VDD. Refer Figure board level connections. Analog, quiescent ground VDDA analog supply. Refer Figure board level connections. Analog, quiescent VCCP, Refer Figure board level connections. Refer Table complete list. Analog, quiescent ground VCCA analog supply. Refer Figure board level connections. Refer Table complete list. power supply peripherals I/Os. Refer Table complete list. Power supply memory DDR-I I/Os (3.3 capable ATE, functional operation). Refer Table complete list.
VCCA[]
APOD
VSSA[]
APOD
VCCP[] VCCM[]
VDDE3V3 VDDE3V3
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Table PNX1500 Interface Name VDD[] VSS[] VSS[] VSS[] Ball Type VDDI VSSIS VSSE VSSE Type GPIO Description core power supply. Refer Table complete list. Ground core. Refer Table complete list. Ground memory I/Os. Refer Table complete list. Ground peripherals I/Os. Refer Table complete list.
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2.3.1
Table Power List Digital Ground AE11 AE17 AE25 AB18 AB21 AB22 AA22 AB11 AB12 AB17
Power List
3.3-V VCCP AB13 AB14 AD12 AD18 AD24 AB19 AB20 DDR-I VCCM Core AB10 AB15 AB16 Analog 3.3-V VSSA VCCA Analog core VSSA_1.2 VDDA
Remark: digital ground signals clocks comes from same digital ground plane. Remark: digital core power supply signals clocks comes from same digital power plane.
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2.3.2
Input and/or Output Input Tolerant POR_IN_N RESET_IN_N PCI_CLK PCI_C/BE03 PCI_C/BE2 PCI_C/BE1 PCI_C/BE0 PCI_PAR PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_STOP_N PCI_IDSEL PCI_DEVSEL_N PCI_REQ_N PCI_GNT_N PCI_REQ_A_N PCI_GNT_A_N PCI_REQ_B_N PCI_GNT_B_N PCI_PERR_N PCI_SERR_N PCI_INTA_N XIO_ACK XIO_D15 XIO_D14 XIO_D13 XIO_D12 XIO_D11 XIO_D10 XIO_D09 XIO_D08 XIO_SEL4 XIO_SEL3 XIO_SEL2 XIO_SEL1 XIO_SEL0 XIO_AD LAN_CRS LAN_COL IIC_SDA IIC_SCL RESERVED PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD09 PCI_AD08 PCI_AD07 PCI_AD06 PCI_AD05 PCI_AD04 PCI_AD03 PCI_AD02 PCI_AD01 PCI_AD00 GPIO15 GPIO11 GPIO10 GPIO09 GPIO08 GPIO07 SPDI AI_SD3 AI_SD2 AI_SD1 AI_SD0
Reference Voltage
VCCP Input and/or Output PCI_SYS_CLK SYS_RST_OUT_N VDO_CLK1 VDO_CLK2 VDO_D33 VDO_D32 VDO_D31 VDO_D30 VDO_D29 VDO_D28 VDO_D27 VDO_D26 VDO_D25 VDO_D24 VDO_D23 VDO_D22 VDO_D21 VDO_D20 VDO_D19 VDO_D18 VDO_D17 VDO_D16 VDO_D15 VDO_D14 VDO_D13 VDO_D12 VDO_D11 VDO_D10 VDO_D09 VDO_D08 VDO_D07 VDO_D06 VDO_D05 VDO_D04 VDO_D03 VDO_D02 VDO_D01 VDO_D00 VDO_AUX FGPO_REC_SYNC FGPO_BUF_SYNC VDO_D34 AI_OSCLK AI_SCK AI_WS AO_OSCLK AO_SCK AO_WS AO_SD3 AO_SD2 AO_SD1 AO_SD0 SPDO LAN_CLK LAN_TX_CLK LAN_TX_EN LAN_TDX03 LAN_TDX02 LAN_TDX01 LAN_TDX00 LAN_TX_ER LAN_RX_CLK LAN_RXD3 LAN_RXD2 LAN_RXD1 LAN_RXD0 LAN_MDIO LAN_MDC LAN_RX_DV LAN_RX_ER GPIO14 GPIO13 GPIO12 GPIO06 GPIO05 GPIO04 GPIO03 GPIO02 GPIO01 GPIO00 JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO VDI_CLK1 VDI_CLK2 VDI_D33 VDI_D32 VDI_D31 VDI_D30 VDI_D29 VDI_D28 VDI_D27 VDI_D26 VDI_D25 VDI_D24 VDI_D23 VDI_D22 VDI_D21 VDI_D20 VDI_D19 VDI_D18 VDI_D17 VDI_D16 VDI_D15 VDI_D14 VDI_D13 VDI_D12 VDI_D11 VDI_D10 VDI_D09 VDI_D08 VDI_D07 VDI_D06 VDI_D05 VDI_D04 VDI_D03 VDI_D02 VDI_D01 VDI_D00 VDI_V1 VDI_V2 VCCM SSTL DDR-I MM_CLK MM_CLK_N MM_CKE1 MM_CKE2 MM_DQS3 MM_DQS2 MM_DQS1 MM_DQS0 MM_ADDR12 MM_ADDR11 MM_ADDR10 MM_ADDR09 MM_ADDR08 MM_ADDR07 MM_ADDR06 MM_ADDR05 MM_ADDR04 MM_ADDR03 MM_ADDR02 MM_ADDR01 MM_ADDR00 MM_BA1 MM_BA0 MM_CS1_N MM_CS0_N MM_RAS_N MM_CAS_N MM_WE_N MM_DQM3 MM_DQM2 MM_DQM1 MM_DQM0 Special MM_DATA31 XTAL_IN MM_DATA30 XTAL_OUT MM_DATA29 MM_DATA28 MM_DATA27 MM_DATA26 MM_DATA25 MM_DATA24 MM_DATA23 MM_DATA22 MM_DATA21 MM_DATA20 MM_DATA19 MM_DATA18 MM_DATA17 MM_DATA16 MM_DATA15 MM_DATA14 MM_DATA13 MM_DATA12 MM_DATA11 MM_DATA10 MM_DATA09 MM_DATA08 MM_DATA07 MM_DATA06 MM_DATA05 MM_DATA04 MM_DATA03 MM_DATA02 MM_DATA01 MM_DATA00
Table Reference Voltage
Absolute Maximum Ratings
Permanent damage occur absolute maximum ratings exceeded. Prolonged operation above operation range described Section below maximum ratings significantly reduce reliability PNX1500.
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Chapter Integrated Circuit Data
Table Absolute Maximum Ratings Symbol
ICCP
Description supply voltage SSTL DDR-I supply voltage Core supply voltage Input voltage tolerant input pins (i.e. pins supplied CCP) Storage temperature range Operating temperature range junction Human Body Model Electrostatic handling pins Machine Model Electrostatic handling pins Charged Device Model
Minimum -0.5 -0.5 -0.5 -0.5
Maximum 2000
Units
Note
Tstg
Jrange
HBMESD MMESD CDMESD
CLASS JEDEC Standard 22-A114-C, March 2005 CLASS JEDEC Standard 22-A115-A, October 1997 CLASS (Corner pins AEC-Q100-011 standard, July 2003
PNX15xx/952x Series Operating Conditions
PNX15xx/952x Series consist several devices called PNX1500, PNX1501, PNX1502, PNX1520, PNX9520 PNX9525 that mainly differ there speed grades (see following sections). Ordering information found Table page 1-79. following sections detail operating condition device type/grade. tables used:
Functional operation, long-term reliability AC/DC characteristics
guaranteed operating conditions described `Operating Range Thermal Characteristics' tables.
PNX15xx/952x Series designed support dynamic change
different clock frequencies system. `Maximum Operating Speeds' tables describe maximum values device type/grade. Clock speeds adjusted each module individually TM3260 external host. Chapter Clock Module details set-up different clock speeds each PNX15xx/952x Series module.
PNX1500 Device
Table PNX1500 Operating Range Thermal Characteristics Symbol
Description Global supply voltage DDR-I supply voltage. DDR333 lower DDRs require 2.5V Input reference level voltage I/Os. CCM/2 Core supply voltage
Minimum 3.13 2.37 1.15 1.14
Typical 3.30
Maximum 3.47 2.73
Units
1.25 1.26
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Table PNX1500 Operating Range Thermal Characteristics Symbol
Description Operating case temperature range junction case thermal resistance (same junction ambient thermal resistance (still air)
Minimum
Typical 24.3
Maximum
Units °C/W °C/W
case
Table PNX1500 Maximum Operating Speeds QVCP VLIW TM3260 (MHz) DDR-I (MHz) MMIO (MHz) 2DDE (MHz) (qvcp_out, qvcp_proc, Dual Edge) (MHz) 74.25 FGPO (MHz) FGPI (MHz) DVDD (MHz) PCIXIO (MHz) (MHz) (MHz) SPDO (MHz) GPIO (MHz)
PNX1501 Device
Table PNX1501 Operating Range Thermal Characteristics Symbol
Tcase
Description Global supply voltage DDR-I supply voltage. DDR400 DDRs require 2.6V Input reference level voltage I/Os. CCM/2 Core supply voltage Operating case temperature range junction case thermal resistance (same junction ambient thermal resistance (still air)
Minimum 3.13 2.37 1.15 1.14
Typical 3.30
Maximum 3.47 2.73
Units °C/W °C/W
1.25 24.3 1.26
Table PNX1501 Maximum Operating Speeds QVCP VLIW TM3260 (MHz) DDR-I (MHz) MMIO (MHz) 2DDE (MHz) (qvcp_out, qvcp_proc, Dual Edge) (MHz) (MHz) FGPO FGPI (MHz) DVDD (MHz) PCIXIO (MHz) (MHz) (MHz) SPDO (MHz) GPIO (MHz)
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PNX1502 Device
Table PNX1502 Operating Range Thermal Characteristics Symbol
Description Global supply voltage
Minimum 3.13
Typical 3.30 24.3
Maximum 3.47 2.73 1.37
Units °C/W °C/W
DDR-I supply voltage. DDR400 Operating Mode requires 2.6V 2.47 Input reference level voltage I/Os. CCM/2 Core supply voltage Operating case temperature range junction case thermal resistance (same junction ambient thermal resistance (still air) 1.23
case
Table PNX1502 Maximum Operating Speeds QVCP VLIW TM3260 (MHz) DDR-I (MHz) MMIO (MHz) 2DDE (MHz) (qvcp_out, qvcp_proc, Dual Edge) (MHz) (MHz) FGPO FGPI (MHz) DVDD (MHz) PCIXIO (MHz) (MHz) (MHz) SPDO (MHz) GPIO (MHz)
PNX1520 Device
Wide temperature grade.
Table PNX1520 Operating Range Thermal Characteristics Symbol
Tambient
Description Global supply voltage Analog supply voltage (Input Analog filtering circuit) DDR-I supply voltage. DDR333 lower DDRs require 2.5V Input reference level voltage I/Os. CCM/2 Core supply voltage Operating ambient temperature range. junction case thermal resistance (same junction ambient thermal resistance (still air)
Minimum 3.13 3.13 2.37 1.15 1.23
Typical 3.30 3.30
Maximum 3.47 3.47 2.73
Units °C/W °C/W
1.25 24.3 1.37
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Chapter Integrated Circuit Data
Table PNX1520 Maximum Operating Speeds QVCP VLIW TM3260 (MHz) DDR-I (MHz) MMIO (MHz) 2DDE (MHz) (qvcp_out, qvcp_proc, Dual Edge) (MHz) (MHz) FGPO FGPI (MHz) DVDD (MHz) PCIXIO (MHz) (MHz) (MHz) SPDO (MHz) GPIO (MHz)
PNX9520 Device
Qualified accordance with AEC-Q100 grade
Table PNX9520 Operating Range Thermal Characteristics Symbol
Tambient
Description Global supply voltage Analog supply voltage (Input Analog filtering circuit) DDR-I supply voltage. DDR333 lower DDRs require 2.5V Input reference level voltage I/Os. CCM/2 Core supply voltage Operating ambient temperature range. junction case thermal resistance (same junction ambient thermal resistance (still air)
Minimum 3.13 3.13 2.37 1.15 1.23
Typical 3.30 3.30
Maximum 3.47 3.47 2.73
Units °C/W °C/W
1.25 24.3 1.37
Table PNX9520 Maximum Operating Speeds QVCP VLIW TM3260 (MHz) DDR-I (MHz) MMIO (MHz) 2DDE (MHz) (qvcp_out, qvcp_proc, Dual Edge) (MHz) (MHz) FGPO FGPI (MHz) DVDD (MHz) PCIXIO (MHz) (MHz) (MHz) SPDO (MHz) GPIO (MHz)
PNX9525 Device
Qualified accordance with AEC-Q100 grade
Table PNX9525 Operating Range Thermal Characteristics Symbol
Description Global supply voltage Analog supply voltage (Input Analog filtering circuit) DDR-I supply voltage. DDR333 lower DDRs require 2.5V Input reference level voltage I/Os. CCM/2 Core supply voltage
Minimum 3.13 3.13 2.37 1.15 1.23
Typical 3.30 3.30
Maximum 3.47 3.47 2.73
Units
1.25 1.37
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Product data sheet
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Chapter Integrated Circuit Data
Table PNX9525 Operating Range Thermal Characteristics Symbol
Description junction case thermal resistance (same junction ambient thermal resistance (still air)
Minimum
Typical 24.3
Maximum
Units °C/W °C/W
ambient Operating ambient temperature range.
Table PNX9525 Maximum Operating Speeds QVCP VLIW TM3260 (MHz) DDR-I (MHz) MMIO (MHz) 2DDE (MHz) (qvcp_out, qvcp_proc, Dual Edge) (MHz) (MHz) FGPO FGPI (MHz) DVDD (MHz) PCIXIO (MHz) (MHz) (MHz) SPDO (MHz) GPIO (MHz)
Power Considerations
Power Supply Sequencing
special power sequence required operate PNX15xx/952x Series. However, order guarantee that MM_CKE remains power PNX1500 required have power supply come-up before VCCM power supply. This JEDEC specification requirement. Remark: SDRAM devices power supply sequence must also met. Refer SDRAM vendor specification.
Leakage current Power Consumption
Leakage current variable advanced CMOS processes. maximum current leakages are:
(case temperature) VCCM (case temperature) VCCP (case temperature)
resultant power dissipation most (includes different power supplies).
Standby Power Consumption
During standby (sleep) mode, clocks PNX1500 system turned off. small amount logic stays alive order wake-up system.
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Chapter Integrated Circuit Data
standby mode obtain specifically turning different clocks, i.e. just simple flip into register. Once clocks have been shutdown power dissipation most (includes leakage current) (case temperature).
Power Consumption
power consumption PNX15xx/952x Series dependent activity TM3260, number modules operating, frequencies which system running, core voltage, well loads board level each pin. these reasons difficult provide precise power consumption numbers. 5.4.1 Typical Power Consumption Typical Applications Three main techniques applied reduce `Out Box' power consumption PNX1500 system:
Turn unused modules. After reset, modules clocked with
clock (input crystal clock, XTAL_IN). Turning clocks unused modules significantly reduces power consumption.
PNX1500 system with adjusted clock speeds each active module.
This include dynamic tuning TM3260 speed.
Powerdown TM3260 every time (Operating System) reaches idle
task. Example: Table presents typical case (not optimized power consumption savings).
Table MPEG-2 Decoding with 720x480P Output PNX1502 PNX1502 1002 1.302 VCCM 0.270 VCCP 0.175 Total 1.747
Typical power consumption typical applications PNX15xx/952x Series expected ranges from 5.4.2 Expected Maximum Currents Table presents estimated maximum currents, i.e. modules operating full speed which what real application will Board design, i.e. decoupling regulators, should plan peak current. Peak currents possible cycles sustained current consumption. These peaks will averaged decoupling capacitors, regulators should also under-dimensioned.
Table Estimated PNX15xx/952x Series Maximum Peak current PNX15xx/952x Series Maximum, Peak, 1400 2000 VCCM VCCP
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Volume
PNX15xx/952x Series
Chapter Integrated Circuit Data
DC/AC Characteristics
characteristics listed following tables apply worst case operating condition defined Section page 1-49. voltages referenced digital ground). following characteristics includes effect process variation.
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Chapter Integrated Circuit Data
Input Clock Specification
Table Specification HC-49U 27.00000 Crystal Frequency Temperature range Typical Load Capacitance (CL) Series resonance resistor Shunt capacitance (CP) Drive level External capacitance (CX1, Figure Table Specification Oscillator Mode Frequency Temperature range Duty Cycle 27.00000 85°C 45-55% maximum assymetry 27.00000 fundamental 85°C max. max. max. max. each
Frequency accuracy (all included: temperature, aging, frequency 85°C)
Frequency accuracy (all included: temperature, aging, frequency 85°C) +/-50 Rising/Falling Times Minimum Input High Voltage, Maximum Input Voltage, Maximum 3ns, Minimum 0.8*VDD 0.2*VDD
VSSA_1.2
PNX1500
PNX1500
XTAL_IN
XTAL_OUT n.c. Clock
XTAL_IN
XTAL_OUT
Input Voltage VDD.
Figure
Application Diagram Crystal Oscillator
SSTL_2 type Circuit
Table SSTL_2 AC/DC Characteristics Symbol Parameter Output High Voltage Output Voltage Input High Voltage Input Voltage This overshoot/ undershoot protection specification Condition/Notes 0.9VCCM 0.1VCCM VCCM -0.3 Unit Notes
PNX15XX_PNX952X_SER_N_4
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Volume
PNX15xx/952x Series
Chapter Integrated Circuit Data
Table SSTL_2 AC/DC Characteristics Symbol VIH-DC VIL-DC VIH-AC VIL-AC RSSTL TSLEW Parameter Input High Voltage Input Voltage Input High Voltage Input Voltage Condition/Notes Logic Threshold Logic Threshold Used timing specification. Figure Used timing specification. Figure VREF 0.18 VREF 0.35 Unit Notes
VREF 0.18 VREF 0.35
Series Output Resistance High/Low level output state Slew rate, (VIH-AC VIL-AC)/dt Input capacitance
[24-1] [24-2] Notes:
V/ns
Refer Figure Figure
Measured into load terminated VCCM/2.
PNX1500
Output
rise/fall test point true length
Buffer
Figure
SSTL_2 Test Load Condition
VIH-AC
VIH-DC
VREF
VIL-DC
VIL-AC
Figure
SSTL_2 Receiver Signal Conditions
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
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Semiconductors
Volume
PNX15xx/952x Series
Chapter Integrated Circuit Data
BPX2T14MCP Type Circuit
Table BPX2T14MCP Characteristics Symbol VIHT VILT Pull Parameter Output High Voltage Output Voltage Input High Voltage Input Voltage Input High Voltage Input Voltage Output Impedance Pull-up/down Resistor Input capacitance Logic Threshold Logic Threshold This overshoot/ undershoot protection specification High/Low level output state applicable VCCP -0.3 Condition/Notes 0.9VCCP 0.1VCCP Unit
BPX2T14MCP I/Os require board level 27-33 series resistor reduce ringing.
PNX1500
Output
rise/fall test point true length
Buffer
Figure
BPX2T14MCP Test Load Condition
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
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Semiconductors
Volume
PNX15xx/952x Series
Chapter Integrated Circuit Data
BPTS1CHP BPTS1CP Type Circuit
Table BPTS1CHP BPTS1CP Characteristics Symbol VIHT VILT Pull Parameter Output High Voltage Output Voltage Input High Voltage Input Voltage Input High Voltage Input Voltage Output Impedance Output Rise/Fall Time Pull-up/down Resistor Input capacitance Logic Threshold Logic Threshold This overshoot/ undershoot protection specification High/Low level output state Test Load Figure applicable VCCP -0.3 Condition/Notes 0.9VCCP 0.1VCCP Unit
PNX1500
Output
rise/fall test point true length
Buffer
Figure
BPTS1CHP BPTS1CP Test Load Condition
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
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Semiconductors
Volume
PNX15xx/952x Series
Chapter Integrated Circuit Data
BPTS3CHP BPTS3CP Type Circuit
Table BPTS3CHP BPTS3CP Characteristics Symbol VIHT VILT Pull Parameter Output High Voltage Output Voltage Input High Voltage Input Voltage Input High Voltage Input Voltage Output Impedance Output Rise/Fall Time Pull-up/down Resistor Input capacitance Logic Threshold Logic Threshold This overshoot/ undershoot protection specification High/Low level output state Test Load Figure applicable VCCP -0.3 Condition/Notes 0.9VCCP 0.1VCCP Unit
PNX1500
Output
rise/fall test point true length
Buffer
Figure
BPTS3CHP BPTS3CP Test Load Condition
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
Rev. December 2007
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Semiconductors
Volume
PNX15xx/952x Series
Chapter Integrated Circuit Data
IPCHP IPCP Type Circuit
Table IPCHP IPCP Characteristics Symbol VIHT VILT Pull Parameter Input High Voltage Input Voltage Input High Voltage Input Voltage Pull-up/down Resistor Input capacitance Condition/Notes Logic Threshold Logic Threshold This overshoot/ undershoot protection specification applicable -0.3 Unit
BPT3MCHDT5V BPT3MCHT5V Type Circuit
Table BPT3MCHDT5V BPT3MCHT5V Characteristics Symbol VIHT VILT Pull Parameter Output High Voltage Output Voltage Input High Voltage Input Voltage Input High Voltage Input Voltage Output Impedance Output Rise/Fall Time Pull-up/down Resistor Input capacitance Logic Threshold Logic Threshold This overshoot/ undershoot protection specification High/Low level output state Test Load Figure applicable -0.3 Condition/Notes 0.9VCCP 0.1VCCP Unit
PNX1500
Output
rise/fall test point true length
Buffer
Figure
BPT3MCHDT5V BPT3MCHT5V Test Load Condition
PNX15XX_PNX952X_SER_N_4
B.V. 2007. rights reserved.
Product data sheet
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Volume
PNX15xx/952x Series
Chapter Integrated Circuit Data
IIC3M4SDAT5V IIC3M4SCLT5V type circuit
Table IIC3M4SDAT5V IIC3M4SCLT5V Characteristics Symbol VHYS Parameter Input High Voltage Input Voltage Input Schmitt trigger Hysteresis Output Voltage Output Fall Time Input capacitance Condition/Notes -0.5 0.25 Unit
PCIT5V type circuit
Table PCIT5V Characteristics Symbol VIH-5V VIL-5V VIH-3V Parameter Input High Voltage Input Voltage Input High Voltage Input Voltage Output High Voltage Output Voltage Output Fall Time Input capacitance Between VCCP VCCP Condition/Notes -0.5 -0.5 0.55 5.75 5.75 1.08 Unit
PNX1500
Output Buffer Vccp
Figure
Tval(min) Slew Rate Test Load Condition
Timing Specification
characteristics listed following tables apply worst case operating condition defined Section page 1-49. following characteristics includes effect process variation.
PNX15XX_PNX952X_SER_N_4
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PNX15xx/952x Series
Chapter Integrated Circuit Data
Reset
TLOWP POR_IN_N THOLD
RESET_IN_N TLOWR
Figure
Reset Timing
Table Reset Timing Symbol TLOWP THOLD TLOWR Parameter Reset active time after power clock stable Reset active after POR_IN_N pulled high Reset active time after power clock stable
[32-1] [32-2] [32-3] Notes: asserted de-asserted asynchronously with respect CLK. POR_IN_N RESET_IN_N asserted then RESET_IN_N must stay least long POR_IN_N asserted low.
Units
Notes
DRAM Interface
PNX1500 supports DDR200, DDR266, DDR400{A,B,C} devices defined JEDEC STANDARD JESD79C, March 2003. Refer Section 10.3 SDRAM interface more details.
Table DRAM Interface Timing Symbol Fddr Tddr Tpd-cmd Ts-dq Toh-dq Parameter MM_CLK MM_CLK_N frequency MM_CLK MM_CLK_N period MM_CLK MM_CLK_N skew Propagation delay command signals Setup time MM_DQ MM_DQM (when writing SDRAM) Output hold time MM_DQ MM_DQM (when writing SDRAM) 0.12 Tddr 0.12 Units Notes i.e. DDR400
Section 0.01 Tddr
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PNX15xx/952x Series
Chapter Integrated Circuit Data
Table DRAM Interface Timing Symbol Tiskew-dqs Tis-dq Tih-dq Parameter Maximum input skew supported (when reading from SDRAM) Input setup time MM_DQ (when reading from SDRAM) Input hold time MM_DQ (when reading from SDRAM)
[33-1] [33-2] [33-3] [33-4] [33-5] Notes: Command signals include MM_CKE_N[1:0], MM_CS[1:0]_N, MM_RAS_N, MM_CAS_N, MM_WE_N, MM_BA[1:0] MM_A[13:0] signals. Times measured w.r.t. positive edge MM_CLK crossing point MM_CLK MM_CLK_N. Refer Figure page 1-53 load conditions. Times measured w.r.t. corresponding edge MM_DQS[3:0], i.e. MM_DQS[0] device organized x32, respectively MM_DQ[31:24], MM_DQ[23:16], MM_DQ[15:8] MM_DQ[7:0] (when applicable) devices organized used. These timings allow maximum board level skew MM_CK. MM_CK_N, MM_DQS[3:0] MM_DQ[31:0] operating frequency (i.e. DDR400).
Units
Notes
[33-6]
Interface
Table Timing Symbol Tclock Tclock-low Tclock-high Tval-PCI (Bus) Tval-PCI (ptp) Ton-PCI TOff-PCI Tsu-PCI Tsu-PCI (ptp) Th-PCI Trst-off-PCI Parameter Clock cycle time Clock time Clock High time signal valid delay, signals signal valid delay, point-to-point signals Float active delay Active float delay Input setup time signals Input setup time point-to-point signals Input hold time from Reset active output float delay
[34-1] [34-2] [34-3] [34-4] [34-5] [34-6] Notes: timing measurement conditions Figure Minimum times measured package with load circuit shown Figure Maximum times measured with load circuits shown Figure PCI_REQ_N PCI_GNT_N point-to-point signals have different input setup times. other signals bused. timing measurement conditions Figure output drivers floated when PCI_RST (PCI reset signal card) (may connected RESET_IN_N and/or POR_IN_N) active.
Units
Notes 1,2,3 1,2,3
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Chapter Integrated Circuit Data
[34-7]
purpose Active/Float timing measurements, Hi-Z `off' state defined when total current delivered through component less than equal leakage current specification.
V_test T_fval
V_th V_tl
Output Delay T_rval Output Delay Tri-State Output
V_tfall
V_trise
T_on T_off
V_test T_su V_th V_test V_tl inputs valid
V_th V_tl
Input
V_test
V_max
Signaling Vmax
Signaling VCCP VCCP Vmax VCCP
Figure Output Input Timing Measurement Conditions
PNX1500
Output Buffer
PNX1500
Output
Buffer
Vccp
Figure Tval(max) Rising Falling Edge
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Product data sheet
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PNX15xx/952x Series
Chapter Integrated Circuit Data
QVCP, FGPO Interfaces
Table QVCP, FGPO Timing With Internal Clock Generation Symbol FQVCP FFGPO TCLK-DV Parameter VDO_CLK1 frequency VDO_CLK2 frequency Clock VDO_D[34:0] VDO_AUX PNX1502 Clock VDO_D[34:0] VDO_AUX PNX1501 Clock VDO_D[34:0] VDO_AUX PNX1500 Clock VDO_D[34:0] VDO_AUX PNX1500 TSU-CLK TH-CLK Input setup time Input hold time
[35-1] [35-2] [35-3] [35-4] [35-5] [35-6]
Units
Notes
Section
timing measurement conditions Figure Timing applies when data output positive negative edge double edge clock mode, Table page 3-114. VDO_CLK[1,2] inverted internally then timing applies negative edge. Timing applies VDO_D[29], FGPO_REC_SYNC FGPO_BUF_SYNC. VDO_D[29] FGPO_BUF_SYNC. This inputs assumed asynchronous. double edge clock mode, maximum VDO_CLK1 frequency lower than single edge clock mode. Refer Section differences between different devices. SAA7104H/5H input hold time specification data lines, PD[11:0], actually SAA7104H/5H input hold time specification xSVGC lines (SYNC signals) remains therefore traces board should compensate missing delay.
Table QVCP, FGPO Timing With External Clock Generation Symbol FQVCP FFGPO TCLK-DV TSU-CLK TH-CLK Parameter VDO_CLK1 frequency VDO_CLK2 frequency Clock VDO_D[34:0] VDO_AUX Input setup time Input hold time Units Notes
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Chapter Integrated Circuit Data
VDO_CLK TCLK-DV VDO_D[34:0] FGPO_REC_SYNC FGPO_BUF_SYNC valid
VDO_CLK TSU-CLK
VDO_D[29] FGPO_REC_SYNC FGPO_BUF_SYNC
TH-CLK valid
Figure QVCP FGPO Timing
[36-1] [36-2] [36-3] [36-4] [36-5] timing measurement conditions Figure Timing applies when data output positive negative edge double edge clock mode, Table page 3-114. VDO_CLK[1,2] inverted internally then timing applies negative edge. Timing applies VDO_D[29], FGPO_REC_SYNC FGPO_BUF_SYNC. VDO_D[29] FGPO_BUF_SYNC. These inputs assumed asynchronous. Maximum frequency reduced wide spread propagation delay depending application needs, i.e. input setup/hold time requirements receiving device.
FGPI Interfaces
Table FGPI Timing Symbol FVIP FFGPI TSU-CLK TH-CLK Parameter VDI_CLK1 frequency VDI_CLK2 frequency Input setup time Input hold time
[37-1] [37-2] [37-3] [37-4] Notes: Timing applies whether clock external internal. Timing applies whether data output positive negative edge. timing measurement conditions Figure
Units
Notes
VDI_CLK TSU-CLK
VDI_D[33:0] VDI_V[1:0]
TH-CLK valid
Figure FGPI Timing
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Chapter Integrated Circuit Data
10/100 Mode
Table 10/100 Timing Symbol FLAN_CLK FCLK TCLK-DV TSU-CLK TH-CLK Parameter LAN_CLK frequency LAN_TX_CLK LAN_RX_CLK frequency Clock Outputs Input setup time Input hold time
[38-1] [38-2] [38-3] [38-4] Notes: Timing applies whether clock external internal. Timing applies whether data output positive negative edge. timing measurement conditions Figure
Units
Notes
LAN_TX_CLK LAN_RX_CLK LAN_TXD[3:0] LAN_TX_EN LAN_TX_ER LAN_MDIO LAN_MDC TCLK-DV valid
LAN_RX_CLK LAN_TX_CLK
LAN_RXD[3:0] LAN_CRS/COL LAN_RX_DV LAN_RX_ER LAN_MDIO
TSU-CLK valid
TH-CLK
Figure 10/100 Timing Mode
10/100 RMII Mode
Table 10/100 RMII Timing Symbol FLAN_CLK FCLK TCLK-DV TSU-CLK TH-CLK Parameter LAN_CLK frequency LAN_TX_CLK LAN_RX_CLK frequency Clock Outputs Input setup time Input hold time
[39-1] [39-2] [39-3] Notes: Timing applies whether clock external internal. Timing applies whether data output positive negative edge.
Units
Notes
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Chapter Integrated Circuit Data
[39-4]
timing measurement conditions Figure
LAN_REF_CLK TCLK-DV LAN_TXD[1:0] LAN_TX_EN valid
LAN_REF_CLK TSU-CLK
LAN_RXD[1:0] LAN_CRS_DV LAN_RX_ER
TH-CLK valid
Figure 10/100 Timing RMII Mode
Audio Input Interface
Table Audio Input Timing Symbol FOSCLK FAI_CLK TCLK-DV TSU-CLK TH-CLK Parameter Audio Input oversampling frequency Audio Input frequency Clock AI_WS Input setup time Input hold time
[40-1] [40-2] [40-3] Notes: Timing applies whether clock external internal. Timing applies whether data output positive negative edge.
Units
Notes
PNX15XX_PNX952X_SER_N_4
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Chapter Integrated Circuit Data
timing measurement conditions Figure
AI_SCK TCLK-DV AI_WS valid
AI_SCK TSU-CLK
AI_SD[3:0] AI_WS
TH-CLK valid
Figure Audio Input Timing
Audio Output Interface
Table Audio Output Timing Symbol FOSCLK FAO_CLK TCLK-DV TSU-CLK TH-CLK Parameter Audio Output oversampling frequency Audio Output frequency Clock AO_WS AO_SD[3:0] Input setup time Input hold time
[41-1] [41-2] [41-3] Notes: Timing applies whether clock external internal. Timing applies whether data output positive negative edge.
Units
Notes
PNX15XX_PNX952X_SER_N_4
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Chapter Integrated Circuit Data
timing measurement conditions Figure
AO_SCK TCLK-DV
AO_SD[3:0] AO_WS
valid
AO_SCK TSU-CLK
AO_SD[3:0] AO_WS
TH-CLK valid
Figure Audio Output Timing
7.10 SPDIF Interface
Table SPDIF Timing Symbol THIGH TLOW TIHIGH TILOW Parameter Data/Clock Output High Time Data/Clock O
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