FB_D[0:31] FB_D[0:31] 1DIR 2DIR Bi-Buffers B_D[16:31] TOUT0 MC74L

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FB_D[0:31] FB_D[0:31] 1DIR 2DIR Bi-Buffers B_D[16:31] TOUT0 MC74L

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FB_D[0:31]
FB_D[0:31] 1DIR 2DIR Bi-Buffers B_D[16:31] TOUT0 MC74LCX16245DT Uni-Buffers +3.3 PP[0:7] INITIAL RESET CONFIGURATION: PRESET DIV0 PRESET DIV1 PRESET DIV2 BE[3:0] CONF ADDR_CONF BOOT PORT SIZE BOOT PORT SIZE ENABLE TOUT1 B_D16 B_D17 B_D18 B_D19 B_D20 B_D21 B_D22 B_D23 B_D24 B_D25 B_D26 B_D27 B_D28 B_D29 B_D30 B_D31 +3.3 FB_D16 FB_D17 FB_D18 FB_D19 FB_D20 FB_D21 FB_D22 FB_D23 FB_D24 FB_D25 FB_D26 FB_D27 FB_D28 FB_D29 FB_D30 FB_D31 +3.3 R/-W -CS_FPCIBD 1DIR 2DIR Bi-Buffers FB_D0 FB_D1 FB_D2 FB_D3 FB_D4 FB_D5 FB_D6 FB_D7 FB_D8 FB_D9 FB_D10 FB_D11 FB_D12 FB_D13 FB_D14 FB_D15 +3.3 A[0:31] Uni-Buffers 1DIR 2DIR MA10 MA11 MA12 MA13 MA14 MA15 +3.3 MA[0:20]
R/-W -CS_FPCIB
MC74LCX16245DT B_D[16:31]
MC74LCX16245DT
MC74LCX16245DT
Bi-Buffers Uni-Buffers +3.3 4.7K 1DIR 2DIR +3.3 MA16 MA17 MA18 MA19 MA20
D[0:31]
D[0:31]
1DIR 2DIR
R/-W -BD_CS3
DEFAULT SETTING JUMPERS SHOULD INSTALLED DURING ASSEMBLY. +3.3 4.7K 4.7K JP10
JUMPER DEFAULT SETTING INSTALLED DURING ASSEMBLY. TOUT0 TOUT1
MC74LCX16245DT
+3.3
Title Size Date:
SESG ColdFire Group
MCF5407 Evaluation Board
Document Number MCF5407.BUFFERS Sunday, June 2000 Sheet
MC74LCX16244DT -CF_RSTI
PSTDDATA[4:7] +3.3 4.7K 4.7K
+3.3
PSTDDATA4 PSTDDATA5 PSTDDATA6 PSTDDATA7
DEFAULT SETTING JUMPERS 11&12 SHOULD INSTALLED.
+3.3 JP11 3.3V
+3VP PP[0:7] D[0:31] D[0:31] DREQ1 DREQ0 JP13 JP14 A[0:31]
PSTDDATA[4:7] PP[0:7]
A[0:31] +3.3
IVCC1 EVCC2 EVCC3 EVCC4 EVCC5 EVCC6 EVCC7 EVCC8 IVCC9 EVCC10 IVCC11 EVCC12 EVCC13 EVCC14 IVCC15 EVCC16 EVCC17 EVCC18 EVCC19 EVCC20 IVCC21 IVCC22 EVCC23 IVCC24 IVCC25
IVCC27 EVCC28 IVCC29 EVCC30
PSTDDATA4 PSTDDATA5 PSTDDATA6 PSTDDATA7
TT0/PP0 TT1/PP1 TM0/PP2 TM1/PP3 TM2/PP4 DREQ1/PP5 DREQ0/PP6 XTIP/PP7
-IRQ1 -IRQ3 -IRQ5 -IRQ7 R/-W -CF_RSTI -BWE0 -BWE1 -BWE2 -BWE3
RP13 RP14
IRQ1 IRQ3 IRQ5 IRQ7 RSTI BWE0 BWE1 BWE2 BWE3 SIZ0 SIZ1
SIZ0 SIZ1 -R_RAS0/SO0 -R_RAS1/SO2 -R_CAS0/DQM0 -R_CAS1/DQM1 -R_CAS2/DQM2 -R_CAS3/DQM3 -R_DRAMW -R_SRAS DSCLK_TRST DSDO_TDO DSDI_TDI -BKPT_TMS -HIZ BCLKO -RSTO CLKIN PSTCLK EDGESEL PU_MTMOD0
MCF5407FT150
RAS0/SO0 RAS1/SO2 CAS0/DQM0 CAS1/DQM1 CAS2/DQM2 CAS3/DQM3 DRAMW SRAS SCAS SCKE DSCLK/TRST DSO/TDO DSI/TDI BKPT/TMS BCLKO RSTO CLKIN PSTCLK EDGESEL
ColdFire®
A24/PP8 A25/PP9 A26/PP10 A27/PP11 A28/PP12 A29/PP13 A30/PP14 A31/PP15
DEFAULT SETTING JUMPERS 13&14 SHOULD RP10 INSTALLED. 4.7K
+3.3 +3.3 RP12 4.7K RP11
4.7K
-CS7 -CS6 -CS5 -CS4 -CS3 -CS2 -CS1 -CS0 +3.3 +3.3
-CS7 -CS6 -CS5 -CS4 -CS3 -CS2 -CS1 -CS0 TIN1 TIN0 TOUT1 TOUT0 PSTDDATA0 PSTDDATA1 PSTDDATA2 PSTDDATA3
MTMOD0 MTMOD1 MTMOD2 MTMOD3
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31
TXD0 RXD0 RTS0 CTS0
TXD1 RXD1 RTS1 CTS1
PSTDDATA[0:3] SCKE -SCAS +3.3 RP16 RP17 4.7K +3.3 RP18 4.7K -CS3 +3.3 RP34 4.7K 220pF +3VP IVCC TANT. +3.3 NOTE: 1206 size changed 220uH inductor same package. IVCC RP15 MTMOD3 MTMOD2 MTMOD1 MTMOD0 PSTDDATA3 PSTDDATA2 PSTDDATA1 PSTDDATA0 TOUT0 TOUT1 TIN0 TIN1 -CST1 -RTS1 RXD1 TXD1 -CST0 -RTS0 RXD0 TXD0 TOUT0 TOUT1 TIN0 TIN1 -CTS1 -RTS1 RXD1 TXD1 -CTS0 -RTS0 RXD0 TXD0
4.7K
4.7K PD_MTMOD0
10nF 10nF 10nF 10nF 10nF 220pF 220pF 220pF 220pF 220pF
Title Size
SESG ColdFire Group
MCF5407 Evaluation Board
Document Number MCF5407 Sunday, June 2000 Sheet
ring supply decoupling.
Core supply decoupling. Date:
B_D[16:31] B_D[16:31] B_D16 B_D17 B_D18 B_D19 B_D20 B_D21 B_D22 B_D23 B_D24 B_D25 B_D26 B_D27 B_D28 B_D29 B_D30 B_D31 BALE ECLK RP20 4.7K -IOW -IOR ETH_RESET
Ethernet Base-T SD10 SD11 SD12 SD13 SD14 SD15 SA10 SA11 SA14 SA15 SA16 SA17 SA18 SA19 BALE SYSCLK IOR* IOW* SMEMR* AEN* MEMW* MEMR* AVDD1 AVDD2 AVDD3 AGND1 AGND2 AGND3 GND1 GND2 GND3 GND4 DM9008F TPTX+ TPTXTPRX+ TPRXLILED VCC1 VCC2 VCC3 GND0 RXI+ AGND2 RXIFD22-101G TPRX+ TPRX11 BNCEN TXRX+ RXCD+ CD78 Ethernet Filter TDX+ AGND1 TXDTPTX+ TPTX16 MSD7 MSD6_SLOT MSD5_BNCSW MSD4 MSD3 MSD2_EECK MSD1_EED0 MSD0_EED1 EECS BPCS* IRQ3 IRQ4 IRQ5 IRQ9 IRQ10 IRQ11 IRQ12 IRQ15 IO16* IOCHRDY* Ethernet
RP19
4.7K
RP26
MA[0:20]
AT93C46-10SC-2.7-8S1 populated during assembly
4.7K -ETH_IRQ3
Ethernet Osc. -IO16 -IOCHRDY
FERRITE_BEA
10nF
TANT.
10nF
RJ45 Thur Hole
GREEN Title
Size Date:
SESG ColdFire Group
MCF5407 Evaluation Board
Document Number MCF5407 ETHERNET Sunday, June 2000 Sheet
D[0:31]
D[0:31] +3.3 IVCC +3.3 IVCC +3.3 IVCC +3.3
PP[0:7]
PP[0:7]
-HIZ -BKPT_TMS DSDI_TDI DSDO_TDO DSCLK_TRST
-CS2 -CS3 -CS4 -CS5 -CS6 -CS7 R/-W -CF_RSTI -IRQ7 -IRQ5 -IRQ3 -IRQ1 TOUT1 TOUT0 TIN0 TIN1 -R_RAS0/SO0 -R_RAS1/SO2 -R_CAS0/DQM0 -R_CAS1/DQM1 -R_CAS2/DQM2 -R_CAS3/DQM3 -R_DRAMW -R_SRAS -R_SCAS R_SCKE -BWE0 -BWE1 -BWE2 -BWE3 SPP0 PSTDDATA7 PSTDDATA6 PSTDDATA5 PSTDDATA4 PSTDDATA3 PSTDDATA2 PSTDDATA1 PSTDDATA0 PSTCLK MTMOD3 MTMOD2
PSTDDATA[4:7]
PSTDDATA[0:3]
MTMOD1 MTMOD0 CLKIN -RSTO BCLKO EDGESEL TXD0 RXD0 -RTS0 -CTS0 TXD1 RXD1 -RTS1 -CTS1 -CS_FPCIB2
SIZ0 SIZ1 -CS0 -CS1
-A31
177983-5 120way Receptacle
177983-5 120way Receptacle
+3.3
A[0:31]
A[0:31]
+3.3
+3.3
Title Size Date:
SESG ColdFire Group
MCF5407 Evaluation Board Document Number Expansion Connectors Sunday, June 2000 Sheet
FB_D[0:31] MA[0:20]
FB_D[0:31] MA20 16-BIT WIDE FLASH MA10 MA11 MA12 MA13 MA14 MA15 MA16 MA17 FB_D31 FB_D23 FB_D30 FB_D22 FB_D29 FB_D21 FB_D28 FB_D20 +3.3 +3.3 Am29PL160C-70 RP21 4.7K BCLK_SRAM -BWE2 -BWE0 -BWE1 -BWE3 4.7K
MA[0:20]
FB_D[0:31]
FB_D[0:31]
R/-W
JP15 MA19 MA18 BYTE# DQ15/A-1 DQ14 DQ13 DQ10 DQ12 DQ11
FSRAM 16MBit Flash Boot DEFAULT SETTING JUMPER SHOULD INSTALLED ACROSS PINS 1&2. MA10 MA11 MA12 MA13 MA14 MA15 MA16 MA17 MA18 +3.3 RP22 4.7K -CS2 SA10 SA11 SA12 SA13 SA14 SA15 SA16 ADSP* ADV* ADSC SGW* SBD* SBC* SBB* SBA* LBO* SE1* SE2* SE3* GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 QD35 QD34 QD33 QD32 QD31 QD30 QD29 QD28 QD27 QC26 QC25 QC24 QC23 QC22 QC21 QC20 QC19 QC18 QB17 QB16 QB15 QB14 QB13 QB12 QB11 QB10 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 FB_D15 FB_D14 FB_D13 FB_D12 FB_D11 FB_D10 FB_D9 FB_D8 FB_D31 FB_D30 FB_D29 FB_D28 FB_D27 FB_D26 FB_D25 FB_D24 FB_D23 FB_D22 FB_D21 FB_D20 FB_D19 FB_D18 FB_D17 FB_D16 FB_D7 FB_D6 FB_D5 FB_D4 FB_D3 FB_D2 FB_D1 FB_D0
-CS0 FB_D16 FB_D24 FB_D17 FB_D25 FB_D18 FB_D26 FB_D19 FB_D27
+3.3
PU_CSPCI PU_RDPCI
+3.3
MCM69F737TQ11 populated assembly
+3.3
Title Size Date:
SESG ColdFire Group
MCF5407 Evaluation Board
Document Number MCF5407 FLASH Sunday, June 2000 Sheet
+3.3
RP36
+3.3
RP35 +3.3 4.7K DEFAULT SETTING JUMPERS SHOULD INSTALLED. JP25 JP29 +3.3
-IRQ1 -CF_RSTI
4.7K
4.7K
configued max. 7.5W power.
GNT# REQ#
-IRQ5 -REQ -GNT
AD24 AD25 AD26 AD27 AD28
+3.3 +3.3
AD29 AD30 AD31
NOTE: regulated +/-12V only available when connector fitted, please common ground supply.
+3.3 Universal 32-bit Connector TRST# +12V INTA# INTC# RESERVED +Vi/o RESERVED RESERVED RST# +Vi/o GNT# RESERVED AD30 +3.3V AD28 AD26 AD24 IDSEL +3.3V AD22 AD20 AD18 AD16 +3.3V FRAME# TRDY# STOP# +3.3V SDONE SBO# AD15 +3.3V AD13 AD11 C/BE0# +3.3V +Vi/o REQ64#
AD[0:31] MA[0:20] WRITE PROTECT +3.3 DEFAULT SETTING JP16 JUMPER SHOULD INSTALLED ACROSS PINS 1&2.
VDDP3 AD[24] AD[25] AD[26] AD[27] AD[28] VDDP2 VSSP2 AD[29] AD[30] AD[31] VDDP1 VSSP1 INTA TEST_MODE SELECT VSS3 RSTOUT RSTOUTD RSTOUTD VDD2 VSS2 IRQ_OUT IRQ_IN VSS1 ADR[2] ADR[3] ADR[4] ADR[5] ADR[6] ADR[7] ADR[8] VDD1
-12V INTB# INTD# PRSNT1# RESERVED PRSNT2# RESERVED REQ# +Vi/o AD31 AD29 AD27 AD25 +3.3V C/BE3# AD23 AD21 AD19 +3.3V AD17 C/BE2# IRDY# +3.3V DEVSEL# LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 AD12 AD10 +3.3V +Vi/o ACK64#
+3.3 MA10 MA11 MA12 MA13 MA14
AD31 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD30 AD28 AD26 AD24 AD30 AD22 AD20 AD18 AD16 AD15 AD14 AD13 AD12 AD11 AD10
AD31 AD29 AD27 AD25 AD23 AD21 AD19 AD17
AD14 AD12 AD10
VDDP7 C/BE[0] AD[7] AD[6] AD[5] AD[4] VSSP8 VDDP8 AD[3] AD[2] AD[1] AD[0] VSS4 VDD3 DQ[0] DQ[1] DQ[2] DQ[3] DQ[4] DQ[5] DQ[6] VSS5 VDD4 DQ[7] DQ[8] DQ[9] DQ[10] DQ[11] DQ[12] DQ[13] VSS6 VDD5 DQ[14] DQ[15] DQ[16] DQ[17] DQ[18] DQ[19] DQ[20] VSS7
VSSP3 C/BE[3] IDSEL AD[23] AD[22] AD[21] AD[20] AD[19] VSSP4 VDDP4 AD[18] AD[17] AD[16] C/BE[2] FRAME IRDY TRDY VSSP5 VDDP5 DEVSEL STOP PERR SERR C/BE[1] AD[15] VSSP6 VDDP6 AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] AD[8] VSSP7
VSS12 ADR[9] ADR[10] ADR[11] ADR[12] ADR[13] ADR[14] STROBE BE[0] BE[1] BE[2] BE[3] VDD8 VSS11 CLKIN VSS10 PCLKOUT2 PCLKOUT1 PCLKOUT0 RDY_OUT RDY_IN RDY_IN WRITE READ BLAST VSS9 DQ[31] DQ[30] DQ[29] VDD7 VSS8 DQ[28] DQ[27] DQ[26] DQ[25] DQ[24] DQ[23] DQ[22] DQ[21] VDD6
X24C04S8 -1.8
SIZ0 SIZ1 BCLK_PCI +3.3
RP33 FB_D31 FB_D30 FB_D29 FB_D28 FB_D27 FB_D26 FB_D25 FB_D24 FB_D23 FB_D22 FB_D21
4.7K
R/-W PU_RDPCI
PU_CSPCI -A31 DEFAULT SETTING JUMPER SHOULD INSTALLED ACROSS PINS 1&2. -CS1
JP30 STROBE
JP27
AD15 AD13 AD11
Anchor AN3042Q
FB_D7 FB_D8 FB_D9 FB_D10 FB_D11 FB_D12 FB_D13
FB_D14 FB_D15 FB_D16 FB_D17 FB_D18 FB_D19 FB_D20
10nF
AD[0:31]
FB_D0 FB_D1 FB_D2 FB_D3 FB_D4 FB_D5 FB_D6
DEFAULT SETTING JUMPER SHOULD INSTALLED ACROSS PINS 1&2. FB_D[0:31]
NOTE Ensure clock trace controller inches longer than clock trace connector. RP23 +3.3 XTAL_OUT XTAL_IN Enable2 Enable1 GND1 BCLK5 BCLK0 VDD3 VDD1 BCLK4 BCLK1 GND3 GND2 BCLK3 BCLK2 VDD2 MPC905D +3.3 +3.3
+3.3 +3.3
RP37
AD[0:31]
4.7K RP38
Title Size Date:
SESG ColdFire Group
MCF5407 Evaluation Board Document Number MCF5407 Interface Sunday, June 2000
4.7K
Sheet
+1.8
+3.3 Ethernet -IOW R/-W ECLK BALE -CS1 -CS2 -CS3 -CS_FPCIBD GNT# -ETH_IRQ3 -IRQ3 ETH_RESET REQ# -HIZ I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 TDO*/IN1 TDI*/IN ispEN*/NC TMS*/NC TCK*/Y2 RESET*/Y1 GOE0 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 VCC0 VCC1 SIZ1 -IO16 -CS0 -IOCHRDY -BD_CS3 -CF_RSTI -GNT -BDM_RSTI SIZ0 -A31 -REQ MA16 -IOR +3.3
+3.3
Vcc5 RSTIN Vcc3
MAX6355LSUT-T
HARD_RESET
KS11R23CQD RESET BCLK_FPL
GND0 GND1
ispLSI2032V-100LJ socket +3.3 RP24 PU_IP3 +3.3 KS11R22CQD TLC7733ID RESIN SENSE RESET RESET CONTROL 10nF Title -IRQ7 MODE SCLK RP25 4.7K +3.3 +3.3 4x4.7K
Debounced IRQ7 Signal
Size Date:
SESG ColdFire Group
MCF5407 Evaluation Board
Document Number MCF5407 Sunday, June 2000 Sheet
JUMPER SHOULD INSTALLED ACROSS PINS DURING ASSEMBLY +3.3 JP17 +1.8
JUMPER INSTALLED ACROSS PINS DEFAULT POWER, PINS RESERVED ALTERNATE POWER. +3.3 JP26 PU_IP3 Header -BKPT_TMS DSCLK_TRST DSDI_TDI DSDO_TDO +1.8
IMPORTANT NOTE: ONLY 3.3V debugging cable used with MCF5407 processor.
resistors 0805 body size except which 1206.
caps less than 0805 body size.
+3.3
+3.3
-BDM_RSTI PSTDDATA6 PSTDDATA4 PSTDDATA2 PSTDDATA0
Socketed Osc. +3.3 CLOCK CLKIN JUMPER SHOULD INSTALLED ACROSS PINS 5407 PINS ALTERNATE WITH JP19 FITTED. BCLKDRV_IP PSTDDATA[0:7] BCLKDRV_IP
PSTDDATA7 PSTDDATA5 PSTDDATA3 PSTDDATA1
JP18
PSTCLK
DEBUGGER PORT 100mil header 2x13pin
1.8V Regulator JP12 SHOULD INSTALLED DURING ASSEMBLY. JP12 LT1086CM VOUT +1.8
JP19 BCLKO
+3.3
JUMPER SHOULD ONLY FITTED ALTERNATE CLOCKING CONJUNCTION WITH JP18. +3.3 +3.3 JUMPER SHOULD INSTALLED ACROSS PINS DEFAULT OPERATION PINS RESERVED. JP20
NOTE: Diodes prevent excessive difference between 3.3V 1.8V rails, power MRA4003T3 MRA4003T3 MBRS340T3 +1.8 +3.3
NOTE: Schottky Diode prevents excessive difference between 3.3V 1.8V rails, power down. MBRS340T3 +1.8
TANT.
100uF TANT.
VCC_CORE
~ON/OFF
+1.8 Clock Driver BCLKDRV_IP +3.3 VCC1 VCC2 VCC3 VCC4 GND1 GND2 GND3 GND4 GND5 GND6 RP29
NOTE: Mating connector AMP1-480303-0. Regulated +/-12V needs supplied using common ground PSU. AMP350210-1
LM2596S-3.3 3.3V Regulator 220uF VOUT 25uH MBRS340T3 330uF +3.3
BCLK_SRAM BCLK_PCI BCLK_FPLA BCLK_SDRAM0 BCLK_SDRAM1 BCLK_SDRAM2 BCLK_SDRAM3 CLKIN EDGESEL BCLK_SDRAM[0:3]
Power Jack Connector 2.1mm dia. Switchcraft RAPC712 LM2596S-5 2-way Bare Wire Power Connector Augat 25V-02 0.1uF MBRS340T3 C100 1000uF Fast blow. ~ON/OFF VOUT 5.0V Regulator
25uH MBRS340T3 C101 220uF C103
RP28 RP32
CDC351DB -SCAS SCKE
RP27
Title -R_SCAS R_SCKE Size Date:
SESG ColdFire Group
MCF5407 Evaluation Board
Document Number MCF5407 POWER Sunday, June 2000 Sheet
PP[0:7]
DEFAULT SETTING JUMPERS 21,22,23 SHOULD INSTALLED ACROSS PINS 1&2. SDRAM JP21 I/CLK TCLK MODE I/O/Q0 I/O/Q1 I/O/Q2 I/O/Q3 I/O/Q4 I/O/Q5 I/O/Q6 I/O/Q7 I/O/Q8 I/O/Q9
MA[0:20] MA15 MA14 MA13 MA12 MA11 MA10 MA17 +3.3
A10_AP CKE0 CKE1 CAS* RAS* DQM7 DQM6 DQM5 DQM4 DQM3 DQM2 DQM1 DQM0 SO2* SO0* SO1* SO3* VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18
SDRAM VREF1 VREF2
D[0:31]
D[0:31]
JP22 A[0:31]
SCLK MODE
R_SCKE +3.3 -R_CAS0/DQM0 -R_CAS1/DQM1 -R_CAS2/DQM2 -R_CAS3/DQM3 -R_SCAS -R_SRAS -R_DRAMW
JP23
ispGAL22LV10 socket
JP24 RP31 4.7K +3.3 RP30 4.7K +3.3
-R_RAS1/SO2 -R_RAS0/SO0
+3.3
C104
C105
C106
C107
C108
+3.3
C109
C110
C111
C112
C113
C114
C115
C116
C118
C119
C120
CLK0 BCLK_SDRAM0 BCLK_SDRAM1 CLK1 BCLK_SDRAM2 CLK2 BCLK_SDRAM3 CLK3 NC10 NC11 NC13 NC12 PC100 Unbuffered Bank DIMM 16M, support 512M
BCLK_SDRAM[0:3]
Title Size Date:
SESG ColdFire Group
MCF5407 Evaluation Board
Document Number MCF5407 SDRAM Sunday, June 2000 Sheet
TRANSFER START R/-W RS232 Driver PU_MTMOD0 DEFAULT SETTING JP28 SHOULD PINS NORMAL/BDM MODE PINS NORMAL/JTAG MODE. JP28 MTMOD0 BDM/JTAG 3WAY JUMPER C122 TANT. TXD0 RXD0 -RTS0 -CTS0 C2VCC C1VSS C121 TANT. TERMINAL PORT C123 TANT. -CS0 CHIP SELECT -CS1 CHIP SELECT READ WRITE
MC145407DW
PD_MTMOD0 C124 TANT. RS232 Driver TXD1 RXD1 -RTS1 -CTS1 C125 AUXILARY PORT CLKIN MCF5407 CLOCK ADDRESS STROBE BCLKO CLOCK
NOTE: netlist names label each test points silkscreen.
TRANSFER ACKNOWLEDGE
MC145406DW
REAL-TIME CLOCK.
32.768KHz VBAT OSCI OSCO VBAT FT/OUT +3.3
NOTE: I2C/Mbus MCF5407 will ONLY support 3.3V devices.
NOTE: Place TP10 opposite diagonal corners PCB, attach 'scope ground leads.
POPULATED ASSEMBLY.
TP10
M41T11M
VBAT
Molex Conn. 71565 Title
Size Date:
SESG ColdFire Group
MCF5407 Evaluation Board. Document Number Serial Interfaces, Real-Time Clock Test points. Sunday, June 2000 Sheet
POPULATED ASSEMBLY.
M5407C3 Schematic Executive Summary Notes
Executive Summary M5407C3 Evaluation Board Schematics: Page level schematic indicates major blocks associated interconnects evaluation board. Each major block/function corresponding schematic page that goes into detail design. This level schematic quickly indicates engineer particular functional instantiation M5407C3 ColdFire reference design.
Page 1/11
buffer page type buffers that used this design: Bi-directional Unidirectional. buffers help electrically isolate processor from peripherals also extra drive signals designers wishing increase loading DATA ADDRESS buses expansion header. bi-directional buffers receive their inputs from ColdFire microprocessor output DATA signals system peripherals. direction buffers controlled ColdFire R/~W signals appropriate (chip select) signal. signal come directly from ColdFire microprocessor case buffer) from (page where used with buffers, flash DATA. uni-directional buffers also receive their inputs from ColdFire microprocessor output ADDRESS signals system peripherals. buffers always driving ADDRESS from ColdFire. unique buffer system. used configure ColdFire microprocessor power and/or system reset provide drive capability eight LED's system that controlled ColdFire GPIO parallel port lines. drive control reset buffer ubiquitous ~CF_RSTI (ColdFire reset) signal. This signal generated from which decodes several signals produce ~CF_RSTI signal. Please refer equations additional details. general ~CF_RSTI signal will deassert until either power supply system stabilized push button reset been pushed. MCF5407 DATA D[7:0] either notify processor correct reset configuration when ~CF_RSTI signal negates. NOTE extremely important designers have correct configuration. Incorrect frequency will quickly prevent system from operating properly incorrectly allocating auto terminated global chip select. parallel port signals ColdFire multiplexed with other functions configured reset default parallel port input signals. This prevents correct signal levels parallel port pins being connected other peripherals system. defaulting inputs, this risk eliminated. Note that registers Parallel port control registers (PADDR PADAT) must programmed desired values assert correct values. JP1&2 jumper blocks determine whether timer output signals drive LED's.
Page 2/11
ColdFire microprocessor dominates this schematic. Pull-up pull-down resistors used configure processor normal system operation with (Background Debug Mode) function well. These resistors serve ensure that signals that cause system respond external stimuli only happen when required (i.e. pull-ups IRQ's, CS's, control signals paramount.). Note that there specific filter design ColdFire's processor internal oscillate correctly MHz.
D:\SPS2000\Schematic_overview September 18th, 2000 HESD, Motorola Page
M5407C3 Schematic Executive Summary Notes
Jumper JP11&12 could used power consumption analysis general should left their default configurations fitted.
Page 3/11
ethernet page very straight forward page must understood provides ColdFire translation logic. works don't mess with attitude this same design leveraged from M5307C3 evaluation board. beauty ColdFire evaluation boards that don't change every parameter equation each board. leverage what worked past that tool future. this section replicates ethernet circuitry M5307C3 evaluation board which already proved successful. Please remember that design these boards with cost performance considerations mind always highest performance peripherals.
Page 4/11
expansion header page brings every MCF5407 signal allow expansion daughter card. Motorola will provide daughter card reference design customers. design will plug daughter card into expansion headers (J1&J2) signals Mictor connectors allow quick interface connection Tektronix series Logic Analyzers.
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This consisys 16-bit wide flash chip Motorola FSRAM (not populated cost constraints). Please note Motorola FSRAM longer recommended designs that several other vendors offer same function foot print: Samsung K7B403625M, Cypress CY7C1345, 71V3577 Micron MT58L128L36F1. 16-bit flash device buffered ADDRESS DATA buses connected Global chip select (CS0) used control accesses flash. power system reset global chip select active external accesses made ColdFire processor. until CSMR0 register programmed global chip select disabled. have seen customers initialize DRAM deactivate global chip select thereby causing little contention!!!! Also note that since flash 16-bits wide, starting address signal from MCF5407 processor that address signal required/needed/used. FSRAM populated used benchmarking, time critical code, additional memory space.
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WOW. page complicated even people that know what going This first experience working with PCI. functionality added M5407C3 board allows designer plug slave peripheral device. default arbitration that controller master ColdFire processor master controller. controller being master means that evaluation board must supply clock interrupt arbitration proper functionality. example peripheral usage will posted ColdFire site (http://www/mot.com/ColdFire). This example plugs serial card into slave slot. ColdFire Monitor (dBUG) will function through that interface rather than internal UART. Very important this interface EEPROM that provides initial configuration controller. this properly programmed, interface will function.
D:\SPS2000\Schematic_overview September 18th, 2000 HESD, Motorola Page
M5407C3 Schematic Executive Summary Notes
Without OSC, interface will function, must supply clock master. proper pull-ups pull-downs implemented interface will work. There many parameters which have carefully order have interface work properly. Sounds like experience with this!
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main component this page PLD; U18. This implements ethernet interface Davicom ethernet chip. generates proper ethernet clocking reset ethernet controller, controls reset logic from push button, DEBUG port, voltage sense logic. voltage sense system. power drop below determined minimum, system will placed into reset minimize chance corruption/contention. provides debouncing IRQ7 (non-maskable interrupt) signal ColdFire processor.
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Loads stuff this page that includes clock buffer (U24), system (U21), header (J5), power protection, connectors regulators, connection provide +/12VDC connector should slave device require system MHz. ColdFire microprocessor designed handle system limited maximum frequency controller limited operation. NOTE that socketed allow other frequencies implemented care must ensure that proper reset configuration used filter. clocking M5407C3 differs from M5307C3 that buffered fanned from buffer BCLKO used system. M5307C3 used supplying processor directly then buffered BCLKO feed system clocking requirements. Also note that input clocking MCF5407 frequency used system internal core frequency integral multiple that. MCF5307's processor input frequency does have system frequency. input frequency MCF5307 multiplied generate internal processor frequency frequency integral division from that confusing does generate some technical support questions keep busy! diodes. Great inventions that will guarantee that ColdFire core voltages power down properly. don't want power down with only supply voltage. diodes ensure that core ring voltages power up/down simultaneously therefore never exceed maximum differential. without other (leads reduced life expectancy!). clock driver used clean strengthen clock (gives sharp edges larger current capability) fans ColdFire processor system peripherals. power connectors just give user choice ways power board. barrel connector available, then plug power supply bare wires. Please ALWAYS verify polarity before applying power. typical question powered board incorrectly DRAM started smoking. think have problem???". reply, sticking DRAM what happens". Power regulators take excess voltage regulate system 1.8V required proper system operation. Don't forget have plenty by-pass caps scattered through design. fast blow fuse nice touch too.
D:\SPS2000\Schematic_overview September 18th, 2000 HESD, Motorola Page
M5407C3 Schematic Executive Summary Notes
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SDRAM DIMM understated piece design. NOTE that PC100 DIMM used allow standard SDRAM's used embedded design. Usually based hardware cheaper (than embedded hardware), more available convenient. flexibility SDRAM controller allows 64-bit SDRAM DIMM work 32-bit environment M5407C3 evaluation board. SDRAM controller sets registers which allow physical banks SDRAM used system. Taking advantage this feature allows ~_R_RAS[0:1] signals control 64-bit single bank SDRAM's 32-bit SDRAM banks! ADDRESS multiplexer (U27) implemented dynamically configure address signal properly according SDRAM DIMM eeprom setting that read using ColdFire (aka M-bus). chooses they manually configure using jumpers JP21-JP24. M5407C3UM goes into specifics this topic.
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board isn't board unless test points (TPs) Serial port drivers, real-time clock configure JTAG available board. TP's without much fanfare until have debug system. Bringing signals having place clip ground makes whole process that much more smoothly doesn't cost much process. serial port drivers necessity UARTs provide simple connection that common every dBUG Monitor uses internal UARTs access world. great base line tool you'll see. real-time clock useful those that want implement RTOS where software keeping track time important. JP28 reset configuration jumper that allows ColdFire processor boot normal operation mode with either feature enabled JTAG feature enabled. Most designers debugging their hardware then develop software. Occassionally used manufacturing stage program system flash. Others will JTAG system component verification during manufacturing. Both features very useful powerful ColdFire family.
D:\SPS2000\Schematic_overview September 18th, 2000 HESD, Motorola Page

FB_D[0:31] FB_D[0:31] 1DIR 2DIR Bi-Buffers B_D[16:31] TOUT0 MC74L

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