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LPC2420/2460 Rev. 02.01 August 2008 Flashless 16-bit/32-bit


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LPC2420/2460
Rev. 02.01 August 2008
Flashless 16-bit/32-bit micro; Ethernet, CAN, ISP/IAP, device/host/OTG, external memory interface
Preliminary data sheet
General description
Semiconductors designed LPC2420/2460 microcontroller around 16-bit/32-bit ARM7TDMI-S core with real-time debug interfaces that include both JTAG embedded trace. LPC2420/2460 flashless. LPC2420/2460 execute both 32-bit 16-bit Thumb instructions. Support instruction sets means engineers choose optimize their application either performance code size sub-routine level. When core executes instructions Thumb state reduce code size more than with only small loss performance while executing instructions state maximizes core performance. LPC2420/2460 microcontroller ideal multi-purpose communication applications. incorporates 10/100 Ethernet Media Access Controller (MAC) (LPC2460 only), full-speed Device/Host/OTG Controller with endpoint RAM, four UARTs, Controller Area Network (CAN) channels (LPC2460 only), interface, Synchronous Serial Ports (SSP), three interfaces, interface. Supporting this collection serial communications interfaces following feature components; on-chip internal precision oscillator, 82/98 total consisting local SRAM, SRAM Ethernet (LPC2460 only), SRAM general purpose DMA, battery powered SRAM, External Memory Controller (EMC). These features make this device optimally suited communication gateways protocol converters. Complementing many serial communication controllers, versatile clocking capabilities, memory features various 32-bit timers, improved 10-bit ADC, 10-bit DAC, units, four external interrupt pins, fast GPIO lines. LPC2420/2460 connects GPIO pins hardware based Vector Interrupt Controller (VIC) that means these external inputs generate edge-triggered interrupts. these features make LPC2420/2460 particularly suitable industrial control medical systems.
Features
ARM7TDMI-S processor, running MHz. 82/98 on-chip SRAM includes: SRAM local high performance access. SRAM Ethernet interface. also used general purpose SRAM. (LPC2460 only) SRAM general purpose also accessible USB. SRAM data storage powered from Real-Time Clock (RTC) power domain. Dual Advanced High-performance (AHB) system allows simultaneous Ethernet DMA, with contention (LPC2460 only).
Semiconductors
LPC2420/2460
Fast communication chip
provides support asynchronous static memory devices such RAM, flash, well dynamic memories such Single Data Rate SDRAM. Advanced Vectored Interrupt Controller (VIC), supporting vectored interrupts. General Purpose controller (GPDMA) that used with SSP, I2S, SD/MMC interface well memory-to-memory transfers. Serial Interfaces: Ethernet with MII/RMII interface associated controller (LPC2460 only). These functions reside independent AHB. full-speed dual port Device/Host/OTG Controller with on-chip associated controller. Four UARTs with fractional baud rate generation, with modem control I/O, with IrDA support, with FIFO. controller with channels (LPC2460 only). controller. controllers, with FIFO multi-protocol capabilities. alternate port, sharing interrupt. SSPs used with GPDMA controller. Three I2C-bus interfaces (one with open-drain with standard port pins). (Inter-IC Sound) interface digital audio input output. used with GPDMA. Other peripherals: SD/MMC memory card interface. General purpose pins with configurable pull-up/down resistors. 10-bit with input multiplexing among pins. 10-bit DAC. Four general purpose timers/counters with capture inputs compare outputs. Each timer block external count input. PWM/timer blocks with support three-phase motor control. Each external count inputs. with separate power domain, clock source oscillator clock. SRAM powered from power pin, allowing data stored when rest chip powered off. WatchDog Timer (WDT). clocked from internal oscillator, oscillator, clock. Standard test/debug interface compatibility with existing tools. Emulation trace module supports real-time trace. Single power supply (3.0 Three reduced power modes: idle, sleep, power-down. Four external interrupt inputs configurable edge/level sensitive. pins port port used edge sensitive interrupt sources. Processor wake-up from Power-down mode interrupt able operate during Power-down mode (includes external interrupts, interrupt, activity, port interrupt, Ethernet wake-up interrupt (LPC2460 only), activity (LPC2460 only)). independent power domains allow fine tuning power consumption based needed features.
LPC2420_2460_2 B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Each peripheral clock divider further power saving. These dividers help reducing active power Brownout detect with separate thresholds interrupt forced reset. On-chip power-on reset. On-chip crystal oscillator with operating range MHz. internal oscillator trimmed accuracy that optionally used system clock. When used clock, does allow run. On-chip allows operation maximum rate without need high frequency crystal. from main oscillator, internal oscillator, oscillator. Boundary scan simplified board testing. Versatile function selections allow more possibilities using on-chip peripheral functions.
Applications
Industrial control Medical systems Protocol converter Communications
Ordering information
Table Ordering information Package Name LPC2420FBD208 LQFP208 LPC2460FBD208 LQFP208 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT459-1 SOT459-1 Type number
LPC2460FET208 TFBGA208 plastic thin fine-pitch ball grid array package; balls; body SOT950-1
Ordering options
Table Ordering options Flash (kB) Local SRAM (kB) Ethernet buffer External Ethernet OTG/ OHCI/ FIFO channels channels channels Temp range Type number
GP/USB
LPC2420FBD208 LPC2460FBD208 LPC2460FET208
Full 32-bit Full 32-bit Full 32-bit
Total
MII/RMII MII/RMII
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Block diagram
XTAL1 VDD(3V3) XTAL2 VDDA
trace signals
TRST EXTIN0 DBGEN
RESET VREF VSSA, VSSCORE, VSSIO VDD(DCDC)(3V3)
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
LPC2420/2460
SRAM
system clock
SYSTEM FUNCTIONS INTERNAL OSCILLATOR
HIGH-SPEED GPI/O PINS TOTAL
INTERNAL SRAM CONTROLLER
ARM7TDMI-S
SRAM
EXTERNAL MEMORY CONTROLLER AHB1
D[31:0] A[23:0] control lines
AHB2
BRIDGE
BRIDGE DEVICE/ HOST/OTG WITH CONTROLLER I2SRX_CLK I2STX_CLK I2SRX_WS I2STX_WS I2SRX_SDA I2STX_SDA SCK, SCK0 MOSI, MOSI0 MISO, MISO0 SSEL, SSEL0 SCK1 MOSI1 MISO1 SSEL1 MCICLK, MCIPWR MCICMD, MCIDAT[3:0] TXD0, TXD2, TXD3 RXD0, RXD2, RXD3 TXD1 RXD1 DTR1, RTS1 DSR1, CTS1, DCD1, CAN1(1), CAN2(1) RD1, TD1, SCL0, SCL1, SCL2 SDA0, SDA1, SDA2 VBUS port1 port2
MII/RMII
ETHERNET WITH DMA(1)
SRAM
MASTER SLAVE PORT BRIDGE PORT BRIDGE
EINT3 EINT0 CAP0/CAP1/ CAP2/CAP3 MAT2/MAT3, MAT0, MAT1 PWM0/PWM1 PCAP0, PCAP1
EXTERNAL INTERRUPTS CAPTURE/COMPARE TIMER0/TIMER1/ TIMER2/TIMER3 INTERFACE
PWM0, PWM1
SPI, SSP0 INTERFACE
LEGACY GPI/O PINS TOTAL
SSP1 INTERFACE
CONVERTER
SD/MMC CARD INTERFACE
AOUT VBAT power domain RTCX1 RTCX2 ALARM
CONVERTER UART0, UART2, UART3 BATTERY
OSCILLATOR
REALTIME CLOCK
UART1
WATCHDOG TIMER SYSTEM CONTROL I2C0, I2C1, I2C2
002aad313
LPC2460 only.
LPC2420/2460 block diagram
LPC2420_2460_2 B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Pinning information
Pinning
LPC2420FBD208 LPC2460FBD208
002aad314
LPC2420/2460 pinning LQFP208 package
ball index area
LPC2460FET208
002aad315
Transparent view
LPC2460 pinning TFBGA208 package Table P3[27]/D27/ CAP1[0]/PWM1[4] P1[4]/ENET_TX_EN VSSIO P1[9]/ENET_RXD0 P1[0]/ENET_TXD0 P1[14]/ENET_RX_ER P4[31]/CS1 P1[15]/ ENET_REF_CLK/ ENET_RX_CLK VSSIO P1[12]/ENET_RXD3/ MCIDAT3/PCAP0[0]
B.V. 2008. rights reserved.
allocation table Symbol Symbol Symbol
Symbol
P1[17]/ENET_MDIO P3[20]/D20/ PWM0[5]/DSR1
P1[3]/ENET_TXD3/ MCICMD/PWM0[2] P1[11]/ENET_RXD2/ MCIDAT2/PWM0[6]
P4[15]/A15 P0[8]/I2STX_WS/ MISO1/MAT2[2]
LPC2420_2460_2
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table
allocation table Symbol Symbol Symbol
Symbol P1[5]/ENET_TX_ER/ MCIPWR/PWM0[3] P3[2]/D2 P1[1]/ENET_TXD1 P4[25]/WE VDD(3V3) P2[0]/PWM1[1]/TXD1/ TRACECLK P3[13]/D13 P3[9]/D9 VDD(3V3)
P3[10]/D10 VSSIO P4[29]/BLS3/ MAT2[1]/RXD3 P3[19]/D19/ PWM0[4]/DCD1 P3[1]/D1 P4[30]/CS0 P1[6]/ENET_TX_CLK/ MCIDAT0/PWM0[4] P4[14]/A14 P3[0]/D0 P4[24]/OE
P0[4]/I2SRX_CLK/RD2/ CAP2[0] P4[13]/A13
P3[22]/D22/ PCAP0[0]/RI1 P3[21]/D21/ PWM0[6]/DTR1 P0[9]/I2STX_SDA/ MOSI1/MAT2[3] P3[28]/D28/ CAP1[1]/PWM1[5] P0[3]/RXD0 P1[16]/ENET_MDC P1[7]/ENET_COL/ MCIDAT1/PWM0[5] RTCK P1[8]/ENET_CRS_DV/ ENET_CRS P4[28]/BLS2/ MAT2[0]/TXD3 P3[18]/D18/ PWM0[3]/CTS1 VDD(3V3) VDD(DCDC)(3V3) P2[2]/PWM1[3]/ CTS1/PIPESTAT1 P0[2]/TXD0 P1[10]/ENET_RXD1 P0[5]/I2SRX_WS/TD2/ CAP2[1] P4[12]/A12 P3[12]/D12 P3[8]/D8 VSSCORE P1[13]/ENET_RX_DV
P0[7]/I2STX_CLK/SCK1 /MAT2[1] VDD(3V3) TRST P3[11]/D11 P1[2]/ENET_TXD2/ MCICLK/PWM0[1] P0[6]/I2SRX_SDA/ SSEL1/MAT2[0] P2[4]/PWM1[5]/ DSR1/TRACESYNC P0[26]/AD0[3]/ AOUT/RXD3 P2[1]/PWM1[2]/RXD1/ PIPESTAT0 P0[25]/AD0[2]/ I2SRX_SDA/TXD3 P4[11]/A11
VSSIO P2[3]/PWM1[4]/ DCD1/PIPESTAT2 P3[29]/D29/ MAT1[0]/PWM1[6] P2[5]/PWM1[6]/ DTR1/TRACEPKT0 VDD(3V3) P2[7]/RD2/ RTS1/TRACEPKT2 P3[3]/D3 P2[6]/PCAP1[0]/ RI1/TRACEPKT1 DBGEN P3[16]/D16/ PWM0[1]/TXD1 VDDA P4[10]/A10
P3[4]/D4 P3[17]/D17/ PWM0[2]/RXD1 P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] P4[27]/BLS1
P3[5]/D5 n.c.
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table
allocation table Symbol P3[14]/D14 P2[8]/TD2/ TXD2/TRACEPKT3 Symbol P3[30]/D30/ MAT1[1]/RTS1 P2[9]/ USB_CONNECT1/ RXD2/EXTIN0 P3[31]/D31/MAT1[2] P0[15]/TXD1/ SCK0/SCK RSTOUT VDD(3V3) Symbol
Symbol P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0] VSSIO
VDD(DCDC)(3V3) P4[9]/A9
P3[6]/D6 P0[16]/RXD1/ SSEL0/SSEL VREF P4[22]/A22/ TXD2/MISO1 P3[7]/D7 n.c. VSSA P4[23]/A23/ RXD2/MOSI1 RTCX1 P0[18]/DCD1/ MOSI0/MOSI RTCX2 P4[26]/BLS0 n.c. P4[8]/A8
VSSCORE P0[17]/CTS1/ MISO0/MISO P2[30]/DQMOUT2/ MAT3[2]/SDA2 P0[19]/DSR1/ MCICLK/SDA1 XTAL1 P0[20]/DTR1/ MCICMD/SCL1 XTAL2 P0[22]/RTS1/ MCIDAT0/TD1 P2[28]/DQMOUT0 VDD(3V3) VSSIO P4[19]/A19 P2[25]/CKEOUT1 P1[21]/USB_TX_DM1/ PWM1[3]/SSEL0 P2[14]/CS2/ CAP2[0]/SDA1
B.V. 2008. rights reserved.
VSSIO P4[7]/A7
P3[15]/D15 P4[6]/A6 RESET P4[21]/A21/ SCL2/SSEL1 P2[31]/DQMOUT3/ MAT3[3]/SCL2 P2[10]/EINT0 VBAT P0[21]/RI1/ MCIPWR/RD1 P2[29]/DQMOUT1 VSSIO
ALARM P2[12]/EINT2/ MCIDAT2/I2STX_WS P1[31]/USB_OVRCR2/ SCK1/AD0[5] P2[24]/CKEOUT0 P1[23]/USB_RX_DP1/ PWM1[4]/MISO0 P2[15]/CS3/ CAP2[1]/SCL1 VDD(3V3) P0[12]/USB_PPWR2/ MISO1/AD0[6] P3[24]/D24/ CAP0[1]/PWM1[1] VSSIO
P1[30]/USB_PWRD2/ VBUS/AD0[4] VDD(3V3) VSSCORE P4[17]/A17 P0[13]/USB_UP_LED2/ MOSI1/AD0[7] P0[30]/USB_D-1 P1[26]/USB_SSPND1/ PWM1[6]/CAP0[0] P2[27]/CKEOUT3/ MAT3[1]/MOSI0
P1[18]/USB_UP_LED1/ PWM1[1]/CAP1[0] VDD(DCDC)(3V3) P4[18]/A18 P0[28]/SCL0 P2[19]/CLKOUT1 P2[16]/CAS
LPC2420_2460_2
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table
allocation table Symbol P0[11]/RXD2/SCL2/ MAT3[1] Symbol P4[4]/A4 Symbol P4[5]/A5
Symbol P2[17]/RAS P4[20]/A20/ SDA2/SCK1 P0[27]/SDA0 VSSIO
P0[31]/USB_D+2 P3[23]/D23/ CAP0[0]/PCAP1[0] P3[26]/D26/ MAT0[1]/PWM1[3] P0[14]/USB_HSTEN2/ USB_CONNECT2/ SSEL1 P4[2]/A2 P0[10]/TXD2/SDA2/ MAT3[0] P2[26]/CKEOUT2/ MAT3[0]/MISO0 P2[20]/DYCS0
P1[24]/USB_RX_DM1/ PWM1[5]/MOSI0 P1[28]/USB_SCL1/ PCAP1[0]/MAT0[0] P2[11]/EINT1/ MCIDAT1/I2STX_CLK USB_D-2 P2[23]/DYCS3/ CAP3[1]/SSEL0 P4[0]/A0 VDD(3V3) P4[16]/A16
P1[25]/USB_LS1/ USB_HSTEN1/MAT1[1] P0[1]/TD1/RXD3/SCL1
P1[27]/USB_INT1/ USB_OVRCR1/CAP0[1] P2[13]/EINT3/ MCIDAT3/I2STX_SDA
P3[25]/D25/ MAT0[0]/PWM1[2] P1[19]/USB_TX_E1/ USB_PPWR1/CAP1[1] P4[1]/A1 P1[29]/USB_SDA1/ PCAP1[1]/MAT0[1] P2[18]/CLKOUT0 P1[20]/USB_TX_DP1/ PWM1[2]/SCK0 P2[21]/DYCS1 P0[0]/RD1/TXD3/SDA1 P0[29]/USB_D+1 P1[22]/USB_RCV1/ USB_PWRD1/MAT1[0] P2[22]/DYCS2/ CAP3[0]/SCK0 P4[3]/A3
description
Table Symbol P0[0] P0[31] description Ball Type Description Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected Connect block. P0[0] General purpose digital input/output pin. CAN1 receiver input (LPC2460 only). TXD3 Transmitter output UART3. SDA1 I2C1 data input/output (this open-drain pin). P0[1] General purpose digital input/output pin. CAN1 transmitter output (LPC2460 only). RXD3 Receiver input UART3. SCL1 I2C1 clock input/output (this open-drain pin). P0[2] General purpose digital input/output pin. TXD0 Transmitter output UART0.
P0[0]/RD1/ TXD3/SDA1
94[1]
U15[1]
P0[1]/TD1/RXD3/ SCL1
96[1]
T14[1]
P0[2]/TXD0
202[1]
C4[1]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 204[1] 168[1] Ball D6[1] B12[1] Type Description P0[3] General purpose digital input/output pin. RXD0 Receiver input UART0. P0[4] General purpose digital input/output pin.
P0[3]/RXD0 P0[4]/ I2SRX_CLK/ RD2/CAP2[0]
I2SRX_CLK Receive Clock. driven master received slave. Corresponds signal I2S-bus specification. CAN2 receiver input (LPC2460 only). CAP2[0] Capture input Timer channel P0[5] General purpose digital input/output pin. I2SRX_WS Receive Word Select. driven master received slave. Corresponds signal I2S-bus specification. CAN2 transmitter output (LPC2460 only). CAP2[1] Capture input Timer channel P0[6] General purpose digital input/output pin. I2SRX_SDA Receive data. driven transmitter read receiver. Corresponds signal I2S-bus specification. SSEL1 Slave Select SSP1. MAT2[0] Match output Timer channel P0[7] General purpose digital input/output pin. I2STX_CLK Transmit Clock. driven master received slave. Corresponds signal I2S-bus specification. SCK1 Serial Clock SSP1. MAT2[1] Match output Timer channel P0[8] General purpose digital input/output pin. I2STX_WS Transmit Word Select. driven master received slave. Corresponds signal I2S-bus specification. MISO1 Master Slave SSP1. MAT2[2] Match output Timer channel P0[9] General purpose digital input/output pin. I2STX_SDA Transmit data. driven transmitter read receiver. Corresponds signal I2S-bus specification. MOSI1 Master Slave SSP1. MAT2[3] Match output Timer channel P0[10] General purpose digital input/output pin. TXD2 Transmitter output UART2. SDA2 I2C2 data input/output (this open-drain pin). MAT3[0] Match output Timer channel P0[11] General purpose digital input/output pin. RXD2 Receiver input UART2. SCL2 I2C2 clock input/output (this open-drain pin). MAT3[1] Match output Timer channel
P0[5]/ I2SRX_WS/ TD2/CAP2[1]
166[1]
C12[1]
P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0] 164[1] D13[1] P0[7]/ I2STX_CLK/ SCK1/MAT2[1] 162[1] C13[1] P0[8]/ I2STX_WS/ MISO1/MAT2[2] 160[1] A15[1]
P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] 158[1] C14[1] P0[10]/TXD2/ SDA2/MAT3[0] 98[1] T15[1] P0[11]/RXD2/ SCL2/MAT3[1] 100[1] R14[1]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 41[2] Ball R1[2] Type 45[2] R2[2] Description P0[12] General purpose digital input/output pin.
P0[12]/ USB_PPWR2/ MISO1/AD0[6]
USB_PPWR2 Port Power enable signal port MISO1 Master Slave SSP1. AD0[6] converter input P0[13] General purpose digital input/output pin.
P0[13]/ USB_UP_LED2/ MOSI1/AD0[7]
USB_UP_LED2 port GoodLink indicator. when device configured (non-control endpoints enabled). HIGH when device configured during global suspend. MOSI1 Master Slave SSP1. AD0[7] converter input P0[14] General purpose digital input/output pin. USB_HSTEN2 Host Enabled status port USB_CONNECT2 SoftConnect control port Signal used switch external resistor under software control. Used with SoftConnect feature. SSEL1 Slave Select SSP1. P0[15] General purpose digital input/output pin. TXD1 Transmitter output UART1. SCK0 Serial clock SSP0. Serial clock SPI. [16] General purpose digital input/output pin. RXD1 Receiver input UART1. SSEL0 Slave Select SSP0. SSEL Slave Select SPI. P0[17] General purpose digital input/output pin. CTS1 Clear Send input UART1. MISO0 Master Slave SSP0. MISO Master Slave SPI. P0[18] General purpose digital input/output pin. DCD1 Data Carrier Detect input UART1. MOSI0 Master Slave SSP0. MOSI Master Slave SPI. P0[19] General purpose digital input/output pin. DSR1 Data Ready input UART1. MCICLK Clock output line SD/MMC interface. SDA1 I2C1 data input/output (this open-drain pin). P0[20] General purpose digital input/output pin. DTR1 Data Terminal Ready output UART1. MCICMD Command line SD/MMC interface. SCL1 I2C1 clock input/output (this open-drain pin).
P0[14]/ USB_HSTEN2/ USB_CONNECT2/ SSEL1 69[1] T7[1]
P0[15]/TXD1/ SCK0/SCK 128[1] J16[1] P0[16]/RXD1/ SSEL0/SSEL 130[1] J14[1] P0[17]/CTS1/ MISO0/MISO 126[1] K17[1] P0[18]/DCD1/ MOSI0/MOSI 124[1] K15[1] P0[19]/DSR1/ MCICLK/SDA1 122[1] L17[1] P0[20]/DTR1/ MCICMD/SCL1 120[1] M17[1]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 118[1] Ball M16[1] Type Description P0[21] General purpose digital input/output pin. Ring Indicator input UART1. CAN1 receiver input (LPC2460 only). P0[22] General purpose digital input/output pin. RTS1 Request Send output UART1. MCIDAT0 Data line SD/MMC interface. CAN1 transmitter output (LPC2460 only). P0[23] General purpose digital input/output pin. AD0[0] converter input
P0[21]/RI1/ MCIPWR/RD1
MCIPWR Power Supply Enable external SD/MMC power supply.
P0[22]/RTS1/ MCIDAT0/TD1
116[1]
N17[1]
P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]
18[2]
H1[2]
I2SRX_CLK Receive Clock. driven master received slave. Corresponds signal I2S-bus specification. CAP3[0] Capture input Timer channel P0[24] General purpose digital input/output pin. AD0[1] converter input I2SRX_WS Receive Word Select. driven master received slave. Corresponds signal I2S-bus specification. CAP3[1] Capture input Timer channel P0[25] General purpose digital input/output pin. AD0[2] converter input I2SRX_SDA Receive data. driven transmitter read receiver. Corresponds signal I2S-bus specification. TXD3 Transmitter output UART3. P0[26] General purpose digital input/output pin. AD0[3] converter input AOUT converter output. RXD3 Receiver input UART3. P0[27] General purpose digital input/output pin. SDA0 I2C0 data input/output. Open-drain output (for I2C-bus compliance). P0[28] General purpose digital input/output pin. SCL0 I2C0 clock input/output. Open-drain output (for I2C-bus compliance). P0[29] General purpose digital input/output pin. USB_D+1 port bidirectional line. P0[30] General purpose digital input/output pin. USB_D-1 port bidirectional line. P0[31] General purpose digital input/output pin. USB_D+2 port bidirectional line. Port Port port with individual direction controls each bit. operation port pins depends upon function selected Connect block.
B.V. 2008. rights reserved.
P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]
16[2]
G2[2]
P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 14[2] F1[2] P0[26]/AD0[3]/ AOUT/RXD3 12[2][3] E1[2][3] P0[27]/SDA0 50[4] T1[4] P0[28]/SCL0 48[4] R3[4] P0[29]/USB_D+1 P0[30]/USB_D-1 P0[31]/USB_D+2 P1[0] P1[31] 61[5] 62[5] 51[5] U4[5] R6[5] T2[5]
LPC2420_2460_2
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 196[1] Ball A3[1] Type 194[1] B5[1] 185[1] D9[1] 177[1] A10[1] 192[1] A5[1] 156[1] A17[1] 171[1] B11[1] 153[1] D14[1] 190[1] C7[1] 188[1] A6[1] 186[1] C8[1] 163[1] A14[1] Description P1[0] General purpose digital input/output pin.
P1[0]/ ENET_TXD0 P1[1]/ ENET_TXD1 P1[2]/ ENET_TXD2/ MCICLK/ PWM0[1] P1[3]/ ENET_TXD3/ MCICMD/ PWM0[2] P1[4]/ ENET_TX_EN P1[5]/ ENET_TX_ER/ MCIPWR/ PWM0[3] P1[6]/ ENET_TX_CLK/ MCIDAT0/ PWM0[4]
ENET_TXD0 Ethernet transmit data (RMII/MII interface) (LPC2460 only). P1[1] General purpose digital input/output pin. ENET_TXD1 Ethernet transmit data (RMII/MII interface) (LPC2460 only). P1[2] General purpose digital input/output pin.
ENET_TXD2 Ethernet transmit data (MII interface) (LPC2460 only). MCICLK Clock output line SD/MMC interface. PWM0[1] Pulse Width Modulator output P1[3] General purpose digital input/output pin. ENET_TXD3 Ethernet transmit data (MII interface) (LPC2460 only). MCICMD Command line SD/MMC interface. PWM0[2] Pulse Width Modulator output P1[4] General purpose digital input/output pin. ENET_TX_EN Ethernet transmit data enable (RMII/MII interface) (LPC2460 only). P1[5] General purpose digital input/output pin. ENET_TX_ER Ethernet Transmit Error (MII interface) (LPC2460 only). MCIPWR Power Supply Enable external SD/MMC power supply. PWM0[3] Pulse Width Modulator output P1[6] General purpose digital input/output pin. ENET_TX_CLK Ethernet Transmit Clock (MII interface) (LPC2460 only). MCIDAT0 Data line SD/MMC interface. PWM0[4] Pulse Width Modulator output P1[7] General purpose digital input/output pin. ENET_COL Ethernet Collision detect (MII interface) (LPC2460 only). MCIDAT1 Data line SD/MMC interface. PWM0[5] Pulse Width Modulator output P1[8] General purpose digital input/output pin. ENET_CRS_DV/ENET_CRS Ethernet Carrier Sense/Data Valid (RMII interface)/ Ethernet Carrier Sense (MII interface) (LPC2460 only). P1[9] General purpose digital input/output pin. ENET_RXD0 Ethernet receive data (RMII/MII interface) (LPC2460 only). P1[10] General purpose digital input/output pin. ENET_RXD1 Ethernet receive data (RMII/MII interface) (LPC2460 only). P1[11] General purpose digital input/output pin. ENET_RXD2 Ethernet Receive Data (MII interface) (LPC2460 only). MCIDAT2 Data line SD/MMC interface. PWM0[6] Pulse Width Modulator output
B.V. 2008. rights reserved.
P1[7]/ ENET_COL/ MCIDAT1/ PWM0[5] P1[8]/ ENET_CRS_DV/ ENET_CRS P1[9]/ ENET_RXD0 P1[10]/ ENET_RXD1 P1[11]/ ENET_RXD2/ MCIDAT2/ PWM0[6]
LPC2420_2460_2
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 157[1] Ball A16[1] Type 147[1] D16[1] 184[1] A7[1] 182[1] A8[1] 180[1] 178[1] 66[1] D10[1] A9[1] P7[1] Description P1[12] General purpose digital input/output pin. MCIDAT3 Data line SD/MMC interface. PCAP0[0] Capture input PWM0, channel P1[13] General purpose digital input/output pin.
P1[12]/ ENET_RXD3/ MCIDAT3/ PCAP0[0] P1[13]/ ENET_RX_DV P1[14]/ ENET_RX_ER P1[15]/ ENET_REF_CLK/ ENET_RX_CLK P1[16]/ ENET_MDC P1[17]/ ENET_MDIO P1[18]/ USB_UP_LED1/ PWM1[1]/ CAP1[0]
ENET_RXD3 Ethernet Receive Data (MII interface) (LPC2460 only).
ENET_RX_DV Ethernet Receive Data Valid (MII interface) (LPC2460 only). P1[14] General purpose digital input/output pin. ENET_RX_ER Ethernet receive error (RMII/MII interface) (LPC2460 only). P1[15] General purpose digital input/output pin. ENET_REF_CLK/ENET_RX_CLK Ethernet Reference Clock (RMII interface)/ Ethernet Receive Clock (MII interface) (LPC2460 only). P1[16] General purpose digital input/output pin. ENET_MDC Ethernet MIIM clock (LPC2460 only). P1[17] General purpose digital input/output pin. ENET_MDIO Ethernet MIIM data input output (LPC2460 only). P1[18] General purpose digital input/output pin. USB_UP_LED1 port GoodLink indicator. when device configured (non-control endpoints enabled). HIGH when device configured during global suspend. PWM1[1] Pulse Width Modulator channel output. CAP1[0] Capture input Timer channel P1[19] General purpose digital input/output pin. USB_TX_E1 Transmit Enable signal port (OTG transceiver). USB_PPWR1 Port Power enable signal port CAP1[1] Capture input Timer channel P1[20] General purpose digital input/output pin. USB_TX_DP1 transmit data port (OTG transceiver). PWM1[2] Pulse Width Modulator channel output. SCK0 Serial clock SSP0. P1[21] General purpose digital input/output pin. USB_TX_DM1 transmit data port (OTG transceiver). PWM1[3] Pulse Width Modulator channel output. SSEL0 Slave Select SSP0. P1[22] General purpose digital input/output pin. USB_RCV1 Differential receive data port (OTG transceiver). USB_PWRD1 Power Status port (host power switch). MAT1[0] Match output Timer channel
P1[19]/ USB_TX_E1/ USB_PPWR1/ CAP1[1] P1[20]/ USB_TX_DP1/ PWM1[2]/SCK0 68[1] U6[1] 70[1] U7[1] P1[21]/ USB_TX_DM1/ PWM1[3]/SSEL0 72[1] R8[1] P1[22]/ USB_RCV1/ USB_PWRD1/ MAT1[0] 74[1] U8[1]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 76[1] Ball P9[1] Type 78[1] T9[1] 80[1] T10[1] 82[1] R10[1] 88[1] T12[1] 90[1] T13[1] 92[1] U14[1] 42[2] P2[2] Description P1[23] General purpose digital input/output pin. PWM1[4] Pulse Width Modulator channel output. MISO0 Master Slave SSP0. P1[24] General purpose digital input/output pin.
P1[23]/ USB_RX_DP1/ PWM1[4]/MISO0
USB_RX_DP1 receive data port (OTG transceiver).
P1[24]/ USB_RX_DM1/ PWM1[5]/MOSI0
USB_RX_DM1 receive data port (OTG transceiver). PWM1[5] Pulse Width Modulator channel output. MOSI0 Master Slave SSP0. P1[25] General purpose digital input/output pin. USB_LS1 Low-speed status port (OTG transceiver). USB_HSTEN1 Host Enabled status port MAT1[1] Match output Timer channel P1[26] General purpose digital input/output pin. USB_SSPND1 port Suspend status (OTG transceiver). PWM1[6] Pulse Width Modulator channel output. CAP0[0] Capture input Timer channel P1[27] General purpose digital input/output pin. USB_INT1 port transceiver interrupt (OTG transceiver). USB_OVRCR1 port Over-Current status. CAP0[1] Capture input Timer channel P1[28] General purpose digital input/output pin. USB_SCL1 port serial clock (OTG transceiver). PCAP1[0] Capture input PWM1, channel MAT0[0] Match output Timer channel P1[29] General purpose digital input/output pin. USB_SDA1 port serial data (OTG transceiver). PCAP1[1] Capture input PWM1, channel MAT0[1] Match output Timer channel P1[30] General purpose digital input/output pin. USB_PWRD2 Power Status port VBUS Monitors presence power. Note: This signal must HIGH reset occur. AD0[4] converter input P1[31] General purpose digital input/output pin. USB_OVRCR2 Over-Current status port SCK1 Serial Clock SSP1. AD0[5] converter input Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected Connect block.
P1[25]/ USB_LS1/ USB_HSTEN1/ MAT1[1] P1[26]/ USB_SSPND1/ PWM1[6]/ CAP0[0] P1[27]/ USB_INT1/ USB_OVRCR1/ CAP0[1] P1[28]/ USB_SCL1/ PCAP1[0]/ MAT0[0] P1[29]/ USB_SDA1/ PCAP1[1]/ MAT0[1] P1[30]/ USB_PWRD2/ VBUS/AD0[4]
P1[31]/ USB_OVRCR2/ SCK1/AD0[5]
40[2]
P1[2]
P2[0] P2[31]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 154[1] Ball B17[1] Type 152[1] E14[1] 150[1] D15[1] 144[1] E16[1] 142[1] D17[1] 140[1] F16[1] 138[1] E17[1] Description P2[0] General purpose digital input/output pin. PWM1[1] Pulse Width Modulator channel output. TXD1 Transmitter output UART1. TRACECLK Trace Clock. P2[1] General purpose digital input/output pin. PWM1[2] Pulse Width Modulator channel output. RXD1 Receiver input UART1. PIPESTAT0 Pipeline Status, P2[2] General purpose digital input/output pin. PWM1[3] Pulse Width Modulator channel output. CTS1 Clear Send input UART1. PIPESTAT1 Pipeline Status, P2[3] General purpose digital input/output pin. PWM1[4] Pulse Width Modulator channel output. DCD1 Data Carrier Detect input UART1. PIPESTAT2 Pipeline Status, P2[4] General purpose digital input/output pin. PWM1[5] Pulse Width Modulator channel output. DSR1 Data Ready input UART1. TRACESYNC Trace Synchronization. P2[5] General purpose digital input/output pin. PWM1[6] Pulse Width Modulator channel output. DTR1 Data Terminal Ready output UART1. TRACEPKT0 Trace Packet, P2[6] General purpose digital input/output pin. PCAP1[0] Capture input PWM1, channel Ring Indicator input UART1. TRACEPKT1 Trace Packet, P2[7] General purpose digital input/output pin. CAN2 receiver input (LPC2460 only). RTS1 Request Send output UART1. TRACEPKT2 Trace Packet, P2[8] General purpose digital input/output pin. CAN2 transmitter output (LPC2460 only). TXD2 Transmitter output UART2. TRACEPKT3 Trace Packet,
P2[0]/PWM1[1]/ TXD1/ TRACECLK
P2[1]/PWM1[2]/ RXD1/ PIPESTAT0
P2[2]/PWM1[3]/ CTS1/ PIPESTAT1
P2[3]/PWM1[4]/ DCD1/ PIPESTAT2
P2[4]/PWM1[5]/ DSR1/ TRACESYNC
P2[5]/PWM1[6]/ DTR1/ TRACEPKT0
P2[6]/PCAP1[0]/ RI1/TRACEPKT1
P2[7]/RD2/ RTS1/ TRACEPKT2
136[1]
G16[1]
P2[8]/TD2/ TXD2/ TRACEPKT3
134[1]
H15[1]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 132[1] Ball H16[1] Type Description P2[9] General purpose digital input/output pin.
P2[9]/ USB_CONNECT1/ RXD2/ EXTIN0
USB_CONNECT1 USB1 SoftConnect control. Signal used switch external resistor under software control. Used with SoftConnect feature. RXD2 Receiver input UART2. EXTIN0 External Trigger Input. P2[10] General purpose digital input/output pin.
P2[10]/EINT0 110[6] N15[6]
Note: this while RESET forces on-chip bootloader take over control part after reset. P2[11]/EINT1/ MCIDAT1/ I2STX_CLK 108[6] T17[6] P2[12]/EINT2/ MCIDAT2/ I2STX_WS 106[6] N14[6] EINT0 External interrupt input. P2[11] General purpose digital input/output pin. EINT1 External interrupt input. MCIDAT1 Data line SD/MMC interface. I2STX_CLK Transmit Clock. driven master received slave. Corresponds signal I2S-bus specification. P2[12] General purpose digital input/output pin. EINT2 External interrupt input. MCIDAT2 Data line SD/MMC interface. I2STX_WS Transmit Word Select. driven master received slave. Corresponds signal I2S-bus specification. P2[13] General purpose digital input/output pin. EINT3 External interrupt input. MCIDAT3 Data line SD/MMC interface. I2STX_SDA Transmit data. driven transmitter read receiver. Corresponds signal I2S-bus specification. P2[14] General purpose digital input/output pin. active Chip Select signal. CAP2[0] Capture input Timer channel SDA1 I2C1 data input/output (this open-drain pin). P2[15] General purpose digital input/output pin. active Chip Select signal. CAP2[1] Capture input Timer channel SCL1 I2C1 clock input/output (this open-drain pin). P2[16] General purpose digital input/output pin. active SDRAM Column Address Strobe. P2[17] General purpose digital input/output pin. active SDRAM Address Strobe. P2[18] General purpose digital input/output pin. CLKOUT0 SDRAM clock P2[19] General purpose digital input/output pin. CLKOUT1 SDRAM clock
P2[13]/EINT3/ MCIDAT3/ I2STX_SDA
102[6]
T16[6]
P2[14]/CS2/ CAP2[0]/SDA1
91[6]
R12[6]
P2[15]/CS3/ CAP2[1]/SCL1
99[6]
P13[6]
P2[16]/CAS P2[17]/RAS P2[18]/ CLKOUT0 P2[19]/ CLKOUT1
87[1] 95[1] 59[1] 67[1]
R11[1] R13[1] U3[1] R7[1]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 73[1] 81[1] 85[1] Ball T8[1] U11[1] U12[1] Type Description P2[20] General purpose digital input/output pin. DYCS0 SDRAM chip select P2[21] General purpose digital input/output pin. DYCS1 SDRAM chip select P2[22] General purpose digital input/output pin. DYCS2 SDRAM chip select CAP3[0] Capture input Timer channel SCK0 Serial clock SSP0. P2[23] General purpose digital input/output pin. DYCS3 SDRAM chip select CAP3[1] Capture input Timer channel SSEL0 Slave Select SSP0. P2[24] General purpose digital input/output pin. CKEOUT0 SDRAM clock enable P2[25] General purpose digital input/output pin. CKEOUT1 SDRAM clock enable P2[26] General purpose digital input/output pin. CKEOUT2 SDRAM clock enable MAT3[0] Match output Timer channel MISO0 Master Slave SSP0. P2[27] General purpose digital input/output pin. CKEOUT3 SDRAM clock enable MAT3[1] Match output Timer channel MOSI0 Master Slave SSP0. P2[28] General purpose digital input/output pin.
P2[20]/DYCS0 P2[21]/DYCS1 P2[22]/DYCS2/ CAP3[0]/SCK0
P2[23]/DYCS3/ CAP3[1]/SSEL0
64[1]
U5[1]
P2[24]/ CKEOUT0 P2[25]/ CKEOUT1 P2[26]/ CKEOUT2/ MAT3[0]/MISO0
53[1] 54[1] 57[1]
P5[1] R4[1] T4[1]
P2[27]/ CKEOUT3/ MAT3[1]/MOSI0
47[1]
P3[1]
P2[28]/ DQMOUT0 P2[29]/ DQMOUT1 P2[30]/ DQMOUT2/ MAT3[2]/SDA2
49[1] 43[1] 31[1]
P4[1] N3[1] L4[1]
DQMOUT0 Data mask used with SDRAM static devices. P2[29] General purpose digital input/output pin. DQMOUT1 Data mask used with SDRAM static devices. P2[30] General purpose digital input/output pin. DQMOUT2 Data mask used with SDRAM static devices. MAT3[2] Match output Timer channel SDA2 I2C2 data input/output (this open-drain pin). P2[31] General purpose digital input/output pin. DQMOUT3 Data mask used with SDRAM static devices. MAT3[3] Match output Timer channel SCL2 I2C2 clock input/output (this open-drain pin). Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected Connect block. P3[0] General purpose digital input/output pin. External memory data line
B.V. 2008. rights reserved.
P2[31]/ DQMOUT3/ MAT3[3]/SCL2
39[1]
N2[1]
P3[0] P3[31]
P3[0]/D0
197[1]
B4[1]
LPC2420_2460_2
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol P3[1]/D1 P3[2]/D2 P3[3]/D3 P3[4]/D4 P3[5]/D5 P3[6]/D6 P3[7]/D7 P3[8]/D8 P3[9]/D9 P3[10]/D10 P3[11]/D11 P3[12]/D12 P3[13]/D13 P3[14]/D14
description .continued 201[1] 207[1] 3[1] 13[1] 17[1] 23[1] 27[1] 191[1] 199[1] 205[1] 208[1] 1[1] 7[1] 21[1] Ball B3[1] B1[1] E4[1] F2[1] G1[1] J1[1] L1[1] D8[1] C5[1] B2[1] D5[1] D4[1] C1[1] H2[1] Type Description P3[1] General purpose digital input/output pin. External memory data line P3[2] General purpose digital input/output pin. External memory data line P3[3] General purpose digital input/output pin. External memory data line P3[4] General purpose digital input/output pin. External memory data line P3[5] General purpose digital input/output pin. External memory data line P3[6] General purpose digital input/output pin. External memory data line P3[7] General purpose digital input/output pin. External memory data line P3[8] General purpose digital input/output pin. External memory data line P3[9] General purpose digital input/output pin. External memory data line P3[10] General purpose digital input/output pin. External memory data line P3[11] General purpose digital input/output pin. External memory data line P3[12] General purpose digital input/output pin. External memory data line P3[13] General purpose digital input/output pin. External memory data line P3[14] General purpose digital input/output pin.
External memory data line POR, this serves BOOT0 pin. P3[15] General purpose digital input/output pin. External memory data line POR, this serves BOOT1 pin. BOOT[1:0] selects 8-bit external memory CS1. BOOT[1:0] reserved. use. BOOT[1:0] selects 32-bit external memory CS1. BOOT[1:0] selects 16-bit external memory CS1.
P3[15]/D15
28[1]
M1[1]
P3[16]/D16/ PWM0[1]/TXD1
137[1]
F17[1]
P3[16] General purpose digital input/output pin. External memory data line PWM0[1] Pulse Width Modulator output TXD1 Transmitter output UART1.
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 143[1] Ball F15[1] Type Description P3[17] General purpose digital input/output pin. External memory data line PWM0[2] Pulse Width Modulator output RXD1 Receiver input UART1. P3[18] General purpose digital input/output pin. External memory data line PWM0[3] Pulse Width Modulator output CTS1 Clear Send input UART1. P3[19] General purpose digital input/output pin. External memory data line PWM0[4] Pulse Width Modulator output DCD1 Data Carrier Detect input UART1. P3[20] General purpose digital input/output pin. External memory data line PWM0[5] Pulse Width Modulator output DSR1 Data Ready input UART1. P3[21] General purpose digital input/output pin. External memory data line PWM0[6] Pulse Width Modulator output DTR1 Data Terminal Ready output UART1. P3[22] General purpose digital input/output pin. External memory data line PCAP0[0] Capture input PWM0, channel Ring Indicator input UART1. P3[23] General purpose digital input/output pin. External memory data line CAP0[0] Capture input Timer channel PCAP1[0] Capture input PWM1, channel P3[24] General purpose digital input/output pin. External memory data line CAP0[1] Capture input Timer channel PWM1[1] Pulse Width Modulator output P3[25] General purpose digital input/output pin. External memory data line MAT0[0] Match output Timer channel PWM1[2] Pulse Width Modulator output P3[26] General purpose digital input/output pin. External memory data line MAT0[1] Match output Timer channel PWM1[3] Pulse Width Modulator output
P3[17]/D17/ PWM0[2]/RXD1
P3[18]/D18/ PWM0[3]/CTS1
151[1]
C15[1]
P3[19]/D19/ PWM0[4]/DCD1
161[1]
B14[1]
P3[20]/D20/ PWM0[5]/DSR1
167[1]
A13[1]
P3[21]/D21/ PWM0[6]/DTR1
175[1]
C10[1]
P3[22]/D22/ PCAP0[0]/RI1
195[1]
C6[1]
P3[23]/D23/ CAP0[0]/ PCAP1[0]
65[1]
T6[1]
P3[24]/D24/ CAP0[1]/ PWM1[1]
58[1]
R5[1]
P3[25]/D25/ MAT0[0]/ PWM1[2]
56[1]
U2[1]
P3[26]/D26/ MAT0[1]/ PWM1[3]
55[1]
T3[1]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol
description .continued 203[1] Ball A1[1] Type 5[1] D2[1] 11[1] F3[1] 19[1] H3[1] 25[1] J3[1] Description P3[27] General purpose digital input/output pin. External memory data line CAP1[0] Capture input Timer channel PWM1[4] Pulse Width Modulator output P3[28] General purpose digital input/output pin. External memory data line CAP1[1] Capture input Timer channel PWM1[5] Pulse Width Modulator output P3[29] General purpose digital input/output pin. External memory data line MAT1[0] Match output Timer channel PWM1[6] Pulse Width Modulator output P3[30] General purpose digital input/output pin. External memory data line MAT1[1] Match output Timer channel RTS1 Request Send output UART1. P3[31] General purpose digital input/output pin. External memory data line MAT1[2] Match output Timer channel
P3[27]/D27/ CAP1[0]/ PWM1[4]
P3[28]/D28/ CAP1[1]/ PWM1[5]
P3[29]/D29/ MAT1[0]/ PWM1[6]
P3[30]/D30/ MAT1[1]/ RTS1
P3[31]/D31/ MAT1[2]
P4[0] P4[31]
Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected Connect block. P4[0] ]General purpose digital input/output pin. External memory address line P4[1] General purpose digital input/output pin. External memory address line P4[2] General purpose digital input/output pin. External memory address line P4[3] General purpose digital input/output pin. External memory address line P4[4] General purpose digital input/output pin. External memory address line P4[5] General purpose digital input/output pin. External memory address line P4[6] General purpose digital input/output pin. External memory address line P4[7] General purpose digital input/output pin. External memory address line P4[8] General purpose digital input/output pin. External memory address line
P4[0]/A0 P4[1]/A1 P4[2]/A2 P4[3]/A3 P4[4]/A4 P4[5]/A5 P4[6]/A6 P4[7]/A7 P4[8]/A8
75[1] 79[1] 83[1] 97[1] 103[1] 107[1] 113[1] 121[1] 127[1]
U9[1] U10[1] T11[1] U16[1] R15[1] R16[1] M14[1] L16[1] J17[1]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol P4[9]/A9 P4[10]/A10 P4[11]/A11 P4[12]/A12 P4[13]/A13 P4[14]/A14 P4[15]/A15 P4[16]/A16 P4[17]/A17 P4[18]/A18 P4[19]/A19
description .continued 131[1] 135[1] 145[1] 149[1] 155[1] 159[1] 173[1] 101[1] 104[1] 105[1] 111[1] 109[1] Ball H17[1] G17[1] F14[1] C16[1] B16[1] B15[1] A11[1] U17[1] P14[1] P15[1] P16[1] R17[1] Type Description P4[9] General purpose digital input/output pin. External memory address line P4[10] General purpose digital input/output pin. External memory address line P4[11] General purpose digital input/output pin. External memory address line P4[12] General purpose digital input/output pin. External memory address line P4[13] General purpose digital input/output pin. External memory address line P4[14] General purpose digital input/output pin. External memory address line P4[15] General purpose digital input/output pin. External memory address line P4[16] General purpose digital input/output pin. External memory address line P4[17] General purpose digital input/output pin. External memory address line P4[18] General purpose digital input/output pin. External memory address line P4[19] General purpose digital input/output pin. External memory address line P4[20] General purpose digital input/output pin. External memory address line
P4[20]/A20/ SDA2/SCK1
SDA2 I2C2 data input/output (this open-drain pin). SCK1 Serial Clock SSP1. P4[21] General purpose digital input/output pin. External memory address line SCL2 I2C2 clock input/output (this open-drain pin). SSEL1 Slave Select SSP1. P4[22] General purpose digital input/output pin. External memory address line TXD2 Transmitter output UART2. MISO1 Master Slave SSP1. P4[23] General purpose digital input/output pin. External memory address line RXD2 Receiver input UART2. MOSI1 Master Slave SSP1. P4[24] General purpose digital input/output pin. active Output Enable signal.
P4[21]/A21/ SCL2/SSEL1
115[1]
M15[1]
P4[22]/A22/ TXD2/MISO1
123[1]
K14[1]
P4[23]/A23/ RXD2/MOSI1
129[1]
J15[1]
P4[24]/OE
183[1]
B8[1]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Symbol P4[25]/WE
description .continued 179[1] 119[1] 139[1] 170[1] Ball B9[1] L15[1] G15[1] C11[1] Type Description P4[25] General purpose digital input/output pin. active Write Enable signal. P4[26] General purpose digital input/output pin. BLS0 active Byte Lane select signal P4[27] General purpose digital input/output pin. BLS1 active Byte Lane select signal [28] General purpose digital input/output pin. BLS2 active Byte Lane select signal MAT2[0] Match output Timer channel TXD3 Transmitter output UART3. P4[29] General purpose digital input/output pin. BLS3 active Byte Lane select signal MAT2[1] Match output Timer channel RXD3 Receiver input UART3. P4[30] General purpose digital input/output pin. active Chip Select signal. P4[31] General purpose digital input/output pin. active Chip Select signal.
P4[26]/BLS0 P4[27]/BLS1 P4[28]/BLS2/ MAT2[0]/TXD3
P4[29]/BLS3/ MAT2[1]/RXD3
176[1]
B10[1]
P4[30]/CS0 P4[31]/CS1 ALARM USB_D-2 DBGEN TRST RTCK
187[1] 193[1] 37[8] 9[1] 2[1] 4[1] 6[1] 8[1] 10[1] 206[1]
B7[1] A4[1] N1[8] F4[1] D3[1] C2[1] E3[1] D1[1] E2[1] C3[1]
ALARM controlled output. This pin. goes HIGH when alarm generated. USB_D-2 port bidirectional line. DBGEN JTAG interface control signal. Also used boundary scanning. Test data JTAG interface. Test data JTAG interface. Test Mode Select JTAG interface. TRST Test Reset JTAG interface. Test Clock JTAG interface. This clock must slower than clock (CCLK) JTAG interface operate. RTCK JTAG interface control signal. Note: this while RESET enables Epins (P2[9:0]) operate Trace port after reset.
RSTOUT RESET
35[7]
M2[7]
RSTOUT This pin. this indicates LPC2420/2460 being Reset state. external reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Input oscillator circuit. Output from oscillator circuit.
XTAL1 XTAL2 RTCX1 RTCX2
44[8] 46[8] 34[8] 36[8]
M4[8] N4[8] K2[8] L2[8]
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LPC2420/2460
Fast communication chip
Table Symbol VSSIO
description .continued 114, 133, 148, 169, 189, 200[8] 172[8] 22[8] Ball Type Description ground: reference digital pins. P12, N16, H14, E15, A12, A2[8] P10, D12[8] J2[8]
VSSCORE VSSA
ground: reference core. analog ground: reference. This should nominally same voltage VSSIO/VSSCORE, should isolated minimize noise error. supply voltage: This power supply voltage ports.
VDD(3V3)
112, 125, 146, 165, 181, 198[8]
U13, P17, K16, C17, B13, D7[8]
n.c. VDD(DCDC)(3V3) VDDA
117, L14, G14[8] 141[8] 174[8] 20[8] P11, D11[8] G4[8]
connected pins: These pins must left unconnected (floating). DC-to-DC converter supply voltage: This power supply on-chip DC-to-DC converter. analog supply voltage: This should nominally same voltage VDD(3V3) should isolated minimize noise error. This voltage used power DAC. reference: This should nominally same voltage VDD(3V3) should isolated minimize noise error. level this used reference DAC. power supply: this supplies power RTC.
VREF
24[8]
K1[8]
VBAT
38[8]
M3[8]
tolerant providing digital functions with levels hysteresis. tolerant providing digital functions (with levels hysteresis) analog input. When configured input, digital section disabled. tolerant providing digital with levels hysteresis analog output function. When configured output, digital section disabled. Open-drain tolerant digital pad, compatible with I2C-bus specification. requires external pull-up provide output functionality. When power switched off, this connected I2C-bus floating does disturb lines. Open-drain configuration applies functions this pin. provides digital functions. designed accordance with specification, revision (Full-speed Low-speed mode only). tolerant with glitch filter providing digital functions with levels hysteresis. tolerant with glitch filter providing digital function with levels hysteresis. provides special analog functionality.
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LPC2420/2460
Fast communication chip
Functional description
Architectural overview
LPC2420/2460 microcontroller consists ARM7TDMI-S with emulation support, ARM7 local closely coupled, high-speed access majority on-chip memory, AMBA interfacing high-speed on-chip peripherals external memory, AMBA connection other on-chip peripheral functions. microcontroller permanently configures ARM7TDMI-S processor little-endian byte order. LPC2460 only implements order allow Ethernet block operate without interference caused other system activity. primary AHB, referred AHB1, includes VIC, GPDMA controller, EMC. second (LPC2460 only), referred AHB2, includes only Ethernet block associated SRAM. addition, bridge provided that allows secondary master AHB1, allowing expansion Ethernet buffer space into off-chip memory unused space memory residing AHB1. summary, masters with access AHB1 ARM7 itself, GPDMA function, Ethernet block (via bridge from AHB2). masters with access AHB2 ARM7 Ethernet block. peripherals allocated range addresses very memory space. Each peripheral allocated address space within address space. Lower speed peripheral functions connected APB. bridge interfaces AHB. peripherals also allocated range addresses, beginning address point. Each peripheral allocated address space within address space. ARM7TDMI-S processor general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed complex instruction computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit 16-bit Thumb
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LPC2420/2460
Fast communication chip
Thumb set's 16-bit instruction length allows approach higher density compared standard code while retaining most ARM's performance.
On-chip SRAM
LPC2420/2460 includes SRAM memory reserved processor exclusive use. This used code and/or data storage accessed bits, bits, bits. SRAM block serving buffer Ethernet controller (LPC2460 only) SRAM associated with second used both data code storage, too. SRAM used data storage only. SRAM battery powered retains content absence main power supply.
Memory
LPC2420/2460 memory incorporates several distinct regions shown Table Figure addition, interrupt vectors remapped allow them reside boot SRAM (see Section 7.25.6).
Table LPC2420/2460 memory usage details Address range details description 0x3FFF C000 0x3FFF FFFF 0x4000 0000 0x4000 FFFF 0x7FE0 0000 0x7FE0 3FFF 0x7FD0 0000 0x7FD0 3FFF 0x8000 0000 off-chip memory 0xDFFF FFFF 0x8000 0000 0x80FF FFFF 0x8100 0000 0x81FF FFFF 0x8200 0000 0x82FF FFFF 0x8300 0000 0x83FF FFFF 0xA000 0000 0xAFFF FFFF 0xB000 0000 0xBFFF FFFF 0xC000 0000 0xCFFF FFFF 0xD000 0000 0xDFFF FFFF 0xE000 0000 peripherals 0xEFFF FFFF 0xF000 0000 peripherals 0xFFFF FFFF peripheral blocks, each fast GPIO registers Ethernet (LPC2460 only) static memory bank static memory bank static memory bank static memory bank dynamic memory bank dynamic memory bank dynamic memory bank dynamic memory bank fast
Address range General 0x0000 0000 0x3FFF FFFF
0x4000 0000 on-chip 0x7FFF FFFF
Four static memory banks, each
Four dynamic memory banks, each
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Fast communication chip
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000
0xE000 0000
EXTERNAL STATIC DYNAMIC MEMORY
BOOT
0x8000 0000 0x7FFF FFFF
RESERVED ADDRESS SPACE
ON-CHIP STATIC SPECIAL REGISTERS
0x4000 0000 0x3FFF FFFF 0x3FFF 8000
RESERVED ADDRESS SPACE
002aad316
0x0000 0000
LPC2420/2460 memory
Interrupt controller
processor core interrupt inputs called Interrupt Request (IRQ) Fast Interrupt Request (FIQ). takes interrupt request inputs which programmed vectored types. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. FIQs have highest priority. more than request assigned FIQ, requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then
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LPC2420/2460
Fast communication chip
service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt.
Vectored IRQs, which include interrupt requests that classified FIQs, have programmable interrupt priority. When more than interrupt assigned same priority occur simultaneously, connected lowest numbered channel will serviced first. requests from vectored IRQs produce signal processor. service routine start reading register from jumping address supplied that register.
7.4.1 Interrupt sources
Each peripheral device interrupt line connected have several interrupt flags. Individual interrupt flags also represent more than interrupt source. port port (total pins) regardless selected function, programmed generate interrupt rising edge, falling edge, both. Such interrupt request coming from port and/or port will combined with EINT3 interrupt requests.
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined.
External memory controller
LPC2420/2460 PrimeCell MultiPort Memory Controller peripheral offering support asynchronous static memory devices such RAM, ROM, flash. addition, used interface with off-chip memory-mapped devices peripherals. Advanced Microcontroller Architecture (AMBA) compliant peripheral.
7.6.1 Features
Dynamic memory interface support including Single Data Rate SDRAM. Asynchronous static memory device support including RAM, ROM, flash, with
without asynchronous page mode.
LPC2420_2460_2
transaction latency. Read write buffers reduce latency improve performance. 8/16/32 data address lines wide static memory support. wide chip select SDRAM memory support. Static memory features include:
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LPC2420/2460
Fast communication chip
Asynchronous page mode read Programmable Wait States turnaround delay Output enable write enable delays Extended wait
Four chip selects synchronous memory four chip selects static memory
devices.
Power-saving modes dynamically control CLKOUT SDRAMs. Dynamic memory self-refresh mode controlled software. Controller supports 2048, 4096, 8192 address synchronous memory parts.
That typical parts, with data bits device.
Separate reset domains allow auto-refresh through chip reset desired.
Note: Synchronous static memory devices (synchronous burst mode) supported.
General purpose controller
GPDMA AMBA compliant peripheral allowing selected LPC2420/2460 peripherals have support. GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, memory-to-memory transactions. Each stream provides unidirectional serial transfers single source destination. example, bidirectional port requires stream transmit receive. source destination areas each either memory region peripheral, accessed through master.
7.7.1 Features
channels. Each channel support unidirectional transfer. GPDMA transfer data between SRAM, external memory,
peripherals such SD/MMC, SSPs, interface.
Single burst request signals. Each peripheral connected
GPDMA assert either burst request single request. burst size programming GPDMA.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory,
peripheral-to-peripheral transfers.
Scatter gather supported through linked lists. This means that
source destination areas have occupy contiguous areas memory.
Hardware channel priority. Each channel specific hardware priority.
channel highest priority channel lowest priority. requests from channels become active same time, channel with highest priority serviced first.
slave programming interface. GPDMA programmed writing
control registers over slave interface.
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Fast communication chip
master transferring data. This interface transfers data when
request goes active.
32-bit master width. Incrementing non-incrementing addressing source destination. Programmable burst size. burst size programmed more
efficiently transfer data. Usually burst size half size FIFO peripheral.
Internal four-word FIFO channel. Supports 8-bit, 16-bit, 32-bit wide transactions. interrupt processor generated completion when
error occurred.
Interrupt masking. error terminal count interrupt requests
masked.
interrupt status. error count interrupt status read
prior masking.
Fast general purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back well current state port pins. LPC2420/2460 accelerated GPIO functions:
GPIO registers relocated local that fastest possible
timing achieved.
Mask registers allow treating sets port bits group, leaving other bits
unchanged.
GPIO registers byte half-word addressable. Entire port value written instruction.
Additionally, port port (total pins) that configured analog input/output programmed generate interrupt rising edge, falling edge, both. edge detection asynchronous, operate when clocks present such during Power-down mode. Each enabled interrupt used wake chip from Power-down mode.
7.8.1 Features
level clear registers allow single instruction clear number
bits port.
Direction control individual bits. default inputs after reset. Backward compatibility with other earlier devices maintained with legacy port
port registers appearing original addresses APB.
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Fast communication chip
Ethernet (LPC2460 only)
Ethernet block contains full featured Mbit/s Mbit/s Ethernet designed provide optimized performance through hardware acceleration. Features include generous suite control registers, half full duplex operation, flow control, control frames, hardware acceleration transmit retry, receive packet filtering wake-up activity. Automatic frame transmission reception with scatter-gather off-loads many operations from CPU.
Ethernet block share dedicated subsystem that used access Ethernet SRAM Ethernet data, control, status information. other traffic LPC2420/2460 takes place different subsystem, effectively separating Ethernet activity from rest system. Ethernet also access off-chip memory EMC, well SRAM located another AHB. However, using memory other than Ethernet SRAM, especially off-chip memory, will slow Ethernet access memory increase loading AHB. Ethernet block interfaces between off-chip Ethernet using Media Independent Interface (MII) Reduced (RMII) protocol on-chip Media Independent Interface Management (MIIM) serial bus.
7.9.1 Features
Ethernet standards support:
Supports Mbit/s Mbit/s devices including Base-T, Base-TX, Base-FX, Base-T4. Fully compliant with IEEE standard 802.3. Fully compliant with 802.3x Full Duplex Flow Control Half Duplex back pressure. Flexible transmit receive frame options. Virtual Local Area Network (VLAN) frame support.
Memory management:
Independent transmit receive buffers memory mapped shared SRAM. managers with scatter/gather arrays frame descriptors. Memory traffic optimized buffering pre-fetching.
Enhanced Ethernet features:
Receive filtering. Multicast broadcast frame support both transmit receive. Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) transmit. Selectable automatic transmit frame padding. Over-length frame support both transmit receive allows length frames. Promiscuous receive mode. Automatic collision back-off frame retransmission. Includes power management clock switching.
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Fast communication chip
Wake-on-LAN power management support allows system wake-up: using receive filters magic frame detection filter.
Physical interface:
Attachment external chip through standard RMII interface. register access available MIIM interface.
7.10 interface
Universal Serial (USB) 4-wire that supports communication between host more 127) peripherals. Host Controller allocates bandwidth attached devices through token-based protocol. supports plugging dynamic configuration devices. transactions initiated Host Controller. LPC2420/2460 interface includes device, Host, Controller. Details typical interfacing solutions found Section 11.1 "Suggested interface solutions" page
7.10.1 device controller
device controller enables Mbit/s data exchange with Host Controller. consists register interface, serial interface engine, endpoint buffer memory, controller. serial interface engine decodes data stream writes data appropriate endpoint buffer. status completed transfer error condition indicated status registers. interrupt also generated enabled. When enabled, controller transfers data between endpoint buffer RAM. 7.10.1.1 Features
Fully compliant with specification (full speed). Supports physical logical) endpoints with endpoint buffer RAM. Supports Control, Bulk, Interrupt Isochronous endpoints. Scalable realization endpoints time. Endpoint Maximum packet size selection maximum specification) software time.
Supports SoftConnect GoodLink features. While Suspend mode, LPC2420/2460 enter reduced
power modes wake activity.
Supports transfers with non-control endpoints. Allows dynamic switching between CPU-controlled modes. Double buffer implementation Bulk Isochronous endpoints.
7.10.2 Host Controller
Host Controller enables full- low-speed data exchange with devices attached bus. consists register interface, serial interface engine controller. register interface complies with OHCI specification.
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7.10.2.1
Features
OHCI compliant. downstream ports. Supports per-port power switching.
7.10.3 Controller
supplement specification that augments capability existing mobile devices peripherals adding host functionality connection peripherals. Controller integrates Host Controller, device controller, master-only interface implement dual-role device functionality. dedicated interface controls external transceiver. 7.10.3.1 Features
Fully compliant with On-The-Go supplement Specification, Revision
1.0a.
Hardware support Host Negotiation Protocol (HNP). Includes programmable timer required Session Request Protocol
(SRP).
Supports transceiver compliant with Transceiver Specification
(CEA-2011), Rev. 1.0.
7.11 controller acceptance filters (LPC2460 only)
Controller Area Network (CAN) serial communications protocol which efficiently supports distributed real-time control with very high level security. domain application ranges from high-speed networks cost multiplex wiring. block intended support multiple buses simultaneously, allowing device used gateway, switch, router between buses industrial automotive applications. Each controller register structure similar SJA1000 PeliCAN Library block, 8-bit registers those devices have been combined 32-bit words allow simultaneous access environment. main operational difference that recognition received Identifiers, known terminology Acceptance Filtering, been removed from controllers centralized global Acceptance Filter.
7.11.1 Features
controllers buses. Data rates Mbit/s each bus. 32-bit register access. Compatible with specification 2.0B, 11898-1. Global Acceptance Filter recognizes 11-bit 29-bit receive identifiers buses.
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Acceptance Filter provide FullCAN-style automatic reception selected
Standard Identifiers.
Full messages generate interrupts. 7.12 10-bit
LPC2420/2460 contains ADC. single 10-bit successive approximation with eight channels.
7.12.1 Features
10-bit successive approximation Input multiplexing among pins Power-down mode Measurement range Vi(VREF) 10-bit conversion time 2.44 Burst conversion mode single multiple inputs Optional conversion transition input Timer Match signal Individual result registers each channel reduce interrupt overhead
7.13 10-bit
allows LPC2420/2460 generate variable analog output. maximum output value Vi(VREF).
7.13.1 Features
10-bit Resistor string architecture Buffered output Power-down mode Selectable output drive
7.14 UARTs
LPC2420/2460 contains four UARTs. addition standard transmit receive data lines, UART1 also provides full modem control handshake interface. UARTs include fractional baud rate generator. Standard baud rates such achieved with crystal frequency above MHz.
7.14.1 Features
Receive Transmit FIFOs. Register locations conform 16C550 industry standard. Receiver FIFO trigger points Built-in fractional baud rate generator covering wide range baud rates without need external crystals particular values.
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Fractional divider baud rate control, auto baud capabilities FIFO control
mechanism that enables software flow control implementation. full support hardware flow control (auto-CTS/RTS).
UART1 equipped with standard modem interface signals. This module also provides
UART3 includes IrDA mode support infrared communication. 7.15 serial controller
LPC2420/2460 contains controller. full duplex serial interface designed handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends bits bits data slave, slave always sends bits bits data master.
7.15.1 Features
Compliant with specification Synchronous, Serial, Full Duplex Communication Combined master slave Maximum data rate eighth input clock rate bits bits transfer
7.16 serial controller
LPC2420/2460 contains controllers. controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. Only single master single slave communicate during given data transfer. supports full duplex transfers, with frames bits bits data flowing from master slave from slave master. practice, often only these data flows carries meaningful data.
7.16.1 Features
Compatible with Motorola SPI, 4-wire SSI, National Semiconductor Microwire
buses
Synchronous serial communication Master slave operation 8-frame FIFOs both transmit receive 4-bit 16-bit frame Maximum data rate half (Master mode) twelfth (Slave mode) input clock rate
transfers supported GPDMA 7.17 SD/MMC card interface
Secure Digital Multimedia Card Interface (MCI) allows access external memory cards. card interface conforms Multimedia Card Specification Version 2.11.
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7.17.1 Features
provides functions specific SD/MMC memory card. These include
clock generation unit, power management control, command data transfer.
Conforms Multimedia Card Specification v2.11. Conforms Secure Digital Memory Card Physical Layer Specification, v0.96. used multimedia card secure digital memory card host.
SD/MMC connected several multimedia cards single secure digital memory card.
supported through GPDMA controller. 7.18 I2C-bus serial controller
LPC2420/2460 contains three I2C-bus controllers. I2C-bus bidirectional, inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver) transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master controlled more than master connected I2C-bus implemented LPC2420/2460 supports rates kbit/s (Fast I2C-bus).
7.18.1 Features
I2C0 standard compliant interface with open-drain pins. I2C1 I2C2 standard pins support powering individual
devices connected same lines.
Easy configure master, slave, master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. 7.19 I2S-bus serial controllers
I2S-bus provides standard communication interface digital audio applications.
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I2S-bus specification defines 3-wire serial using data line, clock line, word select signal. basic connection master, which always master, slave. interface LPC2420/2460 provides separate transmit receive channel, each which operate either master slave.
7.19.1 Features
slave mode.
interface separate input/output channels each which operate master Capable handling 8-bit, 16-bit, 32-bit word sizes. Mono stereo audio data supported. sampling frequency range from (16, 22.05, 44.1,
kHz.
Configurable word select period master mode (separately input output). word FIFO data buffers provided, transmit receive. Generates interrupt requests when buffer levels cross programmable boundary. requests, controlled programmable buffer levels. These connected GPDMA block.
Controls include reset, stop mute options separately input output. 7.20 General purpose 32-bit timers/external event counters
LPC2420/2460 includes four 32-bit Timer/Counters. Timer/Counter designed count cycles system derived clock externally-supplied clock. optionally generate interrupts perform other actions specified timer values, based four match registers. Timer/Counter also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt.
7.20.1 Features
32-bit Timer/Counter with programmable 32-bit prescaler. Counter Timer operation. four 32-bit capture channels timer, that take snapshot timer
value when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
four external outputs corresponding match registers, with following
capabilities: match. HIGH match. Toggle match. nothing match.
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7.21 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2420/2460. Timer designed count cycles system derived clock optionally switch pins, generate interrupts perform other actions when specified timer values occur, based seven match registers. function addition these features based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. dedicated match register controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when PWMMR0 match occurs. Three match registers used provide output with both edges controlled. Again, dedicated match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
7.21.1 Features
LPC2420/2460 PWMs with same operational features. These
operated synchronized fashion setting them both same rate, then enabling both simultaneously. PWM0 acts master PWM1 slave this use.
Counter Timer operation (may peripheral clock capture inputs
clock source).
Seven match registers allow single edge controlled double edge
controlled outputs, both types. match registers also allow: Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs high beginning each cycle unless output constant low. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
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Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler. 7.22 Watchdog timer (WDT)
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
7.22.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) (Tcy(WDCLK) multiples Tcy(WDCLK) Internal oscillator (IRC), peripheral clock. This gives wide range potential timing choices Watchdog operation under different power reduction conditions. also provides ability from entirely internal source that dependent external crystal associated components wiring, increased reliability.
Watchdog Clock (WDCLK) source selected from clock,
7.23 battery
counters measuring time when system power optionally when off. uses little power Power-down mode. LPC2420/2460, clocked separate 32.768 oscillator programmable prescale divider based clock. Also, powered power supply pin, VBAT, which connected battery same supply used rest device.
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VBAT supplies power only Battery RAM. These functions require minimum power operate, which supplied external battery. When rest chip functions stopped power removed, supply alarm output that used external hardware restore chip power resume operation.
7.23.1 Features
Measures passage time maintain calendar clock. Ultra power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Dedicated oscillator programmable prescaler from clock. Dedicated power supply connected battery main alarm output included assist waking when chip power
removed functions except Battery RAM.
Periodic interrupts generated from increments field time registers,
selected fractional second values. This enhancement enables used System Timer.
data SRAM powered VBAT. Battery power supply isolated from rest chip. 7.24 Clocking power control
7.24.1 Crystal oscillators
LPC2420/2460 includes three independent oscillators. These Main Oscillator, Internal oscillator, oscillator. Each oscillator used more than purpose required particular application. three clock sources chosen software drive ultimately CPU. Following reset, LPC2420/2460 will operate from Internal oscillator until switched software. This allows systems operate without external crystal bootloader code operate known frequency. 7.24.1.1 Internal oscillator used clock source WDT, and/or clock that drives subsequently CPU. nominal frequency MHz. trimmed accuracy. Upon power-up chip reset, LPC2420/2460 uses clock source. Software later switch other available clock sources. 7.24.1.2 Main oscillator main oscillator used clock source CPU, with without using PLL. main oscillator operates frequencies MHz. This frequency boosted higher frequency, maximum operating frequency, PLL. clock selected input PLLCLKIN. processor clock frequency referred CCLK elsewhere this document. frequencies
LPC2420_2460_2 B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
PLLCLKIN CCLK same value unless active connected. clock frequency each peripheral selected individually referred PCLK. Refer Section 7.24.2 additional information.
7.24.1.3
oscillator
oscillator used clock source and/or WDT. Also, oscillator used drive CPU.
7.24.2
accepts input clock frequency range MHz. input frequency multiplied high frequency, then divided down provide actual clock used block. input, range MHz, initially divided down value `N', which range 256. This input division provides wide range output frequencies from same input frequency. Following input divider multiplier. This multiply input divider output through Current Controlled Oscillator (CCO) value `M', range through 32768. resulting frequency must range MHz. multiplier works dividing output value then using phase-frequency detector compare divided output multiplier input. error value used adjust frequency. turned bypassed following chip Reset entering Power-down mode. enabled software only. program must configure activate PLL, wait lock, then connect clock source.
7.24.3 Wake-up timer
LPC2420/2460 begins operation power-up when awakened from Power-down mode using oscillator clock source. This allows chip operation resume quickly. main oscillator needed application, software will need enable these features wait them stabilize before they used clock source. When main oscillator initially activated, wake-up timer allows software ensure that main oscillator fully functional before processor uses clock source starts execute instructions. This important power types Reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes wake-up Timer. Wake-up Timer monitors crystal oscillator check whether safe begin code execution. When power applied chip, when some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate VDD(3V3) ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g., capacitors), characteristics oscillator itself under existing ambient conditions.
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
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Semiconductors
LPC2420/2460
Fast communication chip
7.24.4 Power control
LPC2420/2460 supports variety power control features. There three special modes processor power reduction: Idle mode, Sleep mode, Power-down mode. clock rate also controlled needed changing clock sources, reconfiguring values, and/or altering clock divider value. This allows trade-off power versus processing speed based application requirements. addition, Peripheral power control allows shutting down clocks individual on-chip peripherals, allowing fine tuning power consumption eliminating dynamic power peripherals that required application. Each peripherals clock divider which provides even better power control.
LPC2420/2460 also implements separate power domain order allow turning power bulk device while maintaining operation small SRAM, referred Battery RAM. 7.24.4.1 Idle mode Idle mode, execution instructions suspended until either Reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates dynamic power used processor itself, memory systems related controllers, internal buses. 7.24.4.2 Sleep mode Sleep mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Sleep mode logic levels chip pins remain static. output disabled powered down fast wake-up later. oscillator stopped because interrupts used wake-up source. automatically turned disconnected. CCLK clock dividers automatically reset zero. Sleep mode terminated normal operation resumed either Reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Sleep mode reduces chip power consumption very value. wake-up from Sleep mode, used before entering Sleep mode, code execution peripherals activities will resume after cycles expire. main external oscillator used, code execution will resume when 4096 cycles expire. customers need reconfigure clock dividers accordingly. 7.24.4.3 Power-down mode Power-down mode does everything that Sleep mode does also turns oscillator. wake-up from Power-down mode, used before entering Power-down mode, will take start-up. After this cycles will expire before code execution then resumed code running from SRAM. customers need reconfigure clock dividers accordingly after wake-up from Power-down mode.
LPC2420_2460_2 B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
7.24.4.4
Power domains
LPC2420/2460 provides independent power domains that allow bulk device have power removed while maintaining operation Battery RAM.
LPC2420/2460, pads powered (VDD(3V3)) pins, while VDD(DCDC)(3V3) pins power on-chip DC-to-DC converter which turn provides power most peripherals. Although both ring core require supply, different powering schemes used depending actual application requirements. first option assumes that power consumption concern design ties VDD(3V3) VDD(DCDC)(3V3) pins together. This approach requires only power supply both pads, CPU, peripherals. While this solution simple, does support powering down ring fly" while keeping peripherals alive.
second option uses power supplies; supply pads (VDD(3V3)) dedicated supply (VDD(DCDC)(3V3)). Having on-chip DC-DC converter powered independently from ring enables shutting down power supply fly", while peripherals stay active. VBAT supplies power only Battery RAM. These functions require minimum power operate, which supplied external battery. When rest chip functions stopped power removed, supply alarm output that used external hardware restore chip power resume operation.
7.25 System control
7.25.1 Reset
Reset four sources LPC2420/2460: RESET pin, Watchdog reset, power-on reset, BrownOut Detection (BOD) circuit. RESET Schmitt trigger input pin. Assertion chip Reset source, once operating voltage attains usable level, starts Wake-up timer (see description Section 7.24.3 "Wake-up timer"), causing reset remain asserted until external Reset de-asserted, oscillator running, fixed number clocks have passed. Once internal reset removed, processor peripheral registers have been initialized predetermined values LPC2420/2460 continues with booting from external static memory.
7.25.2 Boot process
processor always boots from off-chip static memory bank executing code from address 0x8100 0000 (see Table "LPC2420/2460 memory usage details"). During boot process initiated POR, boot pins P3[15]/D15 P3[14]/D14 sampled, external memory banks configured with same data width. data width determined setting boot pins. Unused address pins configured GPIO. Section 11.2 "Suggested boot memory interface solutions" example address data interfacing.
LPC2420_2460_2 B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Remark: After POR, address ranges chip select chip select swapped. user code residing external boot memory must linked execute from address location 0x8000 0000.
When booting from external memory, interrupt vectors mapped bottom external memory. Once booting over, application must interrupt vectors proper domain.
7.25.3 Brownout detection
LPC2420/2460 includes 2-stage monitoring voltage VDD(3V3) pins. this voltage falls below 2.95 asserts interrupt signal Vectored Interrupt Controller. This signal enabled interrupt Interrupt Enable Register order cause interrupt; not, software monitor signal reading dedicated status register. second stage low-voltage detection asserts Reset generates Reset this reset source enabled software) inactivate LPC2420/2460 when voltage VDD(3V3) pins falls below 2.65 circuit maintains this reset down below which point power-on reset circuitry maintains overall Reset. Both 2.95 2.65 thresholds include some hysteresis. normal operation, this hysteresis allows 2.95 detection reliably interrupt, regularly-executed event loop sense condition.
7.25.4
LPC2460 implements order allow Ethernet block operate without interference caused other system activity. primary AHB, referred AHB1, implemented LPC2420 well includes Vectored Interrupt Controller, GPDMA controller, interface, SRAM. second AHB, referred AHB2, implemented LPC2460 only includes only Ethernet block associated SRAM. addition, bridge provided that allows secondary master AHB1, allowing expansion Ethernet buffer space into off-chip memory unused space memory residing AHB1. summary, masters with access AHB1 ARM7 itself, block, GPDMA function, Ethernet block (via bridge from AHB2). masters with access AHB2 ARM7 Ethernet block.
7.25.5 External interrupt inputs
LPC2420/2460 includes edge sensitive interrupt inputs combined with four level sensitive external interrupt inputs selectable functions. external interrupt inputs optionally used wake processor from Power-down mode.
7.25.6 Memory mapping control
memory mapping control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom Boot ROM, SRAM, external memory. This allows code running different memory spaces have control interrupts.
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
7.26 Emulation debugging
LPC2420/2460 support emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs P2[0] P2[9]. This means that communication, timer, interface peripherals residing other pins available during development debugging phase they when application embedded system itself.
7.26.1 EmbeddedICE
EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access ARM7TDMI-S core present target system. core Debug Communication Channel (DCC) function built-in. allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. accessed coprocessor program running ARM7TDMI-S core. allows JTAG port used sending receiving data without affecting normal program flow. data control registers mapped addresses EmbeddedICE logic. JTAG clock (TCK) must slower than clock (CCLK) JTAG interface operate.
7.26.2 Embedded trace
Since LPC2420/2460 have significant amounts on-chip memories, possible determine processor core operating simply observing external pins. Eprovides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. software debugger allows configuration Eusing JTAG interface displays trace information that been captured. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external Trace Port Analyzer captures trace information under software debugger control. trace port broadcast Instruction trace information. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code traced because this restriction.
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
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Semiconductors
LPC2420/2460
Fast communication chip
7.26.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real-time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using DCC, which present EmbeddedICE logic. LPC2420/2460 contain specific configuration RealMonitor software programmed into on-chip memory.
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) Parameter supply voltage (3.3 Conditions core external rail -0.5 related pins tolerant pins; only valid when VDD(3V3) supply voltage present other pins Tstg Ptot(pack) supply current ground current storage temperature total power dissipation (per package) based package heat transfer, device power consumption human body model; pins
+4.6 +4.6 +4.6 +5.1 +6.0
Unit
VDD(DCDC)(3V3) DC-to-DC converter supply voltage (3.3 VDDA Vi(VBAT) Vi(VREF) analog supply voltage input voltage VBAT input voltage VREF analog input voltage input voltage
-0.5 -0.5 -0.5 -0.5
[2][3]
-0.5
VDD(3V3) +150
supply ground
Vesd
electrostatic discharge voltage
following applies limiting values: This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect VSSIO/VSSCORE unless otherwise noted.
Including voltage outputs 3-state mode. exceed peak current limited times corresponding maximum current. Dependent package type. Human body model: equivalent discharging capacitor through series resistor.
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Static characteristics
Table Static characteristics Tamb commercial applications, unless otherwise specified. Symbol VDD(3V3) VDD(DCDC)(3V3) VDDA Vi(VBAT) Vi(VREF) Parameter supply voltage (3.3 DC-to-DC converter supply voltage (3.3 analog supply voltage input voltage VBAT input voltage VREF LOW-level input current HIGH-level input current OFF-state output current latch-up current pull-up VDD(3V3); pull-down VDD(3V3); pull-up/down -(0.5VDD(3V3)) (1.5VDD(3V3)); Vhys IOHS input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short-circuit output current VDD(3V3)
Conditions core external rail
Typ[1]
VDDA
Unit
Standard port pins, RESET, RTCK Ilatch
configured provide digital function output active
[3][4][5]
VDD(3V3)
VDD(3V3)
IOLS
LOW-level short-circuit VDDA output current pull-down current pull-up current VDD(3V3)
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol Parameter Conditions Typ[1] IDD(DCDC)act(3V3) active mode DC-to-DC VDD(DCDC)(3V3) converter supply Tamb code current (3.3 while(1){} executed from on-chip SRAM; peripherals enabled; PCLK CCLK CCLK CCLK peripherals enabled; PCLK CCLK CCLK CCLK peripherals enabled; PCLK CCLK CCLK CCLK IDD(DCDC)pd(3V3) power-down mode DC-to-DC converter supply current (3.3 active mode battery supply current VDD(DCDC)(3V3) Tamb DC-to-DC converter DC-to-DC converter
[10] [10]
Unit
<tbd> <tbd>
<tbd> <tbd>
<tbd> <tbd>
IBATact
I2C-bus pins (P0[27] P0[28]) Vhys Oscillator pins Vi(XTAL1) Vo(XTAL2) Vi(RTCX1) Vo(RTCX2) pins VBUS
LPC2420_2460_2
HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS VDD(3V3) input voltage XTAL1 output voltage XTAL2 input voltage RTCX1 output voltage RTCX2 OFF-state output current supply voltage
0.7VDD(3V3)
0.3VDD(3V3)
0.5VDD(3V3)
[11]
5.25
B.V. 2008. rights reserved.
Preliminary data sheet
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Semiconductors
LPC2420/2460
Fast communication chip
Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol Vth(rs)se Parameter differential input sensitivity differential common mode voltage range single-ended receiver switching threshold voltage LOW-level output voltage low-/full-speed HIGH-level output voltage (driven) low-/full-speed transceiver capacitance driver output impedance driver which high-speed capable pull-up resistance Conditions |(D+) (D-)| includes range Typ[1]
Unit
0.18
Ctrans ZDRV
with series resistor; steady state drive
[12]
44.1
SoftConnect
Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages typically fails when Vi(VBAT) drops below Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded. Please also note mentioned errata sheet. Accounts voltage drop supply lines. Allowed long current limit does exceed maximum current allowed device. Minimum condition maximum condition
[10] VBAT. [11] VSSIO/VSSCORE [12] Includes external resistors
Table static characteristics VDDA Tamb unless otherwise specified; frequency MHz. Symbol EL(adj) Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error
[1][2][3] [1][4] [1][5]
Conditions
VDDA
Unit
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
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Semiconductors
LPC2420/2460
Fast communication chip
Table static characteristics .continued VDDA Tamb unless otherwise specified; frequency MHz. Symbol Rvsi Parameter gain error absolute error voltage source interface resistance
Conditions: VSSA VDDA monotonic, there missing codes.
Conditions
[1][6] [1][7]
±0.5
Unit
differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure Figure
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
offset error
Fast communication chip
gain error
1023
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
offset error (LSBideal)
VDDA VSSA 1024
002aac046
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
LPC2XXX
AD0[y]SAMPLE
AD0[y]
Rvsi
VEXT
VSSIO, VSSCORE
002aad586
Suggested interface LPC2420/2460 AD0[y]
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Dynamic characteristics
Table Dynamic characteristics pins (full-speed) VDD(3V3),unless otherwise specified. Symbol tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise fall time matching output signal crossover voltage source interval source jitter differential transition transition receiver jitter next transition receiver jitter paired transitions width receiver must reject EOP; Figure must accept EOP; Figure
Conditions
13.8 13.7 +18.5
Unit
Figure Figure
-18.5
tEOPR2
width receiver
Characterized implemented production test. Guaranteed design.
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
Table Dynamic characteristics Tamb commercial applications; VDD(3V3) over specified ranges.[1] Symbol External clock fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL I2C-bus tf(o) interface tsu(SPI_MISO) SPI_MISO set-up time Tamb measured Master mode; Figure oscillator frequency clock cycle time clock HIGH time clock time clock rise time clock fall time pins (P0[27] P0[28]) output fall time Cb[3] Tcy(clk) Tcy(clk) Parameter Conditions Typ[2]
1000
Unit
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. capacitance from
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx
Preliminary data sheet Rev. 02.01 August 2008
B.V. 2008. rights reserved. LPC2420_2460_2
Semiconductors
Table Dynamic characteristics: Static external memory interface Tamb VDD(DCDC)(3V3) VDD(3V3) clock Symbol tCSLAV Read cycle tOELAV tCSLOEL th(D) tCSHOEH tOEHANV tOELOEH tBLSLAV tCSHBLSH tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tBLSLBLSH tWEHANV tWEHDNV tBLSHANV tBLSHDNV
Parameter address valid time parameters[6][7] address valid time time memory access time data hold time HIGH HIGH time HIGH address invalid time HIGH address valid time HIGH HIGH time time time data valid time data valid time HIGH time HIGH time HIGH address invalid time HIGH data invalid time HIGH address invalid time HIGH data invalid time
Conditions
0.20 0.20 Tcy(CCLK) WAITOEN (WAITRD WAITOEN Tcy(CCLK) 9.57 4.22 0.20 (WAITRD WAITOEN Tcy(CCLK)
Unit
Common read write cycles[6]
[2][3]
0.49 0.10
Write cycle parameters[6]
0.49 2.54 2.64 Tcy(CCLK) (WAITWR WAITWEN Tcy(CCLK) (WAITWR WAITWEN 0.20 2.54 0.20 2.54
FastFcommunication Tchip
LPC2420/2460
Except initial access, which case address Tcy(CCLK) earlier. Tcy(CCLK) 1/CCLK. Latest address valid, LOW, data valid. Address valid data valid. Earliest HIGH, HIGH, address change data invalid.
Semiconductors
LPC2420/2460
Fast communication chip
Table Dynamic characteristics: Dynamic external memory interface Tamb VDD(DCDC)(3V3) VDD(3V3) clock Symbol Common td(SV) th(S) td(RASV) th(RAS) td(CASV) th(CAS) td(WV) th(W) td(GV) th(G) td(AV) th(A) tsu(D) th(D) td(QV) th(Q) chip select valid delay time chip select hold time address strobe valid delay time address strobe hold time column address strobe valid delay time column address strobe hold time write valid delay time write hold time output enable valid delay time output enable hold time address valid delay time address hold time data input set-up time data input hold time data output valid delay time data output hold time 0.51 0.57 0.49 1.05 1.02 1.51 1.51 0.98 0.97 0.84 0.84 0.95 0.87 0.81 2.24 2.41 2.65 2.61 Parameter Conditions
1.76 1.95 1.27 1.95 1.86 1.95 4.36
Unit
Read cycle parameters
Write cycle parameters
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
10.1 Timing
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
External clock timing (with amplitude least Vi(RMS)
tPERIOD crossover point differential data lines
crossover point extended
source width: tFEOPT differential data SE0/EOP skew tPERIOD tFDEOP
receiver width: tEOPR1, tEOPR2
002aab561
Differential data-to-EOP transition skew width
shifting edges
sampling edges
MOSI
MISO
tsu(SPI_MISO)
002aad326
MISO line set-up time Master mode
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
tCSLAV
tCSHOEH
addr data tCSLOEL tOELAV tOELOEH tOEHANV th(D)
tBLSLAV
tCSHBLSH
002aad955
External memory read access
tAVCSL tWELWEH tBLSLBLSH tWEHANV tCSLBLSL tWELDV tBLSHANV
tCSLWEL BLS/WE
addr tCSLDV data tWEHDNV tBLSHDNV
002aad956
External memory write access
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
reference clock
td(XXX)
th(XXX)
output signal
tsu(D)
th(D)
input signal
002aad636
Signal timing
Application information
11.1 Suggested interface solutions
VDD(3V3)
USB_UP_LED USB_CONNECT
LPC24XX
soft-connect switch
VBUS USB_D+ USB_D- VSSIO, VSSCORE
002aad587
USB-B connector
LPC2420/2460 interface self-powered device
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
VDD(3V3)
LPC24XX
USB_UP_LED VBUS USB_D+ USB_D- VSSIO, VSSCORE
USB-B connector
002aad588
LPC2420/2460 interface bus-powered device
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
RSTOUT
RESET_N ADR/PSW OE_N/INT_N SPEED SUSPENR4
VBUS
Mini-AB connector
ISP1301
VSSIO, VSSCORE
USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D-1 USB_UP_LED1
INT_N
LPC24XX
USB_PPWR2 USB_OVRCR2
VLM3526-L
OUTA FLAGA
USB_PWRD2 USB_D+2 USB_D-2
VBUS VSSIO, VSSCORE USB-A connector
USB_UP_LED2
002aad589
LPC2420/2460 port configuration: port dual-role device, port host
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 VRESET_N OE_N/INT_N DAT_VP SE0_VM VBUS
MINI-AB connector
ISP1301 LPC24XX
ADR/PSW SPEED SUSPEN
VSSIO, VSSCORE
USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1
INT_N
002aad590
LPC2420/2460 port configuration: VP_VM mode
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
Rev. 02.01 August 2008
Semiconductors
LPC2420/2460
Fast communication chip
USB_UP_LED1 VSSIO, VSSCORE USB_D+1 USB_D-1
USB-A connector
USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA
VBUS
LM3526-L
OUTA
LPC24XX
USB_UP_LED2
USB_CONNECT2 VSSIO, VSSCORE USB_D+2 USB_D-2 VBUS
VBUS USB-B connector
002aad595
LPC2420/2460 port configuration: port device, port host
LPC2420_2460_2
B.V. 2008. rights reserved.
Preliminary data sheet
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Semiconductors
LPC2420/2460
Fast communication chip
USB_UP_LED1 VSSIO, VSSCORE USB_D+1 USB_D-1
USB-A connector
USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA OUTA VVBUS
LPC24XX
LM3526-L
OUTB FLAGB
USB_PPWR2 USB_OVRCR2 USB_PWRD2
VBUS
USB_D+2 USB_D-2
VSSIO, VSSCORE VUSB-A connector
USB_UP_LED2
002aad596
LPC2420/2460 port configuration: port host, port host
11.2 Suggested boot memory interface solutions
`a_m' `a_b' following figures refer highest order address line memory chip highest order microcontroller's address line used respectively.
BLS[1] D[15:8] IO[7:0] A[a_m:0] 8-bit MEMORY BLS[0] D[7:0] IO[7:0] A[a_m:0] 8-bit MEMORY
A[a_b:1]
002aad322
Booting from 8-bit memory chips
LPC2420_2460_2
B.V. 2008. right

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RB095B-90 - RB095B-90   RB095B-90 Datasheet
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