ES1946 Solo-1EPCI AudioDrive® solution implements single-chip audio so
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ES1946 Solo-1EPCI AudioDrive Notebook Solution Data Sheet
ES1946 Solo-1EPCI AudioDrive® solution implements single-chip audio solution, providing high-quality audio processing while maintaining full legacy game compatibility. With dynamic range over ES1946 complies with Microsoft® specifications meets WHQL audio requirements. ES1946 forms complete audio subsystem single chip notebook platforms. ES1946 includes Zoom Video port interface which allows playback MPEG audio using 16-bit stereo music DAC; thus reducing total audio solution chip count. ES1946 incorporates microcontroller, ESFMmusic synthesizer, 16-bit stereo wave DAC, 16-bit stereo music DAC, MPU-401 UART mode serial port, Zoom Video port, serial port interface external wavetable music synthesizer, dual game port, hardware master volume control, control logic with FIFO, interface logic. There three stereo inputs (typically line-in, audio, auxiliary line) mono microphone input. ES1946 also incorporates Spatializer® VBXtechnology, provided Desper Products, Inc., subsidiary Spatializer Audio Laboratories, Inc. This processor expands stereo sound field emitted speakers create resonant sound environment. ES1946 integrates ESS' field-proven hardware design game compatibility with hardware synthesis (ESFMsynthesis) three methods legacy audio control interface: PC/PCI, Distributed DMA, Transparent DMA. Transparent requires sideband signals from core logic chipsets addition standard bus. TDMA compatible with Pentium®, Pentium II®, Pentium Pro® chipsets well standard add-in cards. ES1946 provides serial EEPROM interface ease programming Subsystem Subsystem Vendor ES1946 record, compress, play back voice, sound, music with built-in mixer controls. supports stereo full-duplex operation simultaneous record playback. ESFMsynthesizer extended capabilities within native mode operation providing superior sound power-down capabilities. ES1946 compliant with Advanced Power Management (APM) 1.2, Advanced Configuration Power Interface (ACPI) 1.0, Power Management Interface (PPMI) 1.0. available industry-standard 100-pin Thin Quad Flat Pack (TQFP) package.
FEATURES
Single, high-performance, mixed-signal, 16-bit stereo VLSI chip parallel interface, revision Full native games compatibility, three technologies:
TDMA DDMA PC/PCI High-quality ESFMmusic synthesizer
Dynamic range (SNR) over Serial EEPROM interface SVID resource Integrated Spatializer® VBXstereo audio effects
technology provided Desper Products, Inc., subsidiary Spatializer Audio Laboratories, Inc.
Record Playback Features
Record, compress, play back voice, sound, music 16-bit stereo Programmable independent sample rates from
record playback
Full-duplex operation simultaneous record playback 2-wire hardware volume control down, mute
Inputs Outputs
Stereo inputs line-in, auxiliary audio), auxiliary
mono input microphone
Zoom Video port interface MPEG audio MPU-401 (UART mode) interface wavetable synthesizers
MIDI devices
Integrated dual game port Separate mono input (MONO_IN) mono output
(MONO_OUT) speakerphone
Mixer Features
7-channel mixer with stereo inputs line, audio, auxiliary
line, music synthesizer, digital audio (wave files), mono inputs microphone speakerphone
Programmable 6-bit logarithmic master volume control
Power
Advanced power management meets 1.2, ACPI 1.0,
PPMI standards
Compatibility
Supports games applications Sound Blasterand
Sound BlasterPro
Supports Microsoft® WindowsSound System® Meets WHQL specifications
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ES1946 SOLO-1E DATA SHEET FEATURES
LINE_L LINE_R AUXA_L AUXA_R AUXB_L AUXB_R MONO_IN VDDA GNDA CAP3D PCSPKI PCSPKO
ANALOG SUBSYSTEMS RECORDING SOURCE INPUT VOLUME CONTROL STEREO PROGRAMMABLE MIXER OUTPUT VOLUME MUTE CONTROL RECORD MONITOR SWITCHED CAPACITOR LOW-PASS FILTER 16-BIT STEREO GAME DAC/ADC 16-BIT STEREO MUSIC 16-BIT STEREO SYSTEM HARDWARE VOLUME CONTROL ESFMFM MUSIC SYNTHESIZER SVID CONFIGURATION INTERFACE ZOOM VIDEO PORT WAVETABLE SERIAL PORT MPU-401 SERIAL PORT FIFOs DUAL GAME PORT CLOCK GENERATOR TIMER SW(A-D) T(A-D) MCLK IISCLK IISDATA AOUT_L AOUT_R MONO_OUT
FOUT_L FOUT_R CIN_L CIN_R
PROCESSOR* SPEAKER VOLUME CTRL
DATA BUFFER WITH BYTE FIFO
VOLDN SECS VOLUP SEDI
AD[31:0] INTAB SIRQ PCLK PRSTB CBE[3:0]B FRAMEB IRDYB TRDYB STOPB IDSEL DEVSELB REQB GNTB LOCKB CLKRUNB PCPCIREQB PCPCIGNTB
SEDO IISLR SECLK
MICROCONTROLLER
Processor uses Spatializer® VBX3-D technology provided Desper Products, Inc. subsidiary Spatializer Audio Laboratories, Inc.
Figure Block Diagram
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ES1946 SOLO-1E DATA SHEET CONTENTS
CONTENTS
DESCRIPTION FEATURES CONTENTS FIGURES TABLES PINOUT DESCRIPTION FUNCTIONAL DESCRIPTION Digital Subsystems Analog Subsystems MIXER SCHEMATIC BLOCK DIAGRAM TYPICAL APPLICATION INTERFACING DIGITAL AUDIO Simulation Modes Audio Channels Data Formats Audio Transfers legacy Compatibility Mode Audio Transfers Extended Mode Audio Transfers Native Mode Data Transfers Using Second Audio Channel First Channel CODEC INTERRUPTS Interrupt Status Register Interrupt Mask Register PERIPHERAL INTERFACING Serial Interface Wavetable Interface Joystick MPU-401 Interface MONO_IN MONO_OUT Spatializer® VBXAudio Processor Hardware Master Volume Control Speaker Serial EEPROM Interface ANALOG DESIGN CONSIDERATIONS MONO_IN MONO_OUT Reference Generator Switched-Capacitor Filter Audio Inputs Outputs PROGRAMMING ES1946 Identifying ES1946 Resetting Initializing ES1946 Programming Game Compatibility Selecting DMA/IRQ Policy Programming Native Audio Modes Operation Data Formats Compatibility Mode Programming Extended Mode Programming Programming ES1946 Mixer PROGRAMMING MODEL Register Types Configuration Registers Ports Port Summary Port Descriptions Mixer Registers AUDIO MICROCONTROLLER COMMAND SUMMARY POWER MANAGEMENT CLKRUN Protocol Power Management Interface (PPMI) ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Thermal Characteristics Operating Conditions Operating Current (Typical) TIMING DIAGRAMS TIMING CHARACTERISTICS MECHANICAL DIMENSIONS APPENDIX ES689/ES69X DIGITAL SERIAL INTERFACE APPENDIX INTERFACE REFERENCE Overview Audio Interface Audio Interface Timing LRCLK SCLK SDATA MCLK Port Assignments APPENDIX SCHEMATICS APPENDIX BILL MATERIALS APPENDIX LAYOUT GUIDELINES Layout
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ES1946 SOLO-1E DATA SHEET FIGURES
FIGURES
Figure Block Diagram Figure ES1946 Pinout Figure ES1946 Block Diagram Figure ES1946 Mixer Schematic Block Diagram Figure Data Transfer Modes Figure Implementation ES1946 Figure Dual Joystick/MIDI Connector Figure MIDI Serial Interface Figure Speaker Volume Circuitry Figure Serial EEPROM Typical Application Figure Analog Ground Plane Diagram Figure Reference Generator Diagram Figure Switched-Capacitor Filter Diagram Figure Command Transfer Timing Figure PCLK Timing Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure PRST Timing Signal Timing Serial Input Timing Interface Digital Input Format ES1946 Mechanical Dimensions Example Port Implementation Typical Port Audio Implementation Audio Interface Timing Digital Input Format with SCLK periods ES1946 Schematic Amplifier Interface Analog Components Side Analog Components Both Sides
TABLES
Table Interface Pins Table Extended Mode Audio Controller Registers Table Audio Related Mixer Registers Table ES1946 Interrupt Sources Table Interrupt Status Bits IOBase+7h Table Interface Pins Table Wavetable Interface Pins Table Hardware Software Reset Initializations Table Policy Bits Add-On Cards Table Policy Bits Motherboards Table Emulation Policy Bits Table Comparison Operation Modes Table Uncompressed Transfer Modes Table Uncompressed Transfer Modes Table Command Sequences Playback Table Command Sequence Record Table Sound Blaster Pro/Extended Access Registers Table Read Volume Emulation Table Write Volume Emulation Table Extended Access Mixer Volume Values Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Mixer Input Volume Registers Configuration Registers Summary Supported Legacy Audio Addresses Port Base Addresses Port Summary EEPROM Auto-detect Bytes EEPROM Access Command Summary Sound Blaster Support Register Summary Mixer Registers Summary Mixer Register Default Values Music Source Controller Registers Summary Command Summary Digital Characteristics Analog Characteristics Timing Characteristics Common Clock Frequencies Parameters Audio Signals Port Interface Assignments ES1946 Bill Materials (BOM)
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ES1946 SOLO-1E DATA SHEET PINOUT
PINOUT
AD24 CBE3B IDSEL AD23 VDDD GNDD AD22 AD21 AD20 AD19 AD18 AD17 AD16 CBE2B FRAMEB IRDYB TRDYB DEVSELB STOPB LOCKB CBE1B AD15 AD14 GNDD
AD25 AD26 AD27 AD28 AD29 AD30 AD31 REQB GNTB PCLK PRSTB VDDD CLKRUNB PCPCIGNTB PCPCIREQB INTAB SEDO/IISLR SECLK SIRQ PCSPKI PCSPKO GNDD AOUT_R
ES1946S
Solo-1E 100-pin TQFP
AOUT_L LINE_R LINE_L CIN_R CIN_L FOUT_L FOUT_R VDDA CAP3D GNDA AUXA_R AUXA_L AUXB_R AUXB_L MONO_IN
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VDDD AD13 AD12 AD11 AD10 CBE0B VDDD SECS/VOLDN SEDI/VOLUP IISCLK/MCLK IISDATA/MSD GNDD MONO_OUT
Figure ES1946 Pinout
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ES1946 SOLO-1E DATA SHEET
Name VDDD AD[31:0] Number 1,17,64,80 Description Digital supply voltage 5%).
69-76,79, Address data lines from bus. 82-88,98, 2-7,9-16 77,89,97,8 command/byte enable. Oscillator output. Connect external 14.318 crystal. 24,52,81,100 30:27 34:31 Oscillator/external clock input. Connect external 14.318 crystal clock source (must CMOS levels). Active-low volume decrease button input with internal pull-up. Active-low volume increase button input with internal pull-up. Input with internal pull-down. Music serial clock from external wavetable music synthesizer (ES692). Serial shift clock interface. Input with internal pull-down. Music serial data from external wavetable music synthesizer (ES692). Serial data interface. Digital ground.
CBE[3:0]B VOLDN SECS VOLUP SEDI MCLK IISCLK IISDATA GNDD MONO_OUT MONO_IN T(A-D) SW(A-D) AUXB_L AUXB_R AUXA_L AUXA_R GNDA CAP3D VDDA FOUT_R, FOUT_L CIN_L CIN_R LINE_L LINE_R AOUT_L
Serial EEPROM chip select. Serial data output EEPROM.
Mono output with source select volume control (including mute). This drive external load. Mono input mixer ADC. This internal pull-up CMR. Joystick timer pins. These pins connect positioning variable resistors joysticks. Active-low joystick switch setting inputs. These pins have internal pull-up resistors. Auxiliary input, left. AUXB_L internal pull-up resistor CMR. Auxiliary input, right. AUXB_R internal pull-up resistor CMR. Auxiliary input, left. AUXA_L internal pull-up resistor CMR. Normally intended connection internal external CD-ROM analog output. Auxiliary input, right. AUXA_R internal pull-up resistor CMR. Normally intended connection internal external CD-ROM analog output.
Common mode reference voltage (2.25 5%). Bypass this analog ground with electrolytic parallel with capacitor. Microphone input. internal pull-up resistor CMR. Analog ground. Bypass capacitor analog ground effects. Analog supply voltage 5%). Must greater than equal VDDD
Filter output, right. AC-coupled externally CIN_R remove offsets. Filter output, left. AC-coupled externally CIN_L remove offsets. first channel mixer input. This internal pull-up resistor CMR. first channel mixer input. This internal pull-up resistor CMR. Line input, left. LINE_L internal pull-up resistor CMR. Line input, right. LINE_R internal pull-up resistor CMR.
Line-level stereo output, left. This drive load.
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ES1946 SOLO-1E DATA SHEET
Name AOUT_R PCSPKO PCSPKI SIRQ SECLK SEDO IISLR INTAB PCPCIREQB PCPCIGNTB CLKRUNB PRSTB PCLK GNTB REQB IDSEL FRAMEB IRDYB TRDYB DEVSELB STOPB LOCKB
Number
Description Line-level stereo output, right. This drive load. Analog output PCSPKI with volume control. Normally digital speaker signal input. This signal converted analog signal with volume control appears analog output PCSPKO. MIDI serial input. Schmitt trigger input with internal pull-up resistor. Either MPU-401 Sound Blaster formats.
MIDI serial data output.
Serialized IRQ. (Optional motherboard PC/PCI implementation.) Clock serial EEPROM. Serial data input from EEPROM. Left/Right strobe interface.
interrupt request. PC/PCI serialized DREQ output. (Optional motherboard PC/PCI implementation.) PC/PCI serialized DACK input. (Optional motherboard PC/PCI implementation.) reset. clock. This clock times transactions. busmaster grant. device select configuration. clock state power management.
busmaster request, tri-state output. cycle frame. initiator ready. target ready. device select. stop transaction. lock. parity.
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ES1946 SOLO-1E DATA SHEET FUNCTIONAL
FUNCTIONAL This section shows overall structure ES1946 discusses major functional subunits. major subunits ES1946 shown Figure described briefly following paragraphs.
GNDD VDDD AUXB LINE AUXA PREAMP
FOUT
PCSPKI VOL. CTRL.
FILTER
1-BIT
PCSPKO
GNDA
RECORD MIXER RECORD SOURCE VOLUME CONTROL
16-BIT STEREO CODEC
FIFO INTERFACE REGISTER
VDDA
PLAYBACK MIXER
16-BIT STEREO
FIFO
AD[31:0] INTAB SIRQ PCLK PRSTB CBE[3:0]B FRAMEB IRDYB TRDYB STOPB IDSEL DEVSELB REQB GNTB LOCKB CLKRUNB PCPCIREQB PCPCIGNTB
MICROCONTROLLER
CAP3D AOUT VOLUP* VOLDN* MASTER CTRL
3-D** 16-BIT STEREO
ESFMES689/ES69x SERIAL PORT MPU-401 SER. PORT DUAL GAME PORT
EEPROM
SEDI* SEDO* SECLK SECS*
SERIAL PORT MONO IN/OUT
OSCILLATOR
IISLR* IISCLK* IISDATA* MSD* MCLK*
SW(A-D)
T(A-D)
Some these pins shared with other functions. Processor uses Spatializer VBX3-D technology provided Desper Products, Inc., subsidiary Spatializer Audio Laboratories, Inc.
Figure ES1946 Block Diagram
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ES1946 SOLO-1E DATA SHEET FUNCTIONAL
Digital Subsystems RISC microcontroller game-compatible audio
functions performed embedded microcontroller.
Analog Subsystems Record Playback Mixers seven input stereo
mixers. Each input independent left right 4-bit volume control: Line (CD-audio) Digitized audio (wave files) I2S/FM/ES689/ES69x music MONO_IN/MONO_OUT
firmware data
embedded microcontroller.
Oscillator circuitry support external crystal. FIFO 256-byte FIFO data buffer with
first audio channel 64-byte FIFO data buffer with second audio channel.
interface provides interface
signals. compliant interface supports master/slave.
Dual game port integrated dual game port
joysticks.
16-Bit stereo CODEC audio record playback
first audio channel.
MPU-401 serial port asynchronous serial port MIDI
devices such wavetable synthesizer music keyboard input.
16-Bit stereo system audio playback
second audio channel.
16-Bit stereo music ESFMTM, external
wavetable synthesizer, Zoom Video port.
EEPROM interface serial port connection from
93LC66/46 EEPROM providing Subsystem Subsystem Vendor
1-Bit speaker digital input. Processor processor using SpatializerVBXstereo audio effects technology, provided Desper Products, Inc., subsidiary Spatializer Audio Laboratories, Inc.
ESFMmusic synthesizer high-quality, OPL3
superset synthesizer with voices.
Hardware volume control pushbutton inputs with
internal pull-up devices up/down/mute that used adjust master volume control. mute input defined state when both down inputs simultaneously.
Zoom Video serial port supports sample rates
MPEG audio.
Wavetable serial port serial port connection from
output ES689 ES69x that eliminates need external DAC.
Record source input volume control input
source volume control recording. recording source selected from four choices: Line (CD-audio) Record Mixer
Output volume mute control master volume
controlled either programmed volume control switch inputs. master volume supports bits channel.
Reference generator analog reference voltage
generator.
speaker volume control speaker
supported with 1-bit with volume control. analog output PCSPKO intended externally mixed external amplifier.
Filter switched capacitor low-pass filter. Pre-amp microphone pre-amplifier.
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ES1946 SOLO-1E DATA SHEET MIXER SCHEMATIC BLOCK DIAGRAM
MIXER SCHEMATIC BLOCK DIAGRAM
Output Volume
digital audio
digital audio Bypass
Preamp
LINE I2S/ZV
I2S/FM/ HWWT
Mono Select
Playback Mixer**
MONO AUXA AUXB
Only seven channels shown Windows mixer GUI.
Record Monitor 3-D* Master Volume
AOUT
Record Volume
digital audio
Record Source Record Mixer
Input Volume
Processor uses Spatializer VBX3-D technology provided Desper Products, Inc., subsidiary Spatializer Audio Laboratories, Inc.
Figure ES1946 Mixer Schematic Block Diagram
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ES1946 SOLO-1E DATA SHEET TYPICAL APPLICATION
TYPICAL APPLICATION
VDDA GNDA AUXA_L AUXA_R AUXB_L AUXB_R LINE_L LINE_R MONO_IN Left Right AuxB Left AuxB Right Line Left Line Right Mono
ES1946
78L05 Regulator VDDD GNDD PRSTB PCLK GNTB IDSEL FRAMEB TRDYB STOPB
LOCKB REQB AOUT_L DEVSELB AOUT_R IRDYB AD[31:0] MONO_OUT PCSPKO CEB[3:0]B CLKRUNB FOUT_L INTAB CIN_L FOUT_R CIN_R 14.31818 SIRQ PCPCIGNTB PCPCIREQB
Stereo Amplifier
Sideband Connector PC/PCI Implementation IISDATA IISCLK IISLR /SED CAP3D
Zoom Video Audio 93LC46/66 (EEPROM) Hardware Volume DOWN
SECLK
VOLUP/SEDI VOLDN/SECS PCSPKI
From Timer Chip
Game Port
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ES1946 SOLO-1E DATA SHEET INTERFACING
INTERFACING
ES1946 compliant with parallel interface, version 2.2. This section discusses interfacing bus, items relating configuration bus. Table Interface Pins
Pins AD[31:0] CBE[3:0]B CLKRUNB DEVSELB FRAMEB GNTB IDSEL INTAB IRDYB LOCKB PCLK PCPCIGNTB PCPCIREQB PRSTB REQB STOPB TRDYB Descriptions Address data lines from bus. command/byte enable. clock state power management. (optional). device select. cycle frame. busmaster grant. device select configuration. interrupt request. initiator ready. lock. parity. clock. This clock times transactions. PC/PCI serialized DACK input. (Motherboard implementation). PC/PCI serialized DREQ output (Motherboard implementation). reset. busmaster request, tri-state output. stop transaction. target ready.
Table shows pins used interface ES1946 bus.
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ES1946 SOLO-1E DATA SHEET DIGITAL AUDIO
DIGITAL AUDIO
Simulation Modes
Native mode Master used simulate when ES1946 configured native device under Windows. "Programming Native Audio" page more information. Legacy mode used native applications. ES1946 uses TDMA, DDMA, PCPCI simulate DMA. "Programming Game Compatibility" page more information. Once ES1946 programmed, Legacy mode used transparent application using DMA.
Audio Transfers legacy Compatibility Mode
first audio channel programmed using standard commands which support Sound Blaster functionality. These commands written chip through port SBBase+Ch. When programming first audio channel transfers, following modes used:
Direct mode modes
Normal Auto-Initialize addition, both Normal mode AutoInitialize mode special High-Speed mode. Direct Mode Direct mode, timing transfers handled application program. example, system timer reprogrammed generate interrupts desired sample rate. each system timer interrupt, command 10h, 11h, 20h, issued followed sample. Polling Write-Buffer-Available flag (SBBase+Ch [bit required before writing command between writing command data. NOTE: switched capacitor filter initialized reset intended sample rate kHz. Direct mode, application wish adjust this filter appropriate actual sample rate. this programming timer with command just application were using mode. Modes mode, programmable timer ES1946 controls rate which samples sent CODEC. timer programmed using command 40h, which also sets programmable filters inside ES1946. ES1946 firmware maintains internal FIFO levels 16-bit transfers, levels 8-bit transfers) that filled transfers emptied timed transfers DAC. Before transfer, application first programs controller desired transfer size address, then programs ES1946 with same size information. transfer, ES1946 generates interrupt request, indicating that current block transfer complete. FIFO gives application program sufficient time respond interrupt initiate next block transfer. ES1946 supports both Normal mode AutoInitialize mode.
Audio Channels
ES1946 incorporates digital audio channels. Audio first audio channel. This channel used Sound Blaster compatible DMA, Extended mode DMA, programmed I/O. used either record playback. mode, this channel uses TDMA, DDMA, PCPCI emulate bus. Since most games default channel first audio channel should ideally assigned channel However, possible audio three channels (0,1,3) through configuration registers. Windows mode, this channel Master DMA. resources required. Audio second audio channel. This channel used audio playback full-duplex mode. Audio uses Mastering with burst transfers minimize access. Digital Audio
Audio Audio
Compatibility Mode
Extended Mode
Mode
Direct Mode
Mode
Programmed
Mode
Figure Data Transfer Modes
Data Formats
"Data Formats" page
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ES1946 SOLO-1E DATA SHEET DIGITAL AUDIO
Normal Mode
Modes Extended mode supports both Normal Auto-Initialize mode. addition Normal mode Auto-Initialize mode both support Single Demand transfer modes.
Single Transfer
Normal mode transfers, controller must initialized ES1946 commanded every block that transferred.
Auto-Initialize Mode
Auto-Initialize mode, transfer continuous, circular buffer, ES1946 generates interrupt transition between buffer halves. this mode controller ES1946 only need once.
High-Speed Mode
byte transferred request.
Demand Transfer
ES1946 supports mono 8-bit transfers rate kHz. Mono 16-bit transfers supported rate kHz. special "High-Speed mode" allows 8-bit sampling ADC, using commands (auto-initialize) (normal). automatic gain control (AGC) performed. input volume controlled with command DDh.
reduce number requests necessary make transfer, four bytes transferred request (DRQ). Using Demand transfer enables multiple acknowledges each request. description mode including Normal mode Auto-Initialize mode "DMA Modes" page Extended Mode Audio Controller Registers following registers control operation first audio channel Extended mode: Table Extended Mode Audio Controller Registers
Address Name
Audio Sample Rate Generator register Audio Filter Clock Divider register Audio Transfer Count Reload register byte Audio Transfer Count Reload register high byte Legacy Audio Interrupt Control register Audio Control register Input Volume Control register Audio Control register Audio Control register Audio Transfer Type register
Audio Transfers Extended Mode
first audio channel programmed using controller registers internal ES1946. commands written controller registers written chip through port SBBase+Ch. When programming first audio channel transfers, following modes used:
Programmed modes
Normal (Single Demand transfer) Auto-Initialize (Single Demand transfer) addition, both normal mode autoinitialize mode Single transfer Demand transfer modes. Programmed some applications, mode suitable available data transfer, possible take exclusive control system transfers. these situations, block transfers within interrupt handler. OUTSB instruction 80x86 family transfers data from memory port specified register. INSB instruction complementary function. ES1946 port SBBase+Fh block transfers. transfers FIFO nearly identical process, except that access port SBBase+Fh replaces cycle. details about programmed operation "Extended Mode Programmed Operation" page
Audio Transfers Native Mode
Unlike game environments, ES1946 completely controlled drivers. This ES1946 perform Master first channel audio data transfers under Windows other operating systems).
Data Transfers Using Second Audio Channel
second audio channel programmed using mixer registers through 7Ch. commands written mixer registers written chip through ports SBBase+4h SBBase+5h. second audio channel always uses Master transfers instead ISA-like DMA. IOBase+0h IOBase+6h control Audio Master DMA. Both normal auto-initialize modes available, ISA-DMA. counts Audio must multiples bytes, that ES1946 performs DWord burst transfers.
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ES1946 SOLO-1E DATA SHEET DIGITAL AUDIO
Audio Related Mixer Registers following registers control operations second audio channel: Table Audio Related Mixer Registers
Address Name
Audio Sample Rate register Audio Mode register Audio Filter Clock Rate register Audio Transfer Count Reload register byte Audio Transfer Count Reload register high byte Audio Control register Audio Control register Audio Volume Control register
output filtered sent mixer. After reset, input mixer from first audio channel muted prevent pops. ES1946 maintains status flag determine input mixer from first audio channel enabled disabled. Command returns status flag (0h=disabled FFh=enabled). command enable input mixer from first audio channel command disable input. play sound without resetting beforehand, when status analog circuits clear, mute input mixer with command D3h, then direction level using direct-to-DAC command: 10h, Wait milliseconds analog circuitry settle before enabling voice channel with command D1h. sounds still occur level left value other than mid-level (code 8-bit scale) previous play operation. prevent this, always finish transfer with command level mid-range: 10h,
First Channel CODEC
CODEC first audio channel cannot perform stereo simultaneously. either stereo stereo ADC. After reset, CODEC operations. command causes switch "direction," subsequent command switches converter back "direction."
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ES1946 SOLO-1E DATA SHEET INTERRUPTS
INTERRUPTS
There four interrupt sources ES1946, shown Table Table ES1946 Interrupt Sources
Interrupt Source Audio Description interrupt used first channel (Sound Blaster compatible DMA, Extended mode DMA, Extended mode programmed I/O), well MIDI receive that supports Sound Blaster functionality. Controller register controls this interrupt Extended mode programmed I/O. This interrupt request cleared hardware software reset, read from port SBBase+0Eh. interrupt request polled reading from port SBBase+0Ch IOBase+07h. optional interrupt second channel. ES1946 operate full-duplex mode using channels. Audio interrupt masked mixer register 7Ah. polled cleared reading writing register 7Ah.
Audio
Hardware Volume Hardware volume activity interrupt. This interrupt occurs when hardware volume controls changes state. mixer register mask this interrupt. interrupt request polled reading register 64h. interrupt request cleared writing value register 66h. MPU-401 MPU-401 interrupt occurs when MIDI byte received. goes when byte read from MIDI FIFO goes high again quickly there additional bytes FIFO. interrupt status same Read-Data-Available status flag MPU-401 status register. MPU-401 interrupt masked mixer register 64h.
Interrupt Status Register
Port IOBase+7h configuration device read quickly find which ES1946 interrupt sources active. bits are: Table Interrupt Status Bits IOBase+7h
Description Audio interrupt request Audio interrupt request AND'ed with mixer register Hardware volume interrupt request AND'ed with mixer register MPU-401 receive interrupt request AND'ed with mixer register
useful because ES1946 shares interrupts. example, assume that Audio Audio Hardware Volume, MPU-401 share same interrupt Windows. When returning from Windows DOS, Hardware Volume, MPU-401, Audio interrupts masked setting appropriate bits second within interrupt handler. first thing interrupt handler mask interrupt sources mapped interrupt handler. Then, polled decide which sources process. Just before exiting interrupt handler, restored. unprocessed interrupt remains active, generates interrupt request because interrupt de-asserted during masked period then asserted when interrupt sources were unmasked. Also, while interrupts masked, individual interrupt sources change state number times without generating false interrupt request.
Interrupt Mask Register
Port IOBase+7h used mask four interrupt sources, with exception Audio interrupt. Audio interrupt request enabled IOBase+7h, when Configuration register (Legacy Audio Control register) mask bits used force interrupt source zero, without putting interrupt highimpedance state. Each AND'ed with corresponding interrupt source. This register zeros hardware reset. Interrupt Status register (ISR) affected state Interrupt Mask register (IMR). That reflects status interrupt request lines before being masked IMR.
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ES1946 SOLO-1E DATA SHEET PERIPHERAL INTERFACING
PERIPHERAL INTERFACING
Serial Interface
Three input pins, IISDATA, IISCLK, IISLR, used serial interface between external device stereo music within ES1946. IISDATA, IISCLK, IISLR left floating connected ground serial interface used. typical applications serial interface MPEG audio digital audio.
Serial Interface Timing This section discusses serial interface signals. signals when port configured with ES689/ ES69x wavetable synthesizer defined Wavetable Interface section. Three signals used I2S: IISCLK shift clock. maximum rate MHz. minimum number IISCLK periods IISLR period number greater than equal acceptable. Sample synchronization signal. maximum sample rate kHz.
IISLR
IISDATA
CARD
IISCLK IISLR
IISDATA Serial data. Within ES1946, IISLR IISDATA sampled rising edge IISCLK. Figure Figure detailed timing.
ES1946
Figure Implementation ES1946
Wavetable Interface
ES1946 contains synchronous serial interface connection wavetable music synthesizer. Table Wavetable Interface Pins
MCLK Description Serial clock from external ES689/ES69x music synthesizer. Input with pull-down. Serial data from external ES689/ES69x music synthesizer. When both MCLK active, stereo DACs normally used synthesizer acquired external ES689/ES69x. normal output blocked. Input with pull-down.
Table Interface Pins
IISDATA IISCLK IISLR Description Serial data interface. This internal pull-down GNDD. Serial shift clock interface. This internal pull-down GNDD. Left/Right signal interface. This internal pull-down GNDD.
Serial Interface Software Enable mixer register enables data connection interface.
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ES1946 SOLO-1E DATA SHEET PERIPHERAL INTERFACING
Joystick MPU-401 Interface
MPU-401 UART Mode There MIDI interface ES1946, MPU-401 "UART mode" compatible serial port. MPU-401 superior method MIDI serial because does interfere with Sound Blaster commands. MPU-401 requires interrupt channel MIDI receive. This interrupt should selected using mixer register 64h. should different than interrupt selected audio interrupts. Joystick MIDI External Interface joystick portion ES1946 reference design identical that standard game control adaptor game port. compatible joystick connected 15-pin D-sub connector. supports standard joystick-compatible software. system already game card port, remove game card. multiple joysticks required, joystick conversion cable. This cable uses 15-pin D-sub male connector end, 15-pin D-sub female connectors other end. signals this cable have direct pin-to-pin connection, except pins male
connector, pins should left without connection. female connectors, internally connected internally connected dual joystick MIDI port take only slot system, leaving room other cards. Figure shows dual joystick/MIDI connector configuration.
Joystick
Joystick
X-axis
X-axis
Button Button
Y-axis
Button
Button
Y-axis
MIDI MIDI
Figure Dual Joystick/MIDI Connector
Figure shows MIDI serial interface adaptor from joystick/MIDI connector.
GAME PORT
2.2K 5.6K ISO1
2N3904 220pF
2N3904
220pF
MIDI
DB15P
MIDI
Figure MIDI Serial Interface
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ES1946 SOLO-1E DATA SHEET PERIPHERAL INTERFACING
MONO_IN MONO_OUT
MONO_IN line-level analog input. MONO_IN input playback mixer record mixer. mixer volumes controlled mixer registers (playback) (record). Alternately, MONO_IN mixed with AOUT_L AOUT_R after master volume stage. mixer register 7Dh, when high, enables MONO_IN mixed directly (unity gain) with AOUT_L AOUT_R. MONO_OUT line-level mono output. During powerdown during opamp calibration, MONO_OUT held AOUT_L AOUT_R) internal, highimpedance resistor divider. MONO_OUT selected from among four sources bits mixer register 7Dh.
Mixer Register MONO_OUT Source Mute (CMR) First channel filter output (actually CIN_R pin) Second channel DAC, right channel Mono record level stage outputs
Spatializer® VBXAudio Processor
ES1946 incorporates embedded Spatializer® VBXstereo audio processor provided Desper Products, Inc., subsidiary Spatializer Audio Laboratories, Inc. positioned between output playback mixer master volume controls produces wider perceived stereo effect. effect enabled register amount effect controlled directly programming Effect Level register 52h.
Hardware Master Volume Control
external pins, VOLUP VOLDN, connected external momentary switches ground implement hardware master volume controls. Pressing these buttons produces signal inputs thereby changes master volume. MUTE emulated state where both VOLUP VOLDN inputs simultaneously. down buttons produce single step change volume when they first pressed. these buttons held down, they enter fast-scrolling mode. single step change either volume unit (.75 three volume units (2.25 dB). scrolling mode, step change always volume unit. inputs have debounce circuitry within ES1946. Hold each input milliseconds more recognized valid button press. Hold each input high milliseconds more between button presses. software option allows debounce time reduced from milliseconds microseconds. Normally hardware volume controls directly change master volume registers produce interrupt each change. However, ES1946 programmed that hardware volume controls directly change master volume registers. This called "split mode", which hardware volume control counters split from master volume registers. Pressing hardware volume control button changes hardware volume counters produces interrupt. host software read hardware volume counters update master volume registers needed. Split mode enabled mixer register 64h. support mixer master volume control, write mixer registers translates automatically into writes master volume registers. Since register only 3-bit resolution channel, register only 4-bit resolution channel, translation circuit included ES1946 that translates 4-bit volume
Normally bits both zero, that MONO_OUT muted. When MONO_OUT buffered version input CIN_R. CIN_R typically right channel output, filtered first channel switchedcapacitor filter. right channel used ADC, CIN_R will right channel input. MONO_OUT used this application digitized audio playback through first channel DMA, right channel DAC. When MONO_OUT buffered version second channel, right channel DAC. this case, second channel play digitized audio through MONO_OUT. When MONO_OUT buffered version mono record level stage left right outputs. This gives utmost flexibility source sources MONO_OUT. record source select record levels programmed generate combination sources volumes MONO_OUT.
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values into 6-bit volume mute that used master volume registers. Support these mixer registers defeated under software control. Reading master volume registers also requires translation circuit translate 6-bit mute master volumes into 4-bit master volume numbers registers 32h.
Serial EEPROM Interface
ES1946 gets Subsystem (SID) Subsystem Vendor (SVID) from external EEPROM device. external EEPROM accessed ES1946 immediately after PRSTB becomes inactive. ES1946 supports 93LC46 93LC66 serial EEPROMs. EEPROM interface shared with hardware volume controls. When EEPROM interface active, volume controls deactivated. Figure EEPROM FORMAT first byte should EEPROM identifier
Device 93LC46 93LC66 Byte
Speaker
Speaker supported with 1-bit with volume control. analog output PCSPKO intended externally mixed external amplifier. Speaker Volume Control When PCSPKI signal high, resistive path analog power enabled. value resistor selected from among choices control amplitude output signal.
second byte signature byte ES1941 ES1946. signature byte must 38h. Example EEPROM Code
VDDD PCSPKI
PCSPKO
GNDA
Figure Speaker Volume Circuitry
SVID.DAT Example EEPROM (93LC46) Data SVID 1766h Sub-system Vendor Corp) 1480h Sub-system (Model VC1480) 46H, Signature 93LC46/1946 14H, 17H, SVID SVID.DAT
With external circuit shown Figure amplitude square wave output PCSPKO should approximately VDDD/2 maximum volume, i.e., internal resistor approximately ohms 30%). other levels relative this amplitude follows: mute, -24dB, -21dB, -18dB, -15dB, -12dB, -9dB, -6dB purpose circuit, beyond volume control speaker, prevent digital noise from speaker signal being mixed into analog signal. This circuit provides clean analog signal. output either mixed with AOUT_L AOUT_R pins externally used drive simple transistor amplifier drive speaker dedicated producing beeps.
ES1946
93LC46/66
(serial EEPROM) SEDI/VOLUP SEDO SECLK SECS/VOLDN
down
Figure Serial EEPROM Typical Application
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Programming EEPROM After reset, ES1946 reads bytes from EEPROM. ES1946 read, write, erase bits stored EEPROM. ES1946 accesses EEPROM means three ports. IOBase+2Dh IOBase+2Eh IOBase+2Fh Device Select EEPROM Data EEPROM Command
bytes read from EEPROM void eepromRead (int eeaddr, *eedata, gotoAddr(eeaddr); (i=0, p=eedata; i<n; i++) outp(iobase+0x2f, READ); pause (1); *p++ (iobase+0x2e); pause (1); erase data void eepromEraseAll(void) outp(iobase+0x2f, EWEN); //enable erase/write pause(1); outp(iobase+0x2f, ERAL); pause(15); //wait msec outp(iobase+0x2f, EWDS); //disable erase/write void gotoAddr (int addr) (iobase+0x2f); //reset eeprom address pause (1); (i=0; i<addr; i++) outp (iobase+0x2f, READ); pause (1); (void) (iobase+0x2e); pause (1);
EEPROM Access Example
This example illustrates usage EEPROM #define #define #define #define #define #define #define READ EWEN EWDS WRITE WRAL ERASE ERAL
select device type. must called before other routine called, EEPROM didn't contain right Device Identifier (first byte) boot time. void select_eeprom (int dev) switch (dev) case 0x46: outp (iobase+0x2d, 0x01); break; default: outp (iobase+0x2d, 0x03); break; pause (2); bytes write EEPROM void eepromWrite (int eeaddr, *eedata, unsigned index; char line[10]; outp (iobase+0x2f, EWEN); //enable erase/write pause (1); gotoAddr (eeaddr); (i=0; i<n; i++) outp (iobase+0x2e, *eedata++); outp (iobase+0x2f, WRITE); pause (10);// wait msec outp (iobase+0x2f, EWDS); //disable erase/write
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ES1946 SOLO-1E DATA SHEET ANALOG DESIGN CONSIDERATIONS
ANALOG DESIGN CONSIDERATIONS
This section describes design considerations related inputs outputs analog signals related pins chip.
Switched-Capacitor Filter
outputs FOUT_L FOUT_R filters must AC-coupled inputs CIN_L CIN_R. This provides blocking opportunity low-pass filtering with capacitors analog ground these inputs.
MONO_IN MONO_OUT
MONO_IN MONO_OUT bound digital signals either side. When laying PCB, MONO_IN MONO_OUT must analog ground plane well isolated from digital ground plane.
ES1946
FOUT_L CIN_L
ES1946
FOUT_R CIN_R MONO_IN
Figure Switched-Capacitor Filter Diagram
IISDATA/MSD MONO_OUT
Analog Ground Plane
Audio Inputs Outputs
Analog inputs MIC, MONO_IN, LINE_L, LINE_R, AUXA_L, AUXA_R, AUXB_L, AUXB_R should capacitively coupled their respective input signals. have pull-up resistors CMR. ES1946 analog outputs MONO_OUT, AOUT_L and, AOUT_R should AC-coupled amplifier, volume control potentiometer, line-level outputs.
Figure Analog Ground Plane Diagram
Reference Generator
Reference generator shown bypassed analog ground.
ES1946
Figure Reference Generator Diagram
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PROGRAMMING ES1946
Identifying ES1946
ES1946 device identified using standard configuration register. Offset contains registered Vendor (VID), which 125Dh. Offset contains assigned Device (DID), which ES1946 1969h. addition, ES1946 Subsystem Vendor (SVID) Subsystem (SID). These registers default values read from EEPROM immediately after PRSTB becomes inactive. EEPROM signature check fails EEPROM connected, example), default values become 125Dh 8888h respectively. ES1946 mounted motherboard, system BIOS program these registers that EEPROM needed. reset ES1946 software: SBBase+6h. Delay short period reading back SBBase+6h. Clear SBBase+6h. loop lasting least millisecond, poll port SBBase+Eh Read Data Available. Exit loop only high SBBase+Ah returns 0AAh. Table Hardware Software Reset Initializations
Initialization Disable Extended Mode Reset timer divider filter Stop transactions progress Clear active interrupt requests Disable voice input mixer Compatibility/Extended mode counters 2048 bytes audio CODEC direction volumes mid-level input volume 8-bit recording with maximum other mixer registers default values Internal FIFO extended mode Configuration registers Hardware Reset Software Reset
Resetting Initializing ES1946
ES1946 chip reset ways: hardware software reset. hardware reset signal comes from initializes:
configuration registers microcontroller internal FIFOs ESFM synthesizer mixer registers analog mixer CODECs
software reset controlled port SBBase+6h initializes:
microcontroller ESFM synthesizer analog mixer CODEC
SBBase+6h reset internal FIFOs.
After system powers BIOS initializes header portion (00h-3Fh) configuration space. BIOS also program SVID registers. After BIOS initializes device, ES1946 Native mode. configuration registers should properly before ES1946 accesses other registers.
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Programming Game Compatibility
ES1946 fully compatible legacy games with Sound Blaster functionality. achieve high compatibility legacy device bus, major issues need addressed. first issue concerns second issue concerns IRQ. emulate bus, ES1946 employ three different protocols: TDMA DDMA PC/PCI Transparent DMA, chipset independent mechanism Distributed DMA, must supported chipset DMA, must supported chipset
with non-Intel chipset, contact your FAE. policy configured Configuration register 50h, bits [10:8]. Table Policy Bits Add-On Cards
Chipset Intel 430FX (Triton) Intel 430HX (Triton-2) Intel 430VX (Triton-3) Intel 430TX Intel 440LX Intel 440BX/EX Protocol TDMA TDMA TDMA DDMA TDMA DDMA TDMA Policy
Once three protocols ES1946 seen device.
TDMA
Table Policy Bits Motherboards
Chipset Intel 430FX (Triton) Intel 430VX (Triton-3) Intel 430TX Intel 440LX Protocol TDMA TDMA DDMA PCPCI TDMA PCPCI Intel 440BX/EX DDMA TDMA Policy
TDMA, ES1946 snoops transactions legacy controller device then performs master transaction complete DMA.
DDMA
Intel 430HX (Triton-2) TDMA
DDMA, central resource (PCI chipset) includes remap engine. transactions legacy DMACs remapped each client (such ES1946) remap engine. ES1946 then performs master transaction.
PC/PCI
PC/PCI DMA, central resource (PCI chipset) performs PC/PCI cycles, which sideband signals standard bus. ES1946 then acts slave device during DMA. second issue concerns IRQ. edge triggered while level sensitive. configuring policy bits Configuration register 50h, ES1946 emulate IRQ. Setting Legacy Audio Control register (LACR, Configuration register 40h) allows ES1946 decode legacy audio addresses.
emulate bus, program emulation policy bits, unless SERIRQ used. Table lists program Policy bits. Program policy bits according level selected ES1946's INTAB pin. policy configured Configuration register 50h, bits [14:13]. Table Emulation Policy Bits
(INTAB Pin) 5/7/9/10 IRQs other than 5/7/9/10 Policy
Selecting DMA/IRQ Policy
Because chipsets support same protocols, policy should selected according chipset use. Table Table list recommended policies Intel chipsets add-on cards motherboards respectively. find which policy
Configuration register BIOS, indicates which ES1946 INTAB using. Configuration register (Legacy Audio Control register), bits[9:8] indicate which used game.
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Programming Native Audio
When ES1946 configured native device, audio channels must configured properly, shown procedures below. ES1946 master device. Configuring Audio Native Mode DDMA Control register. BIOS reserves regions bytes), stores them VCBase register. Copy VCBase register (PCI Configuration register 18h) DDMA Control register (PCI Configuration register 60h), with set. Select DMA/IRQ policy. policy should DDMA (PCI Configuration register 50h, bits 10:8 000). emulation should disabled (PCI Configuration register 50h, bits 14:13 00). Program legacy compatible module. "Extended Mode Audio Operation" page Program controller. Instead using 8237 (DMAC), program should built-in DMAC inside ES1946. built-in DMAC accessed address range DDMABase+0h DDMABase+Fh. following sequence program built-in DMAC. Master reset. Write data DDMABase+Dh. Mask DMA. Write DDMABase+Fh. mode. Write mode value DDMA Base+Bh. Setup base address counts. Write base address DDMABase+0h. Write base count DDMABase+4h. Unmask DMA. Write DDMABase+Fh.
Configuring Audio Native Mode Unlike programming Audio native mode, spaces allocated BIOS. Program legacy AudioDrive® controller module. "Second Audio Channel Operation" page Program controller. Instead using 8237 (DMAC), program should built-in DMAC inside ES1946. built-in DMAC accessed address range IOBase+0h IOBase+6h. following sequence program built-in DMAC. Disable DMA. Clear IOBase+6h. Preserve other bits. mode. Program IOBase+6h. Preserve other bits. base address counts. Write base address IOBase+0h. Write base count IOBase+4h. Enable DMA. IOBase+6h. Preserve other bits.
Modes Operation
ES1946 operate first audio channel modes: Compatibility mode Extended mode. both modes, mixer controller registers enables application software control analog mixer, record source, output volume. Programming ES1946 Enhanced Mixer described later this document. "Programming ES1946 Mixer" page Compatibility Mode Description first mode, Compatibility mode, compatible legacy DOS. This default mode after reset. this mode, ES1946 microcontroller intermediary functions between CODEC. ES1946 microcontroller performs limited FIFO functions using bytes internal memory. Extended Mode Description ES1946 also supports Extended mode operation. this case, 256-byte FIFO used intermediary between Control registers, various Extended mode controller registers used control. ES1946 microcontroller mostly idle this mode. control handled dedicated logic. Programming Extended mode operation requires accessing various control registers with ES1946 commands.
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Table Comparison Operation Modes
Compatibility Mode (Legacy DOS) Legacy compatible FIFO Size Mono 8-bit ADC, Mono 16-bit ADC, Stereo 8-bit Stereo 8-bit Stereo 16-bit Stereo 16-bit Signed/Unsigned Control Automatic Gain Control during recording Programmed block transfer FIFO status flags Auto reload Time base programmable timer jitter bytes (firmware managed) Yes, Yes, Yes, Yes, Yes, Firmware controlled, kHz, mono only microseconds Extended Mode bytes (hardware managed) Yes, Yes, Yes, Yes, Yes, Yes, Depends XTAL
Mixing Modes Recommended Avoid mixing Extended mode commands with Compatibility mode commands. Audio Enable/ Disable commands safe when using Extended mode process DAC. However, other Compatibility mode commands cause problems. Extended mode commands used channels before entering Compatibility mode.
Legacy Compatible Data Formats There four formats available from combination following options:
8-bit 16-bit Mono stereo
8-bit samples unsigned, ranging from 0FFh, with DC-levels around 80h. 16-bit samples unsigned, ranging from 0000h 0FFFFh, with DC-levels around 8000h. Stereo Transfers Compatibility Mode Stereo transfers only available using rather than Direct mode commands. perform stereo transfer, first mixer register high. Then timer divider twice per-channel sample rate. maximum stereo transfer rate 8-bit data channel, this case program timer divider were mono. maximum stereo transfer rate 16-bit data channel. Stereo transfers 16-bit data allowed Compatibility mode. 8-bit data, ES1946 expects first byte transferred right channel, subsequent bytes alternate left, right etc.
Data Formats
This section briefly describes different audio data formats used ES1946. Compressed Data Formats ES1946 supports ADPCM compressed sound operations. ADPCM transferred only using transfer. first block multiple-block transfer uses different command than subsequent blocks. first byte first block called reference byte. Compatibility mode when transferring compressed data.
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16-bit data, ES1946 expects transfers multiple with repeating groups order: left byte left high byte right byte right high byte ES1946 Data Formats (Extended Mode Audio There eight formats available from combination following three options:
Commands such which control Audio mixer input enable/disable status, command D0h, which suspends pauses DMA, acceptable send during this window. ES1946 chip sets Busy flag when command window longer open. Application software must send command within microseconds after Busy flag goes high command will confused with data. Sending command within command window easy polling done with interrupts disabled. example sending command during DMA, consider case where application wants send command middle transfer. application disables interrupts polls Busy flag. Because FIFO rules used determining command window, possible current transfer complete while waiting Busy flag clear. this event, command function, pending interrupt request from completion generated. interrupt request cleared reading port SBBase+Eh before enabling interrupts having signaling interrupt handler that inactive that does start transfer. Figure shows timing considerations sending command.
Mono stereo 8-bit 16-bit Signed unsigned
stereo data, data stream always alternates channels successive samples: first left, then right. 16-bit data, byte always precedes high byte. Sending Commands During Operations useful understand detailed operation sending command during DMA. ES1946 uses Audio FIFO transfers from CODEC. When FIFO full case DAC) empty case ADC), requests temporarily suspended Busy flag (bit port SBBase+Ch) cleared. This opens window opportunity send command ES1946.
BUSY FLAG POLL BUSY WRITE COMMAND WRITE COMMAND
Figure Command Transfer Timing
µsec
Compatibility Mode Programming
This section describes Compatibility mode programming. Compatibility Mode Operation Reset Write port SBBase+6h. play sound without resetting ES1946 beforehand, when status analog circuits clear, mute input mixer with command prevent pops.
Enable stereo mode (optional). mixer register high. only mode. Clear mixer register after transfer. sample rate filter clock. commands sample rate filter clock divider. filter clock independent from sample rate, command addition 41h.
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stereo transfers, timer divider twice per-channel sample rate. maximum stereo transfer rate 8-bit data channel; this case, program first timer divider were transferring data mono. maximum stereo transfer rate 16-bit data channel. block size. Only this command (48h) with High-Speed transfer modes (commands 91h). Configure system interrupt controller system controller. Start DMA. Start transfer sending command desired transfer type data length. uncompressed modes shown Table Table description commands addition commands transfers compressed data. Table Uncompressed Transfer Modes
Transfer Mode Direct mode Normal High-Speed mode Auto-Initialize High-Speed Data Length 8-bit 16-bit 8-bit 16-bit 8-bit 8-bit 16-bit 8-bit Command
After finished, restore system interrupt controller controller their idle state. Monitor FIFO Empty status flag port SBBase+Ch sure that data transfer completed. Delay milliseconds filter outputs settle DC-levels, then disable Audio input mixer with command D3h. 10.Issue another software reset ES1946 initialize appropriate registers. Compatibility Mode Operation ES1946 analog circuitry switched from direction direction first direct mode command (2xh). Discard first milliseconds samples because pops might occur data change from direction. direction voice input mixer automatically muted. Reset Write port SBBase+6h. play sound without resetting ES1946 beforehand, when status analog circuits clear, mute input mixer with command prevent pops. Select input source using register Sound Blaster three recording sources: microphone, line, auxiliary (CD). Microphone input default source after reset. ES1946 four recording sources: microphone, line, auxiliary (CD), mixer. mixer register choose additional source. Program input volume. selected source passes through input volume stage that programmed with levels gain steps 8-bit recordings (other than HighSpeed mode), volume stage controlled ES1946 firmware purposes automatic gain control (AGC). 16-bit recordings well HighSpeed mode 8-bit recordings, input volume stage controllable from application software. command change input volume level from reset default mid-range, Enable stereo mode (optional). mixer register high. only mode. Clear mixer register after transfer. sample rate filter clock.
Delay approximately milliseconds allow analog circuits settle, then enable Audio input mixer with command D1h. During DMA. Auto-Initialize mode, necessary send commands ES1946 interrupt time, except read SBBase+Eh clear interrupt request. Normal mode, initialize system controller with address count next block size changes. command 48h. start next transfer, command D4h. stop after current auto-initialize block finished, command D0h. Commands such D3h, which control Audio mixer input enable/disable status, command D0h, which suspends DMA, acceptable send during transfers. These commands only sent during certain windows opportunity. "Stereo Transfers Compatibility Mode" page
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commands sample rate filter clock divider. want filter clock independent from sample rate, command addition 41h. stereo transfers, timer divider twice per-channel sample rate. maximum stereo transfer rate 8-bit data channel; this case, program first timer divider were transferring data mono. maximum stereo transfer rate 16-bit data channel. block size. Only this command (48h) with High-Speed transfer modes (commands 99h). Configure system interrupt controller system controller. Start DMA. Start transfer sending command desired transfer type data length. uncompressed modes shown Table Table description commands addition commands transfers compressed data. Table Uncompressed Transfer Modes
Transfer Mode Direct mode Normal High-Speed mode Auto-Initialize High-Speed Data Length 8-bit 16-bit 8-bit 16-bit 8-bit 8-bit 16-bit 8-bit Command
Commands such D0h, which suspends DMA, acceptable send during transfers. These commands only sent during certain windows opportunity. "Writing Commands ES1946 Controller Registers" page After finished, restore system interrupt controller controller their idle state. Monitor FIFO Empty status flag port SBBase+Ch sure that data transfer completed. 12.Issue another software reset ES1946 initialize appropriate registers. maximum sample rate Direct mode kHz. maximum sample rate both 8-bit 16-bit kHz, using commands 24h, 25h, 2Ch, 2Dh. There special High-Speed mode that allows 8-bit sampling kHz. This mode uses commands (auto-initialize) (normal). performed input volume controlled with command DDh.
Extended Mode Programming
This section describes Extended mode programming. Commanding ES1946 Controller Registers Controller registers written read from using commands sent ports SBBase+Ch SBBase+Ah. Commands format Axh, Bxh, Cxh, where numeric value, used Extended mode programming first audio channel. Commands format used access ES1946 controller registers. convenience, registers named after commands used access them. example "register A4h," Audio Transfer Count Reload (low-byte) register, written "command A4h."
Enabling Extended Mode Commands
Delay approximately milliseconds allow analog circuits settle, then enable Audio input mixer with command D1h. 10.During DMA. Auto-Initialize mode, necessary send commands ES1946 interrupt time, except read SBBase+Eh clear interrupt request. Normal mode, initialize system controller with address count next block size changes. command 48h. start next transfer, command D4h. stop after current auto-initialize block finished, command D0h.
After reset, before using Extended mode commands first send command enable Extended mode commands. ES1946 Command/Data Handshaking Protocol This section describes write commands read data from ES1946 controller registers.
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Writing Commands ES1946 Controller Registers
Commands written ES1946 enter write buffer. Before writing command, make sure buffer busy. port SBBase+Ch ES1946 Busy flag. when write buffer full when ES1946 otherwise busy (for example, during initialization after reset during Compatibility mode requests). write command data byte ES1946 microcontroller: Poll port SBBase+Ch until clear. Write command/data byte port SBBase+Ch. following example writing ES1946 controller registers. Audio Transfer Count Reload register F800h, send following command/data bytes:
A4h, 00h; register A5h, F8h; register
Extended Mode Audio Operation Follow steps below program first audio channel Extended mode operation: Reset Write port SBBase+6h, instead Compatibility mode. high specifically clears FIFO. remainder software reset identical Compatibility mode. Reset disables Audio input mixer. This intended mask pops created during setup transfer. After reset, send command enable Extended mode commands. Program direction type: registers B8h, A8h, B9h: Register B8h: Normal mode, high Auto-Initialize mode. Leave CODEC direction. Register A8h: read this register preserve bits then modify only bits Bits Bits Mono Stereo
NOTE: port SBBase+Ch write buffer shared with Compatibility mode write operations. When active, Busy flag cleared during windows time when command received. Normally, only commands that should sent during operations commands such pause/continue Audio enable/disable. this situation recommended disable interrupts between time that Busy polled command written. Also, minimize time between these instructions. "Sending Commands During Operations" page more information.
Reading Read Data Buffer ES1946
register B9h: Bits Bits Bits Single transfer DMA. Demand Transfer DMA: bytes request. Demand transfer DMA: bytes request.
Command used read ES1946 controller registers used Extended mode. Send command followed register number, Bxh. example, read register A4h, send following command bytes:
C0h,
Clocks counters: registers A1h, A2h, A5h: Register A1h: Sample Rate Clock Divider Register A2h: Filter Clock Divider Registers A4h/A5h: Audio Transfer Count Reload register low/high byte, two's complement Initialize configure DACs: registers B7h: Table Register B6h: signed data unsigned data. This also initializes CODEC transfer. Register B7h: programs FIFO (16-bit/8-bit, signed/ unsigned, stereo/mono).
Then poll Read-Data-Buffer-Status bit, port SBBase+Eh, before reading register contents from port SBBase+Ah. Read-Data-Buffer-Status flag polled reading port SBBase+Eh. When byte available, high. NOTE: read port SBBase+Eh also clears active interrupt request from ES1946. alternate polling Read-Data-Buffer-Status through port SBBase+Ch, which same flag. Read-Data-Buffer-Status flag cleared automatically reading byte from port SBBase+Ah.
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Table Command Sequences Playback
Mono Stereo 8-bits 16-bits Unsigned Signed Sequence 80h, 51h, 00h, 71h, 80h, 51h, 00h, 71h, 80h, 51h, 00h, 71h, 80h, 51h, 00h, 71h,
Normal mode, initialize system controller with address count next block transfer. Update ES1946 Transfer Count registers count changed. start next transfer, clear register B8h, then high again. stop transaction progress, clear register B8h. stop transaction after current auto-initialize block finished, clear register B8h, wait interrupt, then clear register B8h. After finished: Restore system interrupt controller controller their idle state. Monitor FIFO Empty status flag port SBBase+Ch sure data transfer completed. delay milliseconds required filter outputs settle DC-levels, then disable first input mixer with command D3h. 12.Finally: Issue another software reset ES1946 initialize appropriate registers. Extended Mode Audio Operation Follow steps below program first audio channel Extended mode operation: Reset Write port SBBase+6h instead Compatibility mode. high specifically clears FIFO. remainder software reset identical Compatibility mode. Reset disables Audio input mixer. This intended mask pops created during setup transfer. Send command enable Extended mode commands. Select input source: ES1946 four recording sources: microphone, line, auxiliary mixer. mixer source playback mixer record mixer. Bits mixer register selects mixer source. record mixer default. Microphone input default after reset. Select source using mixer control register 1Ch. Program input volume register B4h.
Enable/select channel channel, registers B1h, B2h: Register B1h: Interrupt Configuration register. Make sure bits high. Clear bits Register B2h: Configuration register. Make sure bits high. Clear bits Configure system interrupt controller controller. start DMA: register high while preserving other bits. Delay approximately milliseconds allow analog circuits settle, then enable Audio input mixer with command D1h. 10.During Auto-Initialize transfers, read SBBase+Eh clear interrupt request. send other commands ES1946 interrupt time.
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Program direction type: registers B8h, A8h: Register B8h: high program CODEC direction. Normal mode, high Auto-Initialize mode. this point direction analog circuits ADC. Unless recording monitor enabled, there will output from AOUT_L AOUT_R until CODEC direction restored DAC. Register A8h: read this register first preserve bits modify only bits Bits Bits Register B9h: Bits Bits Bits Single Transfer Demand Transfer: bytes request Demand Transfer: bytes request Mono Stereo Disable Record Monitor
Table Command Sequence Record
Mono Stereo 8-bits 16-bits Unsigned Signed Sequence 51h, 71h, 51h, 71h, 51h, 71h, 51h, 71h,
10.Enable/select channel channel, registers B1h, B2h: Register B1h: Interrupt Configuration register. Verify that bits high. Clear bits Register B2h: Configuration register: Verify that bits high. Clear bits Configure system interrupt controller controller. 12.To start DMA: register high. Leave other bits unchanged. 13.During Auto-Initialize transfers, send commands ES1946 interrupt time, except reading SBBase+Eh clear interrupt request. Normal mode, initialize system controller with address count next block transfer. Update ES1946 Transfer Count registers count changed. start next transfer, clear register B8h, then high again. stop transaction progress, clear register B8h. stop transaction after current auto-initialize block finished, clear register B8h, wait interrupt, then clear register B8h. 14.After finished: Restore system interrupt controller controller their idle state.
Clocks counters: registers A1h, A2h, A5h: Register A1h: Sample Rate Clock Divider. high sample rates greater than kHz. Register A2h: Filter Clock Divider. Registers A4h/A5h: Audio Transfer Count Reload register low/high, two's complement Delay milliseconds allow analog circuits settle. Enable Record Monitor desired: Register Enable Record Monitor (optional). Initialize configure ADC: register B7h. Table first command sent register initializes prevents pops. Register B7h: programs FIFO (16-bit/8-bit, signed/ unsigned, stereo/mono).
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15.Finally: Issue another software reset ES1946 initialize appropriate registers. This returns ES1946 CODEC direction turns record monitor. Extended Mode Programmed Operation OUTSB instruction 80x86 family transfers data from memory port specified register. INSB instruction complementary function. ES1946 port SBBase+Fh block transfers. transfers FIFO nearly identical process, except that access port SBBase+Fh replaces cycle. Some differences described here. program this mode useful understand FIFO Half-Empty flag generates interrupt request. interrupt request generated rising edge FIFO Half-Empty flag. This flag polled reading port SBBase+Ch. meaning this flag depends direction transfer: FIFOHE flag high 0-127 bytes FIFO FIFOHE flag high 128-256 bytes FIFO
Programmed Operation
Programmed operation done just explained under "Extended Mode Audio Operation" page with following exceptions:
step programming register
unnecessary.
step leave bits register low.
register high enable interrupt FIFO half-empty transitions. Keep register low.
step addition setting register
high, send OUTSB command.
Programmed Operation
Programmed operation done just explained under "Extended Mode Audio Operation" page with following exceptions:
step programming register
unnecessary.
step leave bits register low.
register high enable interrupt FIFO half-empty transitions. Keep register low.
Therefore, operations, interrupt request generated when number bytes FIFO changes from 128. This indicates system processor that bytes safely transferred without over-filling FIFO. Before first interrupt generated, FIFO needs primed, filled, with more than bytes. Keep mind that data taken FIFO while being filled system processor. that case, there never bytes FIFO unless somewhat more than bytes transferred. Polling ES1946 FIFOHE flag sure goes interrupt handler when priming FIFO) perhaps sending second block bytes solution this problem. ADC, interrupt request generated when number bytes FIFO changes from 128, indicating that system processor safely read bytes from FIFO. Before first interrupt generated, FIFO should emptied mostly reading from SBBase+Fh polling FIFOHE flag. safe FIFO reset port SBBase+6h indiscriminately clear FIFO, because data out-of-sync. mode, register enables transfers between system FIFO inside ES1946.
step addition setting register
high, send OUTSB command. Second Audio Channel Operation Follow steps below program second audio channel operation. Reset Write port SBBase+6h, instead Compatibility mode. high specifically clears FIFO. remainder software reset identical Compatibility mode. reset playback mixer volume second audio channel zero, register 7Ch. This masks pops that might occur during setup process. Program transfer type: mixer register 78h: Mixer register 78h: Normal mode, high Auto-Initialize mode. Clocks counters: registers 70h, 72h, 76h: Register 70h: Sample Rate Generator Register 72h: Filter Clock Divider Registers 74h/76h: Audio Transfer Count Reload register low/high, two's complement
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Initialize configure Audio DAC: register 7Ah. Register 7Ah: high signed data, unsigned. high stereo, mono. high 16-bit samples, 8-bit. Enable channel, register port IOBase+7h: Register 7Ah: Audio Control register. unmasks channel IRQ. Port IOBase+7h: control register. unmasks channel IRQ. Program IOBase+0h, IOBase+4h, IOBase+6h. start DMA: bits register high. Delay approximately milliseconds allow analog circuits settle, then enable Audio playback volume, register 7Ch. During Auto-Initialize transfers, read SBBase+Eh clear interrupt request. send other commands ES1946 interrupt time. Normal mode, initialize IOBase+0h IOBase+4h with address count next block transfer. Update ES1946 Transfer Count registers count changed. start next transfer, clear bits register 78h, then bits high again. stop transaction progress, clear register B8h. stop transaction after current auto-initialize block finished, clear register 78h, wait interrupt, then clear bits register 78h. 10.After finished: Restore system interrupt controller controller their idle state. Monitor FIFO Empty status flag port SBBase+Ch sure data transfer completed. delay milliseconds required filter outputs settle DC-levels, then disable Audio input mixer. Finally: Issue another software reset ES1946 initialize appropriate registers.
Full-Duplex Mode ES1946 supports stereo full-duplex DMA. fullduplex (FD) mode, second audio channel been added ES1946. second audio channel programmed through mixer registers. CODEC used recording Audio used playback. Program first audio channel "Extended Mode Audio Operation" page Extended mode registers define sample rate filter frequency both record playback. Program second audio channel. Mixer registers two's complement transfer count. second audio channel supports both Auto-Initialize Normal modes. playback buffer system memory does have same size record buffer. When transfer count rolls over zero, generate interrupt that independent interrupt generated first audio channel. record playback buffers same size, then single interrupt used. Program Transfer Count Reload registers (A4h, A5h, 74h, 76h) programmed with same value both channels. Enable second audio channel before enabling record channel. example, assume there halfbuffers circular buffer. When record channel completes filling first half, generates interrupt. ensure that playback channel accessing first half time interrupt, start playback channel first. 32-word FIFO that fills quickly through DMA.
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Programming ES1946 Mixer
ES1946 mixer registers that support Sound Blaster Pro. However, some registers accessed "extended" "alternate" way, providing greater functionality. Writing Reading Data from Mixer Registers There addresses used mixer: SBBase+4h address port; SBBase+5h data port. Sound Blaster Pro, SBBase+4h write only, while SBBase+5h read/write.
Writing Data ES1946 Mixer Registers
Table Sound Blaster Pro/Extended Access Registers
Register Function Voice volume Master volume volume (Aux) volume Line volume Extended Access Register bits/Channel
mixer register, write address SBBase+4h, then write data SBBase+5h.
Reading Data from ES1946 Mixer Registers
example, write Sound Blaster register 04h, will read back because bits "stuck high" reads. Inside register, these bits "stuck low," that writing same writing 11h. write read address instead allows direct access bits this mixer register. Extended Access Volume Legacy Compatibility mode register address used control Volume, only bits significant. stuck high reads stuck writes. Since this mono control, panning supported. extended access, register address instead. Register offers bits-per-channel control mono microphone input mixer. Volume
volume left
read register, write address SBBase+4h, then read data from SBBase+5h. Resetting Mixer Registers mixer registers affected software reset. reset registers initial conditions, write zero mixer register 00h: Write SBBase+4h (select mixer register 00h). Write SBBase+5h (write selected mixer register). Extended Access Mixer Volume Controls Sound Blaster Mixer Volume controls mostly bits channel. Sound Blaster Support register Table details. Bits always high when read. ES1946 offers alternate write each mixer register. "extended access" registers volume control bits channel. legacy compatible interface used, bits cleared write forced high reads. Table list Sound Blaster registers extended access counterparts.
(1Ah, R/W)
volume right
Access register through address mapped follows:
Write D2=0, D1=0 D2=0, D1=1 D2=1, D1=0 D2=1, D1=1 Read from volume volume volume volume
Volume register Volume register others undefined.
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Extended Access Source Select Legacy Compatibility mode Sound Blaster mixer, there three choices recording source, bits mixer register 0Ch. Note that zero upon write upon read from 0Ch:
Source Selected Microphone (default) (Aux) input Microphone Line input
Sound Blaster Volume Emulation Sound Blaster emulations master volume means that 6-bit volume counters written through Sound Blaster mixer register 32h). Sound Blaster emulation enabled default, disabled setting mixer register 64h. master volume registers always read, regardless whether Sound Blaster volume emulation enabled, using Sound Blaster mixer registers (and 32h). following 6-bit 4-bit translation table used. Table Read Volume Emulation
Mute Master Volume 0-24 25-30 31-34 35-38 39-42 43-46 47-50 51-54 56-57 59-60 Value Read Value Read
extended access, register address select recording from mixer follows:
Source Selected Microphone (default) Reserved (Aux) input Reserved Microphone Record mixer Line input Reserved
Sound Blaster volume emulation enabled, then mixer reset causes both left right channels their power-on defaults, namely (36h).
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Sound Blaster volume emulation enabled, then write mixer register 32h) causes both left right master volume registers changed follows: Table Write Volume Emulation
Value written Mute 6-Bit Volume
Record Playback Mixer ES1946 stereo mixers playback record. Each stereo mixer eight input sources, each with independent 4-bit left right volume controls. each 4-bit volume control, level mute level maximum volume. ES1946 mixers dual slope method selecting volume. Each increase step volume from settings results increase. Each increase step volume from settings results +1.5 increase. Table Extended Access Mixer Volume Values
Volume Decibels (dB) 4-Bit Value Audio (Record) +3.0 +1.5 -1.5 -3.0 -4.5 -6.0 -7.5 -10.5 -13.5 -16.5 -19.5 -22.5 -25.5 -28.5 mute Audio (Playback) -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -13.5 -16.5 -19.5 -22.5 -25.5 -28.5 -31.5 mute Mic, Music +10.5 +9.0 +7.5 +6.0 +4.5 +3.0 +1.5 -3.0 -6.0 -9.0 -12.0 -15.0 -18.0 -21.0 mute AuxA, AuxB, Line, Mono-In +3.0 +1.5 -1.5 -3.0 -4.5 -6.0 -7.5 -10.5 -13.5 -16.5 -19.5 -22.5 -25.5 -28.5 mute
Audio mixer input gated Sound Blaster "Speaker control. This control toggled (on) (off) Sound Blaster commands.
Table Mixer Input Volume Registers
Mixer Input Audio Audio Microphone Music (FM) AuxA (CD) AuxB Line Mono Playback Volume Register Record Volume Register
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PROGRAMMING MODEL
Register Types
There four types registers ports ES1946:
configuration registers (00h C4h).
These registers accessed through interface. These registers accessed through configuration mechanism described Local Specification available from Special Interest Group.
mapped registers ports
These registers mapped into address space system. They accessed through read/write cycle described Local Specification available from Special Interest Group.
Mixer registers (00h 7Fh).
These registers accessed through ports SBBase+4h SBBase+5h. SBBase+4h written with register address. Then register read written through SBBase+5h. These registers control many functions other than mixer.
Controller registers (A0h BFh).
These registers used control Extended mode playback record through first audio channel. Controller registers accessed through extension Sound Blaster common interface. This interface uses ports SBBase+Ah, SBBase+Ch, SBBase+Eh transfer read data, write data/commands, status respectively.
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Configuration Registers
Register Summary Table Configuration Registers Summary
Device Device status Base class code Reserved Sub-class code Header type Programming interface Master latency timer
Vendor Command Revision Reserved
Offset
Subsystem vendor (read/write-protected) Capability pointer Interrupt Legacy audio control Interrupt line Distributed control Next-Item pointer Capability Power-Management control/status
space base address space base address native audio space base address native audio MPU-401 space base address native audio Game port space base address native audio Reserved Reserved Subsystem (read/write-protected) Reserved Reserved Reserved Maximum latency Reserved Reserved Reserved Reserved ES1946 configuration Reserved Reserved Reserved Reserved Power-Management capabilities Reserved reserved locations read-only with default value zero. Minimum grant
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Register Descriptions Vendor
Vendor
Device Status
(06h, 07h, R/W)
ACPI
(00h, 01h,
Writing clears bit; writing effect bit. default value after reset 0290h.
Definitions: Bits Name Description 15:0 Vendor default value after reset 125Dh, indicating manufacturer this device.
Definitions: Bits Name 15:14
Description Reserved. Returns when read. Master abort status (read/write-clear). Received target abort status (read/write-clear). Signaled target abort. Read-only DEVSEL timing. Read-only 01h. medium. Data parity error detected. Read-only Fast back-to-back capable. Read-only supported. Read-only capable. Read-only ACPI capable. Read-only Reserved. Returns when read.
Device
Device
(02h, 03h,
10:9 ACPI
Definitions: Bits Name 15:0 Device Description default value after reset 1969h, identifying this device member Solofamily ES1938 ES1941 ES1946.
Command
(04h, 05h, R/W)
Revision
Revision
(08h,
default value after reset 0000h.
Definitions: Bits Name 15:3 Description Reserved. Returns when read. Master enable. Reserved. Returns when read. Space access enable.
Definitions: Bits Name Description Revision Identifies revision this device. default value after reset 01h.
Programming Interface
Programming interface
(09h,
Definitions: Bits Name Description Identifies programming interface this device. default value after reset 00h.
Sub-Class Code
Sub-Class code
(0Ah,
Definitions: Bits Name Description default value after reset (assigned PCI-SIG) 01h, indicating audio device with multimedia base class.
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Base Class Code
Base class code
(0Bh,
Base Native-PCI-Audio
(14h 17h, R/W)
SBSB
Definitions: Bits Name Description default value after reset (assigned PCI-SIG) 04h, indicating multimedia device.
default value after reset 0000xxx1h. Bits 15:4 uninitialized reset.
Definitions: Bits Name 31:16 15:4 SBSB Description Read-only 0000h. space base address native audio. ES1946 claims bytes Sound Blaster space. Read-only 000b. space indicator. Read-only
Master Latency Timer
Master latency timer count value
(0Dh, R/W)
default value after reset 00h.
Definitions: Bits Name MLTCV Description Master latency timer count value. Reserved. Returns when read.
Base Native-PCI-Audio (0Eh,
(18h 1Bh, R/W)
Header Type
Header type
VCSB
default value after reset 00h.
Definitions: Bits Name Description HEDT Header type. value indicates singlefunction device.
default value after reset 0000xxx1h. Bits 15:4 uninitialized reset.
Definitions: Bits Name 31:16 15:4 VCSB Description Read-only 0000h. space base address native audio. ES1946 claims bytes driver space. driver allocated ports DDMA base address. Read-only 000b. space indicator. Read-only
Base
(10h 13h, R/W)
IOSB
default value after reset 0000xxx1h. Bits 15:6 uninitialized reset.
Definitions: Bits Name 31:16 15:6 IOSB Description Read-only 0000h. space base address. ES1946 claims bytes space. Read-only 00000b. space indicator. Read-only
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Base Native-PCI-Audio
(1Ch 1Fh, R/W)
Subsystem
Subsystem
(2Eh, 2Fh, R/W)
MPUSB
This register written only when ES1946 Configuration register (50h-53h) there EEPROM, power-on default read from EEPROM, otherwise default value 8888h.
Definitions: Bits Name 15:0 Description Subsystem
default value after reset 0000xxxxh. Bits 15:2 uninitialized reset.
Definitions: Bits Name 31:16 15:2 MPUSB Description Read-only 0000h. space base address native audio. ES1946 claims bytes MPU401 space. Read-only space indicator. Read-only
ACPI Capability Pointer
ACPI capability pointer
(34h,
Definitions:
Base Native-PCI-Audio
(20h 23h, R/W)
Bits Name
Description
GPSB
ACPICP ACPI Cap_Ptr. default value C0h. Read-only.
Interrupt Line
Interrupt line
(3Ch, R/W)
default value after reset 0000xxxxh. Bits 15:2 uninitialized reset.
Definitions: Bits Name 31:16 15:2 GPSB Description Read-only 0000h. space base address native audio. ES1946 claims bytes game port space. Read-only space indicator. Read-only
Definitions: Bits Name Description Interrupt line. Valid values 255. Bits echo value default value 255.
Interrupt
Interrupt
(3Dh,
Subsystem Vendor
Subsystem vendor
(2Ch, 2Dh, R/W)
Definitions: Bits Name Description Interrupt pin. default value 01h, indicating INTA. Read-only.
This register written only when ES1946 Configuration register (50h-53h) there EEPROM, power-on default read from EEPROM, otherwise default value 125Dh.
Definitions: Bits Name 15:0 SVID Description Subsystem Vendor
Minimum Grant
Minimum grant
(3Eh,
Definitions: Bits Name Description Min_Gnt. default value 02h, corresponding Read-only
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Maximum Latency
Maximum latency
(3Fh,
Bits Name
Description
DMACH Sound Blaster channel select. Channel Selection Channel Channel (default) Reserved. Channel
Definitions: Bits Name Description Max_Lat. default value 18h, corresponding
Legacy Audio Control
MIDIIRQ SBIRQ
(40h, 41h, R/W)
DMACH
address aliasing control. 10-Bit address (default). 16-Bit address. MPU-401 enable/mask. Enable MPU-401 (default). Disable MPU-401 IRQ. MPU-401 enable. Enable MPU-401 (default). Disable MPU-401 I/O. Game port enable. Enable game port (default). Disable game port. synthesis enable. Enable synthesis (default). Disable synthesis. Sound Blaster enable. Enable Sound Blaster channel (default). Disable Sound Blaster channel.
default value after reset 907Fh. This also control register mode.
Definitions: Bits Name Description Legacy audio address decode disable. Disable Legacy Audio mode (default). Enable Legacy Audio mode. Reserved. When configuration register write this bit. Otherwise write
13:11 MIDIIRQ MIDI select. Selection 10:8 SBIRQ (default)
Legacy Audio Support
ES1946 supports following legacy audio addresses. Table Supported Legacy Audio Addresses
Legacy Audio Resources Sound Blaster synthesis MPU-401 Joystick Address Base 220h/240h 388h 300h/320h/330h/340h Channel 11-14 201h
Sound Blaster select. Selection (default)
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ES1946 Configuration
IRQP DMAP Reserved
(50h 53h, R/W)
ISAIRQ
Distributed Control
DIOSB
(60h, 61h, R/W)
MPUBA SBBA S(V)ID
default value after reset 0000h.
Definitions: Bits Name 15:4 DIOSB Description Distributed base address. Reserved. Always write Distributed enable. Enable distributed DMA. Disable distributed DMA.
default value after reset 00000000h.
Definitions: Bits Name 29:17 Description Reserved. CLKRUN protocol enable. Reserved.
ISAIRQ serial enable. Reserved. emulation policy. Emulation disabled. 5/7/9/10. 5/7/9/10. Reserved.
Capability
Capability
(C0h,
14:13 IRQP
Definitions: Bits Name Description Read-only. This register identifies linked list item register power management. default value (assigned PCI-SIG) 01h, indicating unique location capabilities pointer value.
12:11
Reserved. Policy Distributed Transparent PC/PCI Reserved Transparent Transparent Transparent Transparent
10:8 DMAP policy.
Next-Item Pointer
Next-Item pointer
(C1h,
Definitions: Bits Name Description Read-only. default value 00h, indicating that there more items linked list power management capabilities.
Reserved. Write Reserved. Returns when read.
MPUBA base address select. MPU-401 SBBA 330h 300h 320h 340h
base address select. Sound Blaster decode 220h. Sound Blaster decode 240h. Reserved. Write
S(V)ID Write-enable subsystem (SID) subsystem vendor (SVID). Read-only (default). Read/write.
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Power-Management Capabilities
(C2h, C3h,
Power-Management Control/Status
(C4h, C5h, R/W)
default value after reset 0621h.
Definitions: Bits Name Description 15:11 Support. This five-bit field indicates power states which function assert PME. value indicates that function capable asserting signal while that power state. [15] PME# cannot asserted from D3cold. [14] PME# cannot asserted from D3hot. [13] PME# cannot asserted from [12] PME# cannot asserted from [11] PME# cannot asserted from Value bits 15:11 00000. Support. This indicates that this function supports power management state. Value Support. This indicates that this function supports power management state. Value Reserved. Value bits 000. DSI. Device Specific Initialization indicates special initialization this function required (beyond standard configuration header) before generic class device driver able Value Auxiliary power source. Value clock. This indicates that clock required function generate PME. Value Version. This 3-bit field indicates that this function complies with Revision Power Management Interface specification. Value bits 001.
default value after reset 0000h.
Definitions: Bits Name 15:2 Description Reserved. Returns when read. Power state. This 2-bit field used both determine current power state function, function into power state. Power State Normal mode (D0) Microcontroller halted (D1) Microcontroller halted analog (D2) Microcontroller halted, analog off, oscillator (D3)
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Ports
These registers divided into groups. Each group corresponding base address. registers addressed base address plus hexadecimal offset. Base addresses determined shown Table
Table Port Base Addresses
Group IOBase SBBase FMBase MPUBase GPBase DDMABase Native Mode PCICONF+10h PCICONF+14h PCICONF+1Ch PCICONF+20h PCICONF+60h Legacy Mode 220/240a 300/320/330/340b 200h
Selected PCICONF+50h[2]. Selected PCICONF+50h[3].
Port Summary
Table Port Summary
Port Device IOBase+0h-IOBase+3h IOBase+4h-IOBase+5h IOBase+6h IOBase+7h IOBase+2Dh IOBase+2Eh IOBase+2Fh Audio/FM Device SBBase+0h-SBBase+3h SBBase+4h SBBase+5h SBBase+6h SBBase+7h SBBase+8h-SBBase+9h SBBase+Ah SBBase+Ch SBBase+Eh SBBase+Fh MPU-401 Device MPUBase+0h-MPUBase+1h Game Port Device GPBase+1h DMAC Device DDMABase+0h-DDMABase+2h Read/write current/base address. DDMABase+4h-DDMABase+5h Read/write current/base count. DDMABase+8h DDMABase+9h DDMABase+Bh DDMABase+Dh DDMABase+Fh Read/write command/status. Write Write Write request. mode. master clear. Read/write Joystick. Read/write MPU-401 port enabled. Read/write 20-voice synthesizer. Address data registers. (FMBase+0h-FMBase+3h) Read/write Mixer address register (port address mixer controller registers). Read/write Mixer data register (port data to/from mixer controller registers). Read/write Audio reset status flags. Read/write Power Management register. Suspend request reset. Read/write 11-voice synthesizer. Address data registers. Alias SBBase+0h-SBBase+3h. Read-only Input data from read buffer command/data I/O. Poll port SBBase+Eh test whether read buffer contents valid. Read/write Output data write buffer command/data I/O. Read embedded processor status. Read-only Data available flag from embedded processor. Read/write Address access FIFO Extended mode. Read/write Audio base/current address. Read/write Audio base/current count. Read/write ES1946 mode register. Read/write control register. Read/write EEPROM type Read/write EEPROM data register Read/write EEPROM command/address register Read/ Write Function
Read/write mask.
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Port Descriptions
This section describes various devices port descriptions. Device This device controls Audio controller internal ES1946 other functions. Audio Base/Current Address (IOBase+0h IOBase+3h, R/W)
A2DMAA (high word) A2DMAA (low word)
Mode
(IOBase+6h, R/W)
Auto-Init BCLK
default value 00h.
Definitions: Bits Name Description Reserved. Always write
Auto-Init Auto-Initialize enable Audio DMA. Enable auto-initialization. Disable auto-initialization. BCLK BCLK select. PCLK/3. PCLK/4. Audio enable. Enable DMA. Disable DMA. Audio Direction. Memory DAC. Read-only.
Write base address register, read from current address register. current address automatically copied from base register when starts. current address then incremented. default value xxxxxxx0h. NOTE: internal counter counts bits [19:0], then concatenates that with upper bits base register.
Definitions: Bits Name Description 31:4 A2DMAA Audio address. Write base address. Read from current address. Read-only
control
MPUIRQ HVIRQ A2IRQ A1IRQ
(IOBase+7h, R/W)
default value 00h.
Definitions: Bits Name HVIRQ A2IRQ A1IRQ Description mask/status hardware volume IRQ. mask/status audio IRQ. mask/status audio IRQ. Reserved. Always write MPUIRQ mask/status MPU-401 IRQ.
Audio Base/Current Count (IOBase+4h IOBase+5h, R/W)
A2DMAC
Write base count register, read from current count register. current count automatically copied from base register when starts. current count then decremented each byte transferred. default value xxx0h. NOTE: DMAC (8237) sets count register. this register needs
Definitions: Bits Name Description 15:4 A2DMAC Audio count. Write base count. Read from current count. Read-only
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EEPROM Type
(IOBase+2Dh, R/W)
Type
EEPROM Command/Address
(IOBase+2Fh,
Command
During normal operation, required program this register. ES1946 auto-detect EEPROM type read first bytes SID/SVID after reset. order EEPROM auto-detect function correctly, first bytes EEPROM must programmed with correct Table EEPROM correctly programmed, 93LC66 used default, subsequent SVID bytes won't recognized. Table EEPROM Auto-detect Bytes
EEPROM 93LC46 93LC66 First Byte Second Byte
This register used modify contents external EEPROM. "Programming EEPROM" page internal address counter incremented issuing command.
Definitions: Bits Name Description Reserved. Always write
Command Table decode command bits.
Table EEPROM Access Command Summary
Symbol Command EWDS WRAL ERAL EWEN WRITE READ ERASE Erase write disable Write Erase Erase write enable Write word Reserved Reserved Reserved Read word Reserved Reserved Reserved Erase word Reserved Reserved Reserved
default value 00h.
Definitions: Bits Name Description Reserved. Always write EEPROM type select. Device auto-detect 93LC46 Reserved. 93LC66
EEPROM Data
(IOBase+2Eh, R/W)
default value undefined.
Definitions: Bits Name Data Description Data port to/from EEPROM.
EEPROM Address Reset
Address counter reset
(IOBase+2Fh,
Reading this register resets internal address counter.
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Audio/FM Device synthesizer operates different modes: Emulation mode Native mode. Emulation mode synthesizer fully compatible with OPL3 synthesizer. Native mode synthesizer increased capabilities performance more realistic music. following register descriptions Emulation mode only. Status
High Bank Data Write
(SBBase+3h,
register write. Writing this register Emulation mode same writing register SBBase+1h. This register also accessed from FMBase+3h. Mixer Address Register (SBBase+4h, R/W)
(SBBase+0h,
Reading this register returns overflow flags timers "interrupt request" from these timers (this real interrupt request supported status flag backward compatibility with OPL3 synthesizer). This register also accessed from FMBase+0h. Bank Address
ES1946 provides means read back Mixer Address register. Reading back this register useful "hot-key" application that needs change mixer while preserving address register. Mixer Data Register
(SBBase+5h, R/W)
(SBBase+0h,
bank register address. This register also accessed from FMBase+0h. NOTE: write this register will also synthesizer Emulation mode currently Native mode. Bank Data Write
(SBBase+1h,
register write. data written SBBase+1h written current address register. Note that register writes must follow timing requirements OPL3 synthesizer. This register also accessed from FMBase+1h. High Bank Address
(SBBase+2h,
High bank register address. This register also accessed from FMBase+2h.
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Reset
(SBBase+6h,
FIFO reset reset
Status Flags
flag flag Serial flag
(SBBase+6h,
MIDI modes FIFO reset reset
Definitions: Bits Name FIFO reset Description Reserved. Always write Hold ES1946 FIFO reset. Release ES1946 FIFO from reset. function Compatibility mode.
Bits port SBBase+6h used monitor activity ES1946. Bits high after read from port SBBase+6h. Then specific activity these bits low. When port SBBase+6h read later time, these bits will indicate whether activity occurred between reads from SBBase+6h. used indicate ES689/ES69x serial interface use. high mixer register high (software serial enable serial reset). also high ES689/ES69x serial interface active, which combination mixer register high, MCLK (ES689/ES69x serial clock) being high periodically.
Definitions: Bits Name Description Reserved. Returns when read.
reset Hold ES1946 reset. Release ES1946 from reset.
NOTE: synthesizer reset SBBase+7h.
flag1 reads/writes audio ports SBBase+4h SBBase+5h. flag writes audio ports SBBase+0h-SBBase+3h, SBBase+6h, SBBase+Ch. reads from audio ports SBBase+0h-SBBase+3h, SBBase+Ah. Also accesses ES1946. Serial Serial activity flag. High external flag ES689/ES69x using MCLK/MSD drive music DAC. MIDI mode Reserved. ES1946 processing controller command 30h, 31h, 34h, waiting command complete. Powering-down cause loss data. ES1946 does automatically wake serial input pin. FIFO Reset bit.
FIFO reset
reset Software reset bit.
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Power Management Register
Suspend request synth reset
(SBBase+7h, R/W)
Buffer Status Register
FIFO BUSY RDAV FIFO full empty flag FIFO half
(SBBase+Ch,
flag2 flag1 flag0
Definitions: Definitions: Bits Name Description Suspend Pulse high, then request suspend. request Reserved. synth Hold synthesizer reset. reset Release synthesizer from reset. Reserved. Always write Reserved. Bits Name Description BUSY Write buffer available ES1946 busy. flag Write buffer available ES1946 busy. RDAV Data available read buffer. Data available read buffer. This flag reset read from port SBBase+Ah. FIFO full Extended mode FIFO Full (256 bytes loaded).
FIFO Extended mode FIFO Empty bytes empty loaded). FIFO half flag2 flag1 flag0 FIFO Half Empty, Extended mode flag. ES1946 processor generated interrupt request (e.g., from Compatibility mode complete). Interrupt request generated FIFO Half Empty flag change. Used programmed interface FIFO Extended mode. Interrupt request generated counter overflow Extended mode.
Read Data Register
(SBBase+Ah,
Read data from embedded audio processor. Poll port SBBase+Eh test whether register contents valid. Write Data Register
(SBBase+Ch,
Read Buffer Status Register
RDAV
(SBBase+Eh,
Write data embedded audio processor. Sets port SBBase+Ch high (write buffer available) until data processed ES1946. This register cannot written when SBBase+Ch high.
Same SBBase+Ch[6:0]
read from port SBBase+Eh will reset interrupt request.
Definitions: Bits Name RDAV Description Data available read buffer. Data available read buffer. This flag reset read from port SBBase+Ah. Same SBBase+Ch[6:0].
Programmed Access FIFO Register (SBBase+Fh, R/W)
This port used replace Extended mode with programmed I/O.
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SAM0219-051998
ES1946 SOLO-1E DATA SHEET PROGRAMMING MODEL
MPU-401 Device MPU-401 Data
(MPUBase+0h, R/W)
Game Port Device joystick device uses only single port. Joystick
(GPBase+1h
This register used read data from MPU-401 receive FIFO command acknowledge byte (0FEh). This register also used write data MPU-401 transmit FIFO. MPU-401 Command
(MPUBase+1h,
value written GPBase+1h port will restart timing sequence. This should done before reading timer status flags. Joystick
(GPBase+1h,
MPU-401 device accepts only commands: Reset/return Smart mode. This command generates acknowledge byte received when already Smart mode. UART mode. This command generates acknowledge byte received while Smart mode. ignored device already UART mode. (MPUBase+1h,
SW(A-D) return current state joystick switch inputs. T(A-D) return current state four one-shot timers connected resistors dual joysticks.
MPU-401 Status
Definitions: Bits Name Description read data available receive FIFO, pending acknowledge byte read (0FEh). there room transmit FIFO accept another byte.
SAM0219-051998
Technology, Inc.
ES1946 SOLO-1E DATA SHEET PROGRAMMING MODEL
DMAC Device DMAC device used Audio controller internal ES1946. DDMA Current/Base Address (DDMABase+0h DDMABase+2h, R/W)
current/base address
Mode
TMODE
(DDMABase+Bh,
TTYPE
Definitions: Bits Name TMODE Transfer Mode Demand transfer Single transfer Block transfer Reserved Description
Write base address register, read from current address register. current address automatically copied from base register when starts. current address then incremented decremented according DDMABase+Bh. DDMA Current/Base Count (DDMABase+4h DDMABase+5h, R/W)
current/base count
Transfer direction. Address decrement. Address increment. Auto-Initialize. Transfer Type Verify transfer Write transfer Read transfer Illegal
TTYPE
Write base count register, read from current count register. current count automatically copied from base register when starts. current count then decremented each byte transferred. Command
DACKPOL DREQPOL
Reserved. Always write
Master Clear
master clear
(DDMABase+Dh,
(DDMABase+8h,
Write value this register reset DMAC. Mask (DDMABase+Fh, R/W)
Mask
Definitions: Bits Name DACKPOL DREQPOL Description DACK signal polarity. DREQ signal polarity. Reserved. Always write Controller enable. Reserved. Always write
Definitions: Bits Name Mask Description Reserved. Always write Mask DREQ.
Status
(DDMABase+8h,
Definitions: Bits Name Description 0000 DREQ asserted. 1111 DREQ negated. 0000 reached terminal count (TC). 1111 reached
Technology, Inc.
SAM0219-051998
ES1946 SOLO-1E DATA SHEET PROGRAMMING MODEL
Mixer Registers
There types mixer registers. Sound Blaster Support mixer registers fully support Sound Blaster Pro. mixer registers specific Technology, Inc. ES1946 AudioDrive® chips, although many registers shared throughout AudioDrive® family chips. Sound Blaster Support Mixer Registers This section provides summary mixer registers which support Sound Blaster ES1946 some comments characteristics these registers. Table Sound Blaster Support Register Summary
play volume left Master volume left volume left AuxA (CD) volume left Line volume left
Description
Mixer reset playback volume volume note note Master volume Music volume AuxA (CD) volume Line volume
Write: reset mixer play volume right volume source Stereo
Master volume right volume right AuxA (CD) volume right Line volume right
Sound Blaster Filter Control bits have equivalent function ES1946 ignored.
Filter Control Bits
Sound Blaster mixer three bits that control input output filters. They labeled Table Table They have equivalent function ES1946 their values ignored.
Mixer Stereo Control
sample rate twice sample rate each channel. example, stereo, program "sample rate" using command 40h. This enables stereo only transfer Compatibility mode. should used Extended mode. Clear this after completing stereo transfer, because this unaffected software reset (only mixer reset). also "Stereo Transfers Compatibility Mode" page
register Mixer Stereo Control bit. normally zero. this high enable legacy compatible stereo functions. this case, program
Mixer Registers This section provides summary mixer registers followed detailed description each register. Table Mixer Registers Summary
Line volume left ES689/ enable Audio play volume left volume left Mute Master volume left volume left AuxA (CD) volume left AuxB volume left
Remark
Reset mixer Audio play volume volume Master volume volume AuxA (CD) volume AuxB volume speaker volume Line volume
Write: reset mixer Audio play volume right volume right Extended record source Master volume right volume right AuxA (CD) volume right AuxB volume right speaker volume Line volume right
Serial mode miscellaneous control
SAM0219-051998
Technology, Inc.
ES1946 SOLO-1E DATA SHEET PROGRAMMING MODEL
Table Mixer Registers Summary (Continued)
channel Master clock 1:New
1:Split mode
1:Mute 1:Mute 1:Mute 1:Mute MPU-401 mask
1:Enable
0:Reset
Remark
enable level Left master volume mute Left hardware volume counter Right master volume mute Right hardware volume counter
level Left master volume Left volume counter Right master volume Right volume counter 1:Count Read-only request Mode mask Disable master control
Master volume control Write-only record volume Audio record volume AuxA (CD) record volume Music record volume AuxB record volume Mono_In play Line record volume Mono_In record volume Audio sample rate
Clear hardware volume interrupt request record volume left Audio record volume left AuxA (CD) record volume left Music record volume left AuxB record volume left Left Mono_In play Line record volume left Mono_In record volume left record volume right Audio record volume right AuxA (CD) record volume right Music record volume right AuxB record volume right Right Mono_In play Line record volume right Mono_In record volume right Two's complement rate divider 1:4x mode 1:SCF1 bypass 1:Async mode 1:FM
Audio mode Audio filter clock rate Audio transfer count reload
Two's complement filter rate divider Two's complement transfer count byte Two's complement transfer count high byte Autoinitialize Enable second channel Stereo /Mono Enable FIFO chan 16-bit/ 8-bit Enable Mono_In AOUTL/R connect music
Audio control
mask
Data sign
Audio control Audio mixer volume preamp, Mono_In Mono_Out
Left channel volume Music digital record Enable
Right channel volume Mono_Out source select clock activity
Reserved
interface
Technology, Inc.
SAM0219-051998
ES1946 SOLO-1E DATA SHEET PROGRAMMING MODEL
Register Detailed Descriptions Reset Mixer
Write: reset mixer
Extended Record Source
Mute
(1Ch, R/W)
Extended record source
(00h,
Definitions: Bits Name Description function. Sound Blaster Filter Control equivalent function ES1946 ignored. Mutes input filters recording. This does affect MONO_OUT. Sound Blaster Filter Control equivalent function ES1946 ignored.
write this register resets mixer registers their default values. Table Mixer Register Default Values
Register Name Sound Blaster Registers playback volume volume Record source Stereo select Master volume Music volume AuxA (CD) volume Line volume Extended Mode Registers Audio play volume volume Record source Master volume volume AuxA (CD) volume AuxB volume speaker volume Line volume middle mute middle middle mute mute middle mute middle mute mono middle middle mute mute Address Value
Mute
Extended Selects record source Extended mode. record Record Source source Microphone Reserved AuxA (CD) Reserved Microphone Record mixer Line Reserved
Master Volume Register
Master volume left
(32h, R/W)
Master volume right
reset, this register assumes value 88h. This register provides backward-compatible access master volume. applications also registers 62h, which have more resolution. Volume Register (36h, R/W)
volume right
Audio Play Volume
Audio play volume left
(14h, R/W)
Audio play volume right
This register controls playback volume first audio channel. reset, this register assumes value 88h. Volume
volume left
volume left
(1Ah, R/W)
volume right
This register controls playback volume music DAC. reset, this register assumes value 88h. AuxA (CD) Volume Register
AuxA (CD) volume left
(38h, R/W)
AuxA (CD) volume right
This register controls playback volume input. reset, this register assumes value 00h.
This register controls playback volume audio input. reset, this register assumes value 00h.
SAM0219-051998
Technology, Inc.
ES1946 SOLO-1E DATA SHEET PROGRAMMING MODEL
AuxB Volume Register
AuxB volume left
(3Ah, R/W)
AuxB volume right
Enable Mode
Enable Reset
(50h, R/W)
This register controls playback volume auxiliary line input. reset, this register assumes value 00h. Speaker Volume Register
Reserved
effect uses Spatializer® VBXtechnology, provided Desper Products, Inc.,
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