ES1988 Allegro audio-modem accelerator combines advanced audio modem f
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ES1988 AllegroPCI Audio-Modem Accelerator Data Sheet
ES1988 Allegro audio-modem accelerator combines advanced audio modem functionality highly integrated solution. Utilizing load, ES1988 provides chip audio-modem solution with digital interface capability AC'97 CODEC dock (a.k.a. digital docking). ES1988 designed provide cost, high-performance solution notebook applications. high-bandwidth integrated high-fidelity CODEC utilized deliver advanced audio features, such DirectSound acceleration, HRTF positional audio. ES1988 implements multi-stream DirectSound DirectSound3D acceleration with digital mixing, sample rate conversion filtering speaker positional audio. programmable audio signal processor provides support multiple audio streams. With built-in core, ES1988 uses dedicated engine handle complex signal processing tasks with bus-mastering interface. support functions ensure efficient transfer audio data streams from system memory buffers, providing system solution with maximum performance minimal host loading. architecture enables implementation communications over Internet from multiple sources. ES1988 maintains full legacy audio compatibility over standard bus. Full game compatibility ensured through either PC/PCI, Distributed (DDMA), Transparent (TDMA). ES1988 includes modem interface secondary AC-Link connecting with ES2828 MC'97 CODEC. MC'97 used analog front modem control. ES56 V.90 data/fax/TAM modem runs host while ES1988 serves bi-directional buffer data transmission reception. modem functions include standard command set, V.42bis Group Fax. ES1988 provides high-quality docking solution through proven AC-link based digital docking. This accomplished using only five wire digital connection. secondary AC'97 link (extension compliant) ES1988 interfaces secondary AC'97 CODEC dock provide high quality audio dock. ES1988, which operates volts digitally volts analog, compliant with Advanced Power Management (APM) 1.2, Advanced Configuration Power Interface (ACPI) 1.0, Power Management Interface (PPMI) 1.0. ES1988 supports (hot cold) powersaving modes power efficiency when audio system both active idle. CLKRUN# support also available. ES1988 available industry-standard 100-pin Thin Quad Flat Pack (TQFP) package.
AUDIO FEATURES
High-performance single-chip audio acceleration Integrated high-fidelity AC'97 codec Multi-stream DirectSound DirectSound acceleration Sensaura Positional High-quality sample rate conversion digital mixing Direct Music support Realtime effects processing S/PDIF output AC-3 content Full legacy game support using TDMA, PC/PCI DDMA hardware implementation methods Supports additional master devices modem interface MC'97 link Supports wakeup-on-ring Digital docking secondary AC-Link
MODEM FEATURES Data Mode capabilities:
V.90 V.34 33.6 kbps fallbacks Standard command V.42 (LAPM) error correction V.42bis/MNP data compression power supply with 5V-tolerant inputs
Mode capabilities:
ITU-T V.17, V.21 ch2, V.27ter, V.29 Group (TIA/EIA Class Class
Supports Wakeup Ring from D3hot D3cold states
control
POWER MANAGEMENT
Compliance with 1.2, ACPI 1.0, PPMI Compliance with Intel's "Mobile Power Guidelines `99" volt digital operation with 5V-tolerant inputs volt analog operation
COMPATIBILITY Supports games applications Sound Blaster
Sound Blaster
Supports Microsoft® Meets PC99 WHQL specifications Compliant with Intel's Audio/Modem Riser Card mini-PCI
specifications
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ES1988 ALLEGRO DATA SHEET CONTENTS
CONTENTS
PINOUT DESCRIPTION FUNCTIONAL GROUPING BLOCK DIAGRAMS FUNCTIONAL DESCRIPTION Audio Subsystems Modem Subsystems Interface Memory Architecture ASSP Memory Mapping ASSP S/PDIF Interface Integrated AC'97 Codec AC-Link Interface. Codec Data Output Framing. Slot Slot Command Address Port Slot Command Data Port Slot Playback Left Channel Slot Playback Right Channel Codec Data Input Framing Slot Slot Status Address Port Slot Status Data Port Slot Record Left Channel Slot Record Right Channel Hardware Master Volume Control Peripheral Interfacing Serial Interface Serial Interface Software Enable Serial Interface Timing Joystick MPU-401 Interface.17 MPU-401 UART Mode.17 Joystick MIDI External Interface Game Compatibility DMA.17 DDMA IRQ. Selecting DMA/IRQ Policy Modem Operation. D3cold Wake-Up Ring. Ring Enable Data Modes. Support Modem Wakeup Configuration Registers Legacy-Compatible Audio Registers. Legacy Audio Support. ACPI Power Management Registers Power Management Registers. Host Interrupt Registers Game Port Control Registers Codec Control Registers Serial Control Registers GPIO Registers ASSP Memory Control Registers. Game Port Address Registers MPU-401 Address Registers ASSP Clock Control Registers. Integrated AC'97 Codec Registers Basic Integrated AC'97 Registers Extended Audio Vendor Registers ASSP Registers ELECTRICAL CHARACTERISTICS ES1988 RECOMMENDED OPERATING CONDITIONS ES1988 TIMING DIAGRAMS MECHANICAL DIMENSIONS. APPENDIX SCHEMATIC EXAMPLES APPENDIX BILL MATERIALS. ORDERING INFORMATION
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ES1988 ALLEGRO DATA SHEET FIGURES
FIGURES
Figure Figure Figure Figure Figure Figure Figure Figure Figure ES1988 Allegro Pinout ES1988 System Block Diagram ES1988 Device Block Diagram Integrated AC'97 Codec Functional Block Diagram ES1988 Bi-directional Data Frame Implementation ES1988 D3cold Wake-Up Ring Sequence Cold Reset Warm Reset Figure Clocks Figure Data Output Input Timing Diagram Figure Port Timing Figure Signal Rise Fall Times Figure AC-Link Power Mode Timing. Figure Mechanical Dimensions Figure ES1988 Allegro Device Interface Figure Audio Interface Figure Game Port S/PDIF Interfaces Figure Interface
TABLES
Table Table Table Table Table Table Table Table Table Dual Registers ES1988 Architecture. Memory Address (Input) Memory Address (Output) Slot Command Address Bits Functions Slot Command Data Bits Functions Status Address Port Assignments Status Port Data Assignments Interface Pins. Modes Supported Table Table Table Table Table Table Table Table Table Table Table Data Modes Supported Supported Legacy Audio Addresses Master Volume Control Bits Beep Volume Attenuation Analog Mixer Input Volume Gain Record Mixer Output Volume Gain Absolute Maximum Ratings Operating Condition Digital Characteristics ES1988 Analog Characteristics Power Management Characteristics
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ES1988 ALLEGRO DATA SHEET PINOUT
PINOUT
VREF LINE_IN_R LINE_IN_L CD_R CD_GND CD_L PHONE PC_BEEP SCLK2/ SDFS2/ SRESET2#/GPI OSCO OSCI SDI2/GPIO8 PME#/SPDIFO/PCGNT#/VOLDN# MC97_DI/ PCREQ#/ VOLUP#/ GPIO7 CAP1 CAP2 NE_OUT_L LINE_OUT_R MONO_OUT AVSS2 AVDD2 GPIO1/ O2/TXD RST# GNT# REQ# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24
ES1988 100-Pin TQFP
I2SCLK/SIRQ#/GPIO4 GD7/GPIO15 GD6/GPIO14 GD5/GPIO13 GD3/ECLK/VOLDN# GD2/EDIN/ VOLUP# GD1/EDOUT CLKRUN#/ C/BE0# AD10
SAM0268-031800
C/BE3# PCREQ#/ SPDI FO/R0#/I DSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 C/BE2# FRAME# RDY# TRDY# DEVSEL# STOP# C/BE1# AD15 AD14 AD13 AD12
Figure ES1988 Allegro Pinout
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ES1988 ALLEGRO DATA SHEET
Name C/BE[3:0]# IDSEL Number Description command/byte enable. During address phase transaction, these pins define command. During data phase, these pins define byte enable. Select. When configured multifunction (see note), IDSEL selected internally AD24. request input from external master device. enabled setting PCIx2 arbiter Select from setting [10] must configured multifunction (see note). Either used R0#. S/PDIF Output. Enable SPDIFO setting Select SPDIFO from setting must configured multifunction (see note). Either used SPDIFO. PC/PCI request output. Enable PCREQ# setting [10:8] 010. used PCREQ# when configured audio-only device. PCREQ# only used from when ES1988 configured multifunction device (see note). must configured multifunction (see note). configured multifunction when pulled low. This will allow additional this RO#, SPDIFO, PCREQ#. open pulled high, then only used IDSEL. 93:100, 4:11, 22:29, 31:38 Digital ground Address data lines from
SPDIFO PCREQ#
(note)
AD[31:0]
FRAME# IRDY# TRDY# DEVSEL# STOP# CLKRUN# GD[0] GD[1] EDOUT GD[2] EDIN VOLUP#
Digital supply voltage, 3.3V Cycle frame Initiator ready Target ready Device select Stop transaction Parity CLKRUN#, Clock status output start accelerate clock function enabling [11] Chip select output EEPROM chip select input. active after power-on reset goes inactive automatically after EEPROM cycle complete. Game port data Input/Output Game port data Input/Output Data output EEPROM data input. EDOUT goes active after power-on reset goes inactive automatically after EEPROM cycle complete. Game port data Input/Output Data input from EEPROM data output. EDIN goes active after power-on reset goes inactive automatically after EEPROM cycle complete. Hardware volume control (volume up). Used combination with (VOLDN#). Hardware volume control enabled setting Pins 44:45 selected hardware volume control setting Pins 53:54 also used hardware volume control.
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ES1988 ALLEGRO DATA SHEET
Name GD[3] ECLK VOLDN#
Number
Game port data Input/Output
Description
Clock output EEPROM clock input. ECLK goes active after power-on reset goes inactive automatically after EEPROM cycle complete. Hardware volume control (volume down). Used combination with (VOLUP#). Hardware volume control enabled setting Pins 44:45 selected hardware volume control setting Pins 53:54 also used hardware volume control. Game port data input Game port data input General purpose input/output serial clock input. input enabled setting Allegro_Base+37h [15] Serial interrupt request. Optional PC/PCI system implementation. Serial enabled setting [14] General purpose input/output frame sync input. input enabled setting Allegro_Base+37h [15] Grant master. GTO# enabled setting PCIx2 arbiter bits [11] Select GT0#/GSO from enabling [10] also used GT0#/GSO. Grant select output control external quick switch grant master phase. enabled setting PCIx2 arbiter [11] Select GS0/GT0# from enabling [10] also used GT0#/GSO. General purpose input/output data input. input enabled setting Allegro_Base+37h [15] request input from external master device. enabled setting PCIx2 arbiter Select from enabling [10] Either used R0#. General purpose input/output Modem CODEC data input. Enabled setting Allegro_Base+38h PC/PCI request output. Enable PCREQ# setting [10:8] 010. used PCREQ# when configured audio-only device. PCREQ# only used from when configured multifunction device (see note). Hardware volume control (volume up). Used combination with (VOLDN#). Hardware volume control enabled setting Pins 53:54 selected hardware volume control setting Pins 44:45 also used hardware volume control. General purpose input/output
GD[4] GD[5:7] GPIO[13:15] I2SCLK SIRQ# GPIO4 I2SLR GTO#
47:49
GPIO5 I2SDATA GPIO6 MC_97DI PCREQ#
VOLUP#
GPIO7
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ES1988 ALLEGRO DATA SHEET
Name PME# SPDIFO PCGNT#
Number
Description PME# output wake system. enabled setting PME_EN (PCI S/PDIF Output. Enable SPDIFO setting Select SPDIFO from setting Either used SPDIFO. PC/PCI grant input. Enable PC/PCI setting [10:8] 010. Select PCGNT# from setting Allegro_Base+58h Either used PCGNT#. Hardware volume control (volume down). Used combination with (VOLUP#). Hardware volume control enabled setting Pins 53:54 selected hardware volume control setting Pins 44:45 also used hardware volume control. volt VAUX voltage supply input. VAUX supported, then VAUX (pin should connected VAUXD (pin should pulled down. External AC-link serial data input. Select secondary Codec enabling Allegro_Base+38h General purpose input/output 49.152 crystal input 49.152 crystal output Reset output AC-Link interface. Select secondary Codec enabling Allegro_Base+38h General purpose input/output Serial data frame sync output AC-Link interface. Select secondary Codec enabling Allegro_Base+38h General purpose input/output pull-down resistor used this pin, ES1988 configured multifunction device (audio-modem). Otherwise, ES1988 configured single function audio-only device.
VOLDN#
VAUX
SDI2 GPIO8 OSCI OSCO SRESET2# GPIO3 SDFS2 GPIO9 (note)
SCLK2 GPIO10 SDO2 GPIO11 VAUXD
Serial clock AC-link interface. Select secondary Codec enabling Allegro_Base+38h General purpose input/output External AC-link serial data output. Select secondary Codec enabling Allegro_Base+38h General purpose input/output VAUX detect. During reset period, VAUXD driven high indicate ACPI support D3cold state, driven indicate ACPI supported D3cold state. VAUX supported, then VAUX (pin should connected VAUXD (pin should pulled down.
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ES1988 ALLEGRO DATA SHEET
Name PCGNT#
Number
Description PC/PCI grant input. Enable PC/PCI setting [10:8] 010. Select PCGNT# from setting Allegro_Base+58h Either used PCGNT#. Grant master. GTO# enabled setting PCIx2 arbiter bits [11] Select GT0#/GSO from enabling [10] also used GT0#/GSO. Grant select output control external quick switch grant master phase. enabled setting PCIx2 arbiter [11] Select GS0/GT0# from enabling [10] also used GT0#/GSO. General purpose input/output Speaker input Mono input CD-audio input: left channel CD-audio input: ground CD-audio input: right channel Microphone input Line input: left channel Line input: right channel Analog supply voltage, Analog ground Reference voltage Anti-aliasing filter channel reference caps Line output: left channel Line output: right channel Mono output MIDI receive data input. Enable MIDI (MPU-401 I/O) setting General purpose input/output MIDI transmit data output. Enable MIDI (MPU-401 I/O) setting General purpose input/output pull down resistor used this pin, then enabled multifunctionality (IDSEL, RO#, SPDIFO, PCREQ#). Otherwise, only used IDSEL.
GT0#
GPIO12 PC_BEEP PHONE CD_L CD_GND CD_R LINE_IN_L LINE_IN_R AVDD[2:1] AVSS[2:1] VREF AFILT[2:1] CAP[2:1] LINE_OUT_L LINE_OUT_R MONO_OUT GPIO1 GPIO2 (note) 76:75 78:77
RST# INT# PCICLK GNT# REQ#
reset input Interrupt request output clock input master grant input master request output
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ES1988 ALLEGRO DATA SHEET STRAPPING OPTIONS
STRAPPING OPTIONS
number (SDFS2/GPIO9) Strapping open high (SDO2/GPIO11/VAUXD) high open high Description ES1988 configured multifunction device (audio-modem). ES1988 configured single function device (audio only). ES1988 does support VAUX cold "Wake Ring"). ES1988 supports VAUX cold "Wake Ring"). multifunction mode. Description only being used Select.
(GPIO2/TXD)
Typical Configurations
Application
number
Strapping open high open high
Description Design audio only. Single configuration space available. Function with device 1988h. Design does support "Wake Ring". (VAUX) connected VCC. used Select. used multifunction. Select configured through AD24. used PCREQ#, S/PDIF output, RO#. Design audio-modem combo. configurations available with separate device ID's (audio: function with device 1988h, modem: function with device 1989h). Design supports "Wake Ring" through VAUX. (VAUX) connected VAUX. Design does support "Wake Ring". (VAUX) connected VCC. used Select. used multifunction. Select configured through AD24. used PCREQ#, S/PDIF output, RO#.
Audio Only Design
high Audio Modem Designs open high
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ES1988 ALLEGRO DATA SHEET FUNCTIONAL GROUPING
FUNCTIONAL GROUPING
Function AC-Link Interface Pins: Digital Docking SDI2* SRESET2* SDFS2* SCLK2* SDO2* AC-Link Interface Pins: MC`97 CODEC MC97_DI* SRESET2* SDFS2* SCLK2* SDO2* ACPI VAUX Pins PME#* VAUX VAUXD* Audio Interface Pins SPDIFO* (Digital) I2SDATA* (Digital) PCBEEP (Analog) PHONE (Analog) CD_L (Analog) GD_GND (Analog) CD_R (Analog) (Analog) LINE_IN_L (Analog) LINE_IN_R (Analog) LINE_OUT_L (Analog) LINE_OUT_R (Analog) MONO_OUT (Analog) RxD* (MIDI) TxD* (MIDI) Master Interface Pins GTO#/GSO Clock Generation Pins CLKRUN#* ECLK* I2SCLK* OSCI OSCO SCLK2* PCICLK Pins Number
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ES1988 ALLEGRO DATA SHEET FUNCTIONAL GROUPING
Function DAA/Speakerphone Interface Pins PHONE
Pins
Number
LINE_OUT_L LINE_OUT_R MONO_OUT EEPROM Interface Pins EDOUT EDIN ECLK Gameport Interface Pins GD0* GD1* GD2* GD3* GD5* GD6* GD7* General-Purpose Pins GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 Hardware Volume Interface Pins VOLUP#* VOLDN#* Interface Pins I2SCLK* I2SLR* I2SDATA*
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET FUNCTIONAL GROUPING
Function Interface Pins IDSEL AD[31:0]
Pins
Number 93:100, 4:11, 22:29,31:38 1,13,
C/BE[3:0]# FRAME# IRDY# TRDY# DEVSEL# STOP# CLKRUN# RST# INT# PCICLK GNT# REQ# PC/PCI Interface Pins PCREQ# SIRQ# PCGNT# Power Ground Pins (3.3V digital supply voltage) AVDD[2:1] (5.0V analog supply voltage) VAUX VREF (digital ground) AVSS[2:1] (analog ground) S/PDIF Interface Pins These pins share more than function. SPDIFO*
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ES1988 ALLEGRO DATA SHEET BLOCK DIAGRAMS
BLOCK DIAGRAMS
ES2828 ES1988 Allegro
Transmit buffer (Tx) Receive buffer (Rx) Link Reset GPIO Control
Chip definitions: ES1988 Allegro: 100-pin audio-modem accelerator ES2828: single 16-bit modem CODEC
Figure ES1988 System Block Diagram
System DRAM
Chipset
master RING legacy audio TDMA DDMA PC/PCI EEPROM interface S/PDIF output HRTF positional audio Effects Processing SID/SVID customization
Line
Integrated Audio CODEC ACPI PPMI Secondary AC-Link audio)
Phone
Line
ASSP Sample Rate Converter Mixer
Digital audio output MPEG audio
Game port
Joystick down
volume
MPU-401
MIDI device
Allegro
Figure ES1988 Device Block Diagram
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ES1988 ALLEGRO DATA SHEET FUNCTIONAL
FUNCTIONAL ES1988 Allegro audio accelerator single-chip audio-modem solution. ES1988 provides flexible audio-modem interface both audio subsystem modem subsystem while serving bidirectional buffer data transmission reception. ES1988 also incorporates both integrated AC'97 Codec AC'97 Extension compliant link interface with secondary, external AC'97 Codec and/or MC'97 compliant modem AFE. This allows system integetrator integrate features on-system high performance audio modem, with digital docking capabilities while using only single load. ES1988 includes following subsystems: (CD-audio) Line Phone
Modem Subsystems
ACPI-compliant power management controller Analog digital sigma-delta modulators signal channels Anti-aliasing filters Decimation filter Interpolation filter
Audio Subsystems AC'97 Compliant Audio Codec analog input
outout interconnect embedded Codec.
Interface
ES1988 audio accelerator features number dedicated registers handling audio data handling modem data during online session power management. These registers include dual configuration registers power management registers. setting Header Type register index determines configuration space ES1988 shall used. ES1988 singlefunction, audio-only device. however, ES1988 becomes multi-function audio-modem device combo configurations. When configured multifunction device, audio modem sections will have their configuration registers. Table lists dual sets registers. Table Dual Registers ES1988 Architecture
Dual Register Name Register Index
AC'97 Link provides interface external,
secondary Codec and/or MC'97 compliant Codec.
ASSP emulation, sample rate conversion, digital
mixing, audio special effects performed embedded asynchronous specific signal processor.
Dual game port integrated dual game port
joysticks.
EEPROM Interface serial port connection from
EEPROM Subsystem Subsystem Vendor
FIFO 128-word FIFO data buffer memorymapped processing.
Hardware volume control pushbutton inputs with
internal pull-up devices up/down/mute that used adjust master volume control. mute input defined state when both down inputs simultaneously.
Zoom Video serial port supports sample rates
MPEG audio.
Configuration Register ES1988 Space Base Address Interrupt Line Power Management Next-Item Pointer Power Management Capabilities Power Management Control/Status Control C2h, (R/W) 10h,11h (R/W) (R/W)
MPU-401 serial port asynchronous serial port MIDI
devices such music keyboard input.
Oscillator circuitry support external crystal. interface provides interface volt
signals. compliant interface supports master/slave.
Record source input volume control input
source volume control recording. recording source selected from four choices:
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ES1988 ALLEGRO DATA SHEET FUNCTIONAL
Memory Architecture
ES1988 includes words on-chip program words on-chip data Application Specific Signal Processor (ASSP) module, which serves device's program data memory. Additionally, ES1988 contains 128-word memory-mapped processing. Figure details Allegro memory architecture. Table Memory Address (Input)
Even Bank 0500 0503 0504 0507 0508 050b 050c 050f 0510 0513 0514 0517
Program words) Program ASSP Core Data Data words)
Bank 0540 0543 0544 0547 0548 054b 054c 054f 0550 0553 0554 0557
Signal Name left right docking left docking right I2S_L I2S_R
ASSP write data either AC-Link S/PDIF addresses listed Table Table Memory Address (Output)_
Even Bank 0520 0523 Bank 0560 0563 0564 0567 0568 056b 056c 056f 0570 0573 0574 0577 0578 057b 057c 057f Signal Name DAC_L (slot DAC_R (slot Center (slot (slot R_SUR (slot LFE_SUR (slot S/PDIF S/PDIF
AC-Link
words
SPDIF
0524 0527 0528 052b 052c 052f
ASSP Memory Mapping
Allegro uses following data program memory maps:
0530 0533 0534 0537 0538 053b 053c 053f
Program Memory
BFFh SRAM)
Data Memory
500h 5FFh (I/O SRAM) 1000h BFFh SRAM) 2000h 2BFFh logical SRAM
S/PDIF Interface
ES1988 allows designer choice routing S/PDIF output either (pin default pin). select SPDIFO GPIO9 pulled down SPDIFO bits (Allegro Configuration register 53h, User Configuration register 58h, enabled. S/PDIF output ES1988 transfers audio data digital format linked data's sampling rate. Each left right channel digital data transferred 32-bit subframe, with subframes making frame data transferred sample rate. Each channel's subframe consists single complement digital sample bits wide conjunction with bits control data. frames data make single data block.
ASSP
Allegro, implemented ping-pong buffer reduce interrupt latency. ASSP read from port 8014h determine which bank available. means Even bank status, while means Even bank status. relative bank available. relative Even bank available. ASSP read data from either AC-Link addresses listed Table
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ES1988 ALLEGRO DATA SHEET FUNCTIONAL
S/PDIF output works conjuction with several control/status registers located space ASSP core. These registers control functionality interface well transfer non-audio data located S/PDIF data stream from DSP.
AC-Link Interface
additional AC-Link ES1988 bi-directional, fixed rate serial digital stream that handles both multiple input output data streams control register accesses using time division multiplexed scheme. Codec Data Output Framing ES1988 AC-Link architecture supports five outgoing data streams, each with 20-bit sample resolution. Specifically, Slots defined AC'97 Rev. spec supported comprise ES1988 SDATA_OUT bi-directional data frame. Figure shows output input frames supported integrated AC'97 Codec.
Integrated AC'97 Codec
integrated AC'97 Codec ES1988 integrates low-pass continuous anti-aliasing filter, 16-bit resolution analog-to-digital converter (ADC), 16-bit digital-toanalog converter. Figure presents block diagram composition.
PCM_L PCM_R AUX_L AUX_GND AUX_R PHONE PCBEEP LINEIN_L LINEIN_R MIC_1
pcmL
vol5 vol5 vol5
pcmR
auxL pseudo -diff singleended auxR
Slot
vol5
zerocrossing) mixL
SYNC
mute mute
zerocrossing) dmixL
vol5 vol4
vol5x vol5x
LINEOUT_L LINEOUT_R
mixR
dmixR
TGOIN STREAM OMIN STREAM Phase
vol5 vol5
0dB/20dB Boost
vol5
dmixL dmixR pcmL pcmR micX AFLT1
Phase
vol5x
MONO_OUT
Mmix dmixL PHONE LINEIN_L auxL micX mixL mixL mixR Mmix dmixR PHONE LINEIN_R auxR micX mixR mixL mixR
Figure ES1988 Bi-directional Data Frame
Rvol
AFLT2 Rvol
Slot Within Slot first global that flags validity entire data frame. valid frame current data frame contains least slot time valid data. next five positions sampled indicate which corresponding five time slots contain valid data.
CAPTURE_L CAPTURE_R digital signals
CAPTURE_R* CAPTURE_L*
Figure Integrated AC'97 Codec Functional Block Diagram
Slot Command Address Port command address port controls features monitors status AC'97 functions. command address port assignments listed Table Table Slot Command Address Bits Functions
18:12 11:0 Function Read/Write command Control Register Index Reserved Description read; write 16-bit locations, addressed even byte boundaries. Stuffed with zeroes.
major functions integrated AC'97 Codec include conversion modem/voice signal data provide interface control logic transfer data between serial terminals Allegro. integrated AC'97 Codec consists signal processing channels associated digital controls each channel. channels operate synchronously that data reception channel data transmission from channel occur during same time interval.
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ES1988 ALLEGRO DATA SHEET FUNCTIONAL
Slot Command Data Port command data port delivers 16-bit control register write data event current command port operation write cycle. current command port operation read cycle, entire time slot must stuffed with zeros digital controller. command data port assignments listed Table Table Slot Command Data Bits Functions
19:4 Function Control Register Write Data Reserved Description Stuffed with zeroes current operation read. Stuffed with zeroes.
Once integrated Codec registers Codec Ready, next five positions sampled ES1988 indicate which corresponding slots assigned input data streams, that they contain valid data. data frame begins with high transition SYNC. SYNC synchronous rising edge BIT_CLK. immediately following falling edge BIT_CLK, integrated Codec samples assertion SYNC.
Slot Playback Left Channel Slot Playback Right Channel Audio output frame slot composite digital audio left playback stream. Audio output frame slot composite digital audio right playback stream. typical "games compatible" this slot composed standard (*.wav) output samples digitally mixed with music synthesis output samples. sample stream resolutions less than bits transferred, Allegro stuffs trailing non-valid positions within this time slot with zeros. Codec Data Input Framing ES1988 AC-Link architecture supports five incoming data streams with 20-bit sample resolution. Specifically, Slots defined AC'97 Rev. spec supported comprise ES1988 SDATA_IN bidirectional data frame. Slot Within Slot first global that flags whether integrated AC'97 Codec Codec Ready state not. Codec Ready integrated AC'97 Codec ready normal operation. This condition normal following deassertion power reset, example, while Allegro's voltage references settle. When Codec Ready Control Status Registers AC-Link fully operational. ES1988 must then further probe Powerdown Control/ Status register determine further subsections, any, ready. Before putting integrated AC'97 Codec into operation, ES1988 polls first data input frame ensure integrated Codec registers have gone Codec Ready.
This falling edge marks time when both sides ACLink aware start data frame. next rising BIT_CLK, integrated Codec transitions SDATA_IN into first position Slot (Codec Ready bit). Each position presented AC-Link rising edge BIT_CLK. Slot Status Address Port status address port controls features monitors status AC'97 functions. status address port assignments listed Table Table Status Address Port Assignments
18:12 Function Reserved Control Register Index SLOTREQ bits Reserved Description Stuffed with zeroes. Echo register index which data being returned. Refer Appendix AC'97 Component Spec. Stuffed with zeroes.
11:2
Slot Status Data Port command data port delivers 16-bit control register read data event current command port operation write cycle. current command port operation read cycle, entire time slot must stuffed with zeros digital controller. status data port assignments listed Table Table Status Port Data Assignments
19:4 Function Control Register Read Data Reserved Description Stuffed with zeroes tagged invalid. Stuffed with zeroes.
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ES1988 ALLEGRO DATA SHEET FUNCTIONAL
Slot Record Left Channel Slot Record Right Channel Audio input frame slot left channel output AC'97's input mux, post-ADC. Audio input frame slot right channel output AC'97's input mux, post-ADC. AC'97 ships output first. There non-valid positions.
I2SDATA
CARD
I2SCLK I2SLR
ES1988
Figure Implementation ES1988
Hardware Master Volume Control
external pins, VOLUP# VOLDN#, connected external momentary switches ground implement hardware master volume controls. Pressing these buttons produces signal inputs thereby changes master volume. MUTE emulated state where both VOLUP# VOLDN# inputs simultaneously. down buttons produce single step change volume when they first pressed. these buttons held down, they enter fast-scrolling mode. inputs have debounce circuitry within ES1988. Hold each input high recognized valid button press. software option allows debounce time reduced. inputs have debounce circuitry within ES1988. Setting bits Allegro Configuration register index 52h/53h enables hardware volume control reduced debounce feature. ES1988 also includes option select from pairs VOLUP# VOLDN# pins User Configuration register index 52h. Setting enables VOLUP# VOLDN# inputs routed pins Setting enables inputs re-routed pins
Table Interface Pins
I2SDATA I2SCLK I2SLR Description Serial data interface. This internal pull-down GNDD. Serial shift clock interface. This internal pulldown GNDD. Left/Right signal interface. This internal pulldown GNDD.
Serial Interface Software Enable mixer register enables data connection interface. Serial Interface Timing Three signals used I2S: I2SCLK shift clock. maximum rate MHz. minimum number I2SCLK periods I2SLR period number greater than equal acceptable. I2SLR Sample synchronization signal. maximum sample rate kHz.
Peripheral Interfacing
Serial Interface input pins I2SDATA, I2SCLK, I2SLR used serial interface external device multiplexed with other functions. Refer Table description interface pins. Allegro_Base+37h register enable input pins. typical application serial interface MPEG audio. Figure
I2SDATA Serial data. Within ES1988, I2SLR I2SDATA sampled rising edge I2SCLK.
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ES1988 ALLEGRO DATA SHEET FUNCTIONAL
Joystick MPU-401 Interface
MPU-401 UART Mode There MIDI interface ES1988, MPU-401 "UART mode" compatible serial port. Joystick MIDI External Interface joystick portion ES1988 reference design identical that standard game control adaptor game port. compatible joystick connected 15-pin D-sub connector. supports standard joystick-compatible software. system already game card port, remove game card.
Selecting DMA/IRQ Policy
Because chipsets support same protocols, policy should selected according chipset use. find which policy use, contact your FAE. policy configured Configuration register 50h, bits [10:8].
Modem Operation
Allegro configureable function modem device, precluding need external modem data pump modem subsystem design. host modem operation, Allegro basic functions related modem operation: Bidirectional circular buffer:
Game Compatibility
emulate bus, ES1988 employ three different protocols: TDMA DDMA PC/PCI Transparent DMA, chipset independent mechanism Distributed DMA, must supported chipset DMA, must supported chipset
Received data sampled ES2828 modem
various frequencies: 7.2, 8.0, 9.0, 9.6, 10.287, depending sample rate. sample rate bits sample) into receive buffer before being sent host.
Transmitted data from host (PCI bus) into
transmit buffer synchronization with receive buffer.
Every samples (configurable), Allegro
checks buffer generates interrupt host buffer (configurable) more samples lets host perform read/write. interrupt level sensitive. control
Once three protocols ES1988 seen device.
TDMA
TDMA, ES1988 snoops transactions legacy controller device then performs master transaction complete DMA. DDMA DDMA, central resource (PCI chipset) includes remap engine. transactions legacy DMACs remapped each client (such ES1988) remap engine. ES1988 then performs master transaction.
PC/PCI
make modem functional, following control
lines recommended: (US/NA version only; handset; universal support) DAA_PM hook Ring indicator Caller (for voice applications) power control
Reset_CDC Reset ES2828 CODEC
PC/PCI DMA, central resource (PCI chipset) performs PC/PCI cycles, which sideband signals standard bus. ES1988 then acts slave device during DMA. edge triggered while level sensitive. configuring policy bits Configuration register 50h, ES1988 emulate IRQ. Setting Legacy Audio Control register (index 40h) allows ES1988 decode legacy audio addresses.
Full interface
Technology, Inc.
SAM0268-031800
ES1988 ALLEGRO DATA SHEET FUNCTIONAL
D3cold Wake-Up Ring
Figure graphically describes basic D3cold wake-up ring operation with ES1988 involved.
Ring Enable
When ES1988 paired with MC'97 part such ES2828 modem AFE, setting Allegro Configuration register index 52h/53h enables RING_IN function received muxed RXD/ GPIO1 muxed TXD/GPIO2 also enabled complete path with ES2828 with interface.
Data Modes
audio-modem configuration, ES1988 supports data modem standards Kb/s. Modulations data rates conform following standards:
Figure D3cold Wake-Up Ring Sequence
During D3cold, VAUX supplies minimal power ES1988 allow power-up system when voltage from ring event detected. When ring event occurs MC97_DI goes high triggers SDATA_IN signal digital controller, which goes high until warm reset applied MC'97 part (such ES2828). PME# event generated ES1988, which turn generates master request power. When master starts send more power digital controller, also sends along RST# signal reset system registers devices peripherals. Before signal completes system-wide reset, PME_EN PME_ST bits control register digital controller need have their values updated MC97_DI's rising edge from ES1988. ES1988 must pass Reset signal integrated AC'97 Codec when PME# event occurred initiation integrated AC'97 Codec, Reset signal will reset device registers prevent digital controller from powering MC97_DI PRD:PRA related logic powered VAUX.
V.90 V.34 V.32bis V.32 V.22bis V.22 V.21 Bell 212A Bell
V.42/MNP error correction V.42bis/MNP data correction reduce error transmission improve data throughput. default command TIES (Time Independent Escape Sequence). Hayes escape sequence, which time dependent, optionally supported. Both escape sequences universally accepted communications software programs.
SAM0268-031800
Technology, Inc.
ES1988 ALLEGRO DATA SHEET FUNCTIONAL
command compatible with EIA/TIA-578 Class Class standards. transmit receive speeds 14.4 Kb/s available. modulations data rates conform standards appearing Table Table Table Modes Supported
Mode V.17 Data Rate (kb/s) 14.4 12.0 Modulation DPSK DPSK
Support Modem Wakeup
Support PME# event generation, modem wakeup, ring input status, time stamp ring data provided ES1988 register level.
Modem Wakeup Control (Allegro_Base+40h/41h):
This register handles PME# event generation from ring input whenPME#_RI (Allegro_Base+40h) enabled.
Data Port (Allegro_Base+50h/+51h): This
register handles ring data input from integrated AC'97 Codec.
V.21ch2 V.27ter
Ring input status (Allegro_Base+42h/43h) Time stamp ring (Allegro_Base+4Ah/
Allegro_BAse+4Ch/4Dh)
V.29
Table Data Modes Supported
Mode V.90 V.34 Data Rate (kb/s) 33.6 31.2 28.8 26.4 24.0 21.6 19.2 16.8 14.4 12.0 14.4 12.0 Modulation DPSK DPSK
V.32bis
V.32
V.22bis V.22 V.21 Bell 212A Bell
Technology, Inc.
SAM0268-031800
ES1988 ALLEGRO DATA SHEET CONFIGURATION REGISTERS
CONFIGURATION REGISTERS
Vendor
Vendor
(00h, 01h,
Revision
Revision
(08h,
Definitions: Bits Name Description 15:0 Vendor Identifies manufacturer this device. 125Dh.
Definitions: Bits Name Description 15:0 Revision Identifies revision this device. assigned Technology, Inc.
Device
Device
(02h, 03h,
Programming Interface Identifier
Programming interface identifier
(09h,
Definitions: Bits Name Description 15:0 Device Identifies ES1988 Allegro. 1988h assigned Technology, Inc.
Definitions: Bits Name Description Identifies programming interface this device. indicates default interface.
Command
(04h, 05h, R/W)
Sub-Class Code
Sub-Class code
(0Ah,
Definitions: Bits 15:3 Name Description Read-only. Returns when read. Master enable/disable. Enable master. master. Read-only. Space access enable/disable. Enable space access. Disable space access.
Definitions: Bits Name Description Identifies type sub-class this device. indicates multimedia device (audiomodem). indicates audio device. indicates modem device.
Base Class Code
Base class code
(0Bh,
Status
Status
(06h, 07h,
Definitions: Bits Name Description Identifies type base class this device. indicates audio device. indicates communication device (modem).
Definitions: Bits 15:0 Name Description Read-only. Returns 0290h when read.
Cache Line Size
Cache line size
(0Ch, R/W)
Definitions: Bits Name Description Identifies cache line size this device 00h.
SAM0268-031800
Technology, Inc.
ES1988 ALLEGRO DATA SHEET CONFIGURATION REGISTERS
Latency Timer
Latency timer
(0Dh, R/W)
Allegro Space Base Address (Modem: Function
IOSB[15:8]
(10h, 11h, R/W)
Definitions: Bits Name Description Number clocks times (read-write audio. Returns when read modem). Read-only. Returns when read.
Definitions: Bits Name Description 15:8 IOSB[15:8] space base address. 128-word space. Reserved. Always write space indicator. Hardwired (2Ch, 2Dh, R/W)
Header Type
Configuration space layout
(0Eh,
Subsystem Vendor
Subsystem Vendor
Definitions: Bits Name Description Single-/multi-function device. ES1988 supports both audio-only single-function multifunction audio-modem device operations. Multi-function device when used audiomodem configuration. Single-function device when used audio-only configuration. Configuration space layout. Read-only. Defines layout bytes configuration space header. ES1988 supports header type.
Definitions: Bits 15:0 Name SVID Description Read/write protected. Default 125Dh. Customizable through register programming EEPROM system BIOS. Writable when
Subsystem
Subsystem
(2Eh, 2Fh, R/W)
BIST Capability
Built-in self test capability
(0Fh,
Definitions: Bits 15:0 Name Description Read/write protected. Default 1988h. Customizable through register programming EEPROM system BIOS. Writable when
Definitions: Bits Name Description BIST Built-in self test capability 00h.
Capability Pointer
Capability pointer
(34h,
Allegro Space Base Address (Audio: Function
IOSB[15:8]
(10h, 11h, R/W)
Definitions: Bits Name Description This register provides pointer into configuration header where power management register block resides. header doublewords contain power management registers. This register read-only returns when read.
Definitions: Bits Name Description 15:8 IOSB[15:8] space base address. 128-word space. Reserved. Always write space indicator. Hardwired
Technology, Inc.
SAM0268-031800
ES1988 ALLEGRO DATA SHEET CONFIGURATION REGISTERS
Interrupt Line (Audio: Function
Interrupt line
Interrupt (3Ch, R/W)
Interrupt
(3Dh,
Definitions: Definitions: Bits Name Description Interrupt line routing information. Indicates which system interrupt ES1988 connected POST software writes routing information Interrupt Line register system initialized configured. value this register depends system architecture. x86-based systems, values correspond with numbers through values from reserved. value (Allegro's default power-up value) signifies either "unknown" connection" system interrupt. default value FFh. Bits [4:0] read/write. Bits [7:5] [4]. (3Ch, R/W)
Interrupt line
Bits
Name Description Interrupt information. Indicates which interrupt ES1988 using. This register read-only returns when read, which indicates INTA#.
Minimum Grant
Minimum grant
(3Eh,
Definitions: Bits Name Description Min_Gnt. Identifies burst period needed. This register read-only returns when read, which corresponds returns modem.
Interrupt Line (Modem: Function
Maximum Latency
Maximum latency
(3Fh,
Definitions: Bits Name Description Interrupt line routing information. Indicates which system interrupt ES1988 connected POST software writes routing information Interrupt Line register system initialized configured. value this register depends system architecture. x86-based systems, values correspond with numbers through values from reserved. value (ES1988's default power-up value) signifies either "unknown" connection" system interrupt. default value FFh. Bits [4:0] read/write. Bits [7:5] [4].
Definitions: Bits Name Description Max_Lat. Identifies often access needed. This register read-only returns when read, which corresponds returns modem.
SAM0268-031800
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ES1988 ALLEGRO DATA SHEET CONFIGURATION REGISTERS
Legacy-Compatible Audio Registers
Legacy Audio Control
MIDIIRQ SBIRQ
(40h, 41h, R/W)
DMACH
Legacy Audio Support ES1988 supports following legacy audio addresses. Table Supported Legacy Audio Addresses
Legacy Audio Resources Sound Blaster Address Base 220h/240h 388h/289h/38Ah/38Bh 300h/320h/330h/340h Channel
Definitions: Bits Name Description Legacy audio disable. Disable legacy audio (default). Enable legacy audio. Serial IRQs enable. Enable serial IRQs. Disable serial IRQs (default).
synthesis MPU-401
Allegro Configuration
(50h, 51h, R/W)
13:11 MIDIIRQ MIDI select. Read-only. Default 010. 10:8 SBIRQ Sound Blaster select. Selection IRQ5 (default) IRQ7 IRQ9 IRQ10 Reserved DMACH Sound Blaster channel select. Channel Selection Channel Channel (default) Reserved Channel address aliasing control. Enable address aliasing (default). Selects 10-bit I/O. Disable address aliasing. MPU-401 enable. Enable MPU-401 (default). Disable MPU-401 IRQ. MPU-401 enable. Enable MPU-401 (default). Disable MPU-401 I/O. Game port enable. Enable game port (default). Disable game port. synthesis enable. Enable synthesis (default). Disable synthesis. Sound Blaster enable. Enable Sound Blaster channel (default). Disable Sound Blaster channel.
PIC1 PIC0 DMAP S(V)ID
Definitions: Bits Name Description Sound Blaster mask. this enable masking when [10] PCI1 snoop mode this mode when ES1988 assigned IRQ5/7/9/10. PCI0 snoop mode this mode when ES1988 assigned IRQ5/7/9/10. High-performance game port mode enable. Enable game port. Disable game port. Safeguard TDMA mode, when bits [10:8] 001. this enable merge during 08h. write-back AutoDMA mode, when bits [10:8] 100. this enable write-back AutoDMA mode.
10:8 DMAP policy. Policy Distributed Transparent PC/PCI Reserved write-back every transfers write-back every transfers write-back every transfers write-back every transfer EN_PW. Posted write enable. Enable ES1988 posted write. Disable ES1988 posted write.
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET CONFIGURATION REGISTERS
Bits Name Description Emulate timing PCI. timing. Emulate timing. -Reserved.
Bits 10:9
Name
Description
MPU_401_DECODE. MPU-401 SB240. Sound Blaster decode. Sound Blaster decode 24x. Sound Blaster decode 22x. Subtractive decoding. Write: Delay grant clock during master cycle enable detection subtractive decoding. Read: Subtractive decoding detected.
CLKSL Clock divider select Sound Blaster. Clock Divider Divided Divided Divided Reserved S/PDIF enable. Enable S/PDIF output. Disable S/PDIF output (default). Hardware volume control enable. Enable hardware volume control. Disable hardware volume control. Reduced debounce hardware volume control enable. Enable reduced debounce. Disable reduced debounce. Up/down hardware volume button input select. Select input from Select input from (default). BIT_CLK Direction Codec Interface Input Output (default) Writable EEPROM Interface Enable. Enable writable EEPROM interface. Disable writable EEPROM interface. Clock Multiplier Mode Select. Used along with (bits 13:12) support eight modes clock multiplier.
Write-enable subsystem (SID) subsystem vendor (SVID). SVID read/write. SVID read-only (default).
Allegro Configuration
(52h, 53h, R/W)
CLKSL SPDIF
CxMS
Definitions: Bits Name Description Internal clock multiplier reset enable. Reset internal clock multiplier. Release internal clock multiplier. ES1988 clock input select. Select 49.152 clock from internal clock multiplier. Select 49.152 clock from external crystal oscillator input (OSCI). Clock multiplier mode select. Mode Mode Mode Mode Mode Mode Mode Mode Mode Power management control CLKRUN# enable. Enable control CLKRUN#. Disable control CLKRUN#.
SPDIF SPDIF test mode. Enable SPDIF test mode. RI_E Ring Enable. Enable Ring from GPIO0 MC97. Disable Ring from GPIO0 MC97.
13:12
SAM0268-031800
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ES1988 ALLEGRO DATA SHEET CONFIGURATION REGISTERS
ACPI Power Management Registers
ACPI Control
Bits
Name Description MIDI ACPI stop clock control MIDI. stop clock state stop clock state ACPI stop clock control game port. stop clock state stop clock state Reserved.
(54h, 55h, R/W)
SPDIF GLUE GPIO ASSP XCLK MIDI
ACPI Control register sets state stop clock each module clocks, clocks, SPDIF, GLUE, interface, hardware volume, modem/GPIO, ASSP interface, clock multiplier, MIDI game port).
Definitions: Bits Name Description ACPI stop clock control clock serial interface secondary Codec output. stop clock state stop clock state ACPI stop clock control clock internal AC97 Codec. stop clock state stop clock state Reserved.
ACPI Control
(56h, 57h, R/W)
SPDIF GLUE GPIO ASSP XCLK MIDI
ACPI Control register enables clock state each module ACPI Control register.
Definitions: Bits Name Description ACPI stop clock enable clock serial interface secondary Codec output. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled. ACPI stop clock enable clock internal AC97 Codec. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled. Reserved.
SPDIF ACPI stop clock control SPDIF. stop clock state stop clock state GLUE ACPI stop clock control GLUE. stop clock state stop clock state Reserved. ACPI stop clock control interface. stop clock state stop clock state ACPI stop clock control volume control. stop clock state stop clock state
SPDIF ACPI stop clock enable SPDIF. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled. GLUE ACPI stop clock enable GLUE. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled. Reserved. ACPI stop clock enable interface. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled. ACPI stop clock enable hardware volume control. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled.
GPIO ACPI stop clock control GPIO. stop clock state stop clock state ASSP ACPI stop clock control ASSP interface. stop clock state stop clock state ACPI stop clock control Sound Blaster. stop clock state stop clock state ACPI stop clock control stop clock state stop clock state
GPIO ACPI stop clock enable GPIO. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled. ASSP ACPI stop clock enable ASSP interface. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled. ACPI stop clock enable Sound Blaster. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled.
XCLK ACPI stop clock control clock multiplier. stop clock state stop clock state
Technology, Inc.
SAM0268-031800
ES1988 ALLEGRO DATA SHEET CONFIGURATION REGISTERS
Bits
Name Description ACPI stop clock enable Enable stop clock state D1/D2. Stop clock state D1/D2 disabled.
Bits
Name Description Tri-state buffer enable. Tri-state output buffers. Don't tri-state buffers. Reserved. AC97 Codec Test Mode Enable Enable test mode internal AC97 Codec. Normal operation. NOTE: signal from internal AC'97 codec will driven GD[4] Reserved. Route SPDIF output IDSEL Route SPDIF output PME# (default). Note: must pulled down order select S/PDIF output
XCLK ACPI stop clock enable clock multiplier. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled. MIDI ACPI stop clock enable MIDI. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled. ACPI stop clock enable game port. Enable stop clock state D1/D2. Stop clock state D1/D2 disabled. Reserved.
User Configuration
(58h, 59h, R/W)
C3OB
Definitions: Bits Name Description REQ# State Enable. Enables driving REQ# state. REQ# Tri-state State Enable Enable tri-state REQ# state. EAPD Drive Enable Enable EAPD signal from internal AC97 Codec. Disable EAPD signal from internal AC97 Codec Stop Clock Enable Crystal Oscillator Enables stop clock crystal oscillator state. Enable external master support without Quick Switch Enable support. External Master Pair Select External Master Pair selected from External Master Pair selected from (default). Multi-Function Enable/Disable Disable multi-function feature through software. Enable multi-function feature through software. clock input. Select input clock internal AC97 Codec from divider external crystal oscillator clock (OSCI/2). Select input clock internal AC97 Codec from external crystal oscillator clock (OSCI).
Arbiter Enable. Default Enable master support. Disable master support (default).
User Configuration
Reserved
(5Ah, 5Bh, R/W)
Definitions: Bits 15:0 Name Description Reserved.
User Configuration
Reserved PMGM
(5Ch, R/W)
Reserved PMGS
Definitions: Bits 15:6 Name PMGM Description Reserved. PME# MC97 Enable. PME# generation enabled from MC97_DI input Reserved. PME# SDI2 Enable PME# generation enabled from SDI2 input
PMGS
SAM0268-031800
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ES1988 ALLEGRO DATA SHEET CONFIGURATION REGISTERS
Distributed Control
DMA[15:4]
60h, 61h, R/W)
Power Management Registers
Next-Item Pointer
Next-Item pointer
(C1h,
Definitions: Bits Name Description 15:4 DMA[15:4] Distributed base address. Always write Distributed enable. Enable distributed DMA. Disable distributed DMA. (6Ch, 6Dh, R/W)
Definitions: Bits Name Description This register used indicate next item linked list power management capabilities. Since ES1988 functions only include capabilities item, this register read-only returns when read audio only.
Subsystem Vendor Shadow
Subsystem Vendor Shadow
Definitions: Bits 15:0 Name SVID [15:0] Description Subsystem Vendor Shadow 2Ch, 2Dh. (6Eh, 6Fh, R/W)
Subsystem Shadow
Subsystem Shadow
Definitions: Bits 15:0 Name [15:0] Description Subsystem Shadow 2Eh, 2Fh.
Capability
Capability
(C0h,
Definitions: Bits Name Description This register identifies linked list item register power management. This register read-only returns when read, which unique assigned location capabilities pointer value.
Technology, Inc.
SAM0268-031800
ES1988 ALLEGRO DATA SHEET CONFIGURATION REGISTERS
Power-Management Capabilities
PMES Reserved
(C2h, C3h,
PMEC
Power-Management Control/Status
(C4h,
STATE
Definitions: Bits Name Description 15:11 PMES PME_Support. This five-bit field indicates power states which function assert PME#. value indicates that function capable asserting PME# signal while that power state. [15] PME# cannot asserted from D3cold. [14] PME# asserted from D3hot. [13] PME# asserted from [12] PME# asserted from [11] PME# cannot asserted from Value bits 15:11 Bits 15:11 01110. Audio Only Function Bits 15:11 =11110. Modem w/VAUX Function D2S. This indicates that this function supports power management state. power management supported. D1S. This indicates that this function supports power management state. power management supported. Reserved. Bits Audio Only Function Bits Modem w/VAUX, Function Device Specific Initialization indicates whether special initialization this function required before generic class device driver able Always Reserved. PMEC clock. This indicates that clock required function generate PME#. Value Version. This 3-bit field indicates that this function complies with Revision Power Management Interface specification. Always 010.
default value this register 00h. This register determines changes current power state ES1988 function. contents this register affected internally-generated reset caused transition from D3hot state.
Definitions: Bits Name Description Bits [7:2] read-only return when read. Power state. This 2-bit field used both determine current power state function, function into power state. Power State D3hot
Control
(C5h, R/W)
Definitions: Bits Name Description PME# status. Read PME# Status PME# active. PME# inactive. Write clear status bit. Bits [6:1] read-only return when read.
PME# enable. Enable PME. Disable PME.
SAM0268-031800
Technology, Inc.
ES1988 ALLEGRO DATA SHEET ALLEGRO REGISTERS
ALLEGRO REGISTERS
Host Interrupt Control
Reserved
Host Interrupt Status (Allegro_Base+18h, +19h, R/W)
Reserved IHWV
(Allegro_Base+1Ah, R/W)
Reserved
Definitions: Definitions: Bits Name Description ES1988 software reset enable. Enable ES1988 software reset. Disable ES1988 software reset. Reserved. Bits Name Description Reserved.
IHWV Hardware volume control interrupt. Hardware volume control interrupt pending. hardware volume control interrupt. Ring indicator interrupt. Ring interrupt pending. ring indicator interrupt. ASSP software interrupt. ASSP interrupt pending. ASSP interrupt. Reserved. MPU-401 receive interrupt. MPU-401 receive interrupt pending. MPU-401 receive interrupt. Sound Blaster interrupt. Sound Blaster interrupt pending. Sound Blaster interrupt.
14:11
Hardware volume control PME# generation enable. Reserved. CLKRUN# generation test mode enable. Enable CLKRUN# generation time. Disable CLKRUN# generation. Reserved.
Hardware volume control interrupt enable. Enable hardware volume control interrupt. Disable hardware volume control interrupt. Ring interrupt enable Enable ring interrupt. Disable ring interrupt. ASSP software interrupt enable. Enable ASSP software interrupt. Disable ASSP software interrupt. Reserved.
Hardware Volume Control
Reserved
(Allegro_Base+1Bh, R/W)
Split
MPU-401 interrupt enable. Enable MPU-401 interrupt. Disable MPU-401 interrupt. Sound Blaster interrupt enable. Enable Sound Blaster interrupt. Disable Sound Blaster interrupt.
Definitions: Bits Name Description Split Reserved. Hardware volume/counter control register split. Split volume register from counter register. split volume from counter register.
Shadow Mixer Register Voice
(Allegro_Base+1Ch, R/W)
Shadow Mixer Voice
Definitions: Bits Name Description Shadow mixer register voice.
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET ALLEGRO REGISTERS
Volume Control Counter Voice
Joystick X-Delay (Allegro_Base+1Dh, R/W)
(Allegro_Base+28h,+29h, R/W)
Delay
Hardware volume control counter voice
Definitions: Definitions: Bits Name Description Hardware volume control counter voice. Bits Name 15:12 2A/2B 1A/1B Description Fire buttons.
11:0 Delay[11:0] Timer delay units microseconds.
Shadow Mixer Register Master
(Allegro_Base+1Eh, R/W)
Joystick Y-Delay
(Allegro_Base+2Ch,+2Dh, R/W)
Delay
Shadow Mixer Master
Definitions: Bits Name Description Shadow mixer register master.
Definitions: Bits Name 15:12 2A/2B 1A/1B Description Fire buttons.
Volume Control Counter Master
11:0 Delay[11:0] Timer delay units microseconds.
(Allegro_Base+1Fh, R/W)
Hardware volume control counter master
Definitions: Bits Name Description Hardware volume control counter master.
Game Port Control Registers Joystick X-Delay
(Allegro_Base+20h,+21h, R/W)
Delay
Definitions: Bits Name 15:12 2A/2B 1A/1B Description Fire buttons.
11:0 Delay[11:0] Timer delay units microseconds.
Joystick Y-Delay
(Allegro_Base+24h,+25h, R/W)
Delay
Definitions: Bits Name 15:12 2A/2B 1A/1B Description Fire buttons.
11:0 Delay[11:0] Timer delay units microseconds.
SAM0268-031800
Technology, Inc.
ES1988 ALLEGRO DATA SHEET ALLEGRO REGISTERS
Codec Control Registers
CODEC Command Status
Serial Control Registers
(Allegro_Base+30h,
Serial Control
(Allegro_Base+36h,+37h, R/W)
Reserved
SDFS SDFS
Definitions: Bits Name Description Read/Write. Read cycle. Write cycle. CODEC register address.
Definitions: Bits Name Description input enable. Enable input. Disable input. Reserved.
AD[6:0]
CODEC Command Status
(Allegro_Base+30h,
EN_IOSRAM. SRAM enable. SRAM Enable SRAM. Disable SRAM. Serial AC-link enable. Enable serial AC-link. Disable serial AC-link.
Definitions: Bits Name Description Reserved. Always read Read/write status. CODEC register read/write progress. CODEC register read/write done.
Driving SDFS local AC-link enable. SDFS Enable driving SDFS local AC-link. Disable driving SDFS local AC-link. Driving from local AC-link. Enable driving from local AC-link. Disable driving from local AC-link.
CODEC Data
(Allegro_Base+32h,+33h,
CODEC Data
Definitions: Bits Name 15:0 Description bits data written CODEC.
Driving SDFS remote AC-link enable. SDFS Enable driving SDFS remote AC-link. Disable driving SDFS remote AC-link. Driving from remote AC-link. Enable driving from remote AC-link. Disable driving from remote AC-link. Reserved.
CODEC Data
(Allegro_Base+34h,+35h,
CODEC Data
Definitions: Bits Name 15:0 Description bits data read from CODEC.
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET ALLEGRO REGISTERS
Serial Control
MC_INT SSPE CDC2 SPDIF
(Allegro_Base+38h, R/W)
Bits Name Description R/LF R_SURR/LFE output. Destination Local Remote Mute Both Center/L_SURR output. Destination Local Remote Mute Both
Definitions: Bits Name Description Interrupt enable. Enable interrupt ASSP. Disable interrupt ASSP. SBMIF Enable Sound Blaster module interface. Disable Sound Blaster module interface. CDC2 Enable second AC-link. Enable single AC-link. SPDIF Enable S/PDIF function. Disable S/PDIF function. Modem Slot Select Enable Select MC97_DI modem slot. Select SDI1 modem slot. Reserved. Second CODEC CODEC Reserved. AC-Link. Reserved.
L1DAC Line output. Destination Local Remote Mute Both output. Destination Local Remote Mute Both Command address output. Destination Local Remote Codec Reserved
Output Destination Control
L2DAC R/LF
(Allegro_Base+3Ah, R/W)
L1DAC
Input Destination Control
L2ADC
(Allegro_Base+3Ch, R/W)
L1ADC
Definitions: Bits Name Description 15:14 control output. Destination Local Remote Mute Both Handset output. Destination Local Remote Mute Both
Definitions: Bits Name Description 15:14 status input. Destination Local Remote Handset input. Destination Local Remote Mute both
13:12
13:12
11:10 L2DAC Line output. Destination Local Remote Mute Both
11:10 L2ADC Line input. Destination Local Remote Mute both
SAM0268-031800
Technology, Inc.
ES1988 ALLEGRO DATA SHEET ALLEGRO REGISTERS
Bits Name Description Reserved. input. Destination Local Remote
Time Stamp Ring
(Allegro_Base+4Ah,+4Bh,
TS0_RI
Definitions: Bits Name Description 15:0 TS0_RI Time stamp Ring.
L1ADC Line input. Destination Local Remote Mute both input. Destination Local Remote Reserved Both Status address/data input. Destination Local Remote Codec Reserved
Time Stamp Ring
(Allegro_Base+4Ch,+4Dh,
TS1_RI
Definitions: Bits Name Description 15:0 TS1_RI Time stamp Ring.
Data Input Output Port
(Allegro_Base+50h,+51h, R/W)
Data
Definitions:
Modem Wakeup Control
Reserved
Bits Name
Description
(Allegro_Base+40h,+41h, R/W)
PMG_RI Reserved
15:1 DDI/O data input/output MC'97. Ring data input from MC'97.
Definitions: Bits Name 15:5 PMG_RI Description Reserved. Enable PME# generation from ring input. Reserved
GPIO Registers
GPIO Data
(Allegro_Base+60h, +61h, R/W)
GPIO data
Definitions: Bits Name Description
Modem Ring Input Status
(Allegro_Base+42h,+43h, R/W)
Reserved
15:0
GPIO data.
GPIO Mask
(Allegro_Base+64h, +65h, R/W)
GPIO write mask
Definitions: Bits Name 15:3 Description Reserved. Ring Input Status Read ring input status. Indicates ring input pulsing. Ring input idle. Write clear status bit. Reserved.
Definitions: Bits Name Description 15:0 GPWM GPIO write mask. Mask write. Unmask write.
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET ALLEGRO REGISTERS
GPIO Direction
(Allegro_Base+68h, +69h, R/W)
GPIO direction
Game Port Address Registers Game Port Address
(Allegro_Base+90h, R/W)
Native address port game port
Definitions: Bits Name Description 15:0 GPIO direction. Output. Input (default).
Definitions: Bits Name NAGP Description Native address port game port. Alias port 200h.
ASSP Memory Control Registers
ASSP Memory Index Port
Game Port Address
(Allegro_Base+91h, R/W)
Native address port game port
(Allegro_Base+80h,+81h, R/W)
ASSP memory/index
Definitions: Bits Name NAGP Description Native address port game port. Alias port 201h.
Definitions: Bits Name 15:0 AM/I Description Host-to-ASSP 16-bit memory index port. Points word ASSP memory.
Game Port Address
(Allegro_Base+92h, R/W)
Native address port game port
ASSP Memory Port
(Allegro_Base+82h,+83h, R/W)
Reserved
Definitions: Bits Name NAGP Description Native address port game port. Alias port 202h.
Definitions: Bits Name 15:2 Description Reserved. memory space selection. Memory Space Reserved ASSP program memory ASSP data memory
Game Port Address
(Allegro_Base+93h, R/W)
Native address port game port
Definitions: Bits Name NAGP Description Native address port game port. Alias port 203h.
ASSP Data Port
(Allegro_Base+84h,+85h, R/W)
ASSP data
Game Port Address
(Allegro_Base+94h, R/W)
Native address port game port
Each time this register accessed read write, ASSP Memory/Index port (Allegro_Base+80h, +81h) incremented index port word paged consecutive access cannot cross this word boundary.
Definitions: Bits Name 15:0 Description 16-bit data (word) port.
Definitions: Bits Name NAGP Description Native address port game port. Alias port 204h.
SAM0268-031800
Technology, Inc.
ES1988 ALLEGRO DATA SHEET ALLEGRO REGISTERS
Game Port Address
(Allegro_Base+95h, R/W)
MPU-401 Port Address
(Allegro_Base+9Ah, R/W)
Native address port game port
Native address port MPU-401
Definitions: Bits Name NAGP Description Native address port game port. Alias port 205h.
Definitions: Bits Name NAMPU Description Native address port MPU-401. Alias port 332h.
Game Port Address
(Allegro_Base+96h, R/W)
MPU-401 Port Address
(Allegro_Base+9Bh, R/W)
Native address port game port
Native address port MPU-401
Definitions: Bits Name NAGP Description Native address port game port. Alias port 206h.
Definitions: Bits Name NAMPU Description Native address port MPU-401. Alias port 333h.
Game Port Address
(Allegro_Base+97h, R/W)
Native address port game port
Clock Multiplier Data Port
(Allegro_Base+9Ch, +9Dh,
Definitions: Bits Name NAGP Description Native address port game port. Alias port 207h. Definitions: Bits Name Description Reserved. counter status. counter status. counter status.
14:10
MPU-401 Address Registers MPU-401 Port Address
(Allegro_Base+98h, R/W)
Native address port MPU-401
Definitions: Bits Name NAMPU Description Native address port MPU-401. Alias port 330h.
MPU-401 Port Address
(Allegro_Base+99h, R/W)
Native address port MPU-401
Definitions: Bits Name NAMPU Description Native address port MPU-401. Alias port 331h.
Technology, Inc.
SAM0268-031800
ES1988 ALLEGRO DATA SHEET ALLEGRO REGISTERS
ASSP Clock Control Registers
ASSP Control
Reserved 36CLK Reserved
(Allegro_Base+A2h, R/W)
33/49CLK Reserved
Definitions: Bits Name 36CLK 33/49 Description Reserved. clock select. Select clock. Reserved. 49.152 ASSP clock select. Enable 49.152 ASSP clock. Enable ASSP clock. Reserved. ASSP 0-wait state enable. Enable ASSP 0-wait state. Disable ASSP 0-wait state.
ASSP Control
Reserved
(Allegro_Base+A4h, R/W)
Reserved ARST
Definitions: Bits Name Description Reserved. Clock run/enable. Stop ASSP clock. Enable ASSP clock. Reserved. ASSP reset/run. ASSP. Reset ASSP.
ARST
ASSP Host Status
(Allegro_Base+ACh, R/W)
ASSP status
Definitions: Bits Name Description ASSP host software interrupt request status. Read pending interrupt status. Interrupt pending. interrupt pending. Write clear pending interrupt request. bits this register ASSP request interrupts from host.
SAM0268-031800
Technology, Inc.
ES1988 ALLEGRO DATA SHEET INTEGRATED AC'97 CODEC REGISTERS
INTEGRATED AC'97 CODEC REGISTERS
Basic
Reset
SE4:SE0 Reserved
Table Master Volume Control Bits
Mute MVx4 MVx3 MVx2 MVx1 MVx0 continued. Description Reserved. Always write -46.0 Gain -1.5 -3.0
(00h,
Writing value this register performs register reset, which causes registers revert their default values except Powerdown Control/Status register.
Definitions: Bits 15:14 13:9 Name
Master Volume Mono
Mute
(06h, R/W)
Master volume mono
SE4:SE0 Stereo Enhancement enable bits. stereo enhancement features enabled. Reserved. Always write
Master Volume Control
Mute Master volume left
(02h, R/W)
Master volume right
This register controls master playback volume mono out. maximum setting (00h) corresponds gain, with each step adding -1.5 gain. reset, default value 8000h.
Bits Definitions: Bits Name Mute Description Mute enabled. Master volume Mute disabled. Don't care.
This register controls master playback volume. maximum setting (00h) corresponds gain, with each step adding -1.5 gain. reset, default value 8000h.
Bits Definitions: Bits Name Mute Description Mute enabled. Master volume Mute disabled. Don't care. Sets volume level LINE_OUT_L output. Don't care. Sets volume level LINE_OUT_R output.
14:5
MN[4:0] Sets volume level mono output.
14:13 12:8
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET INTEGRATED AC'97 CODEC REGISTERS
Beep
Mute Reserved
(0Ah,
PV3:PV0
Analog Mixer Input Gain Registers
These registers control volume each analog inputs. maximum setting (00h) corresponds gain. Each step adds -1.5 gain down minimum -34.5 attenuation (1Fh). Table shows relationship between volume bits gain value registers 0Ch, 0Eh,
This register controls level Beep input. maximum setting (00h) corresponds gain. Each step corresponds approximately gain. this register mute bit. When this level that channel
Table Analog Mixer Input Volume Gain Beep supports motherboard implementations. intention routing Beep through mixer eliminate requirement on-board speaker. Automatically connecting Beep LINE_OUT outputs soon part powers completes calibration supports implementation.
Mute Gain 12.0 10.5
continued. -1.5 -3.0
Beep LINE_OUT connection broken when SYNC sampled high. ES1988 will need route Beep LINE_OUT outputs AC-Link control desired. reset, default value 8000h. Table Beep Volume Gain
Mute continued. +42.0 +45.0 Gain +3.0 +6.0 +9.0
continued. -33.0 -34.5
Phone Volume
Mute
(0Ch, R/W)
Phone volume
This register controls gain attenuation analog phone input. phone input mono input. reset, default value 8008h, which corresponds gain with mute
Bits Definitions: Bits Name Mute Description Extended mode, Mute applies only left channel. Mute enabled. Phone volume Mute disabled. Don't care. Analog phone gain support bits 4:0. Sets volume level Phone input.
14:5
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ES1988 ALLEGRO DATA SHEET INTEGRATED AC'97 CODEC REGISTERS
Line Volume
Mute Gain 12.0 10.5
(10h, R/W)
Line volume right
Mute
Line volume left
continued. -1.5 -3.0
This register controls Line volume. reset, default value 8808h.
Bits Definitions: Bits Name Mute Description Mute enabled. Line volume Mute disabled. Don't care. Sets volume level LINE_IN_L input. Don't care. Sets volume level LINE_IN_R input.
continued. -33.0 -34.5
14:13 12:8
Volume
Mute
(0Eh, R/W)
volume
This register controls volume microphone input. input mono input. reset, default value 8008h.
Bits Definitions: Bits Name Mute Description Mute Enable. Mute enabled. volume Mute disabled. Don't care. boost enabled. boost disabled. Don't care. Sets volume level input.
Mute
Gain 12.0 10.5
continued. -1.5 -3.0
14:7
continued. -33.0 -34.5
Volume
Mute Gain 12.0 10.5
(12h, R/W)
volume left volume right
Mute
This register controls volume. reset, default value 8808h.
Bits Definitions: Bits Name Mute Description Mute enabled. volume Mute disabled. Don't care. Sets volume level input. Don't care. Sets volume level input.
continued. -1.5 -3.0
continued. -33.0 -34.5
14:13 12:8
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET INTEGRATED AC'97 CODEC REGISTERS
Record Select
Mute Gain 12.0 10.5
(1Ah, R/W)
Record select left Record select right
This register selects record sources left right channel. reset, default value 000h.
Bits Definitions: Bits Name 15:11 10:8 SL[2:0] Description Don't care. Selects left channel record source: source (default) mono_mix (output mono before MONO_OUT volume) dmix (signal just before LINE_OUT_L volume) Line left Stereo left (without data mixed) Mono (without data mixed) Phone Don't care. Selects right channel record source: source (default) mono_mix (output mono before MONO_OUT volume) dmix (signal just before LINE_OUT_R volume) LINE_IN_R Stereo left (without data mixed) Mono (without data mixed) Phone
continued. -1.5 -3.0
continued. -33.0 -34.5
Playback Volume Control
Mute volume left
(18h, R/W)
volume right
This register controls volume. reset, default value 8808h.
Bits Definitions: Bits Name Mute Description Mute enabled. volume Mute disabled. Don't care. Sets volume level left channel playback. Don't care. Sets volume level right channel playback. SL[2:0]
14:13 12:8
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ES1988 ALLEGRO DATA SHEET INTEGRATED AC'97 CODEC REGISTERS
Record Gain
Mute Record gain left
(1Ch, R/W)
Record gain right
General Purpose
LPBK
(20h, R/W)
This register sets volume level record input. minimum setting (00h) corresponds gain. Each step adds gain maximum 22.5 gain (0Fh). Table shows relationship between record volume bits gain value register 1Ch. reset, default value 8000h.
Bits Definitions: Bits Name Mute Description Mute enabled. Record gain Mute disabled. Don't care. Sets volume level Record input. Don't care. Sets volume level Record input.
This register controls number miscellaneous functions. This register should read before writing generate mask only bit(s) that need changed. reset, default value 0000h.
Bits Definitions: Bits Name 15:10 Description Don't care. Mono Output Select Mixer Mono Control Output dmix mono micX mono Don't care. This enables loopback output input without involving ACLink. This allows full system performance measurements. Enable ADC/DAC loopback mode. Disable ADC/DAC loopback mode. Don't care.
14:12 11:8
LPBK
Mute
continued.
Gain
21.0 22.5
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET INTEGRATED AC'97 CODEC REGISTERS
Powerdown Control/Status
EAPD PR5:PR0
(26h, R/W)
Bits Name Description This section powered down when state preserved. DACs powered down. DACs powered This section powered down when state preserved. ADCs, input volume control, input powered down. ADCs input powered READ-ONLY. Don't care. READ-ONLY. VREF nominal level. READ-ONLY. Analog mixers, etc. ready. READ-ONLY. section ready accept data. READ-ONLY. section ready transmit data.
This register used program powerdown states monitor subsystem readiness. When AC-Link "CODEC ready" (SDATA_IN slot indicates that AC-Link ES1988 control status registers fully operational. ES1988 must check bits determine exactly which subsections ready. Bits read-only. Writes will have effect these bits. Bits after cold reset. each subsection becomes ready resume normal operation, corresponding becomes This register affected write reset register. integrated AC97 Codec powerdown bits that control powerdown operation throughout ES1988. stored value EAPD (bit routed controller portion ES1988 provide powerdown capabilities external amplifier section standalone AC'97 Codec part.
Bits Definitions: Bits Name Description EAPD External Amplifier Power Down bit. EAPD high signal external amplifier shut down. EAPD signal external amplifier turn (default). Reserved Power down digital section clock. Digital section powered down with clock disabled. Digital section powered with clock enabled. Digital section powered down with oscillator enabled. analog mixer still function. 24.576 oscillator still runs. This cleared either cold warm reset. digital section powers quickly oscillator still running. Digital section powered Analog mixer powered down (Vref off). this case, ADCs, DACs, Mixer, Vref also powered down; however, state PR2:0 preserved. Analog mixer powered This section powered down when state preserved. Analog mixer powered down with reference generator still enabled. Analog mixer powered
Integrated AC'97 Registers Extended Audio
Extended Audio
AMAP
(28h,
This register used identify extended audio features that supported addition original AC'97 features identified Reset register. reset, default value 0002h.
Bits Definitions: Bits Name 15:14 13:10 AMAP Description Reserved. Don't care. AC-Link Slot Audio Select. AC97 Rev. mapping supported. AC'97 mapping supported. Don't care. Double Rate Audio Select. Double rate audio supported. Double rate audio supported. Don't care.
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ES1988 ALLEGRO DATA SHEET INTEGRATED AC'97 CODEC REGISTERS
Extended Audio Status Control
(2Ah, R/W)
Enable
ASSP Registers
Host Memory Address (Low Word)
(ASSPIO_4000h, R/W)
This register used test integrated AC97 Codec. reset, default value 0000h.
Bits Definitions: Bits Name 15:2 Enable Description Don't care. Double Rate Audio Enable. Double rate audio mode enabled. Double rate audio mode disabled. Don't care.
Host Memory Address (Low Word)
This register corresponds address [15:1].
Bits Definitions: Bits Name Description 15:1 HMEA Host Memory Address (Low Word). Reserved. Always write
Vendor Registers
Vendor
First vendor character
Host Memory Address (High Word)
Reserved
(ASSPIO_4001h, R/W)
Host Memory Address (High Word)
(7Ch,
Second vendor character
This register corresponds address [27:16].
Bits Definitions: Bits Name 15:12 Description Reserved. Always write read back Host Memory Address (High Word).
This register encodes first ASCII character vendor
Bits Definitions: Bits Name 15:8 Description Encodes first ASCII character vendor Encodes second ASCII character vendor
11:0 HMEA
ASSP Data Memory Address (ASSPIO_4002h,
ASSP Data Memory Address
Vendor
Third vendor character
(7Eh,
Bits Definitions: Bits Name 15:0 ADMA Description ASSP Data Memory Address.
This register encodes third ASCII character vendor vendor revision number.
Bits Definitions: Bits Name 15:8 Description Encodes third ASCII character vendor Revision number. Returns when read.
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ES1988 ALLEGRO DATA SHEET INTEGRATED AC'97 CODEC REGISTERS
Host Memory Starting Address/ Current Pointer (Low Word) (ASSPIO_4003h, R/W)
Host Memory Address/Pointer (Low Word)
ASSP Data Memory Starting Address/Current Pointer
(ASSPIO_4005h, R/W)
ASSP Data Memory Address/Pointer
When this register written ASSP, means host memory starting address. This register corresponds address [15:1].
Bits Definitions: Bits Name Description 15:1 HMSA Host Memory Starting Address (Low Word). Reserved. Always write
When this register written ASSP, means ASSP data memory starting address.
Bits Definitions: Bits Name 15:0 DDMS Description ASSP Data Memory Starting Address.
When this register read from ASSP, means current host address pointer. pointer updated after each data transfer.
Bits Definitions: Bits Name 15:1 Description Current host address pointer. Reserved. Always read back
When this register read from ASSP, means ASSP data memory address pointer. pointer updated after each data transfer.
Bits Name 15:0 Description ASSP data memory address pointer.
Host Memory Starting Address/ Current Pointer (High Word) (ASSPIO_4004h, R/W)
Reserved Host Memory Starting Address (High Word)
When this register written ASSP, means host memory starting address. This register corresponds address [27:16].
Bits Definitions: Bits Name 15:12 11:0 HMSA Description Reserved. Always write Host Memory Starting Address (High Word).
When this register read from ASSP, means current host address pointer. pointer updated after each data transfer.
Bits Definitions: Bits Name 15:12 11:0 CHAP Description Reserved. Always write Current host address pointer (corresponding address [27:16].
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ES1988 ALLEGRO DATA SHEET INTEGRATED AC'97 CODEC REGISTERS
Control
Reserved AMEAS HMEAS DSPINT
(ASSPIO_4006h, R/W)
DMACTRL
Bits Name CTRL
Description Word transfer counts one-time kickoff from words (00h FFh).
When this register written ASSP, host data memory reads writes being monitored. Hardware interrupts generated necessary address counter crosses host memory boundary. Bits read-only return host ASSP data memory address status when read. Four mechanisms will cause ASSP hardware interrupt generated. Completion data transfer. host memory address been reached (I/O 4206, ASSP memory address been reached (I/O 4206, host memory boundary been crossed (I/O 4206,
Bits Definitions: Bits Name 15:10 DSPINT Description Reserved. Always write ASSP Crossing Boundary Interrupt Enable. Enable. Disable. ASSP Host Memory Read/Write Enable. Read ASSP data memory write host memory. Read host memory write ASSP data memory.
When this register read from ASSP, means ASSP data memory address pointer. pointer updated after each data transfer.
Bits Definitions: Bits Name 15:12 AMEAS Description Reserved. Always write ASSP Memory Address Status (readonly). ASSP memory address reached. ASSP memory address reached. Host Memory Address Status (readonly). Host memory address reached. Host memory address reached. ASSP Hardware Interrupt Enable. ASSP hardware interrupt enabled. ASSP Host Memory Read/Write Enable. transfer progress. transfer complete. Hold transfer bits written.
HMEAS
DSPINT
CTRL
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Table Absolute Maximum Ratings
Ratings Analog supply voltage Digital supply voltage Input voltage Operating temperature range Storage temperature range Symbol TSTG Value -0.3 -0.3 +0.5 Units
WARNING: Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. There stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
ES1988 Recommended operating conditions
Table Power Management Characteristics
State D3hot D3cold Description Fully operational Chip state with internal Codec powered down Chip state with internal Codec DAC, ADC, mixer powered down Chip state with internal Codec powered down. PCICLK 49.152 crystal powered Chip state with internal Codec powered down. PCICLK 49.152 crystal powered down. Analog digital Unit
Table Operating Condition
Parameter 3.3V TAMB Definition Digital supply voltage Analog supply voltage Ambient temperature 3.15 4.75 3.45 5.25 Unit
Table Digital Characteristics
Parameter COUT Definition Operating Conditions (VDDD High-level input voltage (TTL-static) High-level output voltage (TTL-static) Low-level input voltage (TTL-static) Low-level output voltage (TTL-static) Low-level input current (VIN VSS) High-level input current (VIN VDD) Tristate output leakage current (VOUT VDD/VSS) Input capacitance Output capacitance Output current drive (SDATA_IN, BIT_CLK) Unit
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ES1988 ALLEGRO DATA SHEET ELECTRICAL CHARACTERISTICS
Table ES1988 Analog Characteristics
Parameter Full Scale Input Voltage: Line Inputs Inputs Full Scale Output Voltage: Line Output Analog S/N: LINE_OUT Other LINE_OUT Analog Frequency Response Digital Total Harmonic Distortion: Line Output DAC/ADC Frequency Response: Stop Band: Transition Band: Stop Band Rejection Out-of-Band Rejection Group Delay (DAC Only Only 0.21 Power Supply Rejection Ratio kHz) Crosstalk Between Input Channels Attenuation, Gain Step Size Analog Input Impedance Input Impedance Input Capacitance
CONDITIONS: 25°C, AVdd DVdd Input Voltage Levels: Logic Logic High input sine wave; Sample Frequency kHz; Vrms, load, Testbench Characterization kHz, attenuation; tone disabled) NOTE: With boost (1.0 Vrms with boost off). limits ratio output level with full scale input output level with zeros into digital input. Measured wtd" over bandwidth (AES17-1991 Idle Channel Noise EIAJ CP-307 Signal-to-Noise ratio). gain, sample frequency. ±0.25 limits max, ±0.1 typical. Stop Band Rejection determines filter requirements kHz. Out-of-Band Rejection determines audible noise. integrated Out-of-Band noise generated process during normal audio playback over 28.8 bandwidth, with respect Vrms output
Min.
Typ.
Max.
Units
Vrms
0.01
0.02
0.85
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET ES1988 TIMING DIAGRAMS
ES1988 TIMING DIAGRAMS
tRST_LOW RESET#
tRST2CLK
Symbol tRST_LOW
Parameter RESET# active-low pulse width ES2828 Modem RESET# inactive BIT_CLK start-up delay ES2828 Modem
Units
tRST2CLK
162.8
Figure Cold Reset
tFS_HIGH
tFS2SC
Symbol tFS_HIGH tFS2SC
Parameter SYNC active-high pulse width SYNC inactive BIT_CLK start-up delay
162.8
Units
Figure Warm Reset
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ES1988 ALLEGRO DATA SHEET ES1988 TIMING DIAGRAMS
tCLK_LOW BIT_CLK tCLK_HIGH tCLK_PERIOD
tSYNC_LOW SYNC tSYNC_HIGH tSYNC_PERIOD
Symbol tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSYNC_HIGH tSYNC_LOW
Parameter BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BIT_CLK high pulse width* BIT_CLK pulse width* SYNC frequency SYNC period SYNC high pulse width SYNC pulse width
12.288 81.4 40.7 40.7 48.0 20.8 19.5
Units
Worst case duty cycle restricted 45/55 Figure Clocks
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET ES1988 TIMING DIAGRAMS
BIT_CLK SDATA_OUT SDATA_IN SYNC
tSETUP
tHOLD
Symbol
Parameter
tSETUP tHOLD
AC-Link Output Valid Delay Timing Parameters Output Valid Delay from rising edge BIT_CLK Note Timing SDATA SYNC outputs with respect BIT_CLK device driving output. Note external load. AC-Link Input Setup Hold Timing Parameters Input Setup falling edge BIT_CLK Input Hold falling edge BIT_CLK AC-Link Combined Rise Fall Plus Flight Timing Parameters BIT_CLK combined rise fall plus flight time (Primary Codec Controller Secondary) SDATA combined rise fall plus flight time (Output Input) Note: Combined rise fall plus flight times provided worst case scenario modeling purposes.
Units
Figure Data Output Input Timing Diagram
tISC_HI tIS_LO I2SCLK tILH
RIGHT
tILS
RIGHT LEFT
LEFT
tISC I2SDATA
tIDH tIDS
Symbol tISC tIS_HI tIS_LO tIDS tIDH tILS tILH
Parameter I2SCLK cycle time I2SCLK HIGH time I2SCLK time I2DATA setup time I2DATA hold time I2SLR setup time I2SLR hold time
Units
Figure Port Timing
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ES1988 ALLEGRO DATA SHEET ES1988 TIMING DIAGRAMS
tSC_RIS tSC_FA
tFS_RIS tFS_FALL
tSI_RISE
tSI_FALL
tSO_FALL
Symbol tSC_RISE tSC_FALL tFS_RISE tFS_FALL tSI_RISE tSI_FALL tSO_RISE tSO_FALL
Parameter rise time fall time rise time fall time rise time fall time rise time fall time
Units
Figure Signal Rise Fall Times
SYNC
Slot
Slot
BIT_CLK
SDATA_OUT
Write 0x20
Data
SDATA_IN
Note: BIT_CLK scale.
Symbol tS2_PDOWN
Parameter Slot BIT_CLK, SDATA_IN
Units
Figure AC-Link Power Mode Timing
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET MECHANICAL DIMENSIONS
MECHANICAL DIMENSIONS
ES1988
100-Pin TQFP
Symbol
Description Lead lead, X-axis Package's outside, X-axis Lead lead, Y-axis Package's outside, Y-axis Board standoff Package thickness Lead width Lead pitch Lead Foot length Lead length Foot angle Coplanarity Leads X-axis Leads Y-axis Total leads Package type
15.75 13.90 15.75 13.90 0.05 1.35 0.17 0.24 0.45 0.93
Millimeters 16.00 14.00 16.00 14.00 0.10 1.40 0.22 0.50 0.60 1.00 TQFP
16.25 14.10 16.25 14.10 0.15 1.45 0.27 0.75 1.07 0.102
Figure Mechanical Dimensions
SAM0268-031800
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ES1988 ALLEGRO DATA SHEET APPENDIX SCHEMATIC EXAMPLES
APPENDIX SCHEMATIC EXAMPLES
Figure ES1988 Device Interface
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET APPENDIX SCHEMATIC EXAMPLES
Figure Audio Interface
SAM0268-031800
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ES1988 ALLEGRO DATA SHEET APPENDIX SCHEMATIC EXAMPLES
Figure Game Port S/PDIF Interfaces
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SAM0268-031800
ES1988 ALLEGRO DATA SHEET APPENDIX SCHEMATIC EXAMPLES
Figure Interface
SAM0268-031800
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ES1988 ALLEGRO DATA SHEET APPENDIX BILL MATERIALS
APPENDIX BILL MATERIALS
Item
Reference Designator R15, R16, R30, R31, R32, R33, R41, R44, R60, R117 R22, R29, R38, R48, R49, R50, R104, R105, R110 R17, R19, R20, R12, R34, R35, R36, R23, R24, R39, R27, R102 C11, C12, C13, C18, C19, C46, C63, C91, C93, C14, C16, C17, C26, C27, C45, C59, C61, C62, C92, C94, C95, C97, C10, C15, C57, C20, C21, C52, C53, C54, C55, C22, C23, C24, C25, C28, C29, C30, C31, C32, C35, C36, C39, C41, C38, C37, C40, C48, C49, C50,
Component Description ES1988, TQFP MC78M05(DPACK) LMV358M,SO8, Power Dual LM4880M, Stereo Audio Power Amplifier DS75176B, Transceivers LM1117-3.3 93LC46, Serial EEPROM Res, SMD, 0805
Res, 10K, SMD, 0805 Res, SMD, 0805 Res, 6.8K, SMD, 0805 Res, 33K, SMD, 0805 Res, 22K, SMD, 0805 Res, 2.2K, SMD, 0805 Res, 51K, SMD, 0805 Res, 27K, SMD, 0805 Res, 20K, SMD, 0805 Res, SMD, 0805 Res, SMD, 0805 Res, 3.3K, SMD, 0805 Res, 5%,100K,SMD,0805 Res, 5%,220K,SMD,0805 Cap, Cera, SMD, 50V, 10pF, 0805
Cap, Radial 20%,25V, 10uF, Size .100"
Cap, Cera, SMD, 10%, 50V, 0.1uF, 0805 Cap, Cera, SMD, 10%, 50V, 1000pF, 0805 Cap, Cera, SMD, 10%, 50V, 0.01uF, 0805 Cap, Cera, SMD, 10%, 50V, 1uF, 0805 Cap, Cera, SMD, 50V, 180pF, 0805 Cap, Cera, SMD, 50V, 0.33uF, 0805 Cap, Cera, SMD, 50V, 330pF, 0805 Cap, Cera, SMD, 50V, 5pF, 0805 Cap, Radial 20%,25V, 100uF, Size .100" Cap, Radial 20%,25V, 3.3uF, Size .100" Cap, Cera, SMD, 10%, 50V, 47pF, 0805 Cap, Cera, SMD, 50V, 33pF, 0805 Cap, Cera, SMD, 50V, 1500pF, 0805
Technology, Inc.
SAM0268-031800
ES1988 ALLEGRO DATA SHEET APPENDIX BILL MATERIALS
Item
Reference Designator L10, L11,
Component Description Inductor, 1.0uH, 1206 HighCurrentBead, (HH-1H3216-500), 1206 Ferrite Bead, (CB30 0805), 0805 2N7002LT1 Fuse, 1.25A, Thru-hole Xtal, 49.152MHz, Overtone, 50ppm, HC-49/U SCHOTT-67129600, Transformer, Thru-hole 3-179397-0 DB15 female connector (right angle) Stereo jack connector, pin, SJ372N JACK Wafer Socket, HEADER HEADER HEADER HEADER HEADER 10X2 Bracket
ORDERING INFORMATION
Part Number ES1988S Package 100-pin TQFP
part this publication reproduced, stored retrieval system, transmitted, translated form means, electronic, mechanical, manual, optical, otherwise, without prior written permission Technology, Inc. Technology, Inc. makes representations warranties regarding content this document. specifications subject change without prior notice. Technology, Inc. assumes responsibility errors contained herein.
U.S. Patent 4,214,125 others, other patents pending. AudioDrive® registered trademark Technology, Inc. other trademarks owned their respective holders used identification purposes only.
2000 Technology, Inc.
SAM0268-031800
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