ES1878 AudioDrive® mixed-signal single-chip solution that adds 16-bit
|
|
|
Top Searches for this datasheet
ES1878 AudioDrive® Data Sheet
ES1878 AudioDrive® mixed-signal single-chip solution that adds 16-bit stereo sound music synthesis notebook computers. ES1878 includes embedded microprocessor, 20-voice ESFMmusic synthesizer, 16-bit stereo DACs, optional Plug Play (PnP) support, hardware master volume control, control logic with FIFO, interface logic, general-purpose I/O, digital dual game port. ES1878 also incorporates three serial ports which allow interfacing with external DSP, wavetable, MIDI (MPU401 UART Mode compatible). addition, ES1878 offers Zoom Video interface support optional ES978 Expansion Audio Mixer docking stations. 4-wire expansion analog 2-wire serial control connect ES1878 with ES978, allowing ES1878 engage docking station's audio resources when docked. ES1878 AudioDrive® record, compress, play back voice, sound, music with built-in mixer controls. Using high-performance channels, ES1878 supports full-duplex operation simultaneous record playback. ESFMsynthesizer extended capabilities within native mode operation providing superior sound power down capabilities. ES1878 register compatible with Yamaha's OPL3FM synthesizer. ES1878 AudioDrive® supports Plug Play with configuration logical devices: configuration device, audio plus ESFMTM, game port, MPU-401. ES1878 also supports optional non-PnP (BIOS Plug Play) configuration Intel® Mobile Triton chipset which PCA-ISA bridge features Subtractive Decode Positive Decode Modes. MPU-401 serial port interfacing with external MIDI device. digital dual game port supports joysticks with hardware timing which uses less overhead improves system performance. serial interface ES1878 allows external take over resources. wavetable serial port allows ES1878 interface with either ES689 ES690 wavetables. address, DMA, interrupt selection controlled through system software Plug Play. Advanced Power Management (APM) features include suspend resume from disk. ES1878 available industry-standard 100-pin Small Quad Flat Pack (SQFP) package.
FEATURE HIGHLIGHTS
Single, mixed-signal, 16-bit stereo VLSI chip digital audio High-quality, 20-voice ESFMmusic synthesizer; patents pending Supports ES978 Expansion Audio Mixer chip Full Plug Play (PnP) capability
Record Playback Features
Record, compress, play back voice, sound, music 16-bit stereo CODEC additional DACs digital audio, music synthesis, Zoom Video Programmable sample rates from 44.1 record playback Patented ESPCM® compression Full-duplex operation simultaneous record playback 6-bit step) software volume control 2-button 3-button hardware master volume control down, mute
Inputs/Outputs
Stereo inputs LINE, AUXA AUXB, mono input MIDI serial port compatible with MPU-401 UART Mode Serial port interface external DSP, which optionally controls full-duplex operation Supports general-purpose inputs (GPIs) general-purpose outputs (GPOs) that slaved with corresponding pins Expansion Audio Mixer high-performance digital dual game port with hardware timing High-performance supports demand transfer F-type Software address mapping, DMA, selections motherboard implementation
Zoom Video port interface MPEG audio with sample rates Wavetable serial port interface ES689/ES690 access music speaker input/output with volume control serial interface
Plug Play (PnP) Features
On-chip support audio, joystick port, MPU-401 Software address mapping, four selections motherboard implementation
Power Interfaces Expansion Audio Mixer (ES978)
Simple hot-docking interface ES978 Expansion Audio Mixer Two-wire digital status data communication between ES1878 ES978 supports register shadowing with worst case latency approximately microseconds pairs on-chip analog differential signals audio with ES978 Expansion Audio Mixer
Advanced Power Management supports suspend/ resume from disk Supports operation
Compatibility
Supports games Sound Blasterand Sound BlasterPro modes Microsoft® WindowsSound System®
Mixer Features
Operating Systems
6-channel stereo mixer inputs line, auxiliary audio), auxiliary digital audio (wave files), music synthesizer, Zoom Video port, plus mono channel mixer input microphone Programmable 6-bit logarithmic master volume control
Microsoft Windows®95 Microsoft Windows3.1 Microsoft Windows WorkgroupsMicrosoft Windows NT3.51 IBM® OS/2® Warp
COPYRIGHTS TRADEMARKS Copyright Notice
Copyright 1995-1996 Technology, Inc. rights reserved. part this publication reproduced, stored retrieval system, transmitted, translated form means, electronic, mechanical, manual, optical, otherwise, without prior written permission Technology, Inc.
Trademarks
AudioDrive® ESPCM® registered trademarks Technology, Inc. ESFMis trademark Technology, Inc. other brand names product names mentioned this document trademarks registered trademarks their respective owners used identification purposes only.
Disclaimer
Information supplied Technology believed accurate reliable. However, Technology assumes responsibility this information, errors contained herein. Products this document covered U.S. Patent 4,214,125 others; other patents pending.
Revision History
This ES1878 AudioDrive® Data Sheet replaces ES1878 AudioDrive® Preliminary Design Guide/Data Sheet.
ES1878
CONTENTS
GENERAL DESCRIPTION FEATURE HIGHLIGHTS COPYRIGHTS TRADEMARKS CONTENTS FIGURES TABLES FUNCTIONAL BLOCK DIAGRAM MIXER SCHEMATIC BLOCK DIAGRAM Subsystems Description PINOUT DIAGRAM DESCRIPTIONS TYPICAL APPLICATION ANALOG HARDWARE INTERFACE Reference Generator Switch-Capacitor Filter Audio Inputs Outputs DIGITAL HARDWARE INTERFACE Interface Interface Latch Feature Interrupts
Interrupt Sources Interrupt Status Register (ISR) Interrupt Mask Register (IMR) Interrupt Edge Generator Sharing Interrupts Accessing Non-PnP Mode (PNPEN=0)
Access Registers
"Bypass Key"
Configuration Registers
Example Register Card-Control Card-Level Registers (00h 07h) Vendor-Defined Card-Level Registers (20h 2Fh) Logical Devices
Device Configuration
Configuring IRQ, DMA, GPI/O Pins
PORTS Port Descriptions
Audio Device Device MPU-401 Device Joystick Device
PROGRAMMING ES1878 Identifying ES1878 Resetting Audio Device Software Modes Operation
Compatibility Mode Programming Extended Mode Programming
Accessing ES1878 Extended Registers
Writing ES1878 Internal Registers Reading ES1878 Internal Registers
Command/Data Handshaking Protocol
Writing Commands ES1878 Reading Read Data Buffer ES1878
PERIPHERAL INTERFACING Serial Interface
Serial Interface Format Select Serial Interface Timing
Programming ES1878 Mixer
Extended Access Volume Extended Access Source Select Programming FIFO Playback Programming FIFO Record Programming FIFO Block Transfer
MPU-401 Interface
MIDI
Wavetable Interface Interface
Interface Serial Data Format
Game/Joystick Interface
Joystick/MIDI External Interface Connector
Full-Duplex Mode Serial Port) Serial Interface Software Enable Volume Control
ES978 Interface
Docking Status Playback Mode Record Mode ES978 Differential AOUT Mode Mono Full-Duplex Mode Power Management Expansion Audio Interface Digital Expansion Audio Interface Analog
AUDIO REGISTERS Types Register Access Mixer Registers
Sound Blaster Compatible Mixer Registers Sound Blaster Master Volume Emulation Mixer Registers Extension Registers
Mono FDXI FDXO General-Purpose
GPI/O Registers
AUDIO PROCESSOR COMMAND SUMMARY POWER MANAGEMENT Power Management Characteristics
Mode Transitions
BIOS Power Management
Suspend-to-Disk Resume-from-Disk Interrupts During Suspend-to-Disk
Master Volume Hardware Volume Controls Speaker
Speaker Volume Control
CONFIGURATION DESCRIPTION Plug Play (PnP) Configuration
Using Mode (PNPEN=1)
TIMING DIAGRAMS ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Thermal Characteristics
Data Sheet
Operating Condition Electrical Characteristics Power Management Characteristics
MECHANICAL DIMENSIONS APPENDIX ES1878 INTERNAL RESOURCE APPENDIX ES689/ES690 DIGITAL SERIAL
INTERFACE APPENDIX INTERFACE REFERENCE APPENDIX SCHEMATIC EXAMPLES APPENDIX LAYOUT GUIDELINES APPENDIX ES1878 BILL MATERIALS
FIGURES
Figure ES1878 Functional Block Diagram Figure ES1878 Mixer Schematic Block Diagram Figure ES1878 Pinout Figure ES1878 Typical Application Figure Reference Generator Diagram Figure Switch-Capacitor Filter Diagram Figure Latch Figure Implementation ES1878 Figure 16-Bit Data, Positive Sync Pulse Figure Dual Joystick/MIDI Connector Figure MIDI Serial Interface Figure Speaker Volume Circuitry Figure Configuration Register Outline Figure Command Transfer Timing Figure Reset Timing Figure Read Cycle Figure Write Cycle Figure Compatibility Mode Write Cycle Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Compatibility Mode Read Cycle Serial Mode Receive Operation Serial Mode Transmit Operation Serial Input Timing Interface Digital Input Format with SCLK Periods ES1878 Physical Dimensions Example Port Implementation Typical Port Audio Implementation Audio Interface Timing Digital Input Format with SCLK periods ES1878 Schematic Interface Amplifier Section Switch Connector Section Analog Components Side Analog Components Both Sides PCB.
TABLES
Table Analog Pins Table Digital Pins Table ES1878 Interface Table Wavetable Interface Pins Table Interface Pins Table Digital Joystick Read Values Table Download Period Table Upload Period Data Configuration Table Docked Modes Analog Audio Table Logical Device Summary Table Configuration Device Table Port Joystick, Audio, MPU-401 Devices Table Command Sequences Playback Table Command Sequence Record Table Table Table Table Table Table Table Table Table Table Table Table Table Table Sound Blaster Compatibility Registers Sound Blaster Master Volume Emulation Mixer Registers Summary Audio Processor Extension Registers Command Summary Power Mode Description ES1878 Timing Characteristics Digital Characteristics Analog Characteristics. Current Consumption Power Modes Common Clock Frequencies Parameters Audio Signals Port Interface Assignments ES1878 Bill Materials (BOM)
ES1878
FUNCTIONAL BLOCK DIAGRAM
VDDD GNDD
VREF
FOUT
GPI[6:0]* GPO[6:0]*
PCSPKI VOL. CTRL.
VDDA OSCILLATOR GNDA FILTER GENERAL PURPOSE 1-BIT
PCSPKO
LINE AUXA AUXB* FDXI/O* XA[3:0]
PREAMP RECORD SELECT VOLUME ES978 ANALOG 16-BIT STEREO CODEC INTERFACE REGISTER FIFO FIFO
A[11:0] D[7:0] IRQ(A-E)* DRQ(A-C)* DACKB(A-C)* IOWB IORB RESET PNPEN
AOUT VOLUP* VOLDN* MUTE*
MIXER
MASTER CTRL
PROCESSOR
SER. PORT DCLK ES978 DIG. DOCKED
ESFM
16-BIT 16-BIT STEREO STEREO
IILR IISCLK
SER. PORT
ES689/ES690 SER. PORT
MPU-401 SER. PORT
DIGITAL DUAL-GAME SER. PORT
IIDATA
IIMCLK
MCLK
SW(A-D)
T(A-D)
Some these pins shared with other functions.
Figure ES1878 Functional Block Diagram
Data Sheet
MIXER SCHEMATIC BLOCK DIAGRAM
ADC/DAC
Output Volume
Channel
port
Preamp
LINE HWWT AUXA AUXB
Record Source Record Monitor
FDXI/AUXB_L (DSP Interface enabled)
Playback Mixer
Master Volume
AOUT
Input Volume
Figure ES1878 Mixer Schematic Block Diagram
ES1878
Subsystems Description
This section discusses major subsystems shown Figure
Recording source input volume control input source volume control record. recording source selected from five choices: Line (CD) Mixer FDXI (mono full-duplex mode, interface enabled) first four cases, selected recording source mixed with audio from ES978 selected source also enabled ES978 chips docked.
RISC processor game-compatible audio functions performed embedded microprocessor. Oscillator circuitry support external crystal. firmware data embedded processor. FIFO 256-byte FIFO data buffer. interface provides interface address, data, control signals. Digital dual game ports high-performance digital switches joysticks with hardware timing. ES978 interface allows support Expansion Audio Mixer docking station using two-wire control signals four-wire analog bus. Zoom Video interface supports sample rates MPEG audio. MPU-401 serial port asynchronous serial port MIDI devices such wavetable synthesizer music keyboard input. Wavetable serial port serial port connection from output ES689 ES690 that eliminates requirements external DAC. serial port interface optional external control CODEC. ESFMmusic synthesizer high-quality 20-voice synthesizer. Stereo programmable mixer seven input stereo mixer. Each input independent left right 4-bit. Line (CD) FDXI) Digitized audio (wave files) FM/ES689/ES690 music serial port 16-Bit Stereo Zoom Video MPEG audio DAC. 16-Bit stereo CODEC audio record playback CODEC. 16-Bit stereo music ESFMor external wavetable synthesizer. 1-Bit speaker digital input.
Output volume mute control master volume controlled either programmed volume control switch inputs. master volume supports bits channel plus mute. When docked, ES1878 first transmits master volume information ES978 mixer before take effect. 3-pushbutton inputs with internal pull-up devices up/down/mute used adjust master volume control. state these pins logically AND'ed with state corresponding pins ES978 when docked. software-selectable option allows mute input omitted. mute input defined state when both down inputs low. default, this feature disabled. hardware volume inputs ES1878 used general-purpose inputs (see bits VendorDefined Card-Level register 25h). They cannot used volume control inputs. Reference generator analog reference voltage generator. speaker volume control speaker supported with 1-bit with volume control. analog output PCSPKO intended externally mixed external amplifier. speaker audio transmitted ES978 through expansion audio interface (XA[3:0]) always heard through portable unit's speakers.
Data Sheet
PINOUT DIAGRAM
GNDD VDDD GNDD
PCSPKI GNDD GPO0 GPO1 GPO2 DRQC DACKB DRQB DACKBB DRQA DACKBA VOLU IRQE GPO6 IRQD GPO5 IRQC GPO4 IRQB GPO3 IRQA IORB IOWB VDDD
VDDD RESET DOCKED IIMCLK IILR IISCLK MCLK DCLK GNDD PNPEN GNDA
ES1878 AudioDrive®
PCSPKO AOUT_R AOUT_L LINE_R LINE_ IN_R IN_L FOUT_L FOUT_R VDDA VREF GNDA AUXA_R AUXA_L AUXB_R/FDXO AUXB_L/FDXI
Figure ES1878 Pinout
ES1878
DESCRIPTIONS
Table Name VDDA GNDA LINE_L LINE_R AUXA_L AUXA_R AUXB_L AUXB_R AOUT_L AOUT_R PCSPKO XA[3:0] Analog Pins Number 51:54 Description
Power Ground (Pwr) Analog power supply, 4.75 5.25 (Pwr) Analog ground. Line input left. pull-up pin. Line input right. pull-up CMR. (CD) input left. pull-up CMR. (CD) input right. pull-up CMR. Multipurpose pin, AUXB_L (Aux input left) FDXI. pull-up CMR. Multipurpose pin, AUXB_R (Aux input left) FDXO. pull-up CMR. input internal preamp. pull-up CMR. Analog output left from master volume. This drive load. Analog output right from master volume. This drive load. speaker analog output. Bidirectional differential transmitter/receivers. Expansion audio bus. These analog signals that DC-coupled corresponding XA[3:0] pins ES978. Multipurpose pin, AUXB_L FDXI. When used FDXI with interface, provides line-level mono input. Multipurpose pin, AUXB_R FDXO. When used FDXO with interface, line-level mono output, capable driving load. Capacitive coupled input left. input resistance about ohms. Capacitive coupled input right. input resistance about ohms. Filter output left. This normally AC-coupled CIN_L. output resistance about ohms. Filter output right. This normally AC-coupled CIN_R. output resistance about ohms. 2.25 buffered common mode reference output. 2.25 reference generator.
Recording Source Input Volume Control
Output Volume Control Record Monitor
ES978 Analog Interface
Interface FDXI FDXO
Miscellaneous Analog Pins CIN_L CIN_R FOUT_L FOUT_R VREF
These pins shared with other functions.
Data Sheet
Table Name VDDD GNDD A[11:0] D[7:0] IOWB IORB IRQA IRQB IRQC IRQD IRQE DACKBA DRQA DACKBB DRQB
Digital Pins Number 13:2 23:16 28:25 32:29
Description
Power Ground (Pwr) Digital power supply (3.0 (Pwr) Digital ground. address bus. address valid when active-low, when high. data bus. drivers. active-low write strobe. active-low read strobe.
Interface
O/Hi interrupt request. driver. Connect IRQ9 PNPEN O/Hi Multipurpose pin, IRQB GPO3. Connect IRQ5 PNPEN O/Hi Multipurpose pin, IRQC GPO4. Connect IRQ7 PNPEN O/Hi Multipurpose pin, IRQD GPO5. Connect IRQ10 PNPEN O/Hi Multipurpose pin, IRQE GPO6. Connect IRQ11 PNPEN I/O/ active-low acknowledge. Connect DACK0 PNPEN active-low acknowledge. Connect DACK1 PNPEN Multipurpose pin, DACKBC GPI3. used DACKBC, active-low acknowledge. Connect DACK3 PNPEN Multipurpose pin. DRQC GPI2. used DRQC, active-high request. Connect DRQ3 PNPEN active-high reset. Input that active-high when ES1878 docked ES978. This internal pull-down GNDD. Expansion serial clock frame sync. High-impedance when DOCKED Expansion serial data I/O. High-impedance when DOCKED MIDI serial output. MIDI serial input. internal pull-up VDDD. Joystick switch inputs. These pins have internal pull-ups VDDD. Joystick timers. digital power supply. These pins have internally weak pull-downs GNDD ohms). Serial shift clock interface. This internal pull-down GNDD. Serial data interface. This internal pull-down GNDD. Left/right signal interface. This internal pull-down GNDD. Reserved future oversampling clock interface (software selectable x256, x384 x512 sample rate). This internal pull-down GNDD. current design using ES1878 does require IIMCLK. O/Hi active-high request. Connect DRQ0 PNPEN O/Hi active-high request. Connect DRQ1 PNPEN
DACKBC DRQC RESET DOCKED SW(A-D) T(A-D) Interface IISCLK IIDATA IILR IIMCLK
ES978 Digital Interface
MPU-401 Serial Port (MIDI) FIFOs
Dual Game Port Joystick
ES1878
Table Name MCLK DCLK MUTE VOLDN VOLUP
Digital Pins (Continued) Number
Description Serial clock input from ES689/ES690. Serial data input from ES689/ES690. This internal pull-down GNDD. Frame sync input. Software programmable active-high active-low. This internal pull-down GNDD. Serial clock input. This internal pull-down GNDD. Serial data receive. This internal pull-down GNDD.
ES689/ES690 Interface
DSP/CODEC Interface
O/Hi Serial data transmit. Multipurpose pin, MUTE GPI4. When used MUTE, active-low mute input. This internal pull-up VDDD. Multipurpose pin, VOLDN GPI6. When used VOLDN, active-low volume-down input. This internal pull-up VDDD. Multipurpose pin, VOLUP GPI5. When used VOLUP, active-low volume-up input. This internal pull-up VDDD. Multipurpose pin, VOLDN GPI6. used GPI6, general-purpose input Multipurpose pin, VOLUP GPI5. used GPI5, general-purpose input Multipurpose pin, MUTE GPI4. used GPI4, general-purpose input Multipurpose pin, DACKBC PGI3. used GPI3, general-purpose input Multipurpose pin, DRQC GPI2. used GPI2, general-purpose input General-purpose inputs 1:0. Multipurpose pin, IRQE GPO6. used GPO6, general-purpose output Multipurpose pin, IRQD GPO5. used GPO5, general-purpose output Multipurpose pin, IRQC GPO4. used GPO4, general-purpose output Multipurpose pin, IRQB GPO3. used GPO3, general-purpose output General-purpose outputs 2:0. 14.31818 clock input, external crystal. Output external 14.31818 crystal. enable. When high, Plug Play enabled; when low, Plug Play disabled. speaker digital input. This internal pull-down.
External Hardware Volume Control
General-Purpose/PnP Interface GPI6 GPI5 GPI4 GPI3 GPI2 [1:0] GPO6 GPO5 GPO4 GPO3 GPO[2:0] PNPEN PCSPKI 80:79 83:81 I/O/
Miscellaneous Digital Pins
These pins shared with other functions.
Data Sheet
TYPICAL APPLICATION
ES1878
Interface Serial Port Buttons Down, Mute AOUT Stereo ES938
Audio Tone Control
Speakers
Control
ES981
Mbyte Wavetable
Hardware Volume Control Joystick Controls
MPU-401
MIDI Serial Port
General MIDI Interpreter
Wavetable Synthesizer
Wavetable Audio Port
Serial Port
Chorus Reverb (ES690 only)
ES689/ES690
(stereo) (stereo) Line (stereo) (mono) GPI/O ES978 Interface
Interface
MPEG Audio (I2S
CARD OPTIONAL
DOCKING UNIT
Port ES689/ES690 Wavetable Serial Port Oversampling Stereo Differential Transceiver Digital Controller
ES978
Speakers
Record Playback Mixers
Analog
(stereo) (stereo) Line (stereo) (mono)
PORTABLE UNIT
MIDI Joysticks GPI/O Volume Control Buttons Down, Mute
Figure ES1878 Typical Application
ES1878
ANALOG HARDWARE INTERFACE Reference Generator
Reference generator pins VREF connected through bypass capacitors analog ground.
Switch-Capacitor Filter
outputs FOUT_L FOUT_R filters must AC-coupled inputs CIN_L CIN_R respectively, which provides blocking opportunity lowpass filtering with capacitors analog ground these inputs.
ES1878
ES1878
FOUT_L CIN_L .001
VREF
FOUT_R
.001
Figure Reference Generator Diagram
CIN_R
Figure Switch-Capacitor Filter Diagram
Audio Inputs Outputs
Analog inputs MIC, stereo LINE, stereo AUXA, stereo AUXB capacitively coupled their respective input signals. have pull-up resistors CMR. ES1878 analog outputs AOUT_L AOUT_R intended AC-coupled amplifier, volume control potentiometer, line-level outputs.
Data Sheet
DIGITAL HARDWARE INTERFACE Interface
Table shows pins used interface ES1878 with bus.
Table A[11:0] D[7:0] IOWB IORB IRQ(A-E) DACKB(A-C) DRQ(A-C) RESET ES1878 Interface Description O/Hi O/Hi address bus. address valid when active low, when high. data drivers. active-low write strobe. active-low read strobe. interrupt request. driver. active-low acknowledge. active-high request. active-high reset.
Latch Feature
latch feature enabled when VendorDefined Card-Level register high (see Figure this feature enabled, each three audio DRQs will latched high until following occurs:
DACK pulse occurs while goes DACK pulse. hardware reset occurs. 8-16 milliseconds elapse while low.
Interface
ES1878 incorporates channels. There sources requests targets acknowledge: Audio first audio channel. This channel used Sound Blaster-compatible DMA, Extended Mode DMA. used either record playback. Ideally, this channel should assigned channel Audio second audio channel. This channel used audio playback full-duplex mode. This channel mapped three 8-bit channels: sources mapped three pairs through registers. Also, three pairs assigned channel numbers VendorDefined Card-Level registers 24h. order output driving opposed high-impedance), things must occur: register given device must match channel number given device must activated (that register must high). detailed information, Description' section. `Configuration
-DACK -RESET
Figure Latch
Interrupts
Interrupt Sources
Interrupt sources mapped five interrupt output pins registers. given have zero, one, more interrupts mapped Each assigned interrupt channel number Vendor-Defined Card-Level registers 20h, 21h, 22h. These registers automatically loaded from 8byte header configuration data. given interrupt more sources assigned more those sources activated (register 30h, then interrupt will active; that will always driving high low. Each interrupt also more mask bits that AND'ed with interrupt request. There four interrupt sources ES1878:
audio audio hardware volume MPU-401
ES1878
Audio
This interrupt used first channel (Sound Blaster-compatible DMA, Extended Mode DMA, Extended Mode programmed I/O), well Sound Blaster-compatible MIDI receive. Extended register controls this interrupt Extended Mode programmed I/O. This interrupt request cleared hardware software reset, read from port Audio_Base+Eh. interrupt request polled reading from port Audio_Base+Ch. This interrupt assigned interrupt channel register
Interrupt Status Register (ISR)
Register configuration device read quickly find current state ES1878 interrupt sources. Audio interrupt request Audio interrupt request AND'ed with Mixer Extension register Hardware volume interrupt request AND'd with Mixer Extension register MPU-401 receive interrupt request AND'ed with Mixer Extension register
Audio
Optional second channel. ES1878 operate full-duplex mode using channels. However, second channel must have same sample rate first channel. this reason, necessary separate interrupt second channel. This interrupt masked Mixer Extension register 7Ah. polled cleared reading writing same register. This interrupt assigned interrupt channel register
Interrupt Mask Register (IMR)
Register configuration device used mask seven interrupt sources. mask bits used force interrupt source zero, they interrupt highimpedance state. Each AND'ed with corresponding interrupt source. This register ones hardware reset. Interrupt Status Register (ISR) affected state Interrupt Mask Register (IMR). That reflects status interrupt request lines before being masked IMR. useful when interrupts shared. example, assume that audio audio hardware volume, MPU-401 share same interrupt WindowsTM. When returning from Windows DOS, hardware volume, MPU-401, Audio interrupts masked setting appropriate bits second within interrupt handler. first thing interrupt handler mask interrupt sources mapped interrupt handler. then polled decide which sources process. Just before exiting interrupt handler, restored. unprocessed interrupt remains active, will generate interrupt request because interrupt during masked period then went high when interrupt sources were unmasked. While interrupts masked, individual interrupt sources change state number times without generating false interrupt request.
Hardware Volume
Hardware volume activity interrupt. This interrupt occurs when three hardware volume controls generates change status event). Mixer Extension register mask this interrupt. interrupt request polled reading same register. interrupt request cleared writing value register 66h. This interrupt assigned interrupt channel register 28h. Typically this interrupt, used, shared with audio interrupt.
MPU-401
This interrupt generated when MIDI byte received. goes when byte read from MIDI FIFO goes high again quickly there additional bytes FIFO. interrupt status same Read-DataAvailable status flag MPU-401 Status register. This interrupt masked Mixer Extension register assigned interrupt channel ways: MPU-401 part audio device, then register used assign MPU-401 interrupt. MPU-401 logical device, also assigned interrupt register Both these methods access same physical register.
Interrupt Edge Generator
interrupt logic feature that makes sharing interrupts easier. more than interrupt source shares interrupt request pin, interrupt normally logical shared interrupt requests. However, interrupt request goes from high low, circuitry inside ES1878 will hold interrupt request briefly generate clock edge other interrupt sources also high.
Data Sheet
Sharing Interrupts
Plug Play does support sharing interrupts resource assignment decision making. device wants share interrupt with another device that been assigned interrupt PnP, first device cannot request interrupt itself. logical device that supports interrupts assigned interrupt after sequence generated Windows driver. this case, logical device would typically forced share interrupt with first audio interrupt. most cases, this done simply programming appropriate register (70h 72h) selected device. special case hardware volume interrupt. This interrupt source assigned interrupt through Vendor-Defined Card-Level register 28h, bits 7:4. second special case MPU-401 interrupt. MPU401 device either part audio device logical device. part audio device, interrupt assigned writing Vendor-Defined Card-Level register 28h, bits 3:0. MPU-401 device logical device, assigned interrupt either VendorDefined Card-Level register LDN#3 register 70h.
ES1878
PERIPHERAL INTERFACING Serial Interface
Three input pins, IIDATA, IISCLK, IILR, used serial interface between external device stereo within ES1878. fourth input, IIMCLK, reserved future devices that incorporate oversampling should left floating connected ground. IIDATA, IISCLK, IILR left floating connected ground serial interface used. Typical applications serial interface MPEG audio, digital audio.
IISCLK
clock/shift clock. maximum rate MHz. minimum number IISCLK periods IILR period number greater than equal acceptable. Sample synchronization signal. maximum sample rate kHz. Serial data. Optional oversampling clock (for future use).
IILR IIDATA IIMCLK
Within ES1878, IILR IIDATA sampled rising edge IISCLK. Figure Figure detailed timing.
IIDATA
MPU-401 Interface
MPU-401 port used interfacing with either MIDI with ES938 stereo sound effects signals. Refer ES938 Data Sheet technical details.
CARD
IISCLK IILR
ES1878 MIDI
Figure Implementation ES1878
ES1878 MPU-401 MIDI interface with 23-byte receive FIFO 8-byte transmit FIFO. output transmit FIFO serialized also sent ES978 expansion unit, where serialized that chip. MIDI data received from either ES1878 from ES978 expansion unit. unlikely event that MIDI data received from both sources simultaneously, data might corrupted. Data received ES978 transmitted back ES1878 next upload frame then placed MPU-401 receive FIFO.
Serial Interface Format Select
This serial interface supports different formats: ES689/ ES690 two-wire serial interface, I2S. When used ES689/ES690 format, IIDATA serial data IISCLK clock. IILR input used left floating connected ground. Vendor-Defined CardLevel register bits select format (this register accessed through configuration device). Vendor-Defined Card-Level register `Configuration Description' section more detailed information.
Wavetable Interface
ES1878 contains synchronous serial interface connection wavetable music synthesizer.
Table Pins MCLK Wavetable Interface Pins Descriptions Serial clock from external ES689/ES690 music synthesizer (2.75 MHz). Input with pull-down. Serial data from external ES689/ES690 music synthesizer. When both MCLK active, stereo DACs normally used synthesizer acquired external ES689/ES690. normal output blocked. Input with pull-down.
Serial Interface Timing
This section discusses serial interface signals. signals when port configured with ES689/ ES690 wavetable synthesizer defined Wavetable Interface section. Three signals (plus optional) used I2S:
Data Sheet
Interface
ES1878 contains synchronous serial interface connection serial interface. typical application this interface speakerphone.
Table Pins DCLK Interface Pins Descriptions Data clock. rate vary, typical value 2.048 256). Input with pull-down. Data transmit. Active output when data being transmitted serially from ES1878; otherwise high-impedance. Tri-state output. Serial data input with pull-down. Frame sync input. Software programmable active-high active-low. Input with pull-down.
Interface Serial Data Format
DCLK
Hi-Z
(MSB)
(MSB)
Figure 16-Bit Data, Positive Sync Pulse
ES1878
Game/Joystick Interface
ES1878 includes pins dual joystick port. digital game port address decoded timer pins switch pins SWA, SWB, SWC, SWD. MIDI serial input output also come from game port connector most applications. Four these eight pins, SW(A-D), inputs switches joysticks. remaining pins, T(A-D), "one-shot" timers that generate pulses varying widths, where width corresponds current resistance joystick potentiometers.
Joystick/MIDI External Interface Connector
joystick portion ES1878 reference design identical that standard game control adaptor game port. PC-compatible joystick connected 15-pin D-sub connector. supports standard joystick compatible software. need support joysticks, joystick conversion cable required. This cable uses 15-pin D-sub male connector 15-pin D-sub female connectors other end. signals this cable have direct pin-to-pin connection, except pins male connector, pins should left without connection. female connector, internally connected internally connected dual joystick port MIDI port take only slot your leaving room other cards. dual joystick/MIDI connector configuration shown Figure MIDI Serial Interface Adaptor from Joystick/MIDI Connector shown Figure
Joysticks
Normally, host processor responsible measuring width pulse. ES1878 also this automatically. host processor read measured widths directly rather than having timing itself. This referred "digital joystick." VendorDefined Card-Level register determines whether joystick port digital analog joystick.
Digital Joysticks
digital joysticks, host processor first writes value joystick port, then reads back seven separate values (shown Table
Joystick Joystick
Table Read Read Read Read Read Read Read
Digital Joystick Read Values
X-axis
X-axis
byte timer byte timer byte timer byte timer Bits Upper nibble timer Bits Upper nibble timer Bits Upper nibble timer Bits Upper nibble timer switch switch switch switch
Y-axis
Button Button
Button
Button
Y-axis
MIDI MIDI
Figure Dual Joystick/MIDI Connector
timer values reported range from FFFh (0-4095). timer clock kHz. When docked, software programmable (bit Vendor-Defined Card-Level register 29h) causes joystick connected ES978 replace connected ES1878 automatically.
Data Sheet
JOYSTICK PORT
2.2K 5.6K
2N3904
2N3904
220pF
220pF
MIDI
DB15P
ISO1
MIDI
Figure MIDI Serial Interface
ES978 Interface
When docked, ES1878 constant communication with ES978 expansion unit. half-duplex, bidirectional serial link keeps each chip updated status other. example, Mixer registers located ES1878 transmitted down ES978. MIDI data received ES978 transmitted ES1878. addition digital control link, four analog wires connect chips directly. These four wires configured pair differential audio channels.The ES1878 uses these audio channels three ways: stereo playback (ES1878 transmits ES978), stereo record (the ES978 transmits ES1878), mono full-duplex (one mono channel each direction). when docked. Except when recording, expansion audio sources mixed expansion unit within ES978, played through speakers expansion unit. most cases, speakers within portable unit programmed automatically muted when docked. exception speaker beeps, which always heard portable, even when docked. Each audio input programmed individually respond docking situation, three ways:
analog input, such mic, which remains portable (ES1878) when docked muted ES978. analog input, such line-in, which disabled ES1878 when docked enabled ES978 when docked, i.e. muted mixers ES1878 ES978. analog input which enabled both ES1878 ES978 mixers, shares common volume control. (Note: exception sharing common volume control allowed Mappable Volume register 6Ah; below).
Docking Status
ES1878 either docked undocked state. state determined DOCKED input, which active high when docked. undocked state, pins driven low. XA[3:0] pins mode (differential outputs), except they follow AOUT outputs directly (i.e., after master volume).
Playback Mode
ES1878/ES978 design assumes that active speakers move from portable expansion unit
playback master volume controlled through software programming up/down/mute switch inputs. latter method, called hardware volume control, activelow switch inputs both ES1878 ES978.
ES1878
Record Mode
record mode, expansion audio turned around, sound data sent from expansion unit ES978 chip ES1878 portable unit. sound data from expansion unit mixed inside ES1878 with local sources before recording. Because portable unit sources (for example, mixed into recording, possible record monitor function through expansion unit speakers (they automatically muted record mode). possible record monitor speakers portable unit (see Vendor-Defined Card-Level register 2Bh). default situation most applications have speakers muted during recording. previous chips, four record sources selected: Mic, Line, Mixer. When docked, ES1878 chip knows whether each resource present portable, docking station, both, acts accordingly.
Power Management
Power management controlled Vendor-Defined CardLevel register 2Dh. previous AudioDrive® chips, power management controlled port Audio_Base+7h. Only reset) (suspend request) port Audio_Base+7h supported ES1878.
Expansion Audio Interface Digital
wires used transmit serial data between ES1878 ES978. first signal XSC, acts frame sync shift clock. clock rate 3.58 MHz. typical frame consists
Sync period clocks wide Download period clocks wide Turn-around period clocks wide Upload Period clocks wide
ES978 Differential AOUT Mode
some applications, there ES978 expansion unit. this case, XA[3:0] used differential outputs that follow AOUT intended connect differential-input power amplifier expansion unit. This mode operation selected automatically whenever DOCKED input zero. When DOCKED zero, high-impedance.
Total: clocks/frame, which equivalent frame rate. function upload download periods continually update corresponding registers within each device. example, pressing VOLUP button expansion unit transmits state ES1878 where AND'ed with same ES1878. ES1878 updates copy master volume register. ES978 will receive value master volume register during next download period next frame.
Mono Full-Duplex Mode
ES1878, host-based software applications full-duplex mode through 8-bit channels. restrictions that both record playback monophonic, that record playback synchronous (i.e., same sample rate). record channel record from analog input either ES1878 remote ES978 chips, same, from FDXI input ES1878 when using serial port.
Sync Period
sync period, 12-bit clock periods, then high 12-bit clock periods.
Download Period
download period, data transmitted serially from ES1878 ES978 signal XSD. shift clock. Data shifted ES1878 falling edge XSC. Data shifted into ES978 rising edge XSC. download period bits wide. Each takes oscillator clocks (bit rate 3.58 MHz). last bits checksum byte. upload period bits wide. last bits checksum byte. Table contains data configuration download period.
Data Sheet
Table Byte
Download Period Bits 15:8 23:15 31:24 39:32 47:40 55:48 63:56 71:64 79:72 87:80 95:88 103:96 111:104 119:112 126:120 134:128 143:136 Function Mode expansion analog interface Record source select Master output enable MIDI loopback test MIDI transmit signal (byte contains MIDI data) MIDI data byte high) XGPO[7:0] data Playback mixer Host audio volume Playback mixer Line volume Playback mixer volume Playback mixer (CD) volume Playback mixer volume Playback mixer S/ES689 volume
Table Byte
Upload Period Data Configuration Bits 15:8 Function Joystick switch status VOLUP input status VOLDN input status MUTE input status MIDI receive data following MIDI receive data byte set.
23:16 XGPI input state 31:24 byte joystick timer 39:32 byte joystick timer 47:40 byte joystick timer 55:48 byte joystick timer 59:56 High nibble joystick timer 63:60 High nibble joystick timer 67:64 High nibble joystick timer 71:68 High nibble joystick timer 79:72 checksum
Reserved Record mixer Line volume Record mixer volume Record mixer (CD) volume Record mixer volume Record mixer S/ES689 volume
Expansion Audio Interface Analog
This interface uses wires: analog ground wires four analog signal wires (XA[3:0]). four signal wires used five different modes. each these modes, master always refers ES1878 slave always refers ES978.
Master volume left Mute left Master volume right Mute right checksum
Turn Around Period
There bits between download period start upload period.
Mode Stereo playback. differential pairs left right channels, transmitted from master slave. Mode Stereo record. differential pairs left right channels, transmitted from slave master. Mode Monophonic full-duplex. differential pairs. pair monophonic playback from master slave, second pair monophonic recording from slave master. mono playback signal input both left right host audio inputs playback mixer. mono record signal derived averaging left right outputs record mixer. Mode Stereo full-duplex. four signals used differentially (note that this mode supported ES1878). Mode docked (DOCKED=0). Like Mode except analog outputs follow AOUT_L AOUT_R rather than output mixer.
Upload Period
upload period, data transmitted serially opposite direction, from ES978 ES1878 same signal wire, XSD. Table contains data configuration upload period.
After change mode, data muted receiving period milliseconds. responsibility master have contention caused both ends transmitting same signal wire.
ES1878
Table shows mode configurations when notebook unit docked.
Table Docked Modes Analog Audio
+Left Play -Left Record +Play Left Play
worst-case latency between ES978 ES1878, serial interconnection, about µsec.
Mode
-Left Play +Left Record -Play Left Record
-Right Play
+Right Play
GPI/O Registers
GPI/O registers follows:
+Right Record -Right Record +Record Right Record -Record Right Play
Configuration_Device_Base+2h Bits this register state GPO[6:0] pins that enabled outputs mapped pins ES978.
supported ES1878
Configuration_Device_Base+3h Bits this register state XGPO[7:0] pins ES978 that mapped pins ES1878.
Mono FDXI FDXO
FDXI shared with AUXB_L FDXO shared with AUXB_R. ES1878 supports FDXI FDXO input output from when using serial port. ES1878 also supports function, which FDXI general mono input mixer, controlled AUXB volume register, FDXO mono output input volume stage (i.e., recording source select input volume control). Mono FDXI/O mode useful with external modem that integrated CODEC speakerphone applications. Mixer Extension register enables FDXI mono input FDXO mono output. When FDXI mono input mixer, input impedance half ohms. When FDXO output, output impedance. When FDXO output AUXB_R input mixer pull-up CMR. Contact Field Application Engineer application note FDXI/FDXO feature.
Vendor-Defined Card-Level register This register controls whether shared function pins general-purpose inputs/outputs.
Vendor-Defined Card-Level register Vendor-Defined Card-Level register 26h, which register, selects whether controlled Configuration_Device_Base+2h ES978. Vendor-Defined Card-Level register Vendor-Defined Card-Level register 27h, which register, selects whether controls XGPO ES978, XGPO controlled Configuration_Device_Base+3h.
Note: Bits register Audio_Base+7h control GPO0 GPO1 previous AudioDrive® chips. Also, feature previous audio controllers that causes GPO0 GPO1 change state automatically when chip powered down longer supported ES1878.
General-Purpose
seven general-purpose inputs seven generalpurpose outputs available. Four pins have other functions (ISA interrupt request outputs) available general-purpose outputs. Five pins have other functions (volume control, DRQC, DACKBC) available generalpurpose inputs. more information, refer `GPI/O Registers' section. Each enabled input read host processor time. Also, each input programmed remotely control corresponding output ES978, thereby saving interconnects between portable expansion unit. Each enabled controlled either writeby host ES1878 register remotely from corresponding ES978.
Master Volume
master volume controlled through programmed volume control switch inputs. master volume supports 6-bits channel plus mute. When docked, ES1878 transmits master volume information ES978 where takes effect after output ES978 mixer.
Data Sheet
Hardware Volume Controls
VOLUP, VOLDN, MUTE three input pins with internal pull-up devices. state these pins AND'ed with state corresponding pins ES978 when docked. software selectable option enables mute input omitted. mute input defined state when both down inputs low. default, this feature disabled. hardware volume inputs ES1878 used general-purpose inputs (see bits VendorDefined Card-Level register 25h). this case they cannot used volume control inputs.
PCSPKI VDDA PCSPKO
GNDA Figure Speaker Volume Circuitry
Speaker
speaker supported 1-bit with volume control. analog output PCSPKO intended externally mixed external amplifier, which means that speaker audio transmitted ES978 through expansion audio interface (XA[3:0]) always heard through portable speakers.
With external circuit shown Figure amplitude square wave output PCSPKO should approximately VDDA/2 maximum volume, i.e., internal resistor approximately ohms 30%). other levels relative this amplitude follows: off, -18dB, -15dB, -12dB, -9dB, -6dB, -3dB, +0dB purpose circuit, beyond volume control speaker, prevent digital noise from speaker signal being mixed into analog signal. This circuit provides clean analog signal. output either mixed with AOUT_L AOUT_R pins externally used drive simple transistor amplifier drive speaker dedicated producing beeps.
Speaker Volume Control
When PCSPKI signal high, resistive path analog ground enabled. value resistor selected from among choices control amplitude output signal.
ES1878
CONFIGURATION DESCRIPTION Plug Play (PnP) Configuration
ES1878 supports industry-standard Plug Play (PnP) specification, well software configuration method that does rely PnP. input ES1878 called PNPEN determines configuration method.
PNPEN (ground) (Vcc) Mode Non-PnP Mode Mode
When PNPEN=0, bypass required enable configuration device ES1878. Once configuration device enabled, registers ES1878 accessible programmed.
Access Registers
"Bypass Key"
registers directly accessed, bypassing sequence, writing special sequence port 279h concluding with writes 279h base address configuration ports. sequence also sets activate configuration device. supported system, possible bypass issuing special "bypass key" time ES1878 force configuration device enabled specific address. special bytes long, written Address register (279h PNPEN=1, 388h PNPEN=0). bypass must followed immediately writes Address register high bytes Address register configuration device. configuration device also activated bypass key. address configuration device must range 100h-FF8h aligned multiple might "alias" audio device address that intend use: example, E20h configuration device audio 220h. Note: entire sequence should performed with interrupts disabled order minimize chance that interrupt will cause sequence corrupted. With interrupts disabled, following bytes written address 388h (address 279h PNPEN=1).
<config_address_low>, <config_address_high>
Using Mode (PNPEN=1)
There several design implications using PnP: PCI-ISA bridge ES1878 must subtractive decode mode. This mode required because place addresses ES1878 devices very large number locations. devices within system must share same bridge. internal resource cannot changed. addresses, interrupts, channels must supported defined resource ROM. joystick port must supported. five lines must connected interrupt request channels follows: IRQA -IRQ9 IRQB -IRQ5 IRQC -IRQ7 IRQD -IRQ10 IRQE -IRQ11 three DRQ/DACK pairs must connected signals follows: DRQA DRQ0 DACKBA -DACK0 DRQB DRQ1 DACKBB -DACK1 DRQC DRQ3 DACKBC -DACK3
Accessing Non-PnP Mode (PNPEN=0)
Because above restrictions imposed PnP, separate configuration method implemented ES1878. special sequence bytes written consecutively address 388h. This sequence called "bypass key" because used when PNPEN=1 short-circuit process directly enable configuration device ES1878 (note that when PNPEN=1, sequence written address 279h rather than 388h).
After writing this key, configuration device will activated specified address. specified address should even multiple range 100h-0FF8h (800h-0FF8h recommended). bypass written time, used move location configuration device PNPEN=1, bypass will work unless ES1878 "wait-for-key" mode). more detailed description "wait-for-key" mode, `Device Configuration' section.
Data Sheet
Configuration Registers
specification defines register configuration "card" consisting multiple "logical devices". ES1878 acts card three logical devices: configuration device, audio+FM+MPU-401 device, joystick device. register consists registers "card", bank-selected registers each logical device. addition, specification sets aside register space Vendor-Defined Card-Level registers. function these registers determined designer card chip. ES1878 Vendor-Defined Card-Level registers defined, from register 2Dh. configuration registers ES1878 accessed ways. First, PNPEN=1, registers read written defined specification. Second, regardless state PNPEN, registers read written using locations configuration device. first location configuration device written with register number read written. After programming register number, register read written accessing second location configuration device.
29h: high recommended. bits based interface use. should left BIOS. based system design. 2Ah: this register default value 0Eh. 2Bh: leave bits 00h. Bits settings based system design. 2Ch: settings based system design. 2Dh: leave this register value (fully powered on). Configure enable audio device. register (LDN number) 01h. Then program device registers 60h-65h, 70h, 75h. Leave register (second interrupt used). Finally, register order activate audio device. (Optional) Configure enable joystick device. register (LDN number) 02h. Then program registers with base address. register order activate joystick device.
Example
Using Non-PnP Method Configure ES1878: Enable configuration device address 800h sending bypass with interrupts disabled. Program Vendor-Defined Card-Level registers 20h2Dh follows: write Vendor-Defined Card-Level register number address 800h data address 801h. 20h, 21h, 22h: assign channels pins. Unused pins assigned IRQ1. 23h, 24h: assign channels pins. Unused pins assigned DRQ2. 25h: low, other bits needed enable GPOs GPIs. 26h: defines whether GPOs under software ES978 control. 27h: defines whether GPIs control ES978 GPOs. 28h: leave bits until Windows starts Windows driver will write this register allow sharing MPU-401 volume interrupts.
ES1878
Register
shown Figure below, Card-Level registers supported ES1878 Card-Control Card-Level registers addresses 00h-07h, Vendor-Defined Card-Level registers addresses 20h-2Fh. CardControl Card-Level register address pointer Logical Device registers supported ES1878 (one registers each logical device "card"). ES1878, there three logical devices: configuration device, audio+FM+MPU-401 device, joystick device. Card-Level Registers
(one card)
Address Card-Control Card-Level Registers Reserved Card-Level Registers (Not supported) Vendor-Defined Card-Level Registers bits Read Port Address Serial Isolation Configuration Control Wake Command Resource Data Status Card Select Number (CSN) Logical Device Number
Card-Control Card-Level Registers (00h 07h)
RD_DATA Port
(00h, Read/Write)
Bits RD_DATA port Read port written only when card isolation mode. reset hardware reset. read only from configuration mode. Bits read port always Serial Isolation (01h, Read-only)
data
Logical Device Registers
(one logical device card)
Address Activate Range Check Reserved Logical Device Control (Not supported) Vendor-Defined Logical Device Control (Not supported) Memory Configuration Registers (Not supported) Configuration Registers Interrupt Configuration Registers Configuration Registers 32-bit Memory Configuration Registers (Not supported) Reserved Logical Device Configuration (Not supported) Vendor-Defined Logical Device Configuration (Not supported) Reserved bits
Read-only isolation state. Configuration Control
RESET_CSN
(02h, Write-only)
RESET_CSN command. WAIT_FOR_KEY command. Software reset command. Does work WAIT_FOR_KEY state. (03h, Write-only)
data
Wake
data written matches CSN, then this card goes from Sleep state Isolation state CSN=0 from Sleep state Configuration Resource Data
resource data
(04h, Read-only)
Returns next byte resource data. Only works configuration mode. Status
reserved
(05h, Read-only)
status
Returns status ready. ready read resource data. Only works configuration mode.
Figure Configuration Register Outline
Data Sheet
card select number
(06h, Read/Write)
Vendor-Defined Card-Level Registers (20h 2Fh)
IRQB, IRQA
IRQB
(20h, Read-only)
IRQA
Read/write card select number. Write only works isolation mode. Causes transition configuration mode. Read only works configuration mode.
logical device number
(07h, Read/Write)
Defines number assigned pins. Loaded from Configuration Header after reset. Unused pins should assigned IRQD, IRQC
IRQD
(21h, Read-only)
IRQC
Read/write logical device configuration mode.
number.
Only
works
Defines number assigned pins. Loaded from Configuration header after reset. Unused pins should assigned IRQE
(22h, Read-only)
IRQE
Defines number assigned pin. Loaded from Configuration header after reset. Unused pins should assigned DRQB, DRQA
DRQB/DACKBB
(23h, Read-only)
DRQA/DACKBA
Defines number assigned pins. Loaded from Configuration header after reset. Unused pins should assigned DRQC
(24h, Read-only)
DRQC
Defines number assigned pin. Loaded from Configuration header after reset. Unused pins should assigned Shared Function Assignment
part LDN1/ LDN3 VOLUP, MUTE/ IRQE/ VOLDN/ GPI4 GPO6 GPI5,GPI6
(25h, Read-only)
IRQB/ GPO3 IRQD/ IRQC/ GPO5 GPO4
part LDN#1. LDN#3. VOLUP/VOLDN. GPI5/GPI6. 91/92.
ES1878
MUTE. GPI4. IRQE. GPO6. IRQD. GPO5. IRQC. GPO4. IRQB. GPO3. (26h, Read-only)
GPO[6:0]
Miscellaneous Digital Control
latch feature
(29h, Read/Write)
Analog/ digital Joystick ES1878 /ES978 joystick toggle
MIDI loopback test
port enable/ disable
port format
latch feature disabled (default). latch feature enabled. Disable port. Enable port. hardware reset default, interface disabled. port ES689/ES690 format. IIDATA data. IISCLK clock. IILR should connected float. Reserved. port format (hardware reset default). Reserved. Enable ES978 MIDI loopback test. Reserved. Analog joystick (default). Digital joystick. ES1878 joystick when docked. ES978 joystick when docked (default).
Bits
each GPO[6:0]: Bits controlled port Configuration_Device_Base+2h. controlled corresponding ES978.
This register reset zero hardware reset reset.
GPI[6:0]
(27h, Read-only)
This register reset hardware reset reset. hardware reset default format I2S. Special Volume
Volume mixed into ES978 playback
(2Ah, Read-only)
Volume mixed into ES978 record
each GPI[6:0]: Bits does control ES978. ES978 controlled port Configuration_Device_Base+3h. controls corresponding ES978.
Bits Bits
Volume host audio mixed into ES978 record mixer (default Volume host audio mixed into ES978 playback mixer (default 0Eh).
This register reset zero hardware reset reset. MPU-401 Volume Number (28h, Read-only)
volume number MPU-401 number
This register reset hardware reset reset. Miscellaneous Analog Control
ES1878 master volume mute toggle ES978 ES1878 external record sources
(2Bh, Read-only)
ES978 mappable mixer target
Bits Bits
volume number (must shared with audio1 audio2). MPU-401 number (alias address with register MPU-401 #3).
volume tracking
volume control
volume track volume when Mixer Volume Control register
Data Sheet
used. This useful when interface used external wavetable synthesizer. Vendor-Defined Card-Level register when high will enable tracking with volume. Bits Common volume with external record sources: (default) -1.5 -4.5 ES1878 master volume muted when docked (default). ES1878 master volume muted when docked ES978 volume tracks Mixer register ES1878 (default). ES978 volume tracks Mixer register ES1878. ES1878 volume controlled Mixer register (default). ES1878 volume controlled Mixer register 36h. Assigns ES978 target Mappable Mixer register 6Ah: None (default). Line I2S/ES689/ES690 interface
Resource Assignment
control Line control
(2Ch, Read-only)
AuxA control AuxB control
Bits Bits Bits Bits
AuxB control (see table below). AuxA control (see table below). Line control (see table below). control (see table below).
ES1878 Mute Mute Enabled Enabled ES978 Mute Enabled: track corresponding 1878 Mixer register Mute Enabled: track corresponding 1878 Mixer register
Values
After hardware reset reset, this register Power Management
used
(2Dh, Read/Write)
Power
Bits
Bits Fully powered down. Oscillator enabled, everything else powered down. Low-power mode: analog enabled, expansion interface enabled, mpu-401 enabled, joystick enabled, interface enabled, enabled. ES689/ES690 serial interfaces disabled, audio device disabled. Fully powered
This register reset zero hardware reset reset.
After hardware reset reset, this register Suspend Resume operation requires programming register Audio_Base+7h.
ES1878
Logical Devices
Table Logical Device Summary (mandatory) Range Check base address bits 11:8. this device disabled. locations base address bits Audio device Activate activate bit. Range Check base address Audio Processor bits 11:8. this device accessable.16 locations base address Audio Processor bits base address alias, bits 11:8. this device accessible. locations base address alias, bits 7:0. base address MPU-401, bits 11:8. this device accessible. MPU-401 also accessible through locations base address MPU-401, bits 7:0. Interrupt Request Level Select0 Returns Interrupt Request Level Select1 Returns channel select (default channel select (default Joystick device Activate activate bit. Range Check base address bits 11:8. this device disabled. location base address bits MPU-401 device Activate activate bit. Range Check base address bits 11:8. this device disabled. locations base address bits Interrupt Request Level Select0 Returns Device Configuration device Activate activate bit.
LDN0: Configuration Device
Activate
reserved
(30h, Read/Write)
activate
deactivate (default), activate.
After reset after written reset card's configuration control bit, default this register Range Check
enable range check reserved
(31h, Read/Write)
pattern select
(mandatory)
Verifies that range assigned logical device does conflict with range used another device. Enable range check: disable, enable. Pattern select: AAh, 55h. (60h, Read/Write)
A[11:8]
Configuration Device high
Used assign base address decoder logical device. base address bits 11:8. Configuration Device
A[7:3]
(61h, Read/Write)
base address, bits 7:3.
(mandatory)
(optional)
Data Sheet
LDN1: Audio Device
This device actually supports three functions: audio, MPU-401. Audio requires sixteen locations, interrupt which shared with MPU-401, channels. requires four locations. MPU-401 requires locations. Activate
reserved
MPU-401 Base Address
(64h, Read/Write)
A[11:8]
base address MPU-401 bits 11:8. (MPU-401 also accessible through #3). locations. MPU-401 Base Address
A[7:2]
(30h, Read/Write)
activate
(65h, Read/Write)
deactivate (default), activate. (31h, Read/Write)
enable range check pattern select
base address MPU-401, bits 7:2. Interrupt Request Level Select
Range Check
reserved
(70h, Read/Write)
data
Verifies that range assigned logical device does conflict with range used another device. Enable range check: disable, enable. Pattern select: AAh, 55h.
Interrupt request level select Bits select which interrupt level used Interrupt (71h, Read/Write)
Interrupt Request Type Select
Audio Processor Base Address (60h, Read/Write)
A[11:8]
Interrupt request type select Returns (low-to-high transition). Interrupt Request Level Select
base address audio processor, bits 11:8. Sixteen locations. Audio Processor Base Address (61h, Read/Write)
A[7:4]
(72h, Read/Write)
data
Interrupt request level select Bits select which interrupt level used Interrupt (73h, Read/Write)
base address audio processor, bits 7:4. Alias Base Address
(62h, Read/Write)
A[11:8]
Interrupt Request Type Select
base address alias, bits 11:8. Four locations. Alias Base Address
A[7:2]
Interrupt request type select Returns (low-to-high transition). Channel Select
(63h, Read/Write)
(74h, Read/Write)
data
base address alias, bits 7:2.
Bits
select which channel (75h, Read/Write)
data
Channel Select
Bits
select which channel
ES1878
LDN2: Joystick Device
Activate Register
reserved
LDN3: MPU-401
(30h, Read/Write)
activate
MPU-401, independent device, optional; normally MPU-401 part AudioDrive®. Activate Register
reserved
(30h, Read/Write)
activate
deactivate (default), activate. (31h, Read/Write)
enable range check pattern select
Range Check
reserved
deactivate (default), activate. (31h, Read/Write)
enable range check pattern select
Range Check
reserved
Verifies that range assigned logical device does conflict with range used another device. Enable range check: disable, enable. Pattern select: AAh, 55h. (60h, Read/Write)
A[11:8]
Verifies that range assigned logical device does conflict with range used another device. Enable range check: disable, enable. Pattern select: AAh, 55h. (60h, Read/Write)
A[11:8]
Decoder Base Address
Decoder Base Address
base address bits 11:8. location. Decoder Base Address
A[7:0]
(61h, Read/Write)
base address bits 11:8. locations. Decoder Base Address
A[7:0]
(61h, Read/Write)
base address, bits 7:0.
base address, bits 7:0. Interrupt Request Level Select
(70h, Read/Write)
data
Interrupt request level select Bits select which interrupt level used Interrupt (71h, Read/Write)
Interrupt Request Type Select
Interrupt request type select Returns (low-to-high transition).
Data Sheet
Device Configuration
ES1878 logical device configuration device. Table shows eight ports assigned configuration device using sequence. configuration device ports used address direct Configuration registers that define resources activation controls audio, MPU-401, joystick devices. These ports listed Table
Table Configuration Device Address Offset Name Base+0h Base+1h Base+2h Base+3h Base+4h Base+5h Base+6h Base+7h Configuration register address Configuration register data ES1878 General-Purpose Output register ES978 General-Purpose Output register ES1878 General-Purpose Input register (read-only) ES978 General-Purpose Input register (read-only) Interrupt Status register (read-only) Secondary Interrupt Mask register
Base+6h
Interrupt Status register Audio Audio Hardware volume MPU-401 bits 4,5:
Bits wait-for-key sleep isolation configure States
PNPOK status Current docking state (status; interrupt request) Base+7h Sets Secondary Interrupt Mask register. Audio (Set high hardware reset.) Audio (Set high hardware reset.) Hardware volume (Set high hardware reset.) MPU-401 (Set high hardware reset.) reserved reserved reserved reserved
Base+0h Base+1h Base+2h Base+3h Base+4h Base+5h
Sets Configuration Address register. Sets Configuration Data register. Sets state ES1878 pins that mapped pins ES978. Sets state ES978 pins that mapped pins ES1878. ES1878 General-purpose input status (read-only). ES978 General-purpose input status (read-only).
ES1878
Configuring IRQ, DMA, GPI/O Pins
(Registers 20h, 21h, 22h, 70h, 72h)
only channel (IRQA) connected bus, Vendor-Defined Card-Level registers 20h, 21h, programmed follows: register IRQA_channel_number "1"=IRQB unused register IRQC/D unused register IRQE unused recommended lines are: first choice second choice third choice
channel number must also programmed into register LDN1. When register matches channel numbers registers 20h, 21h, 22h, connection made. second interrupt audio device used register should zero.
DRQ/DACK (Registers 23h, 24h, 74h, 75h)
DRQA/DACKBA first audio channel DRQB/DACKBB second audio channel DMA, program register first channel number bits second channel number bits 7:4. Registers LDN1 must also programmed match DRQA DRQB channel numbers. Example: First channel second channel "3". register register DRQC/DACKBC unused register 74h, LDN1 register 75h, LDN1
GPI/O Vendor-Defined Card-Level Register 25h)
long DRQC/DACKBC selected, these pins usable general purpose inputs without further setup. General-purpose inputs, MUTE, VOLUP, VOLDN inputs. They read time, pins hardware volume control, bits Vendor-Defined Card-Level register must set. IRQ(B-E) GPOs, appropriate bits VendorDefined Card-Level register must set.
Data Sheet
PORTS
Table Port Joystick, Audio, MPU-401 Devices Port Audio Device Base+0h Base+3h Base+4h Base+5h Base+6h Base+7h Base+8h Base+9h Base+Ah Base+Ch Base+Eh Base+Fh Device Base+0h Base+3h MPU-401 Device Base+0h Base+1h Joystick Device Base+0h Read/write Joystick. Read/write MPU-401 port (x=0,1,2, enabled. Read/write 20-voice synthesizer. Address data registers. Read/write Read/write Read/write Read/write Read/write Read/write Read-only Read/write Read-only Read/write 20-voice synthesizer. Address data registers. Mixer Address register (port address Mixer Indirect registers). Mixer Data register (port data to/from Mixer Indirect registers). Audio reset status flags. Power Management register. Suspend request reset. 11-voice synthesizer. Address data registers. Input data from read buffer command/data I/O. Poll port Audio_Base+Eh test whether read buffer contents valid. Output data write buffer command/data I/O. Read embedded processor status. Data available flag from embedded processor. Address access FIFO Extended Mode. Read/Write Function
Port Descriptions
Audio Device
Mixer Address Register Audio_Base+4h
(Read/Write)
Reset Status Flags Audio_Base+6h
Serial flag power -down MIDI mode FIFO reset flag flag flag
(Read)
reset
Reading back this register useful "hot-key" application that needs change mixer while preserving address register. Mixer Data Register Audio_Base+5h
Bits port Audio_Base+6h used monitor activity ES1878. Bits high after read from port Audio_Base+6h. Specific activity then these bits low. When port Audio_Base+6h read later time, these bits indicate whether activity occurred between reads from Audio_Base+6h. addition, used indicate either ES689/ES690 serial interface use. high bits Mixer register high (software serial enable serial reset). also high ES689/ ES690 serial interface active, which combination
(Read/Write)
Reset Status Flags Audio_Base+6h
FIFO reset
(Write)
reset
ES1878
Mixer register high MCLK (ES689/ ES690 serial clock) being high periodically. Reading port Audio_Base+6h returns information: following
Read Data Register Audio_Base+Ah
(Read-only)
reads/writes MPU-401, Joystick, Configuration Device, well activity (the last including almost write 279h A79h PNPEN=1. reads/writes audio ports Audio_Base+4h Audio_Base+5h (mixer ports) writes audio ports excepting Audio_Base+4h, Audio_Base+5h, Audio_Base+7h. reads from audio ports excepting Audio_Base+4h, Audio_Base+5h, Audio_Base+6h, Audio_Base+7h. Also accesses ES1878. Serial activity flag. High serial mode enabled input high Mixer Extension register high) external ES689/ES690 using MCLK/MSD drive DACs. ES1878 digital audio currently powered down (power mode ES1878 processing MIDI command 30h, 31h, 34h, 35h. this mode, ES1878 monitoring serial input. Powering down cause loss data. Note that ES1878 does automatically wake based serial input pin.
Read data from embedded audio processor. Write Data Register Audio_Base+Ch
(Write)
Write data embedded audio processor. Read Data Register Audio_Base+Ch
(Read)
Write data write buffer command/data I/O. Write-Buffer-Not-Available flag until data processed ES1878 write buffer available ES1878 busy. write buffer available ES1878 busy. Same port Audio_Base+Eh. Extended Mode FIFO Full (256 bytes loaded). Extended Mode FIFO Empty bytes loaded). FIFO Half Empty, Extended Mode flag. ES1878 processor generated interrupt request (e.g., from Compatibility Mode complete). Interrupt request generated FIFO Half Empty flag change. Used programmed interface FIFO Extended Mode. Interrupt request generated counter overflow Extended Mode.
FIFO Reset register. Software Reset register. (Read/Write)
Power Management Register Audio_Base+7h
Suspend request 1:Reset Synth
Reading writing port Audio_Base+7h automatically wake ES1878. Bits
will
Read Buffer Status Register Audio_Base+Eh
(Read-only)
Suspend request. Pulse high, then request suspend. Reserved, should low. synthesizer reset. Release synthesizer reset. Reserved, should low.
read from port Audio_Base+Eh will reset request. Data available read buffer.
Data Sheet
Programmed Access FIFO Audio_Base+Fh
(Read/Write)
Data Write Register FM_Base+3h
(Write-only)
This port used replace Extended Mode with programmed I/O.
register write. Writing this register Emulation Mode same writing register FM_Base+1h.
Device
synthesizer operates different modes: Emulation Mode Native Mode. Emulation Mode synthesizer fully compatible with OPL3 synthesizer. Native Mode synthesizer increased capabilities performance more realistic music. following register descriptions Emulation Mode only. Status Register FM_Base+0h
MPU-401 Device
MPU-401 Data Register MPU_Base+0h
(Read/Write)
(Read)
This register used read data from MPU-401 receive FIFO command acknowledge byte (0FEh). This register also used write data MPU-401 transmit FIFO. MPU-401 Command Register MPU_Base+1h
(Write)
Reading this register returns overflow flags timers "interrupt request" from these timers (this real interrupt request supported status flag backward compatibility with OPL3 synthesizer). Bank Address Register FM_Base+0h
MPU-401 device accepts only commands: Reset/return Smart Mode. This command generates acknowledge byte received when already Smart Mode. UART Mode. This command generates acknowledge byte received while Smart Mode. ignored device already UART Mode.
(Write)
bank register address. Note: write this register will also synthesizer Emulation Mode currently Native Mode. Data Write Register FM_Base+1h
MPU-401 Status Register MPU_Base+1h
(Read)
(Write-only)
read data available receive FIFO, pending acknowledge byte read (0FEh). there room transmit FIFO accept another byte.
register write. data written FM_BASE+1h written current address register. Note that register writes must follow timing requirements OPL3 synthesizer. High Bank Address Register FM_Base+2h
(Write-only)
High bank register address.
ES1878
Joystick Device
joystick device uses only single port. device function modes: Analog Mode Digital Mode. this port defferent depending Mode. This section describes Analog Mode. Digital Mode described `Game/Joystick Interface' section. Joystick_Base+0h
(Write)
value written Joystick_Base+0h port will restart timing sequence. This should done before reading timer status flags. Joystick_Base+0h
(Read)
SW(A-D) return current state joystick switch inputs. T(A-D) return current state four one-shot timers connected resistors dual joysticks.
Data Sheet
PROGRAMMING ES1878 Identifying ES1878
ES1878 identified reading Mixer Extension register successively. Mixer Extension register returns following 8-bit values four successive reads: 18h, 78h, A[11:8], A[7:0] where data reads indicating part number (1878) A[11:0] base address configuration device. Writing Mixer Address register (Audio_Base+4h) resets sequence that next read returns 18h. addition performing actions above list, hardware reset will reset Mixer registers default values.
Modes Operation
ES1878 supports modes operation: Compatibility Mode Extended Mode. Compatibility Mode compatible Sound Blaster Pro, default mode after reset. this mode, ES1878 processor intermediary functions between CODEC Control register. Extended Mode operation uses 256-byte FIFO intermediary between CODEC Control register. ES1878 processor mostly idle this mode. control handled dedicated logic. commands have been added access various control registers needed extended operations. Some these commands also useful Compatibility Mode, such those configuring channels. both modes, Mixer Control registers allows application software control analog mixer, record source, output volume.
Resetting Audio Device Software
ES1878 audio embedded processor reset ways: hardware reset software reset. hardware reset signal comes from bus. Software reset controlled port Audio_Base+6h. reset ES1878 audio processor software: Write port Audio_Base+6h. Delay short period, example, reading back Audio_Base+6h microseconds. Write port Audio_Base+6h. loop that lasts from milliseconds, poll port Audio_Base+Eh read data available. 7=1, then read byte from port Audio_Base+Ah. Exit loop content 0AAh; otherwise, continue polling. Both hardware reset software reset will:
Compatibility Mode Programming
following sections describe Compatibility Mode programming considerations.
Compatibility Mode Operation
After reset, analog circuitry operations. command will cause switch "direction," subsequent command will switch ES1878 back "direction." output filtered connected voice input mixer. After reset, voice input mixer muted: prevent pops. ES1878 maintains status flag called Voice-Enable/Disable flag that indicates when voice channel muted. command enable voice channel command disable voice channel. ES1878 should reset before playing sound, status analog circuits certain, mute voice input mixer with command D3h, then direction level using direct-to-DAC command: Wait milliseconds analog circuitry settle before enabling voice channel with command D1h.
Disable Extended Mode. Reset timer divider filter registers sampling. Stop progress. Clear active interrupt request. Disable voice input mixer (see D1h/ commands). Reset Compatibility Mode Extended Mode counters 2048 bytes. analog direction DAC, with value mid-level. input volume 8-bit recording with maximum. input volume 16-bit recording mid-range.
ES1878
sounds still occur level left value other than mid-level (code 8-bit scale) previous play operation. prevent this, always finish transfer with command level midrange:
complete. FIFO gives application program sufficient time respond interrupt initiate next block transfer. "normal mode" transfers, controller must initialized ES1878 commanded every block that transferred. "auto-initialize mode", transfer continuous, circular buffer, ES1878 generates interrupt transition between buffer halves. this mode controller ES1878 need only once. ES1878 supports mono 8-bit transfers rate kHz. Mono 16-bit transfers supported rate kHz.
8-Bit, 16-Bit, Compressed Data Formats
8-bit samples unsigned, ranging from 0FFh, with level around 80h. 16-bit samples unsigned, least significant byte first, ranging from 0000h 0FFFFh with level around 8000h. ES1878 supports types compressed sound operations: ESPCM®, which uses variety proprietary compression techniques developed Technology, ADPCM, which supported other sound cards lower quality. Both ADPCM ESPCM® only transferred using transfer. first block multiple-block transfer uses different command than subsequent blocks. first byte first block called reference byte.
Stereo Transfers Compatibility Mode
Stereo transfers only available using rather than direct mode commands. perform stereo transfer, first program Mixer register high. Then timer divider twice per-channel sample rate. maximum stereo transfer rate 8-bit data channel; this case, program timer divider were doing mono. maximum stereo transfer rate 16-bit data channel. 8-bit data, ES1878 expects first byte transferred right channel, subsequent bytes alternate left, right etc. 16-bit data, ES1878 expects transfers multiple with repeating groups order: left byte left high byte right byte right high byte sure clear Mixer register when done with transfer.
Direct Mode Mode
direct mode, timing transfers handled application program. example, system timer reprogrammed generate interrupts desired sample rate. each system timer interrupt, command 16-bit data) issued followed sample. Polling Write-Buffer-Available flag required before writing command between command data. Note: switched capacitor filter initialized reset intended sample rate kHz. direct mode, application wish adjust this filter appropriate actual sample rate. easiest this program timer with command just application were using mode. mode, programmable timer ES1878 controls rate which samples sent DAC. timer programmed using command 40h, which also sets programmable filters inside ES1878. ES1878 firmware maintains internal FIFO levels 16-bit transfers, levels 8-bit transfers) that filled transfers emptied timed transfers DAC. Before transfer, application first programs controller desired transfer size address, then programs ES1878 with same size information. transfer, ES1878 will generate interrupt request, indicating that current block transfer
Compatibility Mode Operation
ES1878 analog circuitry switched from direction direction first direct mode command. Discard first 25-100 milliseconds samples because pops might occur data change from direction. direction voice input mixer automatically muted. ES1878 four recording sources: microphone, line, aux/CD, mixer. Microphone input source after reset. Select source using Mixer Control register 0Ch/1Ch. selected source passes through input volume stage that programmed with levels gain from
Data Sheet
+22.5 steps 8-bit recordings (other than "high-speed mode"), volume stage controlled ES1878 firmware purposes automatic gain control (AGC). 16-bit recordings well "high-speed mode" 8-bit recordings, input volume stage controllable from application software. command change input volume level from reset default mid-range, ES1878 supports direct mode ADC, "normal mode" ADC, well "auto-initialize mode" ADC. differences between various types described above DAC. Note: switched capacitor filter initialized reset intended sample rate kHz. direct mode, application wish adjust this filter appropriate actual sample rate. best this program timer with command just application were using mode. maximum sample rate direct mode kHz. maximum sample rate both 8-bit 16-bit kHz, using commands 24h, 25h, 2Ch, 2Dh. There special "high-speed mode" that allows 8-bit sampling kHz. This mode uses commands ("auto-initialization ("normal"). performed: input volume controlled with command DDh.
ES1878 internal 64-byte FIFO used from ADC. When FIFO full case DAC, empty case ADC), requests temporarily suspended Busy flag (bit port 22Ch) cleared. This allows window opportunity send command ES1878. only commands such which control mixer voice enable/disable status, command D0h, which suspends (i.e., pauses) transaction. ES1878 chip sets Busy flag when command window longer open. Application software must send command within microseconds after Busy flag goes high command will confused with data. This normally easy polling done with interrupts disabled. example sending command during DMA, consider case where application desires send command middle transfer. application disables interrupts polls Busy flag. Because FIFO rules used determining command window, possible current transfer complete while waiting Busy flag clear. this event, command function, there will pending interrupt request from completion. This interrupt request cleared reading port 22Eh before enabling interrupts signaling interrupt handler that inactive that does start transfer. Figure shows timing considerations sending command.
Sending Commands during Compatibility Mode Operations
useful understand detailed operation sending command during operation.
BUSY FLAG POLL BUSY WRITE COMMAND WRITE COMMAND
Figure Command Transfer Timing
µsec
ES1878
Extended Mode Programming
This section describes Extended Mode programming considerations. Extended Mode registers indirect registers, that they written read from using commands sent port.
Reading ES1878 Internal Registers
Command used read ES1878 Internal registers used Extended Mode. Send command followed register number, Bxh. example, read register A4h, send following command bytes: C0h, Then poll Read Data Buffer Status bit, port Audio_Base+Eh, before reading register contents.
Mixing Modes Recommended
recommended Extended Mode commands with Compatibility Mode commands. Voice-Enable/ Disable commands safe when using Extended Mode process DAC. However, there other Compatibility Mode commands that likely cause problems. Extended Mode commands used just channels before entering Compatibility Mode.
Command/Data Handshaking Protocol
Writing Commands ES1878
Commands written chip enter write buffer. Before writing command, must make sure buffer busy. port Audio_Base+Ch ES1878 Busy flag. when write buffer full when ES1878 otherwise busy (for example, during initialization after reset during Compatibility Mode requests). write command data byte ES1878 processor: Poll port Audio_Base+Ch milliseconds. Write command/data byte port Audio_Base+Ch. Note: port Audio_Base+Ch write buffer shared with Compatibility Mode write operations. When active, Busy flag will cleared during time windows when command received. Normally, only commands that should sent during operations 0Dxh commands: pause/continue, voice enable/disable, etc. this situation recommended that interrupts disabled between time that Busy polled command written. Also, time between these instructions should minimized. more information, section entitled `Sending Commands During Compatibility Mode Operations'.
Accessing ES1878 Extended Registers
This section describes send commands command-related data ES1878's Extended registers, which indirect registers. Commands format used write indirect registers within ES1878. After reset, command must issued before using Extended Mode command. Commands format Axh, Bxh, Cxh, where numeric value, used Extended Mode programming. Commands format used access "internal" indirect registers ES1878. convenience, registers named after commands used access them. example, "register A4h", Counter Low-Byte register, written "command A4h."
Writing ES1878 Internal Registers
following shows example writing ES1878 internal register. FIFO Counter Reload register F800h, send following command/data bytes: A4h, 00h; register A5h, F8h; register A5=F8 Always check write buffer before writing command port Audio_Base+Ch, make sure busy. Also, sure send command after every reset Extended Mode commands will used.
Reading Read Data Buffer ES1878
Read-Data-Buffer-Status flag polled reading port Audio_Base+Eh. When byte available will high. Note that read port Audio_Base+Eh will also clear active interrupt request from ES1878. alternative polling read buffer status port Audio_Base+Ch, which same flag. buffer status flag cleared automatically reading byte from port Audio_Base+Ah.
Data Sheet
Programming ES1878 Mixer
ES1878 Mixer registers that backward compatible with Sound Blaster Pro, with extended, alternate accessing registers provide greater functionality. There addresses used mixer: Audio_Base+4h address port; Audio_Base+5h data port. Sound Blaster Pro, Audio_Base+4h write only, while Audio_Base+5h read/write. Mixer register, write address Audio_Base+4h, then write data Audio_Base+5h. read register, read from Audio_Base+5h after setting address into Audio_Base+4h. Mixer registers affected software reset. reset registers initial conditions, write value mixer address Write Audio_Base+4h (set mixer address Write Audio_Base+5h (write address reset mixer) Sound Blaster Mixer Volume controls mostly bits channel. Sound Blaster Compatibility register Table details. Bits always high when read. ES1878 offers alternative write each Mixer register: address high, bits register readable writable. This called "Extended Access." address low, interface Sound Blaster compatible, bits cleared write forced high reads. Sound Blaster registers that have bits channel listed below:
Register Function Voice Volume Master Volume Volume (Aux) Volume Line Volume Extended Access Register Bits/Channel
significant. stuck high read stuck writes. Furthermore, this mono control, panning supported. Extended Access, register address instead. This offers 4-bits/channel control mono microphone input mixer. Refer Preamp register `Extension Registers' section. Volume
volume left volume right
reset, this register assumes value 00h. Access this register address mapped follows:
Write D2=0, D1=0 D2=0, D1=1 D2=1, D1=0 D2=1, D1=1 Read from Volume Volume Volume Volume
Volume register Volume register Others undefined.
Extended Access Source Select
Sound Blaster Compatibility Mode Sound Blaster mixer, there three choices recording source, bits Mixer register 0Ch. Note that upon write upon read from 0Ch:
Source Selected Microphone (default) (Aux) Input Microphone Line input
example, written Sound Blaster register 04h, read back because bits "stuck high" reads. Inside register, these bits "stuck low," that writing same writing 11h. write read address instead allows direct access bits Mixer register.
Extended Access, register address select recording from mixer follows:
Source Selected Microphone (default) (Aux) input Line input Mixer
Extended Access Volume
Sound Blaster Compatibility Mode register address used control Volume, only bits
ES1878
Programming FIFO Playback
Data Formats
There eight formats available from combination following three options shown Table
Register Configuration register. Make sure bits high; clear bits Configure system interrupt controller controller
Mono stereo 8-bit 16-bit Signed unsigned
Table Command Sequences Playback
Mono Stereo 8-bits 16-bits Unsigned Signed Sequence
stereo data, data stream always alternates channels successive samples: first left, then right. 16-bit data, byte always precedes high byte.
Programming Steps Playback:
Reset. Write port Audio_Base+6h instead Compatibility Mode. high specifically clears FIFO. remainder software reset identical Compatibility Mode. After reset, command issued enable Extended Mode commands. Reset disables voice input mixer. This intended mask pops created during setup transfer. Program direction type: registers B8h, A8h, B9h: Register B8h: normal transfer, auto-initialize transfer. Register A8h: read this register first preserve bits. Modify only bits Bits mono. Bits stereo. Register B9h: Single Transfer DMA. Demand Transfer DMA: bytes request. Demand Transfer DMA: bytes request.
Recommended: Delay approximately milliseconds before enabling voice input mixer. Enable voice mixer with command D1h. Start DMA: register high while preserving other bits. 10.During DMA: auto-initialize, send commands ES1878 interrupt time, except reading Audio_Base+Eh clear interrupt request. normal mode, initialize system controller with address count next block transfer. Update ES1878 transfer count registers count changed. start next transfer, clear register B8h, then high again. stop transaction progress, clear register B8h. stop after current auto-initialize block finished, clear register B8h, wait interrupt, then clear B8h. After transaction finished, restore system interrupt controller controller their idle state. Monitor FIFO Empty status flag register Audio_Base+Ch sure data transfer completed. delay milliseconds required
Clocks counters: registers A1h, A2h, A4h, A5h: Register Sample Rate Clock Divider Register Filter Clock Divider Registers A4h/A5h Counter Reload register low/ high, complement Initialize Configure DACs: registers B7h. DACs must configured initialized with command sequence depending data format shown Table Enable/Select Channel Channel, registers B2h: Register Interrupt Configuration register. Make sure bits high, clear bits
Data Sheet
filter outputs settle levels, then mute voice input mixer with command D3h. 12.Finally, issue another software reset ES1878 initialize appropriate registers.
Programming FIFO Record
Data Formats
There eight formats available from combination following three options:
high sample rates greater than kHz. Register Filter Clock Divider. Registers A4h/A5h Counter Reload Register low/high, complement. Delay milliseconds allow analog circuits settle. Enable record monitor desired: Register 3=1: Enable Record Monitor (optional). Initialize Configure ADC: register B7h. ADCs must configured initialized with command sequence depending data format shown Table
Table Command Sequence Record
Mono Stereo 8-bits 16-bits Unsigned Signed Sequence
Mono stereo 8-bit 16-bit Signed unsigned
stereo data, data stream always alternates channels successive samples: first left, then right. 16-bit data, byte always precedes high byte.
Automatic Gain Control 8-bit Recordings
Extended Mode, there Automatic Gain Control (AGC) performed while recording. necessary, 16-bit recordings perform system software.
Programming Steps Recording:
Reset. Write port Audio_Base+6h instead Compatibility Mode. high specifically clears FIFO. remainder software reset identical Compatibility Mode. After reset, command issued enable Extended Mode commands. Select input source using Mixer register 0Ch. Program Input Volume register B4h. Program direction type: registers B8h, A8h. Register B8h: normal transfer, auto-initialize transfer. this point, direction analog circuits becomes rather than DAC. Unless recording monitor enabled, there will output from AOUT_L AOUT_R until direction restored DAC. Register A8h: read this register first preserve bits. Modify only bits Bits mono stereo. Disable record monitor now. Register B9h: Single Transfer DMA. Demand Transfer, bytes request. Demand Transfer, bytes request. Clocks counters: registers A1h, A2h, A4h, A5h. Register Sample Rate Clock Divider.
Enable/select Channel Channel registers B2h: Register B1h: Interrupt Configuration register. Verify that bits high. Clear bits Register B2h: Configuration register: Verify that bits high. Clear bits 10.Configure system interrupt controller controller. start DMA: register high. Leave other bits unchanged. 12.During DMA: auto-initialize, send commands ES1878 interrupt time, except reading Audio_Base+Eh clear interrupt request. normal mode, initialize system controller with address count next block transfer. Update ES1878 Transfer Count registers count changed. start next transfer, clear register B8h, then high again.
ES1878
stop transaction progress, clear register B8h. stop transaction after current auto-initialize block finished, clear register B8h, wait interrupt, then clear B8h. 13.After transaction finished, restore system interrupt controller controller their idle state. 14.Finally, issue another software reset ES1878 initialize appropriate registers. This will return ES1878 direction turn record monitor.
bytes transferred. solution poll ES1878 FIFOHE flag sure goes interrupt handler when priming FIFO) perhaps send second block bytes. ADC, interrupt request generated when number bytes FIFO changes from 128, indicating that system processor safely read bytes from FIFO. Before first interrupt generated, FIFO should emptied mostly reading from Audio_Base+Fh polling FIFOHE flag. safe indiscriminately FIFO reset, port Audio_Base+6h clear FIFO, because data out-of-sync. mode, register enables transfers between system FIFO inside ES1878. Note: ES1878 designed block transfer speed 8.33 MHz.
Programming FIFO Block Transfer
some applications, suitable available data transfer, possible take exclusive control system transfers. these situations, block transfers within interrupt handler. OUTSB instruction 80x86 family transfers data from memory port specified register. INSB instruction complementary function. ES1878 port Audio_Base+Fh block transfers. transfers FIFO nearly identical process described above, except that access port Audio_Base+Fh replaces cycle. Some differences described here. Control Register B2h, bits should low. This because actual DRQ/DACKB cycle needed. Control Register must have high enable interrupt FIFO half-empty transitions. should avoid interrupt generated counter. program this mode, useful understand FIFO Half-Empty flag generates interrupt request: interrupt request generated rising edge FIFO Half-Empty flag. This flag polled reading port Audio_Base+Ch. meaning this flag depends direction transfer: FIFOHE flag high 0-127 bytes FIFO. FIFOHE flag high 128-256 bytes FIFO.
DAC, interrupt request generated when number bytes FIFO changes from 128. This indicates system processor that bytes safely transferred without overfilling FIFO. Before first interrupt generated, FIFO needs primed, filled, with more than bytes. Keep mind that data taken FIFO while being filled system processor. this case, there never bytes FIFO unless more than
Data Sheet
Full-Duplex Mode Serial Port)
ES1878 supports monophonic full-duplex DMA. mode, left channel records while right channel plays back. support mode, second channel been added ES1878. This second channel programmed through Mixer Extension registers. mode, first channel (the ES1788 channel) programmed mono recording same manner usually done. Extended Mode registers define sample rate filter frequency both record playback. other words, record playback must same sample rate (synchronous). After first channel new, second channel programmed. Mixer Extension registers complement transfer count. second channel supports auto-initialize mode well normal mode. playback buffer system memory does have same size record buffer. When transfer count rolls over generate interrupt that independent interrupt generated first channel. record playback buffers same size, then single interrupt used. Transfer Count registers programmed with same value both channels. second channel should enabled first, before record channel. example, assume there half-buffers circular buffer. When record channel completes filling first half, will generate interrupt. necessary assure that playback channel still accessing first half time interrupt. This guaranteed starting playback channel first. 32-word FIFO that will filled quickly DMA. recommended method follows: Program both controllers auto-initialize within separate circular buffers same size,
Before starting second channel DMA, clear second channel interrupt request writing Mixer Extension register 7Ah. Enable full-duplex mode setting Mixer Extension register 78h. Since playback FIFO presumably empty, value transferred playback each sample clock. click heard when full-duplex mode enabled. prevent this, command enable input mixer after suitable delay (about milliseconds). Enable playback setting Mixer Extension register 78h. After bytes transferred, should high. Poll this with suitable time-out (for example, milliseconds). After goes high, enable recording setting Extended Mode register Extended Mode register B8h. usual, first milliseconds recorded data should discarded until analog circuits have settled.
exit full-duplex mode, clear bits Mixer Extension register 78h.
Serial Interface Software Enable
hardware reset default, interface disabled. Vendor-Defined Card-Level register enables interface when high. This register accessed through Configuration Device.
Volume Control
mixer volume control register mixer register 68h. This register reset zero (mute) hardware reset. Bits select left channel volume, bits select right channel volume. Alternatively, volume volume register 36h. This useful when interface used external wavetable synthesizer. Vendor-Defined Card-Level register when high will enable tracking with volume.
Program record channel monophonic, 16-bit recording, auto-initialize mode, don't Extended register Extended register this time. This includes setting registers define sample rate filter frequency, well programming complement half-buffer-size (N/2) into Extended registers A5h. Program playback channel monophonic, 16bit playback, auto-initialize mode. complement transfer count bytes. Since second channel auto-initialize mode, second channel interrupt being used, value used transfer count. Sixty-four bytes allows playback channel "head-start" record channel polling second channel interrupt request after starting second channel DMA.
ES1878
AUDIO REGISTERS Types Register Access
There types audio registers ES1878:
Mixer registers. These registers accessed through ports Audio_Base+4h Audio_Base+5h. Audio_Base+4h written with register address. register then read/written Audio_Base+5h. These registers control many functions other than mixer.
Extension Extended Mode registers These registers used control Extended Mode playback record through first channel. Extended Mode registers accessed extension Sound Blaster common interface. This interface uses ports Audio_Base+Ah, Audio_Base+Ch, Audio_Base+Eh transfer read data, write data/commands, write status respectively. Examples this reading default settings disabling preamp register A9h. Reading default settings Write Audio_Base+Ch register Write Audio_Base+Ch register C0h. Write Audio_Base+Ch register A9h. Read Audio_Base+Ah Disabling preamp Write Audio_Base+Ch register Write Audio_Base+Ch
Mixer Registers
Sound Blaster Compatible Mixer Registers
more information, Sound Blaster Technical Reference.
Table Sound Blaster Compatibility Registers Line volume left Line volume right volume left (AUXA) volume left volume right (AUXA) volume right Master volume left Master volume right volume Source Stereo note note play volume left play volume right Digital audio playback volume Remark Mixer reset
Write: reset mixer
Sound Blaster filter control bits have function ES1878 ignored.
Data Sheet
Sound Blaster Master Volume Emulation
Sound Blaster emulations master volume means that 6-bit volume counters written Sound Blaster Mixer register 32h). Sound Blaster emulation enabled default, disabled setting Mixer register 62h. master volume registers always read, regardless whether Sound Blaster emulation enabled, using Sound Blaster Mixer registers (and 32h). following 6-bit 4-bit translation table used:
Table Sound Blaster Master Volume Emulation Mute Master Volume 0-24 25-30 31-34 35-38 39-42 43-46 47-50 51-54 56-57 59-60
Value Read
Value Read
Filter Control Registers
Sound Blaster mixer three bits that control input output filters. They labeled Table Table They have function ES1878 their values ignored.
16-bit stereo DAC, data always expected order: left low, left high, right low, right high transfers should multiples four bytes. Clear this after completing stereo transfer, because this unaffected software reset (only mixer reset).
Mixer Stereo Control
mixer stereo control register 0Eh. normally zero. this high enable Sound Blaster compatible stereo functions, program sample rate twice sample rate each channel. example, stereo, program "sample rate" using command 40h. This enables stereo only transfer Compatibility Mode. should used Extended Mode. After write Mixer register 0Eh, ES1878 will expect next 8-bit sample right channel. Subsequent samples will then alternate left, right, left, right.
ES1878
Mixer Registers
Table Mixer Registers Summary Input override Output override Analog control override Output signal Left Right Line volume left ES1878 identification value (read only) Input volume Output volume FDXO enable Mono FDXI/O FDXI enable Interleave Mode play volume left volume left Remark
Write: reset mixer play volume right volume right source Stereo Master volume right volume right (AuxA) volume right AuxB volume right speaker volume Line volume right Identifies ES1878 Serial mode input control Serial mode output control Serial mode miscellaneous analog control Serial mode miscellaneous control
volume
Master volume left volume left (AuxA) volume left AuxB volume left
comp
Serial reset 16/8
Enable ES689/ ES690 Intfc stereo/ mono
Active sync
Wavetable input enable FDXI/FDXO enable
Filter override 2-wire mode
1:Mute 1:Mute MPU-401 mask
complement filter divider 16/8 stereo/ mono
Serial mode filter divider control Serial mode format/source/target control Left master volume counter value Right master volume counter value
Left master volume Right master volume Read-only request mask Disable master volume emulation
Master volume control
Single/demand transfer
Clear hardware volume interrupt request (write-only) Left volume Mappable volume register value Two's complement transfer count byte Two's complement transfer count high byte Autoinitialize 1:Enable second channel Stereo Mono 1:Enable full-duplex mode 16-bit 8-bit Second transfer count reload register Second control Right volume volume control
Second channel
mask
Signed
Second control
Sound Blaster filter control bits have function ES1878 ignored.
Data Sheet
Register Detailed Descriptions
Reset Mixer Register
Write: reset mixer
Volume Register
volume left volume right
reset, this register assumes value 88h. Play Volume Register
play volume left play volume right
(AuxA) Volume Register
(AuxA) volume left
(AuxA) volume right
reset, this register assumes value 88h. Volume Register
volume left volume right
reset, this register assumes value 00h.
AuxB Volume Register
AuxB volume left AuxB volume right
reset, this register assumes value 00h. Record Source Select Register
source
reset, this register assumes value 00h.
Speaker Volume Register
reserved
speaker volume
reset, this register assumes value 00h. Sound Blaster filter control bits have function ES1878 ignored. extended access, register address select recording from mixer follows:
Source Selected Microphone (default) (Aux) input Line input Mixer
reset, this register assumes value 04h. Line Volume Register
Line volume left Line volume right
reset, this register assumes value 00h. ES1878 Identification Register
ES1878 identification value
Stereo Flag
Stereo
ES1878can identified reading Mixer Extension register successively. Mixer Extension register returns successive reads: 18h, 78h, A[11:8], A[7:0] where data reads indicating part number (1878) A[11:0] base address configuration device. Writing Mixer Address register (Audio_Base+4h) resets sequence that next read returns 18h. Serial Mode Input Control
Input override Input volume
reset, this register assumes value 00h. Sound Blaster filter control function ES1878 ignored. Master Volume Register
Master volume left Master volume right
reset, this register assumes value 88h. This register provides backward compatible access master volume. applications also registers which have more resolution.
IS1/IS0 input volume replace normal values programmed application when ES1878 serial mode.
ES1878
IS1/IS0 input volume unchanged during serial mode. Bits microphone preamp bypassed during serial mode high). IS1/IS0 select input source during serial mode high. These values override normal mixer settings shown following: Input source LINE AUXA (CD) Microphone Mixer Input volume. high during serial mode, this value overrides input volume settings command B4h.
Right channel combined mode. Right channel combined mode. Analog control bits 1:0. These special control signals control interconnections analog circuitry. They should appropriately application follows: Application Stereo wave playback record. Mono wave playback record. Full-duplex (mono record playback).
Bits
Bits
Serial Mode Output Control
Output override Output signal Output volume
Enables FDXO output connection output FOUT_R (right channel filter output). FDXO pull-up CMR. Enables FDXI input connection from left channel filter input thus input left channel ADC. FDXI input pull-up CMR. left channel filter input comes from input volume stage usual.
Mono FDXI/O Interleave Mode
Output volume during serial mode from this register rather than from Mixer Master Volume register. Output signal control always force during serial mode regardless state this bit. Controls signal routed speaker outputs AOUT_L AOUT_R.
Signal Mute FDXI monitor both channels FDXO monitor both channels FDXI monitor left channel, FDXO right Mixer output Mixer output except playback Mixer output except playback Reserved
Serial Mode Miscellaneous Control
comp Serial reset Enable Active ES689/ ES690 sync intfc
Bits
Force serial mode. This synchronized input clock DCLK, which must running. Data format complement. Data format unsigned. Reset Serial register left/right toggle flags. Release reset. Serial reset also inhibits FDXO connection FOUT_R "zeros" shift registers.
Bits
Output volume. Replaces normal mixer master volume setting high during serial mode.
FDXI
Serial Mode Miscellaneous Analog Control
Analog control override Left Right FDXO enable
bits this register take effect during serial mode. bits ever take effect. Reserved. Should Left channel combined mode. Left channel combined mode.
Enable ES689/ES690 acquire DACs when serial activity present pins MCLK MSD. Prevent ES689/ES690 from acquiring DACs. Sync pulses (FSR, FSX) active low. Reserved. Always writes Enable mono FDXI/FDXO mode. Enable Interleave Mode.
Data Sheet
Serial Mode Filter Divider
Filter override
complement filter divider
Bits
Receive register target.
Source None: Receive register held "zero" code FIFO mono, right channel receives data, left channel receives complement data) mono, right channel receives data, left channel receives complement data)
Controls filter clock rate during serial mode. During serial mode, filter clock generated dividing down serial clock. During serial mode, filter clock generated usual. Reserved. Always write Reserved. Always write Reserved. Always write These bits complement value that divides serial clock. ratio filter frequency filter clock about 1:41. Examples: (-14) External Serial Clock 2.048 3568 8000 sample rate. Internal Serial Clock 1.591 19.4 44,100 sample rate. Note that sample rate divider integer multiple filter divider 44,100, which gives maximum performance DACs ADCs.
Bits
Receive length bits, unsigned. Receive length bits, unsigned. Receive mode stereo. Left right channels alternate, with left channel data preceding right channel data. Receive mode mono.
Left Master Volume Counter Value
MUTE Left master volume
(-2)
Bits
select attenuation level steps -1.5 maximum setting corresponds attenuation.
Right Master Volume Counter Value
MUTE Right master volume
Serial Mode Format/Source/Target
16/8
stereo/ mono
16/8
stereo/ mono
Bits
select attenuation level steps -1.5 maximum setting corresponds attenuation.
Readonly interrupt request interrupt mask Disable master volume control
Bits
Transmit register source.
Source None: Transmit register held "zero" code FIFO Left stereo transmission Right
Master Volume Control
2-wire mode MPU-401 interrupt mask
Transmit length bits, unsigned. Transmit length bits, unsigned. Transmit mode stereo. Left right channels alternate, with left channel data preceding right channel data. Transmit mode mono.
When high, having both DOWN inputs will produce MUTE input low. This AND
Other recent searches
UT30P03 - UT30P03 UT30P03 Datasheet
TC-1 - TC-1 TC-1 Datasheet
SN74ABT16245 - SN74ABT16245 SN74ABT16245 Datasheet
SN54ABT16245 - SN54ABT16245 SN54ABT16245 Datasheet
MDX-19-6-1-X-X - MDX-19-6-1-X-X MDX-19-6-1-X-X Datasheet
GXO-E93 - GXO-E93 GXO-E93 Datasheet
GXO-E93NS - GXO-E93NS GXO-E93NS Datasheet
GXO-E93ND - GXO-E93ND GXO-E93ND Datasheet
GXO-E93PS - GXO-E93PS GXO-E93PS Datasheet
GXO-E93PD - GXO-E93PD GXO-E93PD Datasheet
CM6323 - CM6323 CM6323 Datasheet
74ALVC162334A - 74ALVC162334A 74ALVC162334A Datasheet
1N4150UR-1 - 1N4150UR-1 1N4150UR-1 Datasheet
1N3600UR - 1N3600UR 1N3600UR Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
