DS1009 Version 01.6, August 2008 LatticeXP2 Family Data Sheet Int
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LatticeXP2Family Data Sheet
DS1009 Version 01.6, August 2008
LatticeXP2 Family Data Sheet Introduction
February 2008 Data Sheet DS1009
Features
flexiFLASHArchitecture
Instant-on Infinitely reconfigurable Single chip FlashBAKtechnology Serial memory Design security
Flexible Buffer
sysIObuffer supports: LVCMOS 33/25/18/15/12; LVTTL SSTL 33/25/18 class HSTL15 class HSTL18 class LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS
Live Update Technology
TransFRtechnology Secure updates with encryption Dual-boot with external
Pre-engineered Source Synchronous Interfaces
DDR2 interfaces LVDS interfaces support display applications XGMII
sysDSPBlock
Three eight blocks high performance Multiply Accumulate 18x18 multipliers Each block supports 36x36 multiplier four 18x18 eight multipliers
Density Package Options
LUT4s, I/Os csBGA, TQFP PQFP ftBGA fpBGA packages Density migration supported
Flexible Device Configuration
(master slave) Boot Flash Interface Dual Boot Image supported Soft Error Detect (SED) macro embedded
Embedded Distributed Memory
Kbits sysMEMEBR Kbits Distributed
System Level Support
IEEE 1149.1 IEEE 1532 Compliant On-chip oscillator initialization general Devices operate with 1.2V power supply
sysCLOCKPLLs
four analog PLLs device Clock multiply, divide phase shifting Table 1-1. LatticeXP2 Family Selection Guide
Device LUTs Distributed (KBits) SRAM (KBits) SRAM Blocks sysDSP Blocks Multipliers Voltage GPLL Available Packages Combinations 132-Ball csBGA 144-Pin TQFP 208-Pin PQFP 256-Ball ftBGA 484-Ball fpBGA 672-Ball fpBGA XP2-5 XP2-8
XP2-17
XP2-30
XP2-40
2008 Lattice Semiconductor Corp. Lattice trademarks, registered trademarks, patents, disclaimers listed www.latticesemi.com/legal. other brand product names trademarks registered trademarks their respective holders. specifications information herein subject change without notice.
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DS1009 Introduction_01.2
Lattice Semiconductor
Introduction LatticeXP2 Family Data Sheet
Introduction
LatticeXP2 devices combine Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells architecture referred flexiFLASH. flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, chip storage with FlashBAK embedded block memory Serial memory design security. parts also support Live Update technology with TransFR, 128-bit Encryption Dual-boot technologies. LatticeXP2 FPGA fabric optimized technology from outset with high performance cost mind. LatticeXP2 devices include LUT-based logic, distributed embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous support enhanced sysDSP blocks. ispLEVER® design tool from Lattice allows large complex designs efficiently implemented using LatticeXP2 family FPGA devices. Synthesis library support LatticeXP2 available popular logic synthesis tools. ispLEVER tool uses synthesis tool output along with constraints from floor planning tools place route design LatticeXP2 device. ispLEVER tool extracts timing from routing back-annotates into design timing verification. Lattice provides many pre-designed Intellectual Property (IP) ispLeverCOREmodules LatticeXP2 family. using these standardized blocks, designers free concentrate unique aspects their design, increasing their productivity.
LatticeXP2 Family Data Sheet Architecture
August 2008 Data Sheet DS1009
Architecture Overview
Each LatticeXP2 device contains array logic blocks surrounded Programmable Cells (PIC). Interspersed between rows logic blocks rows sysMEMEmbedded Block (EBR) sysDSPDigital Signal Processing blocks shown Figure 2-1. left right sides Programmable Functional Unit (PFU) array, there Non-volatile Memory Blocks. configuration mode nonvolatile memory programmed IEEE 1149.1 port sysCONFIGperipheral port. power configuration data transferred from Non-volatile Memory Blocks configuration SRAM. With this technology, expensive external configuration memory required, designs secured from unauthorized read-back. This transfer data from non-volatile memory configuration SRAM wide busses happens microseconds, providing "instant-on" capability that allows easy interfacing many applications. LatticeXP2 devices also transfer data from sysMEM blocks Non-volatile Memory Blocks user request. There kinds logic blocks, without (PFF). contains building blocks logic, arithmetic, functions. block contains building blocks logic, arithmetic functions. Both blocks optimized flexibility allowing complex designs implemented quickly efficiently. Logic Blocks arranged two-dimensional array. Only type block used row. LatticeXP2 devices contain more rows sysMEM blocks. sysMEM EBRs large dedicated 18Kbit memory blocks. Each sysMEM block configured variety depths widths ROM. addition, LatticeXP2 devices contain rows Blocks. Each block multipliers adder/accumulators, which building blocks complex signal processing capabilities. Each block encompasses PIOs (PIO pairs) with their respective sysIO buffers. sysIO buffers LatticeXP2 devices arranged into eight banks, allowing implementation wide variety standards. addition, separate bank provided programming interfaces. pairs left right edges device configured LVDS transmit/receive pairs. logic also includes pre-engineered support implementation high speed source synchronous standards such LVDS interfaces, found many display applications, memory interfaces including DDR2. Other blocks provided include PLLs configuration functions. LatticeXP2 architecture provides four General Purpose PLLs (GPLL) device. GPLL blocks located corners device. configuration block that supports features such configuration bit-stream de-encryption, transparent updates dual boot support located between banks three. Every device LatticeXP2 family supports sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. JTAG port provided between banks three. This family also provides on-chip oscillator Soft Error Detect (SED) capability. LatticeXP2 devices 1.2V their core voltage.
2008 Lattice Semiconductor Corp. Lattice trademarks, registered trademarks, patents, disclaimers listed www.latticesemi.com/legal. other brand product names trademarks registered trademarks their respective holders. specifications information herein subject change without notice.
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DS1009 Architecture_01.4
Lattice Semiconductor
Figure 2-1. Simplified Block Diagram, LatticeXP2-17 Device (Top Level)
Architecture LatticeXP2 Family Data Sheet
sysIO Buffers, Pre-Engineered Source Synchronous Support
On-chip Oscillator
Programmable Function Units (PFUs) Port sysMEM Block
JTAG Port
Blocks
Flash
sysCLOCK PLLs
Flexible Routing
Blocks
core LatticeXP2 device made logic blocks forms, PFUs PFFs. PFUs programmed perform logic, arithmetic, distributed distributed functions. blocks programmed perform logic, arithmetic functions. Except where necessary, remainder this data sheet will term refer both blocks. Each block consists four interconnected slices, numbered Slice through Slice shown Figure 2-2. interconnections from blocks from routing. There inputs outputs associated with each block.
Lattice Semiconductor
Figure 2-2. Diagram
From Routing
Architecture LatticeXP2 Family Data Sheet
LUT4 CARRY
LUT4 CARRY
LUT4 CARRY
LUT4 CARRY
LUT4 CARRY
LUT4 CARRY
LUT4
LUT4
Slice
Slice
Slice
Slice
Routing
Slice
Slice through Slice contain 4-input combinatorial Look-Up Tables (LUT4), which feed registers. Slice contains LUT4s registers. PFUs, Slice Slice also configured distributed memory, capability available blocks. Table shows capability slices both blocks along with operation modes they enable. addition, each contains logic that allows LUTs combined perform functions such LUT5, LUT6, LUT7 LUT8. There control logic perform set/reset functions (programmable synchronous/asynchronous), clock select, chip-select wider RAM/ROM functions. Figure shows overview internal logic slice. registers slice configured positive/negative edge triggered level sensitive clocks. Table 2-1. Resources Modes Available Slice
BLock Slice Slice Slice Slice Slice Resources LUT4s Registers LUT4s Modes Logic, Ripple, Logic, Resources LUT4s Registers LUT4s Block Modes Logic, Ripple, Logic, Ripple, Logic, Ripple, Logic,
LUT4s Registers Logic, Ripple, RAM, LUT4s Registers LUT4s Registers Logic, Ripple, RAM, LUT4s Registers
Slice through Slice have input signals: signals from routing from carry-chain (from adjacent slice PFU). There seven outputs: routing carry-chain adjacent PFU). Slice input signals from routing four signals routing. Table lists signals associated with Slice Slice
Lattice Semiconductor
Figure 2-3. Slice Diagram
from Slice/PFU, into Different Slice/PFU
Architecture LatticeXP2 Family Data Sheet
SLICE
LUT4 CARRY*
OFX1 F/SUM Routing
LUT5
From Routing
OFX0
LUT4 CARRY* F/SUM
Slice
into Slice/PFU, from Different Slice/PFU
Slices memory control signals generated from Slice follows: from DI[3:2] Slice DI[1:0] Slice data [A:D] 4bit address from slice input
Table 2-2. Slice Signal Descriptions
Function Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Type Data signal Data signal Multi-purpose Multi-purpose Control signal Control signal Control signal Inter-PFU signal Inter-slice signal Inter-slice signal Data signals Data signals Data signals Data signals Inter-PFU signal Signal Names OFX0 OFX1 Inputs LUT4 Inputs LUT4 Multipurpose Input Multipurpose Input Clock Enable Local Set/Reset System Clock Fast Carry-In1 Intermediate signal generate LUT6 LUT7 Intermediate signal generate LUT6 LUT7 LUT4 output register bypass signals Register outputs Output LUT5 Output LUT6, LUT7, LUT82 depending slice Slice each fast carry chain output1 Description
Figure connection details. Requires PFUs.
Lattice Semiconductor Modes Operation
Architecture LatticeXP2 Family Data Sheet
Each slice four potential modes operation: Logic, Ripple, ROM. Logic Mode this mode, LUTs each slice configured LUT4s. LUT4 possible input combinations. Fourinput logic functions generated programming LUT4. Since there LUT4s slice, LUT5 constructed within slice. Larger LUTs such LUT6, LUT7 LUT8, constructed concatenating more slices. Note that LUT8 requires more than four slices. Ripple Mode Ripple mode allows efficient implementation small arithmetic functions. ripple mode, following functions implemented each slice: Addition 2-bit Subtraction 2-bit Add/Subtract 2-bit using dynamic control counter 2-bit Down counter 2-bit Up/Down counter with async clear Up/Down counter with preload (sync) Ripple mode multiplier building block Multiplier support Comparator functions inputs greater-than-or-equal-to not-equal-to less-than-or-equal-to carry signals, FCO, generated slice this mode, allowing fast arithmetic functions constructed concatenating slices. Mode this mode, 16x4-bit distributed Single Port (SPR) constructed using each block Slice Slice 16x1-bit memory. Slice used provide memory address control signals. 16x2-bit Pseudo Dual Port (PDPR) memory created using slice read-write port other companion slice read-only port. Lattice design tools support creation variety different size memories. Where appropriate, software will construct these using distributed memory primitives that represent capabilities PFU. Table shows number slices required implement different distributed primitives. more information using LatticeXP2 devices, please TN1137, LatticeXP2 Memory Usage Guide. Table 2-3. Number Slices Required Implementing Distributed
16X4 Number slices
Note: Single Port RAM, PDPR Pseudo Dual Port
PDPR 16X4
Mode mode uses logic; hence, Slices through used mode. Preloading accomplished through programming interface during configuration.
Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
Routing
There many resources provided LatticeXP2 devices route signals individually busses with related control signals. routing resources consist switching circuitry, buffers metal interconnect (routing) segments. inter-PFU connections made with (spans PFU), (spans three PFU) (spans seven PFU) connections. connections provide fast efficient connections horizontal vertical directions. resources buffered allow both short long connections routing between PFUs. LatticeXP2 family enhanced routing architecture produce compact design. ispLEVER design tool takes output synthesis tool places routes design. Generally, place route tool completely automatic, although interactive routing editor available optimize design.
sysCLOCK Phase Locked Loops (PLL)
sysCLOCK PLLs provide ability synthesize clock frequencies. LatticeXP2 family supports between four full featured General Purpose PLLs (GPLL). architecture GPLL shown Figure 2-4. CLKI, reference frequency, provided either from from routing; feeds into Input Clock Divider block. CLKFB, feedback signal, generated from CLKOP (the primary clock output) from user clock pin/logic. CLKFB feeds into Feedback Divider used multiply reference frequency. Both input path feedback signals enter Voltage Controlled Oscillator (VCO) block. phase frequency determined from input path feedback signals. LOCK signal generated indicate that locked with input clock signal. output feeds into CLKOP Divider, post-scalar divider. duty cycle CLKOP Divider output fine tuned using Duty Trim block, which creates CLKOP signal. allowing operate higher frequencies than CLKOP, frequency range GPLL expanded. output CLKOP Divider passed through CLKOK Divider, secondary clock divider, generate lower frequencies CLKOK output. applications that require even lower frequencies, CLKOP signal passed through divideby-three divider produce CLKOK2 output. CLKOK2 output provided applications that source synchronous logic. Phase/Duty Cycle/Duty Trim block used adjust phase duty cycle CLKOP Divider output generate CLKOS signal. phase/duty cycle setting pre-programmed dynamically adjusted. clock outputs from GPLL; CLKOP, CLKOK, CLKOK2 CLKOS, clock distribution network. further information GPLL please TN1126, LatticeXP2 sysCLOCK Design Usage Guide.
Lattice Semiconductor
Figure 2-4. General Purpose (GPLL) Diagram
WRDEL DDUTY DPHASE
Architecture LatticeXP2 Family Data Sheet
Phase/ Duty Cycle/ Duty Trim CLKFB CLKFB Divider VCO/ LOOP FILTER CLKOP Divider Duty Trim
CLKOK2
CLKOS
CLKI
CLKI Divider
CLKOP
CLKOK CLKOK Divider Lock Detect LOCK
Internal Feedback RSTK
Table provides description signals GPLL blocks. Table 2-4. GPLL Block Signal Descriptions
Signal CLKI CLKFB RSTK DPHASE [3:0] DDDUTY [3:0] WRDEL CLKOS CLKOP CLKOK CLKOK2 LOCK Clock input from external routing feedback input from CLKOP (PLL internal), from clock (CLKOP) from user clock (PIN logic) reset counters, VCO, charge pumps M-dividers reset K-divider Phase Adjust input Duty Cycle Select input Fine Delay Adjust input output clock clock tree (phase shifted/duty cycle changed) output clock clock tree phase shift) output clock tree through secondary clock divider output clock tree (CLKOP divided indicates LOCK CLKI Description
Clock Dividers
LatticeXP2 devices have clock dividers, left side right side device. These intended generate slower-speed system clock from high-speed edge clock. block operates mode maintains known phase relationship between divided down clock high-speed clock based release reset signal. clock dividers from CLKOP output from GPLLs from Edge Clocks (ECLK). clock divider outputs serve primary clock sources feed into clock distribution network. Reset (RST) control signal resets input forces outputs low. RELEASE signal releases outputs input clock. further information clock dividers, please TN1126, sysCLOCK Design Usage Guide. Figure shows clock divider connections.
Lattice Semiconductor
Figure 2-5. Clock Divider Connections
Architecture LatticeXP2 Family Data Sheet
ECLK CLKOP (GPLL)
CLKDIV
RELEASE
Clock Distribution Network
LatticeXP2 devices have eight quadrant-based primary clocks between eight flexible region-based secondary clocks/control signals. high performance edge clocks available each edge device support high speed interfaces. clock inputs selected from external I/Os, sysCLOCK PLLs, routing. Clock inputs throughout chip primary, secondary edge clock networks.
Primary Clock Sources
LatticeXP2 devices derive primary clocks from four sources: outputs, CLKDIV outputs, dedicated clock inputs routing. LatticeXP2 devices have four sysCLOCK PLLs, located four corners device. There eight dedicated clock inputs, each side device. Figure shows primary clock sources.
Lattice Semiconductor
Figure 2-6. Primary Clock Sources XP2-17
Clock Input Clock Input From Routing
Architecture LatticeXP2 Family Data Sheet
Input
GPLL
GPLL
Input
Clock Input
Primary Clock Sources Eight Quadrant Clock Selection
Clock Input
Clock Input
Clock Input
Input
GPLL
GPLL
Input
From Routing
Clock Input
Clock Input
Note: This diagram shows sources XP2-17 device. Smaller LatticeXP2 devices have GPLLs.
Lattice Semiconductor Secondary Clock/Control Sources
Architecture LatticeXP2 Family Data Sheet
LatticeXP2 devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads rest from routing. Figure shows secondary clock sources. Figure 2-7. Secondary Clock Sources
Clock Input Clock Input
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
Clock Input
Clock Input
Secondary Clock Sources
Clock Input Clock Input
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
Clock Input Clock Input
From Routing
From Routing
2-10
Lattice Semiconductor Edge Clock Sources
Architecture LatticeXP2 Family Data Sheet
Edge clock resources driven from variety sources same edge. Edge clock resources driven from adjacent edge clock PIOs, primary clock PIOs, PLLs clock dividers shown Figure 2-8. Figure 2-8. Edge Clock Sources
Clock Input From Routing Clock Input From Routing
Sources edge clocks
CLKOP
CLKOP CLKOS GPLL
Input
GPLL
CLKOS
Input
From Routing Clock Input Clock Input From Routing
CLKOP CLKOP CLKOS GPLL
From Routing Clock Input Clock Input From Routing
Eight Edge Clocks (ECLK) Clocks Edge
Input
GPLL
CLKOS
Input
Sources left edge clocks Sources bottom edge clocks
From Routing Clock Input Clock Input From Routing
Sources right edge clocks
Note: This diagram shows sources XP2-17 device. Smaller LatticeXP2 devices have GPLLs.
2-11
Lattice Semiconductor Primary Clock Routing
Architecture LatticeXP2 Family Data Sheet
clock routing structure LatticeXP2 devices consists network eight primary clock lines (CLK0 through CLK7) quadrant. primary clocks each quadrant generated from muxes located center device. clock sources connected these muxes. Figure shows clock routing quadrant. Each quadrant identical. desired, clock routed globally. Figure 2-9. Quadrant Primary Clock Selection
Primary Clock Sources: PLLs CLKDIVs PIOs Routing
30:1
30:1
30:1
30:1
30:1
30:1
29:1
29:1
29:1
29:1
CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6
CLK7
Primary Clocks (CLK0 CLK7) Quadrant
Dynamic Clock Select (DCS)
smart multiplexer function available primary clock routing. switches between independent input clock sources without glitches runt pulses. This achieved irrespective when select signal toggled. There blocks quadrant; total, eight blocks device. inputs block come from center muxes. output connected primary clocks CLK6 CLK7 (see Figure 29). Figure 2-10 shows timing waveforms default operating mode. block programmed other modes. more information DCS, please TN1126, LatticeXP2 sysCLOCK Design Usage Guide. Figure 2-10. Waveforms
CLK0
CLK1
DCSOUT
Secondary Clock/Control Routing
Secondary clocks LatticeXP2 devices region-based resources. benefit region-based resources relatively injection delay skew within region, compared primary clocks. rows, rows special vertical routing channel bound secondary clock regions. This special vertical routing channel aligns with either left edge center block center row. Figure 2-11 shows this special vertical routing channel eight secondary clock regions LatticeXP2-40.
2-12
Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
LatticeXP2-30 smaller devices have secondary clock regions. devices LatticeXP2 family have four secondary clocks (SC0 SC3) which distributed every region. secondary clock muxes located center device. Figure 2-12 shows structure secondary clock routing. Secondary clocks used clock control used high fan-out signals. Figure 2-11. Secondary Clock Regions XP2-40
Bank Bank Vertical Routing Channel Regional Boundary Secondary Clock Region Secondary Clock Region Regional Boundary
Bank
Bank
Secondary Clock Region
Secondary Clock Region
Bank
Secondary Clock Region
Secondary Clock Region
Regional Boundary
Bank
Secondary Clock Region
Secondary Clock Region
Regional Boundary
Bank
Bank
2-13
Lattice Semiconductor
Figure 2-12. Secondary Clock Selection
Architecture LatticeXP2 Family Data Sheet
Secondary Clock Feedlines: PIOs Routing
24:1
24:1
24:1
24:1
24:1
24:1
24:1
24:1
Secondary Clocks/CE/LSR (SC0 SC3) Region
Clock/Control High Fan-out Data Signals (SC4 SC7) Region
High Fan-out Data
Slice Clock Selection
Figure 2-13 shows clock selections Figure 2-14 shows control selections Slice0 through Slice2. primary clocks four secondary clocks routed this clock selection mux. Other signals, routing, used clock inputs slices. Slice controls generated from secondary clocks other signals connected routing. none signals selected both clock control, then default value output Slice does have registers; therefore does have clock control muxes. Figure 2-13. Slice0 through Slice2 Clock Selection
Primary Clock Secondary Clock Routing Clock Slice 25:1
2-14
Lattice Semiconductor
Figure 2-14. Slice0 through Slice2 Control Selection
Architecture LatticeXP2 Family Data Sheet
Secondary Clock Slice Control Routing 16:1
Edge Clock Routing
LatticeXP2 devices have eight high-speed edge clocks that intended with PIOs implementation high-speed interfaces. Each device edge clocks edge. Figure 2-15 shows selection muxes these clocks. Figure 2-15. Edge Clock Connections
Bottom Edge Clocks ECLK1/ ECLK2 (Both Muxes) Routing
Clock Input
Input GPLL Input
Left Right Edge Clocks ECLK1
GPLL Output CLKOP Routing
Input GPLL Input
Left Right Edge Clocks ECLK2
GPLL Output CLKOS Routing
2-15
Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
sysMEM Memory
LatticeXP2 devices contains number sysMEM Embedded Block (EBR). consists Kbit with dedicated input output registers.
sysMEM Memory Block
sysMEM block implement single port, dual port pseudo dual port memories. Each block used variety depths widths shown Table 2-5. FIFOs implemented sysMEM blocks using support logic with PFUs. block supports optional parity each data byte facilitate parity checking. blocks provide byte-enable support configurations with18-bit 36-bit data widths. Table 2-5. sysMEM Block Configurations
Memory Mode Configurations 16,384 8,192 4,096 2,048 1,024 16,384 8,192 4,096 2,048 1,024 16,384 8,192 4,096 2,048 1,024
Single Port
True Dual Port
Pseudo Dual Port
Size Matching
multi-port memory modes support different widths each ports. bits mapped word word word word Although word size number words each port varies, this mapping scheme applies each port.
FlashBAK Content Storage
memory LatticeXP2 shadowed Flash memory. Optionally, initialization values memory blocks defined using Lattice ispLEVER tools. initialization values loaded into Flash memory during device programming into SRAM power whenever device reconfigured. This feature ideal storage variety information such look-up tables microprocessor code. also possible write current contents memory back Flash memory. This capability useful storage data such error codes calibration information. additional information FlashBAK capability TN1137, LatticeXP2 Memory Usage Guide.
2-16
Lattice Semiconductor
Figure 2-16. FlashBAK Technology
Make Infinite Reads Writes
Architecture LatticeXP2 Family Data Sheet
Write Flash During Programming
Flash
JTAG Port
FPGA Logic
Write From Flash During Configuration Write From Flash User Command
Memory Cascading
Larger deeper blocks RAMs created using sysMEM Blocks. Typically, Lattice design tools cascade memory transparently, based specific design inputs.
Single, Dual Pseudo-Dual Port Modes
sysMEM modes input data address ports registered input memory array. output data memory optionally registered output. memory supports forms write behavior single port dual port operation: Normal Data output appears only during read cycle. During write cycle, data current address) does appear output. This mode supported data widths. Write Through copy input data appears output same port during write cycle. This mode supported data widths.
Memory Core Reset
memory array utilizes latches output ports. These latches reset asynchronously synchronously. RSTA RSTB local signals, which reset output latches associated with Port Port respectively. GSRN, global reset signal, resets both ports. output data latches associated resets both ports shown Figure 2-17. Figure 2-17. Memory Core Reset
Memory Core
Port A[17:0]
LCLR
Output Data Latches
Port B[17:0]
LCLR
RSTA
RSTB GSRN Programmable Disable
2-17
Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
further information sysMEM block, please TN1137, LatticeXP2 Memory Usage Guide.
Asynchronous Reset
asynchronous reset used) only applied clock enables clock cycle before reset applied released clock cycle after low-to-high transition reset signal, shown Figure 2-18. input always asynchronous. Figure 2-18. Asynchronous Reset (Including GSR) Timing Diagram
Reset
Clock
Clock Enable
clock enables remain enabled, asynchronous reset only applied released after read write clock inputs steady state condition minimum 1/fMAX (EBR clock). reset release must adhere synchronous reset setup time before next active read write clock edge. pre-loaded during configuration, input must disabled release during device Wake must occur before release device I/Os becoming active. These instructions apply implementations. Note that there reset restrictions synchronous reset used input disabled.
sysDSPBlock
LatticeXP2 family provides sysDSP block making ideally suited cost, high performance Digital Signal Processing (DSP) applications. Typical functions used these applications include Correlators, Fast Fourier Transform (FFT) functions, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/ Decoder Convolutional Encoder/Decoder. These complex signal processing functions similar building blocks such multiply-adders multiply-accumulators.
sysDSP Block Approach Compare General
Conventional general-purpose chips typically contain four (Multiply Accumulate) units with fixed data-width multipliers; this leads limited parallelism limited throughput. Their throughput increased higher clock speeds. LatticeXP2 family, other hand, many blocks that support different datawidths. This allows designer highly parallel implementations functions. designer optimize performance area choosing appropriate levels parallelism. Figure 2-19 compares fully serial mixed parallel serial implementations.
2-18
Lattice Semiconductor
Figure 2-19. Comparison General LatticeXP2 Approaches
Architecture LatticeXP2 Family Data Sheet
Operand
Operand Operand Operand
Operand Operand
Operand
Operand
Single Multiplier
loops
Multiplier Multiplier
adds)
Output
loops Multiplier
Accumulator
Function implemented General purpose
accumulate
Function implemented LatticeXP2
sysDSP Block Capabilities
sysDSP block LatticeXP2 family supports four functional elements three data path widths. user selects function element block then selects width type (signed/unsigned) operands. operands LatticeXP2 family sysDSP Blocks either signed unsigned mixed within function element. Similarly, operand widths cannot mixed within block. elements concatenated. resources each sysDSP block configured support following four elements: MULT (Multiply) (Multiply, Accumulate) MULTADDSUB (Multiply, Addition/Subtraction) MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate) number elements available each block depends width selected from three available options: x18, x36. number these elements concatenated highly parallel implementations functions. Table shows capabilities block. Table 2-6. Maximum Number Elements Block
Width Multiply MULT MULTADDSUB MULTADDSUBSUM
Some options available four elements. input register elements directly loaded loaded shift register from previous operand registers. selecting `dynamic operation' following operations possible: 2-19
Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
`Signed/Unsigned' options operands switched between signed unsigned every cycle. `Add/Sub' option Accumulator switched between addition subtraction every cycle. loading operands switch between parallel serial operations.
MULT sysDSP Element
This multiplier element implements multiply with addition accumulator nodes. operands, multiplied result available output. user enable input/output pipeline registers. Figure 2-20 shows MULT sysDSP element. Figure 2-20. MULT sysDSP Element
Shift Register Multiplicand
Shift Register
Multiplier
Output Register
Input Data Register
Multiplier
Input Data Register
Pipeline Register
(default)
Output
Signed Signed
Input Register Input Register
Multiplier Multiplier
(CLK0,CLK1,CLK2,CLK3) (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3)
Shift Register
Shift Register
2-20
Lattice Semiconductor sysDSP Element
Architecture LatticeXP2 Family Data Sheet
this case, operands, multiplied result added with previous accumulated value. This accumulated value available output. user enable input pipeline registers output register always enabled. output register used store accumulated value. Accumulators blocks LatticeXP2 family initialized dynamically. registered overflow signal also available. overflow conditions provided later this document. Figure 2-21 shows sysDSP element. Figure 2-21. sysDSP
Serial Register Multiplicand
Serial Register
Accumulator
Preload
Input Data Register
Multiplier
Input Data Register
Signed Signed Addn Accumsload
Input Register Input Register Input Register Input Register
Pipeline Register Pipeline Register Pipeline Register Pipeline Register
Output Register
(default) Pipeline Register
Output Register
Multiplier
m+n+16 (default)
Output
m+n+16 (default)
Accumulator Accumulator Accumulator
Overflow signal
(CLK0,CLK1,CLK2,CLK3) Accumulator (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3)
SROB
SROA
2-21
Lattice Semiconductor MULTADDSUB sysDSP Element
Architecture LatticeXP2 Family Data Sheet
this case, operands multiplied result added/subtracted with result multiplier operation operands user enable input, output pipeline registers. Figure 2-22 shows MULTADDSUB sysDSP element. Figure 2-22. MULTADDSUB
Shift Register Multiplicand
Input Data Register Input Data Register Multiplier
Shift Register
(CLK0,CLK1,CLK2,CLK3) (CE0,CE1,CE2,CE3)
Multiplier
(RST0,RST1,RST2,RST3)
Pipeline Register
(default) Add/Sub
Multiplicand
Output Register
Output
m+n+1 (default)
Multiplier
m+n+1 (default) Multiplier (default)
Input Data Register
Input Data Register
Pipeline Pipe Register Pipeline Pipe Register Pipeline Pipe Register
Pipeline Register
Signed Signed Addn
Input Register Input Register Input Register
Add/Sub Add/Sub Add/Sub
Shift Register
Shift Register
2-22
Lattice Semiconductor MULTADDSUBSUM sysDSP Element
Architecture LatticeXP2 Family Data Sheet
this case, operands multiplied result added/subtracted with result multiplier operation operands Additionally operands multiplied result added/ subtracted with result multiplier operation operands result both addition/subtraction added summation block. user enable input, output pipeline registers. Figure 2-23 shows MULTADDSUBSUM sysDSP element. Figure 2-23. MULTADDSUBSUM
Shift Register Multiplicand Multiplier
Input Data Register Input Data Register Multiplier
Shift Register
(CLK0,CLK1,CLK2,CLK3) (CE0,CE1,CE2,CE3)
Input Data Register
Pipeline Register
(default)
RST(RST0,RST1,RST2,RST3)
Add/Sub0
Multiplicand Multiplier
(default) Multiplier
Input Data Register
Pipeline Register
m+n+1
Output Register
Multiplicand Multiplier
Input Data Register
m+n+2
Output
m+n+2
Input Data Register
Multiplier
Input Data Register
Pipeline Register
(default) m+n+1 Add/Sub1
Multiplicand Multiplier
(default) Multiplier
Input Data Register
Input Register Input Register Input Register Input Register Pipeline Register Pipeline Register Pipeline Register Pipeline Register
Pipeline Register
Signed Signed Addn0 Addn1
Add/Sub0, Add/Sub1 Add/Sub0, Add/Sub1 Add/Sub0 Add/Sub1
Shift Register
Shift Register
Clock, Clock Enable Reset Resources
Global Clock, Clock Enable (CE) Reset (RST) signals from routing available every block. From four clock sources (CLK0, CLK1, CLK2, CLK3) clock selected each input register, pipeline register output
2-23
Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
register. Similarly, selected from their four respective sources (CE0, CE1, CE2, RST0, RST1, RST2, RST3) each input register, pipeline register output register.
Signed Unsigned with Different Widths
block supports other widths, addition widths, signed unsigned multipliers. unsigned operands, unused upper data bits should filled create valid operand. signed two's complement operands, sign extension most significant should performed until width reached. Table provides example this. Table 2-7. Sign Extension Example
Number Unsigned 0101 Unsigned 9-bit 000000101 Unsigned 18-bit 000000000000000101 Signed 0101 1010 Two's Complement Signed Bits 000000101 111111010 Two's Complement Signed Bits 000000000000000101 111111111111111010
OVERFLOW Flag from
sysDSP block provides overflow output indicate that accumulator overflowed. "Roll-over" occurs overflow signal indicated when following true: unsigned numbers added result smaller number than accumulator, positive numbers added with negative negative numbers added with positive sum. Note that when overflow occurs overflow flag present only cycle. counting these overflow pulses FPGA logic, larger accumulators constructed. conditions overflow signal signed unsigned operands listed Figure 2-24. Figure 2-24. Accumulator Overflow/Underflow
011111100 011111101 011111110 011111111 100000000 100000001 100000010
000000011 000000010 000000001 000000000 111111111 111111110 111111101
Carry signal generated cycle when this boundary crossed
Unsigned Operation
Overflow signal generated cycle when this boundary crossed
011111100 011111101 011111110 011111111 100000000 100000001 100000010
-256 -255 -254
000000011 000000010 000000001 000000000 111111111 111111110 111111101
Signed Operation
2-24
Lattice Semiconductor IPexpress
Architecture LatticeXP2 Family Data Sheet
user access sysDSP block ispLEVER IPexpress tool, which provides option configure each module group modules), direct instantiation. addition, Lattice partnered with MathWorks® support instantiation Simulink® tool, graphical simulation environment. Simulink works with ispLEVER dramatically shorten design cycle Lattice FPGAs.
Optimized Functions
Lattice provides library optimized functions. Some cores planned LatticeXP2 include Correlator, functions, Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/Decoder Convolutional Encoder/Decoder. Please contact Lattice obtain latest list available cores.
Resources Available LatticeXP2 Family
Table shows maximum number multipliers each member LatticeXP2 family. Table shows maximum available Blocks Serial Memory bits each LatticeXP2 device. blocks, together with Distributed used store variables locally fast operations. Table 2-8. Maximum Number Blocks LatticeXP2 Family
Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 Block Multiplier 18x18 Multiplier 36x36 Multiplier
Table 2-9. Embedded SRAM/TAG Memory LatticeXP2 Family
Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 SRAM Block Total SRAM (Kbits) Memory (Bits) 2184 2640 3384
LatticeXP2 Performance
Table 2-10 lists maximum performance Millions (MMAC) operations second each member LatticeXP2 family. Table 2-10. Performance
Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 Block Performance MMAC 3,900 5,200 6,500 9,100 10,400
further information sysDSP block, please TN1140, LatticeXP2 sysDSP Usage Guide.
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Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
Programmable Cells (PIC)
Each contains PIOs connected their respective sysIO buffers shown Figure 2-25. Block supplies output data (DO) tri-state control signal (TO) sysIO buffer receives input from buffer. Table 2-11 provides signal list. Figure 2-25. Diagram
PIOA
OPOS1 ONEG1
IOLT0 Tristate Register Block
OPOS0 OPOS21 ONEG0 ONEG21
PADA IOLD0 Output Register Block
sysIO Buffer
QNEG01 QNEG11 QPOS01 QPOS11 INCK2 INDD INFF IPOS0 IPOS1 GSRN ECLK1 ECLK2 DDRCLKPOL1 DQSXFER1
Control Muxes CLK1 CLK0
Input Register Block
PADB PIOB
Signals available left/right/bottom edges only. Selected blocks.
adjacent PIOs joined provide differential pair (labeled "C") shown Figure 2-25. Labels distinguish PIOs. Approximately pairs left right edges device configured true LVDS outputs. pairs operate inputs.
2-26
Lattice Semiconductor
Table 2-11. Signal List
Name ECLK1, ECLK2 GSRN INCK2 INDD INFF IPOS0, IPOS1 QPOS0 QPOS1
Architecture LatticeXP2 Family Data Sheet
Type Control from core Control from core Control from core Control from core Control from routing Input core Input Input core Input core Input core Input core Input core Output data from core Tristate control from core Control from core Tristate control from core Control from core
Description Clock enables input output block flip-flops System clocks input output blocks Fast edge clocks Local Set/Reset Global Set/Reset (active low) Input Primary Clock Network reference inputs signal from logic (routing) Unregistered data input core Registered input positive edge clock (CLK0) Double data rate registered inputs core Gearbox pipelined inputs core Gearbox pipelined inputs core Output signals from core operation Signals Tristate Register block operation Dynamic input delay control bits Tristate signal from core used operation Controls signal Output block
QNEG01, QNEG11 OPOS0, ONEG0, OPOS2, ONEG2 OPOS1 ONEG1 DEL[3:0] DDRCLKPOL DQSXFER
Control from clock polarity Controls polarity clock (CLK0) that feed input block
Signals available left/right/bottom only. Selected I/O.
contains four blocks: input register block, output register block, tristate register block control logic block. These blocks contain registers operating variety modes along with necessary clock selection logic.
Input Register Block
input register blocks PIOs contain delay elements registers that used condition high-speed interface signals, such memory interfaces source synchronous interfaces, before they passed device core. Figure 2-26 shows diagram input register block. Input signals from sysIO buffer input register block signal DI). desired, input signal bypass register delay elements used directly combinatorial signal (INDD), clock (INCK) and, selected blocks, input delay block. input delay desired, designers select either fixed delay dynamic delay DEL[3:0]. delay, selected, reduces input register hold time requirements when using global clock. input block allows three modes operation. Single Data Rate (SDR) mode, data registered, registers Sync register block, with system clock. mode registers used sample data positive negative edges signal which creates data streams, synchronized with system clock before entering core. Further information this topic found Memory Support section this data sheet. combining input blocks complementary PIOs sharing registers from output blocks, gearbox function implemented, that takes double data rate signal applied PIOA converts four data streams, IPOS0A, IPOS1A, IPOS0B IPOS1B. Figure 2-26 shows diagram using this gearbox function. more information this topic, please TN1138, LatticeXP2 High Speed Interface.
2-27
Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
signal DDRCLKPOL controls polarity clock used synchronization registers. ensures adequate timing when data transferred from system clock domain. further discussion this topic, Memory section this data sheet. Figure 2-26. Input Register Block
(From sysIO Buffer)
Fixed Delay Dynamic Delay
INCK2 Delay Block2 INDD
Registers Sync Registers Clock Transfer Registers
IPOS0A QPOS0A
[3:0]
D-Type /LATCH
D-Type1
D-Type
From Routing
IPOS1A QPOS1A
Delayed
D-Type
D-Type
D-Type /LATCH
D-Type1
Routing
CLK0 DDRCLKPOL CLKA
True LVDS Pair Comp LVDS Pair
(From sysIO Buffer)
DDRSRC
Registers
INCK2 Delay Block2 INDD
Sync Registers
Fixed Delay Dynamic Delay
Clock Transfer Registers
IPOS0B QPOS0B
[3:0]
D-Type
D-Type /LATCH
D-Type1
From Routing
Delayed
IPOS1B
QPOS1B
D-Type
D-Type
D-Type /LATCH
D-Type1
Routing
CLK0 DDRCLKPOL CLKB
Shared with output register Selected PIO. Gearbox Configuration
Note: Simplified version does show SET/RESET details
Output Register Block
output register block provides ability register signals from core device before they passed sysIO buffers. blocks PIOs left, right bottom contain registers operation that combined with additional latch operation. Figure 2-27 shows diagram Output Register Block PIOs. mode, ONEG0 feeds flip-flops that then feeds output. flip-flop configured Dtype latch. mode, ONEG0 OPOS0 into registers positive edge clock. next clock cycle registered OPOS0 latched. multiplexer running same clock cycle selects correct register feed output (D0). combining output blocks complementary PIOs sharing some registers from input blocks, gearbox function implemented, take four data streams ONEG0A, ONEG1A, ONEG1B ONEG1B. Figure 2-27 2-28
Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
shows diagram using this gearbox function. more information this topic, TN1138, LatticeXP2 High Speed Interface. Figure 2-27. Output Tristate Block
Tristate Logic
ONEG1 D-Type /LATCH
OPOS1
Latch
D-Type
sysIO Buffer
From Routing
ONEG0
D-Type*
D-Type /LATCH
Output Registers
OPOS0 D-Type* Latch
Latch
D-Type
CLKA ECLK1 ECLK2 CLK1 (CLKA) DQSXFER
Clock Transfer Registers
Programmable Control
Output Logic True LVDS Pair Comp LVDS Pair
Tristate Logic
ONEG1 D-Type /LATCH
OPOS1
Latch
D-Type
sysIO Buffer
From Routing
ONEG0
D-Type*
D-Type /LATCH
Output Registers
OPOS0 Latch Latch
D-Type*
D-Type
CLKB ECLK1 ECLK2 CLK1 (CLKB) DQSXFER
Clock Transfer Registers
Programmable Control
Output Logic
Shared with input register
Note: Simplified version does show SET/RESET details
2-29
Lattice Semiconductor Tristate Register Block
Architecture LatticeXP2 Family Data Sheet
tristate register block provides ability register tri-state control signals from core device before they passed sysIO buffers. block contains register operation additional latch operation. Figure 2-27 shows Tristate Register Block with Output Block mode, ONEG1 feeds flip-flops that then feeds output. flip-flop configured Dtype latch. mode, ONEG1 OPOS1 into registers positive edge clock. Then next clock registered OPOS1 latched. multiplexer running same clock cycle selects correct register feeding output (D0).
Control Logic Block
control logic block allows selection modification control signals block. clock signal selected from general purpose routing, ECLK1, ECLK2 signal (from programmable pin) provided input register block. clock optionally inverted.
Memory Support
PICs have additional circuitry allow implementation high speed source synchronous memory interfaces. PICs have registered elements that support memory interfaces. Interfaces left right edges designed memories that support bits data, whereas interfaces bottom designed memories that support bits data. every PIOs left right every PIOs bottom contain delay elements facilitate generation signals. signals feed buses which span PIOs. Figure 2-28 Figure 2-29 show assignments each PIOs. exact pins shown dual function Logic Signal Connections table this data sheet. Additional detail provided Signal Descriptions table. signal from used strobe data from memory into input register blocks. additional information using memory support please TN1138, LatticeXP2 High Speed Interface.
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Lattice Semiconductor
Figure 2-28. Input Routing (Left Right)
sysIO Buffer
Delay
Architecture LatticeXP2 Family Data Sheet
PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB
Assigned
PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB
Figure 2-29. Input Routing (Top Bottom)
sysIO Buffer
Delay
PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB
Assigned
PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB PADA
LVDS Pair
PADB
2-31
Lattice Semiconductor Calibrated Delay Block
Architecture LatticeXP2 Family Data Sheet
Source synchronous interfaces generally require input clock adjusted order correctly capture data input register. most interfaces used this adjustment. However, memories clock, referred DQS, free-running, this approach cannot used. Delay block provides required clock alignment memory interfaces. signal (selected PIOs only, shown Figure 2-30) feeds from through delay element dedicated routing resource. signal also feeds polarity control logic which controls polarity clock sync registers input register blocks. Figure 2-30 Figure 2-31 show transition signals routed PIOs. temperature, voltage process variations delay block compensated 6-bit calibration signals from dedicated DLLs (DDR_DLL) opposite sides device. Each compensates delays half device shown Figure 2-30. loop compensated temperature, voltage process variations system clock feedback loop. Figure 2-30. Edge Clock, Calibration Local Distribution
Spans PIOs Left Right Sides
Bank Bank
ECLK1 ECLK2 Bank Bank Input
DDR_DLL (Left) DDR_DLL (Right)
Delayed Polarity Control Bank DQSXFER Delay Control
Spans PIOs Bottom Sides
Bank
Bank
Bank
2-32
Lattice Semiconductor
Figure 2-31. Local
CLK1 ECLK2 ECLK1 Polarity control
Architecture LatticeXP2 Family Data Sheet
DCNTL[6:0]
DQSXFER
DQSXFER Output Register Block Input Register Block CLK1 Reg.
sysIO Buffer
Datain
Sync Reg.
Polarity Control Logic DQSDEL Calibration from DCNTL[6:0]
sysIO Buffer
Strobe
ECLK1 DQSXFER DQSXFERDEL*
DCNTL[6:0]
*DQSXFERDEL shifts ECLK1 associated with particular PIO.
Polarity Control Logic
typical memory interface design, phase relationship between incoming delayed strobe internal system clock (during READ cycle) unknown. LatticeXP2 family contains dedicated circuits transfer data between these domains. prevent set-up hold violations, domain transfer between (delayed) system clock, clock polarity selector used. This changes edge which data registered synchronizing registers input register block requires evaluation start each READ cycle correct clock polarity. Prior READ operation memories, tristate (pulled termination). memory device drives start preamble state. dedicated circuit detects this transition. This signal used control polarity clock synchronizing registers.
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Lattice Semiconductor DQSXFER
Architecture LatticeXP2 Family Data Sheet
LatticeXP2 devices provide DQSXFER signal output buffer assist data transfer memories that require strobe shifted 90o. This shifted strobe generated DQSDEL block. DQSXFER signal runs span data bus.
sysIO Buffer
Each associated with flexible buffer referred sysIO buffer. These buffers arranged around periphery device groups referred banks. sysIO buffers allow users implement wide variety standards that found today's systems including LVCMOS, SSTL, HSTL, LVDS LVPECL.
sysIO Buffer Banks
LatticeXP2 devices have eight sysIO buffer banks user I/Os arranged side. Each bank capable supporting multiple standards. Each sysIO bank supply voltage (VCCIO). addition, each bank voltage references, VREF1 VREF2, that allow completely independent from others. Figure 2-32 shows eight banks their associated supplies. LatticeXP2 devices, single-ended output buffers ratioed input buffers (LVTTL, LVCMOS PCI) powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 LVCMOS12 also fixed threshold inputs independent VCCIO. Each bank support separate VREF voltages, VREF1 VREF2, that threshold referenced input buffers. Some dedicated pins bank configured reference voltage supply pin. Each individually configurable based bank's supply reference voltages. Figure 2-32. LatticeXP2 Banks
CCIO0
REF1(0)
REF1(1)
REF2(1)
CCIO1
Bank
REF2(0)
CCIO2
Bank
CCIO7
Bank
REF1(7) REF2(7)
REF1(2) REF2(2)
Bank
RIGHT
LEFT
CCIO6
CCIO3
Bank
REF1(6) REF2(6)
REF1(3) REF2(3)
Bank
Bank
Bank
CCIO5 VREF1(5)
CCIO4 REF1(4)
REF2(5)
REF2(4)
BOTTOM
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Lattice Semiconductor
LatticeXP2 devices contain types sysIO buffer pairs.
Architecture LatticeXP2 Family Data Sheet
Bottom (Banks sysIO Buffer Pairs (Single-Ended Outputs Only) sysIO buffer pairs banks device consist single-ended output drivers sets single-ended input buffers (both ratioed referenced). referenced input buffers also configured differential input. pads pair described "true" "comp", where true associated with positive side differential input buffer comp (complementary) associated with negative side differential input buffer. Only I/Os bottom banks have programmable clamps. Left Right (Banks sysIO Buffer Pairs (50% Differential 100% Single-Ended Outputs) sysIO buffer pairs left right banks device consist single-ended output drivers, sets single-ended input buffers (both ratioed referenced) differential output driver. referenced input buffers also configured differential input. pads pair described "true" "comp", where true associated with positive side differential I/O, comp associated with negative side differential I/O. LVDS differential output drivers available buffer pairs left right banks.
Typical sysIO Behavior During Power-up
internal power-on-reset (POR) signal deactivated when VCCAUX have reached satisfactory levels. After signal deactivated, FPGA core logic becomes active. user's responsibility ensure that other VCCIO banks active with valid input logic levels properly control output logic states banks that critical application. more information controlling output logic state with valid input logic levels during power-up LatticeXP2 devices, please TN1136, LatticeXP2 sysIO Usage Guide. VCCAUX supply power FPGA core fabric, whereas VCCIO supplies power buffers. order simplify system design while providing consistent predictable behavior, recommended that buffers powered-up prior FPGA core fabric. VCCIO supplies should powered-up before together with VCCAUX supplies.
Supported sysIO Standards
LatticeXP2 sysIO buffer supports both single-ended differential standards. Single-ended standards further subdivided into LVCMOS, LVTTL other standards. buffers support LVTTL, LVCMOS 1.2V, 1.5V, 1.8V, 2.5V 3.3V standards. LVCMOS LVTTL modes, buffer individual configuration options drive strength, maintenance (weak pull-up, weak pull-down, bus-keeper latch) open drain. Other single-ended standards supported include SSTL HSTL. Differential standards supported include LVDS, MLVDS, BLVDS, LVPECL, RSDS, differential SSTL differential HSTL. Tables 2-13 2-14 show standards (together with their supply reference voltages) supported LatticeXP2 devices. further information utilizing sysIO buffer support variety standards please TN1136, LatticeXP2 sysIO Usage Guide.
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Lattice Semiconductor
Table 2-12. Supported Input Standards
Input Standard Single Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33 HSTL18 Class HSTL15 Class SSTL33 Class SSTL25 Class SSTL18 Class Differential Interfaces Differential SSTL18 Class Differential SSTL25 Class Differential SSTL33 Class Differential HSTL15 Class Differential HSTL18 Class LVDS, MLVDS, LVPECL, BLVDS, RSDS 0.75 1.25 VREF (Nom.)
Architecture LatticeXP2 Family Data Sheet
VCCIO1 (Nom.)
When specified, VCCIO anywhere valid operating range (page 3-1).
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Lattice Semiconductor
Table 2-13. Supported Output Standards
Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class HSTL15 Class SSTL33 Class SSTL25 Class SSTL18 Class Differential Interfaces Differential SSTL33, Class Differential SSTL25, Class Differential SSTL18, Class Differential HSTL18, Class Differential HSTL15, Class LVDS1, MLVDS1 BLVDS1 LVPECL1 RSDS
Architecture LatticeXP2 Family Data Sheet
Drive 4mA, 8mA, 12mA, 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA, 16mA, 20mA 4mA, 8mA, 12mA, 16mA 4mA, 2mA, 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA 4mA, 2mA, 4mA, 8mA, 12mA, 16mA, 20mA
VCCIO (Nom.)
LVCMOS33D1
Emulated with external resistors. more detail, please TN1138, LatticeXP2 High Speed Interface. left right edges, LVDS outputs supported with dedicated differential output driver I/Os. This solution does require external resistors driver.
Socketing
LatticeXP2 devices have been carefully designed ensure predictable behavior during power-up powerdown. Power supplies sequenced order. During power-up power-down sequences, I/Os remain tri-state until power supply voltage high enough ensure reliable operation. addition, leakage into pins controlled within specified limits. This allows easy integration with rest system. These capabilities make LatticeXP2 ideal many multiple power supply hot-swap applications.
IEEE 1149.1-Compliant Boundary Scan Testability
LatticeXP2 devices have boundary scan cells that accessed through IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing circuit board, which device mounted, through serial scan path that access critical logic nodes. Internal registers linked internally, allowing test data shifted
2-37
Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
loaded directly onto test nodes, test data captured shifted verification. test access port consists dedicated I/Os: TDI, TDO, TMS. test access port supply voltage VCCJ operate with LVCMOS3.3, 2.5, 1.8, standards. more information, please TN1141, LatticeXP2 sysCONFIG Usage Guide.
flexiFLASH Device Configuration
LatticeXP2 devices combine Flash SRAM single chip provide users with flexibility device programming configuration. Figure 2-33 provides overview arrangement Flash SRAM configuration cells within device. remainder this section provides overview these capabilities. TN1141, LatticeXP2 sysCONFIG Usage Guide, more detailed description. Figure 2-33. Overview Flash SRAM Configuration Cells Within LatticeXP2 Devices
Blocks Flash Memory
Massively Parallel Data Transfer Instant-ON Flash Single-Chip Solution
SRAM Configuration Bits
Blocks
FlashBAK Storage
Decryption Device Lock
Memory
Device Lock Design Security
JTAG
power-up, user command, data transferred from on-chip Flash memory SRAM configuration cells that control operation device. This done with massively parallel buses enabling parts operate within microseconds power supplies reaching valid levels; this capability referred Instant-On. on-chip Flash enables single-chip solution eliminating need external boot memory. This Flash programmed through either JTAG Slave ports device. SRAM configuration space also infinitely reconfigured through JTAG Master ports. JTAG port IEEE 1149.1 IEEE 1532 compliant. described section data sheet, FlashBAK capability parts enables contents blocks written back into Flash storage area without erasing reprogramming other aspects device configuration. Serial memory also available allow storage small amounts data such calibration coefficients error codes. applications where security important, lack external bitstream provides solution that inherently more secure than SRAM only FPGAs. This further enhanced device locking. device three modes:
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Lattice Semiconductor
Unlocked
Architecture LatticeXP2 Family Data Sheet
Locked Presenting through programming interface allows device unlocked. Permanently Locked device permanently locked. further complement security device Time Programmable (OTP) mode available. Once device this mode possible erase re-program Flash portion device.
Serial Memory
LatticeXP2 devices offer 3.3kbits Flash memory form Serial memory. memory area on-chip Flash that used non-volatile storage including electronic codes, version codes, date stamps, asset calibration settings. block diagram memory shown Figure 2-34. memory accessed same external Flash read programmed either through JTAG, external Slave Port, directly from FPGA logic. read memory, start address specified entire memory contents read sequentially first-in-first-out manner. memory independent Flash used device configuration given general-purpose storage functions always accessible regardless device security settings. more information, TN1137, LatticeXP2 Memory Usage Guide, TN1141, LatticeXP2 sysCONFIG Usage Guide. Figure 2-34. Serial Memory Diagram
External Slave Port JTAG FPGA Logic Data Shift Register External Slave Port JTAG FPGA Logic
Sequential Address Counter
Flash Flash Memory Array
Live Update Technology
Many applications require field updates FPGA. LatticeXP2 devices provide three features that enable this configuration done secure failsafe manner while minimizing impact system operation. Decryption Support LatticeXP2 devices provide on-chip, non-volatile storage support decryption 128-bit encrypted bitstream, securing designs deterring design piracy. TransFR (Transparent Field Reconfiguration) TransFR (TFR) unique Lattice technology that allows users update their logic field without interrupting system operation using single ispVM command. TransFR allows states frozen during device configuration. This allows device field updated with minimum system disruption downtime. more information please TN1143, LatticeXP2 TransFR I/O. Dual Boot Image Support Dual boot images supported applications requiring reliable remote updates configuration data system FPGA. After system running with basic configuration, boot image downloaded remotely stored separate location configuration storage device. time after update LatticeXP2 re-booted from this configuration file. there problem such corrupt data during download incorrect version number with this boot image, LatticeXP2 device revert back
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Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
original backup configuration again. This done without power cycling system. more information please TN1144, LatticeXP2 Dual Boot Usage Guide. more information device configuration, please TN1141, LatticeXP2 sysCONFIG Usage Guide.
Soft Error Detect (SED) Support
LatticeXP2 devices have dedicated logic perform Cyclic Redundancy Code (CRC) checks. During configuration, configuration data bitstream checked with logic block. addition, LatticeXP2 devices programmed checking soft errors SRAM. operation background during user mode (normal operation). event soft error occurs, device programmed either reload from known good boot image (from internal Flash external memory) generate error signal. further information support, please TN1130, LatticeXP2 Soft Error Detection (SED) Usage Guide.
On-Chip Oscillator
Every LatticeXP2 device internal CMOS oscillator that used derive Master Clock (CCLK) configuration. oscillator CCLK continuously available user logic after configuration complete. available CCLK frequencies listed Table 2-14. When different CCLK frequency selected during design process, following sequence takes place: Device powers with default CCLK frequency. During configuration, users select different CCLK frequency. CCLK frequency changes selected frequency after clock configuration bits received. This internal CMOS oscillator available user routing input clock clock tree. further information this oscillator configuration user mode, please TN1141, LatticeXP2 sysCONFIG Usage Guide. Table 2-14. Selectable CCLKs Oscillator Frequencies During Configuration User Mode
CCLK/Oscillator (MHz) 2.51 3.12 1633
Software default oscillator frequency. Software default CCLK frequency. Frequency valid CCLK.
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Lattice Semiconductor
Architecture LatticeXP2 Family Data Sheet
Density Shifting
LatticeXP2 family designed ensure that different density devices same family same package have same pinout. Furthermore, architecture ensures high success rate when performing design migration from lower density devices higher density devices. many cases, also possible shift lower utilization design targeted high-density device lower density device. However, exact details final resource utilization will impact likely success each case.
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LatticeXP2 Family Data Sheet Switching Characteristics
August 2008 Data Sheet DS1009
Absolute Maximum Ratings1,
Supply Voltage -0.5 1.32V Supply Voltage VCCAUX -0.5 3.75V Supply Voltage VCCJ -0.5 3.75V Supply Voltage VCCPLL4 -0.5 3.75V Output Supply Voltage VCCIO -0.5 3.75V Input Tristate Voltage Applied5 -0.5 3.75V Storage Temperature (Ambient) 150°C Junction Temperature Under Bias (Tj) +125°C
Stress above those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation device these other conditions above those indicated operational sections this specification implied. Compliance with Lattice Thermal Management document required. voltages referenced GND. VCCPLL only available csBGA, PQFP TQFP packages. Overshoot undershoot (VIHMAX volts permitted duration <20ns.
Recommended Operating Conditions
Symbol VCCAUX
Parameter Core Supply Voltage Auxiliary Supply Voltage Supply Voltage Driver Supply Voltage Supply Voltage IEEE 1149.1 Test Access Port Junction Temperature, Commercial Operation Junction Temperature, Industrial Operation
Min. 1.14 3.135 3.135 1.14 1.14
Max. 1.26 3.465 3.465 3.465 3.465
Units
VCCPLL1 VCCIO2, VCCJ2 tJCOM tJIND
VCCPLL only available csBGA, PQFP TQFP packages. VCCIO VCCJ 1.2V, they must connected same power supply VCC. VCCIO VCCJ 3.3V, they must connected same power supply VCCAUX. recommended voltages standard subsequent table. ensure proper behavior, VCCIO must turned same time earlier than VCCAUX.
On-Chip Flash Memory Specifications
Symbol NPROGCYC tRETENTION Parameter Flash Programming Cycles tRETENTION Flash Functional Programming Cycles Data Retention Max. 10,000 100,000 Units Cycles Years
2008 Lattice Semiconductor Corp. Lattice trademarks, registered trademarks, patents, disclaimers listed www.latticesemi.com/legal. other brand product names trademarks registered trademarks their respective holders. specifications information herein subject change without notice.
www.latticesemi.com
DS1009 Switching_01.6
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
Socketing Specifications1,
Symbol
Parameter Input Leakage Current
Condition (MAX.)
Min.
Typ.
Max. +/-1
Units
Insensitive sequence VCC, VCCAUX VCCIO. However, assumes monotonic rise/fall rates VCC, VCCAUX VCCIO. (MAX), VCCIO VCCIO (MAX) VCCAUX VCCAUX (MAX). additive IPU, IBH. LVCMOS LVTTL only.
Electrical Characteristics
Over Recommended Operating Conditions
Symbol IIL, IIH1 IBHLS IBHHS IBHLO IBHHO VBHT Parameter Input Leakage Active Pull-up Current Active Pull-down Current Condition VCCIO VCCIO (MAX) VCCIO (MAX) VCCIO Min. (MAX) VCCIO 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1.2V, (MAX) VCCIO 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1.2V, (MAX) Typ. Max. -150 -150 (MIN) Units
Hold Sustaining Current (MAX) Hold High Sustaining Current VCCIO Hold Overdrive Current VCCIO Hold High Overdrive Current VCCIO Hold Trip Points Capacitance2 Dedicated Input Capacitance
Input leakage current measured with configured input with output driver tri-stated. measured with output driver active. maintenance circuits disabled. 25oC, 1.0MHz.
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
Supply Current (Standby)1,
Over Recommended Operating Conditions
Symbol Parameter XP2-5 XP2-8 Core Power Supply Current XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 ICCAUX Auxiliary Power Supply Current6 XP2-17 XP2-30 XP2-40 ICCPLL ICCIO ICCJ
Device
Typical5 0.25
Units
Power Supply Current (per PLL) Bank Power Supply Current (per bank) VCCJ Power Supply Current
further information supply current, please TN1139, Power Estimation Management LatticeXP2 Devices. Assumes outputs tristated, inputs configured LVCMOS held VCCIO GND. Frequency 0MHz. Pattern represents "blank" configuration data file. 25oC, power supplies nominal voltage. fpBGA ftBGA packages PLLs connected powered from auxiliary power supply. these packages, actual auxiliary supply current ICCAUX ICCPLL. csBGA, PQFP TQFP packages PLLs powered independent auxiliary power supply.
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
Initialization Supply Current1,
Over Recommended Operating Conditions
Symbol Parameter Device XP2-5 XP2-8 Core Power Supply Current XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 ICCAUX Auxiliary Power Supply Current7 XP2-17 XP2-30 XP2-40 ICCPLL ICCIO ICCJ
Typical (25°C, Max. Supply)6
Units
Power Supply Current (per PLL) Bank Power Supply Current (per Bank) VCCJ Power Supply Current
further information supply current, please TN1139, Power Estimation Management LatticeXP2 Devices. Assumes outputs tristated, inputs configured LVCMOS held VCCIO GND. Frequency 0MHz. Does include additional current from bypass decoupling capacitor across supply. specific configuration pattern used that scales with size device; consists utilization, EBR, configuration. 25°C, power supplies nominal voltage. fpBGA ftBGA packages PLLs connected powered from auxiliary power supply. these packages, actual auxiliary supply current ICCAUX ICCPLL. csBGA, PQFP TQFP packages PLLs powered independent auxiliary power supply.
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
Programming Erase Flash Supply Current1,
Over Recommended Operating Conditions
Symbol Parameter XP2-5 XP2-8 Core Power Supply Current XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 ICCAUX Auxiliary Power Supply Current7 XP2-17 XP2-30 XP2-40 ICCPLL ICCIO ICCJ
Device
Typical (25°C, Max. Supply)6
Units
Power Supply Current (per PLL) Bank Power Supply Current (per Bank) VCCJ Power Supply Current8
further information supply current, please TN1139, Power Estimation Management LatticeXP2 Devices. Assumes outputs tristated, inputs configured LVCMOS held VCCIO GND. Frequency 0MHz (excludes dynamic power from FPGA operation). specific configuration pattern used that scales with size device; consists utilization, EBR, configuration. Bypass decoupling capacitor across supply. 25°C, power supplies nominal voltage. fpBGA ftBGA packages PLLs connected powered from auxiliary power supply. these packages, actual auxiliary supply current ICCAUX ICCPLL. csBGA, PQFP TQFP packages PLLs powered independent auxiliary power supply. When programming JTAG.
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
sysIO Recommended Operating Conditions
Over Recommended Operating Conditions
VCCIO Standard LVCMOS332 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS122 LVTTL332 PCI33 SSTL18_I SSTL18_II2 SSTL25_I2, SSTL25_II2 SSTL33_I2, SSTL33_II2 HSTL15_I2 HSTL18_I2, HSTL18_II2 LVDS252 MLVDS25 BLVDS25 RSDS1, SSTL18D_I SSTL18D_II2 SSTL25D_ SSTL25D_II2 SSTL33D_ SSTL33D_ HSTL15D_ HSTL18D_ HSTL18D_
VREF Max. 3.465 2.625 1.89 1.575 1.26 3.465 3.465 1.89 2.625 3.465 1.575 1.89 2.625 2.625 3.465 2.625 2.625 1.89 2.625 3.465 1.575 1.89 Min. 0.833 1.15 0.68 0.816 Typ. 1.25 0.75 Max. 0.969 1.35 1.08
Min. 3.135 2.375 1.71 1.425 1.14 3.135 3.135 1.71 2.375 3.135 1.425 1.71 2.375 2.375 3.135 2.375 2.375 1.71 2.375 3.135 1.425 1.71
Typ.
LVPECL331,
Inputs chip. Outputs implemented with addition external resistors. Input this standard does depend value VCCIO.
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
sysIO Single-Ended Electrical Characteristics
Over Recommended Operating Conditions
Input/Output Standard LVCMOS33 Min. -0.3 Max. Min. Max. Max. LVTTL33 -0.3 LVCMOS25 -0.3 LVCMOS18 -0.3 0.35 VCCIO 0.65 VCCIO LVCMOS15 LVCMOS12 PCI33 SSTL33_I SSTL33_II SSTL25_I SSTL25_II SSTL18_I SSTL18_II HSTL15_I HSTL18_I HSTL18_II -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.35 VCCIO 0.35 VCCIO VREF VREF VREF 0.18 VREF 0.18 0.65 VCCIO 0.65 VCCIO VREF VREF VREF 0.18 VREF 0.18 Min. VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO IOL1 (mA) 15.2 IOH1 (mA) -20, -16, -12, -0.1 -20, -16, -12, -0.1 -20, -16, -12, -0.1 -16, -12, -0.1 -0.1 -0.1 -0.5 -7.6 -15.2 -6.7
VCCIO VCCIO VCCIO 0.54 0.35 0.28 VCCIO VCCIO 0.62 VCCIO 0.43 VCCIO VCCIO 0.28 VCCIO VCCIO VCCIO
VREF 0.125 VREF 0.125 VREF 0.125 VREF 0.125 VREF VREF VREF VREF VREF VREF
average current drawn I/Os between connections, between last bank bank, shown logic signal connections table shall exceed 8mA, where number I/Os between bank connections between last bank bank.
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
sysIO Differential Electrical Characteristics
LVDS
Over Recommended Operating Conditions
Parameter VINP, VINM VTHD ISA,ISA ISAB Description Input Voltage Input Common Mode Voltage Differential Input Threshold Input Current Output High Voltage Output Voltage Output Voltage Differential Change Between High Output Voltage Offset Change Between Output Short Circuit Current Output Short Circuit Current Driver Outputs Shorted Ground Driver Outputs Shorted Each Other (VOP VOM)/2, Half Inputs Difference Between Inputs Power Power (VOP VOM), Test Conditions Min. 0.05 +/-100 0.9V 1.125 Typ. 1.38 1.03 1.20 Max. 2.35 +/-10 1.60 1.375 Units
Differential HSTL SSTL
Differential HSTL SSTL outputs implemented pair complementary single-ended outputs. allowable single-ended output classes (class class supported this mode. further information LVPECL, RSDS, MLVDS, BLVDS other differential interfaces please details additional technical information this data sheet.
LVDS25E
bottom sides LatticeXP2 devices support LVDS outputs emulated complementary LVCMOS outputs conjunction with parallel resistor across driver outputs. scheme shown Figure possible solution point-to-point signals. Figure 3-1. LVDS25E Output Termination Example
VCCIO 2.5V (±5%) RS=158 ohms (±1%)
VCCIO 2.5V (±5%) RS=158 ohms (±1%)
ohms (±1%)
ohms (±1%)
Transmission line, differential ON-chip OFF-chip OFF-chip ON-chip
Lattice Semiconductor
Table 3-1. LVDS25E Conditions
Parameter VCCIO ZOUT ZBACK Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage (after Output Voltage (after Output Differential Voltage (After Output Common Mode Voltage Back Impedance Output Current
Switching Characteristics LatticeXP2 Family Data Sheet
Typical 2.50 1.43 1.07 0.35 1.25 100.5 6.03
Units
LVCMOS33D
banks support emulated differential using LVCMOS33D type. This option, along with external resistor network, provides system designer flexibility place differential outputs bank with 3.3V VCCIO. default drive current LVCMOS33D output 12mA with option change device strength 4mA, 8mA, 16mA 20mA. Follow LVCMOS33 specifications characteristics LVCMOS33D.
Lattice Semiconductor BLVDS
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 devices support BLVDS standard. This standard emulated using complementary LVCMOS outputs conjunction with parallel external resistor across driver outputs. BLVDS intended when multi-drop bi-directional multi-point differential signaling required. scheme shown Figure possible solution bi-directional multi-point differential signals. Figure 3-2. BLVDS Multi-point Output Example
Heavily loaded backplane, effective ohms differential 2.5V
16mA
ohms
ohms
2.5V
16mA
45-90 ohms 2.5V
16mA
45-90 ohms
2.5V
16mA
ohms ohms
ohms
ohms
ohms
ohms
2.5V
16mA
2.5V
16mA
2.5V
16mA
2.5V
16mA
Table 3-2. BLVDS Conditions1 Over Recommended Operating Conditions
Typical Parameter VCCIO ZOUT RTLEFT RTRIGHT Description Output Driver Supply (+/- Driver Impedance Driver Series Resistor (+/- Driver Parallel Resistor (+/- Receiver Termination (+/- Output High Voltage (After Output Voltage (After Output Differential Voltage (After Output Common Mode Voltage Output Current 2.50 10.00 90.00 45.00 45.00 1.38 1.12 0.25 1.25 11.24 2.50 10.00 90.00 90.00 90.00 1.48 1.02 0.46 1.25 10.20 Units
input buffer, LVDS table.
3-10
Lattice Semiconductor LVPECL
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 devices support differential LVPECL standard. This standard emulated using complementary LVCMOS outputs conjunction with parallel resistor across driver outputs. LVPECL input standard supported LVDS differential input buffer. scheme shown Figure possible solution pointto-point signals. Figure 3-3. Differential LVPECL
VCCIO 3.3V (+/-5%) 16mA VCCIO 3.3V (+/-5%) 16mA On-chip Off-chip
93.1 ohms (+/-1%)
93.1 ohms (+/-1%)
ohms (+/-1%)
ohms (+/-1%)
Transmission line, differential Off-chip On-chip
Table 3-3. LVPECL Conditions1 Over Recommended Operating Conditions
Parameter VCCIO ZOUT ZBACK Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage (After Output Voltage (After Output Differential Voltage (After Output Common Mode Voltage Back Impedance Output Current Typical 3.30 2.05 1.25 0.80 1.65 100.5 12.11 Units
input buffer, LVDS table.
3-11
Lattice Semiconductor RSDS
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 devices support differential RSDS standard. This standard emulated using complementary LVCMOS outputs conjunction with parallel resistor across driver outputs. RSDS input standard supported LVDS differential input buffer. scheme shown Figure possible solution RSDS standard implementation. Resistor values Figure industry standard values resistors. Figure 3-4. RSDS (Reduced Swing Differential Standard)
VCCIO 2.5V (+/-5%) VCCIO 2.5V (+/-5%) On-chip Off-chip ohms (+/-1%) ohms (+/-1%) ohms (+/-1%)
ohms (+/-1%)
Transmission line, differential Off-chip On-chip
Table 3-4. RSDS Conditions1 Over Recommended Operating Conditions
Parameter VCCIO ZOUT ZBACK Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage (After Output Voltage (After Output Differential Voltage (After Output Common Mode Voltage Back Impedance Output Current Typical 2.50 1.35 1.15 0.20 1.25 101.5 3.66 Units
input buffer, LVDS table.
3-12
Lattice Semiconductor MLVDS
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 devices support differential MLVDS standard. This standard emulated using complementary LVCMOS outputs conjunction with parallel resistor across driver outputs. MLVDS input standard supported LVDS differential input buffer. scheme shown Figure possible solution MLVDS standard implementation. Resistor values Figure industry standard values resistors. Figure 3-5. MLVDS (Reduced Swing Differential Standard)
Heavily loaded backplace, effective Zo~50 ohms differential 2.5V 16mA ohms +/-1% ohms +/-1% 35ohms 35ohms 2.5V 16mA
2.5V 16mA
2.5V 16mA
35ohms 35ohms 35ohms 35ohms
35ohms 35ohms
2.5V 16mA 16mA 2.5V 16mA 2.5V 16mA 2.5V
Table 3-5. MLVDS Conditions1
Typical Parameter VCCIO ZOUT RTLEFT RTRIGHT Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage (After Output Voltage (After Output Differential Voltage (After Output Common Mode Voltage Output Current Zo=50 2.50 10.00 35.00 50.00 50.00 1.52 0.98 0.54 1.25 21.74 Zo=70 2.50 10.00 35.00 70.00 70.00 1.60 0.90 0.70 1.25 20.00 Units
input buffer, LVDS table.
further information LVPECL, RSDS, MLVDS, BLVDS other differential interfaces please details additional technical information this data sheet.
3-13
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
Typical Building Block Function Performance1
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Function Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 16:1 32:1 Timing Units
Register-to-Register Performance
Function Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 16:1 32:1 8-bit Adder 16-bit Adder 64-bit Adder 16-bit Counter 32-bit Counter 64-bit Counter 64-bit Accumulator Embedded Memory Functions 512x36 Single Port RAM, Output Registers 1024x18 True-Dual Port (Write Through Normal, Output Registers) 1024x18 True-Dual Port (Write Through Normal, Output Registers) Distributed Memory Functions 16x4 Pseudo-Dual Port (One PFU) 32x2 Pseudo-Dual Port 64x1 Pseudo-Dual Port Functions 18x18 Multiplier (All Registers) Multiplier (All Registers) 36x36 Multiply (All Registers) 18x18 Multiply/Accumulate (Input Output Registers) 18x18 Multiply-Add/Sub-Sum (All Registers) Timing Units
3-14
Lattice Semiconductor Register-to-Register Performance (Continued)
Function Functions 16-Tap Fully-Parallel Filter 1024-pt Matrix Multiplication
Switching Characteristics LatticeXP2 Family Data Sheet
Timing
Units
These timing numbers were generated using ispLEVER design tool. Exact performance vary with device, design tool version. tool uses internal parameters that have been characterized tested every device. Timing 0.12
Derating Timing Tables
Logic timing provided following sections this data sheet ispLEVER design tools worst case numbers operating range. Actual delays nominal temperature voltage best case process, much better than values given tables. ispLEVER design tool provide logic timing numbers particular temperature voltage.
3-15
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 External Switching Characteristics
Over Recommended Operating Conditions
Parameter Description Device XP2-5 XP2-8 Clock Output Output Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 Clock Data Setup Input Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 Clock Data Hold Input Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSU_DEL Clock Data Setup Input Register with Data Input Delay XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tH_DEL Clock Data Hold Input Register with Input Data Delay XP2-17 XP2-30 XP2-40 fMAX_IO Clock Frequency Register XP2-5 XP2-8 tCOE Clock Output Output Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSUE Clock Data Setup Input Register XP2-17 XP2-30 XP2-40 Min. 0.00 0.00 0.00 0.00 0.00 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 0.00 0.00 0.00 0.00 0.00 Max. 3.80 3.80 3.80 4.00 4.00 Min. 0.00 0.00 0.00 0.00 0.00 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 0.00 0.00 0.00 0.00 0.00 General Parameters (using Primary Clock without PLL)1 4.20 4.20 4.20 4.40 4.40 0.00 0.00 0.00 0.00 0.00 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 0.00 0.00 0.00 0.00 0.00 4.60 4.60 4.60 4.90 4.90 Max. Min. Max. Units
General Parameters (using Edge Clock without PLL)1 0.00 0.00 0.00 0.00 0.00 3.20 3.20 3.20 3.20 3.20 0.00 0.00 0.00 0.00 0.00 3.60 3.60 3.60 3.60 3.60 0.00 0.00 0.00 0.00 0.00 3.90 3.90 3.90 3.90 3.90
3-16
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 External Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter Description Device XP2-5 XP2-8 Clock Data Hold Input Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSU_DELE Clock Data Setup Input Register with Data Input Delay XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tH_DELE Clock Data Hold Input Register with Input Data Delay XP2-17 XP2-30 XP2-40 fMAX_IOE Clock Frequency Register XP2-5 XP2-8 tCOPLL Clock Output Output Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSUPLL Clock Data Setup Input Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tHPLL Clock Data Hold Input Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSU_DELPLL Clock Data Setup Input Register with Data Input Delay XP2-17 XP2-30 XP2-40 Min. 1.00 1.00 1.00 1.20 1.20 1.00 1.00 1.00 1.20 1.20 0.00 0.00 0.00 0.00 0.00 Max. Min. 1.30 1.30 1.30 1.60 1.60 1.30 1.30 1.30 1.60 1.60 0.00 0.00 0.00 0.00 0.00 Max. Min. 1.60 1.60 1.60 1.90 1.90 1.60 1.60 1.60 1.90 1.90 0.00 0.00 0.00 0.00 0.00 Max. Units
General Parameters (using Primary Clock with PLL)1 1.00 1.00 1.00 1.00 1.00 0.90 0.90 0.90 1.00 1.00 1.90 1.90 1.90 2.00 2.00 3.00 3.00 3.00 3.00 3.00 1.20 1.20 1.20 1.20 1.20 1.10 1.10 1.10 1.20 1.20 2.10 2.10 2.10 2.20 2.20 3.30 3.30 3.30 3.30 3.30 1.40 1.40 1.40 1.40 1.40 1.30 1.30 1.30 1.40 1.40 2.30 2.30 2.30 2.40 2.40 3.70 3.70 3.70 3.70 3.70
3-17
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 External Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter Description Device XP2-5 XP2-8 tH_DELPLL Clock Data Hold Input Register with Input Data Delay XP2-17 XP2-30 XP2-40 DDR2 DDR23 Parameters tDVADQ tDVEDQ tDQVBS tDQVAS fMAX_DDR fMAX_DDR2 Primary Clock fMAX_PRI tW_PRI tSKEW_PRI Frequency Primary Clock Tree Clock Pulse Width Primary Clock Primary Clock Skew Within Bank Frequency Edge Clock Clock Pulse Width Edge Clock Data Valid After (DDR Read) Data Hold After (DDR Read) Data Valid Before Data Valid After Clock Frequency Clock Frequency 0.71 0.25 0.25 0.29 0.71 0.25 0.25 0.29 0.71 0.25 0.25 0.29 Min. 0.00 0.00 0.00 0.00 0.00 Max. Min. 0.00 0.00 0.00 0.00 0.00 Max. Min. 0.00 0.00 0.00 0.00 0.00 Max. Units
Edge Clock (ECLK1 ECLK2) fMAX_ECLK tW_ECLK tSKEW_ECLK
Edge Clock Skew Within Edge Device
General timing numbers based LVCMOS 2.5, 12mA, load. timing numbers based SSTL25. DDR2 timing numbers based SSTL18. Timing 0.12
3-18
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 Internal Switching Characteristics1
Over Recommended Operating Conditions
Parameter Description LUT4 delay inputs output) LUT6 delay inputs output) Set/Reset output (Asynchronous) Clock (M0,M1) Input Setup Time Clock (M0,M1) Input Hold Time Clock input setup time Clock input hold time Clock delay, (D-type Register Configuration) Asynchronous reset recovery time Logic Asynchronous reset time Logic Clock Output Port) Data Setup Time Data Hold Time Address Setup Time Address Hold Time Write/Read Enable Setup Time Write/Read Enable Hold Time Input Buffer Delay (LVCMOS25) Output Buffer Delay (LVCMOS25) Input Register Setup Time (Data Before Clock) Input Register Hold Time (Data after Clock) Output Register Clock Output Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time Set/Reset Setup Time Set/Reset Hold Time Asynchronous reset recovery time Logic Min. Max. Min. PFU/PFF Logic Mode Timing tLUT4_PFU tLUT6_PFU tLSR_PFU tSUM_PFU tHM_PFU tSUD_PFU tHD_PFU tCK2Q_PFU tRSTREC_PFU tRST_PFU 0.154 -0.061 0.061 0.002 0.216 0.304 0.720 0.342 0.520 0.720 0.151 -0.057 0.077 0.003 0.238 0.399 0.769 0.363 0.634 0.769 0.148 -0.053 0.093 0.003 0.260 0.494 0.818 0.383 0.748 0.818 Max. Min. Max. Units
Dual Port Memory Mode Timing tCORAM_PFU tSUDATA_PFU tHDATA_PFU tSUADDR_PFU tHADDR_PFU tSUWREN_PFU tHWREN_PFU tIN_PIO tOUT_PIO -0.206 0.239 -0.294 0.295 -0.146 0.158 1.082 0.858 1.561 -0.240 0.275 -0.333 0.333 -0.169 0.182 1.267 0.766 1.403 -0.274 0.312 -0.371 0.371 -0.193 0.207 1.452 0.674 1.246
Input/Output Buffer Timing
IOLOGIC Input/Output Timing tSUI_PIO tHI_PIO tCOO_PIO tSUCE_PIO tHCE_PIO tSULSR_PIO tHLSR_PIO tRSTREC_PIO 0.583 0.062 0.032 -0.022 0.184 -0.080 0.228 0.608 0.893 0.322 0.037 -0.025 0.201 -0.086 0.247 0.661 1.201 0.482 0.041 -0.028 0.217 -0.093 0.266 0.715
3-19
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 Internal Switching Characteristics1 (Continued)
Over Recommended Operating Conditions
Parameter tRST_PIO tDEL Timing tCO_EBR tCOO_EBR tSUDATA_EBR tHDATA_EBR tSUADDR_EBR tHADDR_EBR tSUWREN_EBR tHWREN_EBR tSUCE_EBR tHCE_EBR tRSTO_EBR tSUBE_EBR tHBE_EBR tRSTREC_EBR tRST_EBR Clock (Read) Output from Address Data Clock (Write) Output from Output Register Setup Data Memory (Write Clk) Hold Data Memory (Write Clk) Setup Address Memory (Write Clk) Hold Address Memory (Write Clk) Setup Write/Read Enable Memory (Write/Read Clk) Hold Write/Read Enable Memory (Write/Read Clk) Clock Enable Setup Time Output Register (Read Clk) Clock Enable Hold Time Output Register (Read Clk) Reset Output Delay Time from Output Register (Asynchronous) Byte Enable Set-Up Time Output Register Byte Enable Hold Time Output Register Dynamic Delay Each Asynchronous reset recovery time Asynchronous reset time -0.167 0.194 -0.117 0.157 -0.135 0.158 0.144 -0.097 -0.117 0.157 0.233 2.774 0.360 1.156 1.156 -0.198 0.231 -0.137 0.182 -0.159 0.186 0.160 -0.113 -0.137 0.182 0.291 3.142 0.408 1.341 1.341 -0.229 0.267 -0.157 0.207 -0.182 0.214 0.176 -0.129 -0.157 0.207 0.347 3.510 0.456 1.526 1.526 Description Asynchronous reset time Logic Dynamic Delay Step Size Min. 0.035 Max. 0.386 0.035 Min. 0.035 Max. 0.419 0.035 Min. 0.035 Max. 0.452 0.035 Units
Parameters After RSTK De-assert, Recovery tRSTKREC_PLL Time Before Next Clock Edge Toggle K-divider Counter After De-assert, Recovery Time Before Next Clock Edge Toggle M-divider Counter (Applies M-Divider Portion Only2) Input Register Setup Time Input Register Hold Time Pipeline Register Setup Time 1.000 1.000 1.000
tRSTREC_PLL
1.000
1.000
1.000
Block Timing tSUI_DSP tHI_DSP tSUP_DSP 0.135 0.021 2.505 0.151 -0.006 2.784 0.166 -0.031 3.064
3-20
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 Internal Switching Characteristics1 (Continued)
Over Recommended Operating Conditions
Parameter tHP_DSP tSUO_DSP tHO_DSP tCOI_DSP
Max. 4.513 2.153 0.569 Min. -0.890 5.413 -1.604 -0.298 0.338 Max. 4.947 2.272 0.600 Min. -0.994 5.931 -1.770 -0.327 0.371
Max. 5.382 2.391 0.631 Units
Description Pipeline Register Hold Time Output Register Setup Time Output Register Hold Time Input Register Clock Output Time Pipeline Register Clock Output Time Output Register Clock Output Time AdSub Input Register Setup Time AdSub Input Register Hold Time
Min. -0.787 4.896 -1.439 -0.270 0.306
tCOP_DSP3 tCOO_DSP3 tSUADSUB tHADSUB
Internal parameters characterized, tested every device. resets counters PLL. These parameters include Adder Subtractor block path. Timing 0.12
3-21
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
Timing Diagrams
Figure 3-6. Read/Write Mode (Normal)
CLKA
tCO_EBR tCO_EBR tCO_EBR
Invalid Data
Note: Input data address registered positive edge clock output data appears after positive edge clock.
Figure 3-7. Read/Write Mode with Input Output Registers
CLKA
tCOO_EBR tCOO_EBR
(Regs)
Mem(n) data from previous read
output only updated during read cycle
3-22
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
Figure 3-8. Write Through Read/Write Port Input Registers Only)
CLKA
Three consecutive writes
tACCESS
tACCESS
tACCESS
tACCESS
Data from Prev Read Write
Note: Input data address registered positive edge clock output data appears after positive edge clock.
3-23
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 Family Timing Adders1,
Over Recommended Operating Conditions
Buffer Type Input Adjusters LVDS25 BLVDS25 MLVDS RSDS LVPECL33 HSTL18_I HSTL18_II HSTL18D_I HSTL18D_II HSTL15_I HSTL15D_I SSTL33_I SSTL33_II SSTL33D_I SSTL33D_II SSTL25_I SSTL25_II SSTL25D_I SSTL25D_II SSTL18_I SSTL18_II SSTL18D_I SSTL18D_II LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33 Output Adjusters LVDS25E LVDS25 BLVDS25 MLVDS RSDS LVPECL33 HSTL18_I HSTL18_II HSTL18D_I HSTL18D_II LVDS LVDS BLVDS MLVDS 2.54 RSDS 2.54 LVPECL 3.34 HSTL_18 class drive HSTL_18 class Differential HSTL class drive Differential HSTL class -0.25 -0.25 -0.28 -0.28 -0.25 -0.37 -0.17 -0.29 -0.17 -0.29 0.02 0.02 0.00 0.00 0.02 -0.10 0.13 0.00 0.13 0.00 0.30 0.30 0.28 0.28 0.30 0.18 0.43 0.29 0.43 0.29 LVDS BLVDS LVDS RSDS LVPECL HSTL_18 class HSTL_18 class Differential HSTL class Differential HSTL class HSTL_15 class Differential HSTL class SSTL_3 class SSTL_3 class Differential SSTL_3 class Differential SSTL_3 class SSTL_2 class SSTL_2 class Differential SSTL_2 class Differential SSTL_2 class SSTL_18 class SSTL_18 class Differential SSTL_18 class Differential SSTL_18 class LVTTL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS 3.3V -0.26 -0.26 -0.26 -0.26 -0.26 -0.23 -0.23 -0.28 -0.28 -0.23 -0.28 -0.20 -0.20 -0.27 -0.27 -0.21 -0.21 -0.27 -0.27 -0.23 -0.23 -0.28 -0.28 -0.09 -0.09 0.00 -0.23 -0.20 -0.35 -0.09 -0.11 -0.11 -0.11 -0.11 -0.11 -0.08 -0.08 -0.13 -0.13 -0.09 -0.13 -0.04 -0.04 -0.11 -0.11 -0.06 -0.06 -0.12 -0.12 -0.08 -0.08 -0.13 -0.13 0.05 0.05 0.00 -0.07 -0.02 -0.20 0.05 0.04 0.04 0.04 0.04 0.04 0.07 0.07 0.02 0.02 0.06 0.01 0.12 0.12 0.04 0.04 0.10 0.10 0.03 0.03 0.07 0.07 0.02 0.02 0.18 0.18 0.00 0.09 0.16 -0.04 0.18 Description Units
3-24
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 Family Timing Adders1, (Continued)
Over Recommended Operating Conditions
Buffer Type HSTL15_I HSTL15D_I SSTL33_I SSTL33_II SSTL33D_I SSTL33D_II SSTL25_I SSTL25_II SSTL25D_I SSTL25D_II SSTL18_I SSTL18_II SSTL18D_I SSTL18D_II LVTTL33_4mA LVTTL33_8mA LVTTL33_12mA LVTTL33_16mA LVTTL33_20mA LVCMOS33_4mA LVCMOS33_8mA LVCMOS33_12mA LVCMOS33_16mA LVCMOS33_20mA LVCMOS25_4mA LVCMOS25_8mA LVCMOS25_12mA LVCMOS25_16mA LVCMOS25_20mA LVCMOS18_4mA LVCMOS18_8mA LVCMOS18_12mA LVCMOS18_16mA LVCMOS15_4mA LVCMOS15_8mA LVCMOS12_2mA LVCMOS12_6mA LVCMOS33_4mA LVCMOS33_8mA LVCMOS33_12mA LVCMOS33_16mA LVCMOS33_20mA Description HSTL_15 class drive Differential HSTL class drive SSTL_3 class SSTL_3 class Differential SSTL_3 class Differential SSTL_3 class SSTL_2 class drive SSTL_2 class 16mA drive Differential SSTL_2 class drive Differential SSTL_2 class 16mA drive SSTL_1.8 class SSTL_1.8 class drive Differential SSTL_1.8 class Differential SSTL_1.8 class drive LVTTL drive LVTTL drive LVTTL 12mA drive LVTTL 16mA drive LVTTL 20mA drive LVCMOS drive, fast slew rate LVCMOS drive, fast slew rate LVCMOS 12mA drive, fast slew rate LVCMOS 16mA drive, fast slew rate LVCMOS 20mA drive, fast slew rate LVCMOS drive, fast slew rate LVCMOS drive, fast slew rate LVCMOS 12mA drive, fast slew rate LVCMOS 16mA drive, fast slew rate LVCMOS 20mA drive, fast slew rate LVCMOS drive, fast slew rate LVCMOS drive, fast slew rate LVCMOS 12mA drive, fast slew rate LVCMOS 16mA drive, fast slew rate LVCMOS drive, fast slew rate LVCMOS drive, fast slew rate LVCMOS drive, fast slew rate LVCMOS drive, fast slew rate LVCMOS drive, slow slew rate LVCMOS drive, slow slew rate LVCMOS 12mA drive, slow slew rate LVCMOS 16mA drive, slow slew rate LVCMOS 20mA drive, slow slew rate 0.32 0.32 -0.25 -0.31 -0.25 -0.31 -0.25 -0.28 -0.25 -0.28 -0.17 -0.18 -0.17 -0.18 -0.37 -0.45 -0.52 -0.43 -0.46 -0.37 -0.45 -0.52 -0.43 -0.46 -0.42 -0.48 0.00 -0.45 -0.49 -0.46 -0.52 -0.56 -0.50 -0.45 -0.53 -0.46 -0.55 0.98 0.74 0.56 0.77 0.57 0.69 0.69 0.05 -0.02 0.05 -0.02 0.02 0.00 0.02 0.00 0.13 0.12 0.13 0.12 -0.05 -0.18 -0.24 -0.14 -0.18 -0.05 -0.18 -0.24 -0.14 -0.18 -0.15 -0.21 0.00 -0.18 -0.22 -0.18 -0.25 -0.30 -0.24 -0.17 -0.26 -0.19 -0.29 1.41 1.16 0.97 1.19 0.98 1.06 1.06 0.35 0.27 0.35 0.27 0.30 0.28 0.30 0.28 0.43 0.42 0.43 0.42 0.26 0.10 0.04 0.14 0.09 0.26 0.10 0.04 0.14 0.09 0.13 0.05 0.00 0.08 0.04 0.10 0.02 -0.03 0.03 0.11 0.00 0.08 -0.02 1.84 1.58 1.38 1.61 1.40 Units
3-25
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 Family Timing Adders1, (Continued)
Over Recommended Operating Conditions
Buffer Type LVCMOS25_4mA LVCMOS25_8mA LVCMOS25_12mA LVCMOS25_16mA LVCMOS25_20mA LVCMOS18_4mA LVCMOS18_8mA LVCMOS18_12mA LVCMOS18_16mA LVCMOS15_4mA LVCMOS15_8mA LVCMOS12_2mA LVCMOS12_6mA PCI33 Description LVCMOS drive, slow slew rate LVCMOS drive, slow slew rate LVCMOS 12mA drive, slow slew rate LVCMOS 16mA drive, slow slew rate LVCMOS 20mA drive, slow slew rate LVCMOS drive, slow slew rate LVCMOS drive, slow slew rate LVCMOS 12mA drive, slow slew rate LVCMOS 16mA drive, slow slew rate LVCMOS drive, slow slew rate LVCMOS drive, slow slew rate LVCMOS drive, slow slew rate LVCMOS drive, slow slew rate 3.3V 1.05 0.78 0.59 0.81 0.61 1.01 0.72 0.53 0.74 0.96 -0.53 0.90 -0.55 -0.29 1.43 1.15 0.96 1.18 0.98 1.38 1.08 0.90 1.11 1.33 -0.26 1.27 -0.29 -0.01 1.81 1.52 1.33 1.55 1.35 1.75 1.45 1.26 1.48 1.71 0.00 1.65 -0.02 0.26 Units
Timing Adders characterized tested every device. LVCMOS timing measured with load specified Switching Test Condition table. other standards tested according appropriate specifications. These timing adders measured with recommended resistor values. Timing 0.12
3-26
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
sysCLOCK Timing
Over Recommended Operating Conditions
Parameter fOUT fOUT2 fVCO fPFD tCPA
Description Input Clock Frequency (CLKI, CLKFB) Output Clock Frequency (CLKOP, CLKOS) K-Divider Output Frequency Frequency Phase Detector Input Frequency Output Clock Duty Cycle Coarse Phase Adjust Output Phase Accuracy CLKOK CLKOK2
Conditions
Min. 0.078
Typ.
Max. 217.5 ±125 0.025 ±240 ±200
Units UIPP
Characteristics Default duty cycle selected fOUT tOPJIT1 tOPW tLOCK2 tIPJIT tFBKDLY tRSTKW tRSTW Output Clock Period Jitter Input Clock Output Clock Skew Output Clock Pulse Width Lock-in Time Input Clock Period Jitter External Feedback Delay Input Clock High Time Input Clock Time Input Clock Rise/Fall Time Reset Signal Pulse Width (RSTK) Reset Signal Pulse Width (RST) fOUT fOUT integer 435MHz 25MHz
Jitter sample taken over 10,000 samples primary output with clean reference clock. Output clock valid after tLOCK reset dynamic delay adjustment. Using LVDS output buffers. Relative CLKOP. Timing 0.12
3-27
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
LatticeXP2 sysCONFIG Port Timing Specifications
Over Recommended Operating Conditions
Parameter tICFG tVMC tPRGMRJ tPRGM tDINIT tDPPINIT tDPPDONE tIODISS tIOENSS tMWC tCFGX tCSSPI tCSCCLK tSOCDO tCSPID fMAXSPI tSUSPI tHSPI fMAXSPIS tSTCO tSTOZ tSTSU tSTH tSTCKH tSTCKL tSTVO tSCS tSCSS tSCSH Description Minimum INITN High Time from tICFG valid Master CCLK PROGRAMN Pulse Rejection PROGRAMN Time Start Configuration PROGRAMN High INITN High Delay Delay Time from PROGRAMN INITN Delay Time from PROGRAMN DONE User Disable from PROGRAMN User Enabled Time from CCLK Edge During Wake-up Sequence Additional Wake Master Clock Signals after DONE High INITN High CCLK INITN High CSSPIN CCLK before CSSPIN CCLK Output Valid CSSPIN[0:1] First CCLK Edge Setup Time CCLK Frequency SOSPI Data Setup Time Before CCLK SOSPI Data Hold Time After CCLK Slave CCLK Frequency Rise Fall Time Falling Edge CCLK SOSPI Active Falling Edge CCLK SOSPI Disable Data Setup Time (SISPI) Data Hold Time (SISPI) CCLK Clock Pulse Width, High CCLK Clock Pulse Width, Falling Edge CCLK Valid SOSPI Output CSSPISN High Time CSSPISN Setup Time CSSPISN Hold Time 2cyc 0.02 0.02 600+6cyc Units cycles mV/ns sysCONFIG POR, Initialization Wake
sysCONFIG Port (Master)
sysCONFIG Port (Slave)
3-28
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
On-Chip Oscillator Configuration Master Clock Characteristics
Over Recommended Operating Conditions
Parameter Master Clock Frequency Duty Cycle
Timing 0.12
Min. Selected value -30%
Max. Selected value +30%
Units
Figure 3-9. Master Configuration Waveforms
Capture PROGRAMN DONE INITN Capture CFGx
CSSPIN CCLK SISPI SOSPI Opcode Address Ignore Valid Bitstream
3-29
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
Flash Download Time (from On-Chip Flash SRAM)
Over Recommended Operating Conditions
Symbol Parameter XP2-5 PROGRAMN Low-toHigh. Transition Done XP2-17 High. XP2-30 tREFRESH Power-up refresh when PROGRAMN pulled (VCC=VCC Min) XP2-40 XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 XP2-8 Min. Typ. Max. Units
Flash Program Time
Over Recommended Operating Conditions
Program Time Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 1.2M 2.0M 3.6M 6.0M 8.0M Flash Density Main Array Main Array Main Array Main Array Main Array Typ. Units
Flash Erase Time
Over Recommended Operating Conditions
Erase Time Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 1.2M 2.0M 3.6M 6.0M 8.0M Flash Density Main Array Main Array Main Array Main Array Main Array Typ. Units
3-30
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
FlashBAK Time (from Flash)
Over Recommended Operating Conditions
Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 Density (Bits) 166K 221K 276K 387K 885K Time (Typ.) Units
JTAG Port Timing Specifications
Over Recommended Operating Conditions
Symbol fMAX tBTCP tBTCPH tBTCPL tBTS tBTH tBTRF tBTCO tBTCODIS tBTCOEN tBTCRS tBTCRH tBUTCO tBTUODIS tBTUPOEN
Timing 0.12
Parameter Clock Frequency [BSCAN] clock pulse width [BSCAN] clock pulse width high [BSCAN] clock pulse width [BSCAN] setup time [BSCAN] hold time [BSCAN] rise/fall time controller falling edge clock valid output controller falling edge clock valid disable controller falling edge clock valid enable BSCAN test capture register setup time BSCAN test capture register hold time BSCAN test update register, falling edge clock valid output BSCAN test update register, falling edge clock valid disable BSCAN test update register, falling edge clock valid enable
Min.
Max.
Units mV/ns
3-31
Lattice Semiconductor
Figure 3-10. JTAG Port Timing Waveforms
Switching Characteristics LatticeXP2 Family Data Sheet
tBTS tBTCPH tBTCPL tBTH tBTCP
tBTCOEN Valid Data
tBTCO Valid Data
tBTCODIS
tBTCRS Data captured from tBTUPOEN Data driven
tBTCRH Data Captured
tBUTCO Valid Data
tBTUODIS Valid Data
3-32
Lattice Semiconductor
Switching Characteristics LatticeXP2 Family Data Sheet
Switching Test Conditions
Figure 3-11 shows output test load that used testing. specific values resistance, capacitance, voltage, other test conditions shown Table 3-6. Figure 3-11. Output Test Load, LVTTL LVCMOS Standards
Test
Includes Test Fixture Probe Capacitance
Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition Timing Ref. LVCMOS 1.5V LVCMOS VCCIO/2 LVTTL other LVCMOS settings VCCIO VCCIO
LVCMOS VCCIO/2 LVCMOS VCCIO/2 LVCMOS VCCIO/2
LVCMOS LVCMOS LVCMOS LVCMOS
VCCIO/2 VCCIO/2 0.10 0.10
Note: Output test conditions other interfaces determined respective standards.
3-33
LatticeXP2 Family Data Sheet Pinout Information
June 2008 Data Sheet DS1009
Signal Descriptions
Signal Name General Purpose [Edge] indicates edge device which located. Valid edge designations (Left), (Bottom), (Right), (Top). [Row/Column Number] indicates column device which exists. When Edge (Top) (Bottom), only need specify Number. When Edge (Left) (Right), only need specify Column Number. P[Edge] [Row/Column Number*]_[A/B] [A/B] indicates within which connected. Some these user-programmable pins shared with special function pins. These pins, when used special purpose pins, programmed I/Os user logic. During configuration user-programmable I/Os tri-stated with internal pull-up resistor enabled. used bonded package pin), also tri-stated with internal pull-up resistor enabled after configuration. GSRN VCCAUX VCCPLL VCCIOx VREF1_x, VREF2_x Global RESET signal (active low). GSRN. connect. Ground. Dedicated pins. Power supply pins core logic. Dedicated pins. Auxiliary power supply pin. This dedicated powers differential referenced input buffers. supply pins. csBGA, PQFP TQFP packages only. Dedicated power supply pins bank Reference supply pins bank Pre-determined pins each bank assigned VREF inputs. When used, they used pins. Power supply PLL: LLC, LRC, URC, ULC, from center. General Purpose (GPLL) input pads: LLC, LRC, URC, ULC, from center, true complement, index A,B,C.at each side. Optional feedback GPLL input pads: LLC, LRC, URC, ULC, from center, true complement, index A,B,C.at each side. Primary Clock pads, true complement, side, indexed bank 0,1,2,3 within bank. input pads: (Top), (Right), (Bottom), (Left), DQS, ball function number. configured output. Test Mode Select input, used control 1149.1 state machine. Pull-up enabled during configuration. Test Clock input pin, used clock 1149.1 state machine. pull-up enabled. Test Data pin. Used load data into device using 1149.1 state machine. After power-up, this port activated configuration sending appropriate command. (Note: once configuration port selected locked. Another configuration port cannot selected until power-up sequence). Pull-up enabled during configuration. Description
Clock Functions (Used user programmable pins when clock pins) [LOC][num]_VCCPLL [LOC][num]_GPLL[T, C]_IN_A [LOC][num]_GPLL[T, C]_FB_A PCLK[T, C]_[n:0]_[3:0] [LOC]DQS[num] Test Programming (Dedicated Pins)
2008 Lattice Semiconductor Corp. Lattice trademarks, registered trademarks, patents, disclaimers listed www.latticesemi.com/legal. other brand product names trademarks registered trademarks their respective holders. specifications information herein subject change without notice.
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Pinout Information_01.5
Lattice Semiconductor
Pinout Information LatticeXP2 Family Data Sheet
Signal Descriptions (Cont.)
Signal Name VCCJ Description Output pin. Test Data used shift data device using 1149.1. Power supply JTAG Test Access Port. Mode pins used specify configuration mode values latched rising edge INITN. During configuration, internal pull-up enabled. Open Drain pin. Indicates FPGA ready configured. During configuration, pull-up enabled. Initiates configuration sequence when asserted low. This always active pull-up. Open Drain pin. Indicates that configuration sequence complete, startup sequence progress. Configuration Clock configuring FPGA sysCONFIG mode. Input data slave mode Output data Master mode. Output data slave mode Input data Master mode. Chip select external Flash memory Master mode. This weak internal pull-up. Chip select Slave mode. This weak internal pull-up. Test Output Enable tristates pins when driven low. This weak internal pull-up, when used external pull-up recommended.
Configuration Pads (Used during sysCONFIG) CFG[1:0] INITN1 PROGRAMN DONE CCLK SISPI
SOSPI
CSSPIN
CSSPISN
actively driven, internal pull-up sufficient. external pull-up resistor 4.7k ohms recommended. When using device Master mode, must mutually exclusive from JTAG operations (i.e. tied GND) JTAG must free-running when used system JTAG test environment. Master mode used conjunction with JTAG download cable, device power cycle required after cable unplugged.
Lattice Semiconductor
Pinout Information LatticeXP2 Family Data Sheet
PICs Data (DQ) Pins Associated with Strobe (DQS)
PICs Associated with Strobe Within Strobe (DQS) Data (DQ) Pins [Edge]DQSn [Edge]DQSn Left Right Edges Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3]
Bottom Edges Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] P[Edge] [n+4]
Notes: number. interface designed memories that support strobe bits data left right edges bits data bottom edges. some packages, potential data (DQ) pins available. numbering definitions provided "Signal Names" column Signal Descriptions table.
Lattice Semiconductor
Pinout Information LatticeXP2 Family Data Sheet
Information Summary
XP2-5 Type Single Ended User Differential Pair User Normal Highspeed Configuration Muxed Dedicated Configuration Vccaux VCCPLL Bank0 Bank1 Bank2 VCCIO Bank3 Bank4 Bank5 Bank6 Bank7 GND, GND0-GND7 Bank0 Bank1 Bank2 Single Ended/ Differential Bank Bank3 Bank4 Bank5 Bank6 Bank7 Bank0 Bank1 Bank2 True LVDS Pairs Bank3 Bonding Bank4 Bank Bank5 Bank6 Bank7 Bank0 Bank1 Bank2 Banks Bank3 Bonding Bank4 Bank Bank5 Bank6 Bank7 Muxed Dedicated XP2-8 XP2-17 XP2-30 XP2-40 csBGA TQFP PQFP ftBGA csBGA TQFP PQFP ftBGA PQFP ftBGA fpBGA ftBGA fpBGA fpBGA fpBGA fpBGA 18/9 16/8 14/7 16/8 18/9 16/8 14/7 16/8 52/26 36/18 46/23 44/22 36/18 52/26 46/23 46/23 28/14 22/11 26/13 24/12 26/13 24/12 27/13 24/12 52/26 36/18 46/23 46/23 38/19 53/26 46/23 46/23 70/35 54/27 56/28 56/28 54/27 70/35 56/28 56/28 52/26 36/18 46/23 46/23 38/19 53/26 46/23 46/23 70/35 70/35 64/32 66/33 70/35 70/35 66/33 64/32
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