Supports Modes Maximum Clock Frequency Flexible, Uniform Erase Ar

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Supports Modes Maximum Clock Frequency Flexible, Uniform Erase Ar

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Single 2.3V 3.6V 2.7V 3.6V Supply Serial Peripheral Interface (SPI) Compatible
Supports Modes
Maximum Clock Frequency Flexible, Uniform Erase Architecture
4-Kbyte Blocks 32-Kbyte Blocks 64-Kbyte Blocks Full Chip Erase Individual Sector Protection with Global Protect/Unprotect Feature 16-Kbyte Sector 8-Kbyte Sectors 32-Kbyte Sector Seven 64-Kbyte Sectors Hardware Controlled Locking Protected Sectors Flexible Programming Options Byte/Page Program Bytes) Sequential Program Mode Capability Fast Program Erase Times Typical Page Program (256 Bytes) Time Typical 4-Kbyte Block Erase Time Typical 32-Kbyte Block Erase Time Typical 64-Kbyte Block Erase Time Automatic Checking Reporting Erase/Program Failures JEDEC Standard Manufacturer Device Read Methodology Power Dissipation Active Read Current (Typical) Deep Power-down Current (Typical) Endurance: 100,000 Program/Erase Cycles Data Retention: Years Complies with Full Industrial Temperature Range Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options 8-lead SOIC (150-mil 208-mil Wide) 8-pad Ultra Thin
4-megabit 2.3-volt 2.7-volt Minimum Serial Flash Memory AT25DF041A
Description
AT25DF041A serial interface Flash memory device designed wide variety high-volume consumer-based applications which program code shadowed from Flash memory into embedded external execution. flexible erase architecture AT25DF041A, with erase granularity small Kbytes, makes ideal data storage well, eliminating need additional data storage EEPROM devices.
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physical sectoring erase block sizes AT25DF041A have been optimized meet needs today's code data storage applications. optimizing size physical sectors erase blocks, memory space used much more efficiently. Because certain code modules data storage segments must reside themselves their protected sectors, wasted unused memory space that occurs with large sectored large block erase Flash memory devices greatly reduced. This increased memory space efficiency allows additional code routines data storage segments added while still maintaining same overall device density. AT25DF041A also offers sophisticated method protecting individual sectors against erroneous malicious program erase operations. providing ability individually protect unprotect sectors, system unprotect specific sector modify contents while keeping remaining sectors memory array securely protected. This useful applications where program code patched updated subroutine module basis, applications where data storage segments need modified without running risk errant modifications program code segments. addition individual sector protection capabilities, AT25DF041A incorporates Global Protect Global Unprotect features that allow entire memory array either protected unprotected once. This reduces overhead during manufacturing process since sectors have unprotected one-by-one prior initial programming. Specifically designed 2.5-volt 3-volt systems, AT25DF041A supports read, program, erase operations with supply voltage range 2.3V 3.6V 2.7V 3.6V. separate voltage required programming erasing.
AT25DF041A
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AT25DF041A
Descriptions Pinouts
Table 2-1.
Symbol
Descriptions
Name Function CHIP SELECT: Asserting selects device. When deasserted, device will deselected normally placed standby mode (not Deep Power-down mode), will high-impedance state. When device deselected, data will accepted pin. high-to-low transition required start operation, low-to-high transition required operation. When ending internally self-timed operation such program erase cycle, device will enter standby mode until completion operation. SERIAL CLOCK: This used provide clock device used control flow data from device. Command, address, input data present always latched rising edge SCK, while output data always clocked falling edge SCK. SERIAL INPUT: used shift data into device. used data input including command address sequences. Data always latched rising edge SCK. SERIAL OUTPUT: used shift data from device. Data always clocked falling edge SCK. WRITE PROTECT: controls hardware locking feature device. Please refer section "Protection Commands Features" page more details protection features pin. internally pulled-high left floating hardware-controlled protection will used. However, recommended that also externally connected whenever possible. HOLD: HOLD used temporarily pause serial communication without deselecting resetting device. While HOLD asserted, transitions data will ignored, will high-impedance state. must asserted, must state order Hold condition start. Hold condition pauses serial communication only does have effect internally self-timed operations such program erase cycle. Please refer section "Hold" page additional details Hold operation. HOLD internally pulled-high left floating Hold function will used. However, recommended that HOLD also externally connected whenever possible. DEVICE POWER SUPPLY: used supply source voltage device. Operations invalid voltages produce spurious results should attempted. GROUND: ground reference power supply. should connected system ground. Asserted State Type
Input
Input
Input
Output
Input
HOLD
Input
Power Power
Figure 2-1.
8-SOIC View
HOLD
Figure 2-2.
8-UDFN View
HOLD
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Block Diagram
CONTROL PROTECTION LOGIC
BUFFERS LATCHES
SRAM DATA BUFFER INTERFACE CONTROL LOGIC ADDRESS LATCH
Y-DECODER
Y-GATING
X-DECODER
FLASH MEMORY ARRAY
Memory Array
provide greatest flexibility, memory array AT25DF041A erased four levels granularity including full chip erase. addition, array been divided into physical sectors various sizes, which each sector individually protected from program erase operations. sizes physical sectors optimized both code data storage applications, allowing both code data segments reside their isolated regions. Figure page illustrates breakdown each erase level well breakdown each physical sector.
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Figure 4-1. Memory Architecture Diagram
Block Erase Detail
Internal Sectoring Sector Protection Function 64KB 32KB Block Erase Block Erase (D8h Command) (52h Command) Block Erase (20h Command) Block Address Range
Page Program Detail
1-256 Byte Page Program (02h Command) Page Address Range
16KB (Sector (Sector (Sector 32KB
64KB
32KB (Sector
32KB
32KB
32KB
32KB
64KB (Sector
64KB
32KB
00DF 00CF 00BF 00AF 009F 008F 007F 006F 005F 004F 003F 002F 001F 000F
000h 000h 00D000h 00C000h 00B000h 00A000h 009000h 008000h 007000h 006000h 005000h 004000h 003000h 002000h 001000h 000000h
Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes
64KB (Sector
64KB
07DF 07CF 07BF 07AF 079F 078F 077F 076F 075F 074F 073F 072F 071F 070F 06DF 06CF 06BF 06AF 069F 068F 067F 066F 065F 064F 063F 062F 061F 060F
000h 000h 07D000h 07C000h 07B000h 07A000h 079000h 078000h 077000h 076000h 075000h 074000h 073000h 072000h 071000h 070000h 000h 000h 06D000h 06C000h 06B000h 06A000h 069000h 068000h 067000h 066000h 065000h 064000h 063000h 062000h 061000h 060000h
Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes
D00h C00h B00h A00h 900h 800h 700h 600h 500h 400h 300h 200h 100h 000h D00h C00h B00h A00h 900h 800h
0017F 0016F 0015F 0014F 0013F 0012F 0011F 0010F 000F 000E 000DF 000CF 000BF 000AF 0009F 0008F 0007F 0006F 0005F 0004F 0003F 0002F 0001F 0000F
001700h 001600h 001500h 001400h 001300h 001200h 001100h 001000h 000F 000E 000D00h 000C00h 000B00h 000A00h 000900h 000800h 000700h 000600h 000500h 000400h 000300h 000200h 000100h 000000h
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Device Operation
AT25DF041A controlled instructions that sent from host controller, commonly referred Master. Master communicates with AT25DF041A which comprised four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), Serial Output (SO). protocol defines total four modes operation (mode with each mode differing respect polarity phase polarity phase control flow data bus. AT25DF041A supports most common modes, modes only difference between modes polarity signal when inactive state (when Master standby mode transferring data). With modes data always latched rising edge always output falling edge SCK. Figure 5-1.
Mode
Commands Addressing
valid instruction operation must always started first asserting pin. After been asserted, Master must then clock valid 8-bit opcode bus. Following opcode, instruction dependent information such address data bytes would then clocked Master. opcode, address, data bytes transferred with most significant (MSB) first. operation ended deasserting pin. Opcodes supported AT25DF041A will ignored device operation will started. device will continue ignore data presented until start next operation being deasserted then reasserted). addition, deasserted before complete opcode address information sent device, then operation will performed device will simply return idle state wait next operation. Addressing device requires total three bytes information sent, representing address bits Since upper address limit AT25DF041A memory array 07FFFFh, address bits always ignored device.
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Table 6-1.
Command Read Commands Read Array Read Array (Low Frequency) Program Erase Commands Block Erase Kbytes) Block Erase Kbytes) Block Erase Kbytes) Chip Erase Byte/Page Program Bytes) Sequential Program Mode Protection Commands Write Enable Write Disable Protect Sector Unprotect Sector Global Protect/Unprotect Read Sector Protection Registers Status Register Commands Read Status Register Write Status Register Miscellaneous Commands Read Manufacturer Device Deep Power-down Resume from Deep Power-down Note: 1001 1111 1011 1001 1010 1011 0000 0101 0000 0001 0000 0110 0000 0100 0011 0110 0011 1001 1010 1111 1100 0111 0000 0010 1010 1101
Command Listing
Opcode Address Bytes Dummy Bytes Data Bytes
0000 1011 0000 0011
0010 0000 0101 0010 1101 1000 0110 0000
0(1)
Write Status Register command 0011 1100
Three address bytes only required first operation designate address start programming Afterwards, internal address counter automatically increments, subsequent Sequential Program Mode operations only require clocking opcode data byte until Sequential Program Mode been exited.
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Read Commands
Read Array
Read Array command used sequentially read continuous stream data from device simply providing signal once initial starting address been specified. device incorporates internal address counter that automatically increments every clock cycle. opcodes, 03h, used Read Array command. each opcode depends maximum frequency that will used read data from device. opcode used frequency maximum specified fSCK. opcode used lower frequency read operations maximum specified fRDLF. perform Read Array operation, must first asserted appropriate opcode (0Bh 03h) must clocked into device. After opcode been clocked three address bytes must clocked specify starting address location first byte read within memory array. opcode used, then don't care byte must also clocked after three address bytes. After three address bytes (and don't care byte using opcode 0Bh) have been clocked additional clock cycles will result serial data being output pin. data always output with byte first. When last byte (07FFFFh) memory array been read, device will continue reading back beginning array (000000h). delays will incurred when wrapping around from array beginning array. Deasserting will terminate read operation into high-impedance state. deasserted time does require that full byte data read. Figure 7-1. Read Array Opcode
OPCODE ADDRESS BITS A23-A0
DON'T CARE
DATA BYTE
HIGH-IMPEDANCE
Figure 7-2.
Read Array Opcode
OPCODE ADDRESS BITS A23-A0
DATA BYTE
HIGH-IMPEDANCE
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Program Erase Commands
Byte/Page Program
Byte/Page Program command allows anywhere from single byte data bytes data programmed into previously erased memory locations. erased memory location that eight bits logical state byte value FFh). Before Byte/Page Program command started, Write Enable command must have been previously issued device (see "Write Enable" page command description) Write Enable Latch (WEL) Status Register logical state. perform Byte/Page Program command, opcode must clocked into device followed three address bytes denoting first byte location memory array begin programming After address bytes have been clocked data then clocked into device will stored internal buffer. starting memory address denoted does fall even 256-byte page boundary 0's), then special circumstances regarding which memory locations will programmed will apply. this situation, data that sent device that goes beyond page will wrap around back beginning same page. example, starting address denoted 0000FEh, three bytes data sent device, then first bytes data will programmed addresses 0000FEh 0000FFh while last byte data will programmed address 000000h. remaining bytes page (addresses 000001h through 0000FDh) will unaffected will change. addition, more than bytes data sent device, then only last bytes sent will latched into internal buffer. When deasserted, device will take data stored internal buffer program into appropriate memory array locations based starting address specified number data bytes sent device. less than bytes data were sent device, then remaining bytes within page will altered. programming data bytes internally self-timed should take place time tPP. three address bytes least complete byte data must clocked into device before deasserted, must deasserted even byte boundaries (multiples eight bits); otherwise, device will abort operation data will programmed into memory array. addition, address specified points memory location within sector that protected state (see section "Protect Sector" page 16), then Byte/Page Program command will executed, device will return idle state once been deasserted. Status Register will reset back logical state program cycle aborts incomplete address being sent, incomplete byte data being sent, because memory location programmed protected. While device programming, Status Register read will indicate that device busy. faster throughput, recommended that Status Register polled rather than waiting time determine data bytes have finished programming. some point before program cycle completes, Status Register will reset back logical state. device also incorporates intelligent programming algorithm that detect when byte location fails program properly. programming error arises, will indicated Status Register.
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Byte/Page Program mode default programming mode after device powers-up resumes from device reset. Figure 8-1. Byte Program
OPCODE ADDRESS BITS A23-A0
DATA
Figure 8-2. Page Program
HIGH-IMPEDANCE
OPCODE ADDRESS BITS A23-A0
DATA BYTE
DATA BYTE
HIGH-IMPEDANCE
Sequential Program Mode
Sequential Program Mode improves throughput over Byte/Page Program command when Byte/Page Program command used program single bytes only into consecutive address locations. example, some systems designed program only single byte information time cannot utilize buffered Page Program operation design restrictions. such case, system would normally have perform multiple Byte Program operations order program data into sequential memory locations. This approach considerable system overhead traffic. Sequential Programming Mode helps reduce system overhead traffic incorporating internal address counter that keeps track byte location program, thereby eliminating need supply address sequence device every byte program. When using Sequential Program mode, address locations programmed must erased state. Before Sequential Program mode first entered, Write Enable command must have been previously issued device Status Register logical state. start Sequential Program Mode, must first asserted, either opcode must clocked into device. first program cycle, three address bytes must clocked after opcode designate first byte location program. After address bytes have been clocked byte data programmed sent
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device. Deasserting will start internally self-timed program operation, byte data will programmed into memory location specified After first byte been successfully programmed, second byte programmed simply reasserting pin, clocking opcode, then clocking next byte data. When deasserted, second byte data will programmed into next sequential memory location. process would repeated additional bytes. There need reissue Write Enable command once Sequential Program Mode been entered. When last desired byte been programmed into memory array, Sequential Program Mode operation terminated reasserting sending Write Disable command device reset Status Register back logical state. more than byte data ever clocked during each program cycle, then only last byte data sent will stored internal latches. programming each byte internally self-timed should take place time tBP. each program cycle, complete byte data must clocked into device before deasserted, must deasserted even byte boundaries (multiples eight bits); otherwise, device will abort operation, byte data will programmed into memory array, Status Register will reset back logical state. address initially specified points memory location within sector that protected state, then Sequential Program Mode command will executed, device will return idle state once been deasserted. Status Register will also reset back logical state. There address wrapping when using Sequential Program Mode. Therefore, when last byte (07FFFFh) memory array been programmed, device will automatically exit Sequential Program mode reset Status Register back logical state. addition, Sequential Program mode will automatically skip over protected sectors; therefore, once highest unprotected memory location programming sequence been programmed, device will automatically exit Sequential Program mode reset Status Register. example, Sector protected Sector currently being programmed, once last byte Sector programmed, Sequential Program mode would automatically end. continue programming with Sector Sequential Program mode would have restarted supplying opcode, three address bytes, first byte Sector program. While device programming byte, Status Register read will indicate that device busy. faster throughput, recommended that Status Register polled each program cycle rather than waiting time determine byte finished programming before starting next Sequential Program mode cycle. device also incorporates intelligent programming algorithm that detect when byte location fails program properly. programming error arises, will indicated Status Register.
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Figure 8-3.
Sequential Program Mode Status Register Polling
Seqeuntial Program Mode Command Status Register Read Seqeuntial Program Mode Command Command A15-8 A7-0 Data
Opcode
Seqeuntial Program Mode Write Disable Command Command
Opcode
Opcode A23-16
Data
Data
First Address Program STATUS REGISTER DATA STATUS REGISTER DATA STATUS REGISTER DATA
HIGH-IMPEDANCE
Note: Each transition
shown represents byte bits)
Figure 8-4.
Sequential Program Mode Waiting Maximum Byte Program Time
Seqeuntial Program Mode Command Seqeuntial Program Mode Command A15-8 A7-0 Data
Opcode
Seqeuntial Program Mode Command
Opcode
Write Disable Command
Opcode A23-16
Data
Data
First Address Program
HIGH-IMPEDANCE
Note: Each transition
shown represents byte bits)
Block Erase
block Kbytes erased (all bits logical state) single operation using three different opcodes Block Erase command. opcode used 4-Kbyte erase, opcode used 32-Kbyte erase, opcode used 64-Kbyte erase. Before Block Erase command started, Write Enable command must have been previously issued device Status Register logical state. perform Block Erase, must first asserted appropriate opcode (20h, D8h) must clocked into device. After opcode been clocked three address bytes specifying address within 32-, 64-Kbyte block erased must clocked additional data clocked into device will ignored. When deasserted, device will erase appropriate block. erasing block internally selftimed should take place time tBLKE. Since Block Erase command erases region bytes, lower order address bits need decoded device. Therefore, 4-Kbyte erase, address bits will ignored device their values either logical "0". 32-Kbyte erase, address bits will ignored, 64-Kbyte erase, address bits will ignored device. Despite lower order address bits being decoded device, complete three address bytes must still clocked into device before deasserted, must deasserted even byte boundary (multiples eight bits); otherwise, device will abort operation erase operation will performed.
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AT25DF041A
address specified points memory location within sector that protected state, then Block Erase command will executed, device will return idle state once been deasserted. addition, with larger Block Erase sizes Kbytes, more than physical sector erased (e.g. sectors through time. Therefore, order erase larger block that span more than sector, sectors span must unprotected state. physical sectors within span protected state, then device will ignore Block Erase command will return idle state once deasserted. Status Register will reset back logical state erase cycle aborts incomplete address being sent because memory location within region erased protected. While device executing successful erase cycle, Status Register read will indicate that device busy. faster throughput, recommended that Status Register polled rather than waiting tBLKE time determine device finished erasing. some point before erase cycle completes, Status Register will reset back logical state. device also incorporates intelligent erase algorithm that detect when byte location fails erase properly. erase error occurs, will indicated Status Register. Figure 8-5. Block Erase
OPCODE ADDRESS BITS A23-A0
HIGH-IMPEDANCE
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Chip Erase
entire memory array erased single operation using Chip Erase command. Before Chip Erase command started, Write Enable command must have been previously issued device Status Register logical state. opcodes, C7h, used Chip Erase command. There difference device functionality when utilizing opcodes, they used interchangeably. perform Chip Erase, opcodes (60h C7h) must clocked into device. Since entire memory array erased, address bytes need clocked into device, data clocked after opcode will ignored. When deasserted, device will erase entire memory array. erasing device internally self-timed should take place time tCHPE. complete opcode must clocked into device before deasserted, must deasserted even byte boundary (multiples eight bits); otherwise, erase will performed. addition, sector memory array protected state, then Chip Erase command will executed, device will return idle state once been deasserted. Status Register will reset back logical state sector protected state. While device executing successful erase cycle, Status Register read will indicate that device busy. faster throughput, recommended that Status Register polled rather than waiting tCHPE time determine device finished erasing. some point before erase cycle completes, Status Register will reset back logical state. device also incorporates intelligent erase algorithm that detect when byte location fails erase properly. erase error occurs, will indicated Status Register. Figure 8-6. Chip Erase
OPCODE
HIGH-IMPEDANCE
AT25DF041A
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AT25DF041A
Protection Commands Write Enable
Write Enable command used Write Enable Latch (WEL) Status Register logical state. must before program, erase, Protect Sector, Unprotect Sector, Write Status Register command executed. This makes issuance these commands step process, thereby reducing chances command being accidentally erroneously executed. Status Register prior issuance these commands, then command will executed. issue Write Enable command, must first asserted opcode must clocked into device. address bytes need clocked into device, data clocked after opcode will ignored. When deasserted, Status Register will logical "1". complete opcode must clocked into device before deasserted, must deasserted even byte boundary (multiples eight bits); otherwise, device will abort operation state will change. Figure 9-1. Write Enable
OPCODE
HIGH-IMPEDANCE
Write Disable
Write Disable command used reset Write Enable Latch (WEL) Status Register logical state. With reset, program, erase, Protect Sector, Unprotect Sector, Write Status Register commands will executed. Write Disable command also used exit Sequential Program Mode. Other conditions also cause reset; more details, refer section Status Register description. issue Write Disable command, must first asserted opcode must clocked into device. address bytes need clocked into device, data clocked after opcode will ignored. When deasserted, Status Register will reset logical "0". complete opcode must clocked into device before deasserted, must deasserted even byte boundary (multiples eight bits); otherwise, device will abort operation state will change.
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Figure 9-2.
Write Disable
OPCODE
HIGH-IMPEDANCE
Protect Sector
Every physical sector device corresponding single-bit Sector Protection Register that used control software protection sector. Upon device power-up after device reset, each Sector Protection Register will default logical state indicating that sectors protected cannot programmed erased. Issuing Protect Sector command particular sector address will corresponding Sector Protection Register logical state. following table outlines states Sector Protection Registers. Table 9-1.
Value
Sector Protection Register Values
Sector Protection Status Sector unprotected programmed erased. Sector protected cannot programmed erased. This default state.
Before Protect Sector command issued, Write Enable command must have been previously issued Status Register logical "1". issue Protect Sector command, must first asserted opcode must clocked into device followed three address bytes designating address within sector locked. additional data clocked into device will ignored. When deasserted, Sector Protection Register corresponding physical sector addressed will logical state, sector itself will then protected from program erase operations. addition, Status Register will reset back logical state. complete three address bytes must clocked into device before deasserted, must deasserted even byte boundary (multiples eight bits); otherwise, device will abort operation, state Sector Protection Register will unchanged, Status Register will reset logical "0". safeguard against accidental erroneous protecting unprotecting sectors, Sector Protection Registers themselves locked from updates using SPRL (Sector Protection Registers Locked) Status Register (please refer Status Register description more details). Sector Protection Registers locked, then attempts issue Protect Sector command will ignored, device will reset Status Register back logical return idle state once been deasserted.
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AT25DF041A
Figure 9-3. Protect Sector
OPCODE ADDRESS BITS A23-A0
HIGH-IMPEDANCE
Unprotect Sector
Issuing Unprotect Sector command particular sector address will reset corresponding Sector Protection Register logical state (see Table Sector Protection Register values). Every physical sector device corresponding single-bit Sector Protection Register that used control software protection sector. Before Unprotect Sector command issued, Write Enable command must have been previously issued Status Register logical "1". issue Unprotect Sector command, must first asserted opcode must clocked into device. After opcode been clocked three address bytes designating address within sector unlocked must clocked additional data clocked into device after address bytes will ignored. When deasserted, Sector Protection Register corresponding sector addressed will reset logical state, sector itself will unprotected. addition, Status Register will reset back logical state. complete three address bytes must clocked into device before deasserted, must deasserted even byte boundary (multiples eight bits); otherwise, device will abort operation, state Sector Protection Register will unchanged, Status Register will reset logical "0". safeguard against accidental erroneous locking unlocking sectors, Sector Protection Registers themselves locked from updates using SPRL (Sector Protection Registers Locked) Status Register (please refer Status Register description more details). Sector Protection Registers locked, then attempts issue Unprotect Sector command will ignored, device will reset Status Register back logical return idle state once been deasserted. Figure 9-4. Unprotect Sector
OPCODE ADDRESS BITS A23-A0
HIGH-IMPEDANCE
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Global Protect/Unprotect
Global Protect Global Unprotect features work conjunction with Protect Sector Unprotect Sector functions. example, system globally protect entire memory array then Unprotect Sector command individually unprotect certain sectors individually reprotect them later using Protect Sector command. Likewise, system globally unprotect entire memory array then individually protect certain sectors needed. Performing Global Protect Global Unprotect accomplished writing certain combination data Status Register using Write Status Register command (see "Write Status Register" section page command execution details). Write Status Register command also used modify SPRL (Sector Protection Registers Locked) control hardware software locking. perform Global Protect, appropriate SPRL conditions must met, system must write logical bits Status Register. Conversely, perform Global Unprotect, same SPRL conditions must system must write logical bits Status Register. Table details conditions necessary Global Protect Global Unprotect performed.
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Table 9-2. Valid SPRL Global Protect/Unprotect Conditions
Write Status Register Data 76543210 0x0000xx 0x0001xx 0x1110xx 0x1111xx 1x0000xx 1x0001xx 1x1110xx 1x1111xx Global Unprotect Sector Protection Registers reset change current protection. change current protection. change current protection. Global Protect Sector Protection Registers Protection Operation Global Unprotect Sector Protection Registers reset change current protection. change current protection. change current protection. Global Protect Sector Protection Registers
State
Current SPRL Value
SPRL Value
change current protection level. sectors currently protected will remain protected sectors currently unprotected will remain unprotected. xxxxxxxx Sector Protection Registers hard-locked cannot changed when current state SPRL Therefore, Global Protect/Unprotect will occur. addition, SPRL cannot changed (the must HIGH order change SPRL back Global Unprotect Sector Protection Registers reset change current protection. change current protection. change current protection. Global Protect Sector Protection Registers Global Unprotect Sector Protection Registers reset change current protection. change current protection. change current protection. Global Protect Sector Protection Registers change current protection level. sectors currently protected will remain protected, sectors currently unprotected will remain unprotected. Sector Protection Registers soft-locked cannot changed when current state SPRL Therefore, Global Protect/Unprotect will occur. However, SPRL changed back from since HIGH. perform Global Protect/Unprotect, Write Status Register command must issued again after SPRL been changed from
0x0000xx 0x0001xx 0x1110xx 0x1111xx 1x0000xx 1x0001xx 1x1110xx 1x1111xx 0x0000xx 0x0001xx 0x1110xx 0x1111xx 1x0000xx 1x0001xx 1x1110xx 1x1111xx
Essentially, SPRL Status Register logical state (Sector Protection Registers locked), then writing Status Register will perform Global Unprotect without changing state SPRL bit. Similarly, writing Status Register will perform Global Protect keep SPRL logical state. SPRL can, course, changed logical writing software-locking hardware-locking desired along with Global Protect.
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desire only change SPRL without performing Global Protect Global Unprotect, then system simply write Status Register change SPRL from logical logical provided deasserted. Likewise, system write change SPRL from logical logical without affecting current sector protection status changes will made Sector Protection Registers). When writing Status Register, bits will actually modified will decoded device purposes Global Protect Global Unprotect functions. Only SPRL bit, will actually modified. Therefore, when reading Status Register, bits will reflect values written them will instead indicate status sector protection status. Please refer "Read Status Register" section Table 10-1 page details Status Register format what values read bits
Read Sector Protection Registers
Sector Protection Registers read determine current software protection status each sector. Reading Sector Protection Registers, however, will determine status pin. read Sector Protection Register particular sector, must first asserted opcode must clocked Once opcode been clocked three address bytes designating address within sector must clocked After last address byte been clocked device will begin outputting data during every subsequent clock cycle. data being output will repeating byte either denote value appropriate Sector Protection Register. Table 9-3.
Output Data
Read Sector Protection Register Output Data
Sector Protection Register Value Sector Protection Register value (sector unprotected). Sector Protection Register value (sector protected).
Deasserting will terminate read operation into high-impedance state. deasserted time does require that full byte data read. addition reading individual Sector Protection Registers, Software Protection Status (SWP) Status Register read determine all, some, none sectors software protected (refer "Status Register Commands" page more details). Figure 9-5. Read Sector Protection Register
OPCODE ADDRESS BITS A23-A0
DATA BYTE
HIGH-IMPEDANCE
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Protected States Write Protect (WP)
linked memory array itself direct effect protection status memory array. Instead, pin, conjunction with SPRL (Sector Protection Registers Locked) Status Register, used control hardware locking mechanism device. hardware locking active, conditions must must asserted SPRL must logical state. When hardware locking active, Sector Protection Registers locked SPRL itself also locked. Therefore, sectors that protected will locked protected state, sectors that unprotected will locked unprotected state. These states cannot changed long hardware locking active, Protect Sector, Unprotect Sector, Write Status Register commands will ignored. order modify protection status sector, must first deasserted, SPRL Status Register must reset back logical state using Write Status Register command. When resetting SPRL back logical "0", possible perform Global Protect Global Unprotect same time since Sector Protection Registers remain soft-locked until after Write Status Register command been executed. permanently connected GND, then once SPRL logical "1", only reset back logical state power-cycle reset device. This allows system power-up with sectors software protected hardware locked. Therefore, sectors unprotected protected needed then hardware locked later time simply setting SPRL Status Register. When deasserted, permanently connected VCC, SPRL Status Register still logical lock Sector Protection Registers. This provides software locking ability prevent erroneous Protect Sector Unprotect Sector commands from being processed. When changing SPRL logical from logical "0", also possible perform Global Protect Global Unprotect same time writing appropriate values into bits Status Register. Tables detail various protection locking states device. Table 9-4.
(Don't Care) Note: represents sector number
Sector Protection Register States
Sector Protection Register n(1) Sector n(1) Unprotected Protected
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Table 9-5.
Hardware Software Locking
Locking SPRL Change Allowed Sector Protection Registers Unlocked modifiable using Protect Unprotect Sector commands. Global Protect Unprotect also performed. Locked current state. Protect Unprotect Sector commands will ignored. Global Protect Unprotect cannot performed. Unlocked modifiable using Protect Unprotect Sector commands. Global Protect Unprotect also performed. Locked current state. Protect Unprotect Sector commands will ignored. Global Protect Unprotect cannot performed.
SPRL
modified from
Hardware Locked
Locked
modified from
Software Locked
modified from
AT25DF041A
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Status Register Commands
10.1 Read Status Register
Status Register read determine device's ready/busy status, well status many other functions such Hardware Locking Software Protection. Status Register read time, including during internally self-timed program erase operation. read Status Register, must first asserted opcode must clocked into device. After last opcode been clocked device will begin outputting Status Register data during every subsequent clock cycle. After last (bit Status Register been clocked out, sequence will repeat itself starting again with long remains asserted being pulsed. data Status Register constantly being updated, each repeating sequence will output data. Deasserting will terminate Read Status Register operation into high-impedance state. deasserted time does require that full byte data read. Table 10-1.
Bit(1) SPRL
Status Register Format
Name Sector Protection Registers Locked Type(2) Sector Protection Registers locked. Byte/Page Programming Mode (default). Sequential Programming Mode entered. Erase program operation successful. Erase program error detected. asserted. deasserted. sectors software unprotected (all Sector Protection Registers Some sectors software protected. Read individual Sector Protection Registers determine which sectors protected. Reserved future use. sectors software protected (all Sector Protection Registers default). Device write enabled (default). Device write enabled. Device ready. Device busy with internal operation. Description Sector Protection Registers unlocked (default).
Sequential Program Mode Status
Erase/Program Error
Write Protect (WP) Status
Software Protection Status Write Enable Latch Status Notes: RDY/BSY Ready/Busy Status Readable writable Readable only
Only Status Register will modified when using Write Status Register command.
3668D-DFLASH-9/08
10.1.1
SPRL SPRL used control whether Sector Protection Registers modified not. When SPRL logical state, Sector Protection Registers locked cannot modified with Protect Sector Unprotect Sector commands (the device will ignore these commands). addition, Global Protect Global Unprotect features cannot performed. sectors that presently protected will remain protected, sectors that presently unprotected will remain unprotected. When SPRL logical state, Sector Protection Registers unlocked modified (the Protect Sector Unprotect Sector commands, well Global Protect Global Unprotect features, will processed normal). SPRL defaults logical state after power-up device reset. SPRL modified freely whenever deasserted. However, asserted, then SPRL only changed from logical (Sector Protection Registers unlocked) logical (Sector Protection Registers locked). order reset SPRL back logical using Write Status Register command, will have first deasserted. SPRL only Status Register that user modified Write Status Register command.
10.1.2
indicates whether device Byte/Page Program mode Sequential Program Mode. default state after power-up device reset Byte/Page Program mode.
10.1.3
indicates whether last erase program operation completed successfully not. least byte during erase program operation erase program properly, then will logical state. will erase program operation aborts reason such attempt erase program protected region prior erase program operation. will updated after every erase program operation.
10.1.4
read determine been asserted not.
10.1.5
Bits bits provide feedback software protection status device. There three possible combinations bits that indicate whether none, some, sectors have been protected using Protect Sector command Global Protect feature. bits indicate that some sectors have been protected, then individual Sector Protection Registers read with Read Sector Protection Registers command determine which sectors fact protected.
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10.1.6 indicates current status internal Write Enable Latch. When logical state, device will accept program, erase, Protect Sector, Unprotect Sector, Write Status Register commands. defaults logical state after device power-up reset. addition, will reset logical state automatically under following conditions: Write Disable operation completes successfully Write Status Register operation completes successfully aborts Protect Sector operation completes successfully aborts Unprotect Sector operation completes successfully aborts Byte/Page Program operation completes successfully aborts Sequential Program Mode reaches highest unprotected memory location Sequential Program Mode reaches memory array Sequential Program Mode aborts Block Erase operation completes successfully aborts Chip Erase operation completes successfully aborts Hold condition aborts logical state, will reset logical operation aborts incomplete unrecognized opcode being clocked into device before deasserted. order reset when operation aborts prematurely, entire opcode program, erase, Protect Sector, Unprotect Sector, Write Status Register command must have been clocked into device. 10.1.7 RDY/BSY RDY/BSY used determine whether internal operation, such program erase, progress. poll RDY/BSY detect completion program erase cycle, Status Register data must continually clocked device until state RDY/BSY changes from logical logical "0". Figure 10-1. Read Status Register
OPCODE
STATUS REGISTER DATA
STATUS REGISTER DATA
HIGH-IMPEDANCE
3668D-DFLASH-9/08
10.2
Write Status Register
Write Status Register command used modify SPRL Status Register and/or perform Global Protect Global Unprotect operation. Before Write Status Register command issued, Write Enable command must have been previously issued Status Register logical "1". issue Write Status Register command, must first asserted opcode must clocked into device followed byte data. byte data consists SPRL value, don't care bit, four data bits denote whether Global Protect Unprotect should performed, additional don't care bits (see Table 10-2). additional data bytes that sent device will ignored. When deasserted, SPRL Status Register will modified, Status Register will reset back logical "0". values bits state SPRL before Write Status Register command executed (the prior state SPRL bit) will determine whether Global Protect Global Unprotect will perfomed. Please refer "Global Protect/Unprotect" section page more details. complete byte data must clocked into device before deasserted; otherwise, device will abort operation, state SPRL will change, potential Global Protect Unprotect will performed, Status Register will reset back logical state. asserted, then SPRL only logical "1". attempt made reset SPRL logical while asserted, then Write Status Register command will ignored, Status Register will reset back logical state. order reset SPRL logical "0", must deasserted. Table 10-2.
SPRL
Write Status Register Format
Global Protect/Unprotect
Figure 10-2. Write Status Register
OPCODE STATUS REGISTER
HIGH-IMPEDANCE
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Other Commands Functions
11.1 Read Manufacturer Device
Identification information read from device enable systems electronically query identify device while system. identification method command opcode comply with JEDEC standard "Manufacturer Device Read Methodology Compatible Serial Interface Memory Devices". type information that read from device includes JEDEC defined Manufacturer vendor specific Device vendor specific Extended Device Information. read identification information, must first asserted opcode must clocked into device. After opcode been clocked device will begin outputting identification data during subsequent clock cycles. first byte that will output will Manufacturer followed bytes Device information. fourth byte output will Extended Device Information String Length, which will indicating that Extended Device Information follows. After Extended Device Information String Length byte output, will into high-impedance state; therefore, additional clock cycles will have affect data will output. indicated JEDEC standard, reading Extended Device Information String Length subsequent data optional. Deasserting will terminate Manufacturer Device read operation into high-impedance state. deasserted time does require that full byte data read. Table 11-1. Manufacturer Device Information
Byte Data Type Manufacturer Device (Part Device (Part Extended Device Information String Length Value
Table 11-2.
Data Type Manufacturer
Manufacturer Device Details
Value Family Code Density Code Code Product Version Code Family Code: Density Code: (AT25/26DFxxx series) 00100 (4-Mbit) Details JEDEC Code: 0001 1111 (1Fh Atmel)
JEDEC Assigned Code
Device (Part
Device (Part
Code: (Standard series) Product Version: 00001 (First major revision)
3668D-DFLASH-9/08
Figure 11-1. Read Manufacturer Device
OPCODE
HIGH-IMPEDANCE
MANUFACTURER
DEVICE BYTE
DEVICE BYTE
EXTENDED DEVICE INFORMATION STRING LENGTH
Note: Each transition
shown represents byte bits)
11.2
Deep Power-down
During normal operation, device will placed standby mode consume less power long remains deasserted internal operation progress. Deep Power-down command offers ability place device into even lower power consumption state called Deep Power-down mode. When device Deep Power-down mode, commands including Read Status Register command will ignored with exception Resume from Deep Power-down command. Since commands will ignored, mode used extra protection mechanism against program erase operations. Entering Deep Power-down mode accomplished simply asserting pin, clocking opcode B9h, then deasserting pin. additional data clocked into device after opcode will ignored. When deasserted, device will enter Deep Power-down mode within maximum time tEDPD. complete opcode must clocked before deasserted, must deasserted even byte boundary (multiples eight bits); otherwise, device will abort operation return standby mode once deasserted. addition, device will default standby mode after power-cycle device reset.
Deep Power-down command will ignored internally self-timed operation such program erase cycle progress. Deep Power-down command must reissued after internally self-timed operation been completed order device enter Deep Power-down mode.
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AT25DF041A
Figure 11-2. Deep Power-down
tEDPD
OPCODE
HIGH-IMPEDANCE
Active Current
Standby Mode Current Deep Power-Down Mode Current
11.3
Resume from Deep Power-down
order exit Deep Power-down mode resume normal device operation, Resume from Deep Power-down command must issued. Resume from Deep Power-down command only command that device will recognize while Deep Power-down mode. resume from Deep Power-down mode, must first asserted opcode must clocked into device. additional data clocked into device after opcode will ignored. When deasserted, device will exit Deep Powerdown mode within maximum time tRDPD return standby mode. After device returned standby mode, normal command operations such Read Array resumed. complete opcode clocked before deasserted, deasserted even byte boundary (multiples eight bits), then device will abort operation return Deep Power-down mode. Figure 11-3. Resume from Deep Power-down
tRDPD
OPCODE
HIGH-IMPEDANCE
Active Current
Deep Power-Down Mode Current Standby Mode Current
3668D-DFLASH-9/08
11.4
Hold
HOLD used pause serial communication with device without having stop reset clock sequence. Hold mode, however, does have affect internally self-timed operations such program erase cycle. Therefore, erase cycle progress, asserting HOLD will pause operation, erase cycle will continue until finished. Hold mode only entered while asserted. Hold mode activated simply asserting HOLD during pulse. HOLD asserted during high pulse, then Hold mode won't started until beginning next pulse. device will remain Hold mode long HOLD asserted. While Hold mode, will high-impedance state. addition, both will ignored. pin, however, still asserted deasserted while Hold mode. Hold mode resume serial communication, HOLD must deasserted during pulse. HOLD deasserted during high pulse, then Hold mode won't until beginning next pulse. deasserted while HOLD still asserted, then operation that have been started will aborted, device will reset Status Register back logical state.
Figure 11-4. Hold Mode
HOLD
Hold
Hold
Hold
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Electrical Specifications
12.1 Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Temperature under Bias -55° +125° Storage Temperature -65° +150° Input Voltages (including Pins) with Respect Ground .-0.6V +4.1V Output Voltages with Respect Ground .-0.6V 0.5V
12.2
Operating Range
AT25DF041A (2.3V version) AT25DF041A -40° 2.7V 3.6V Ind. -40° 2.3V 3.6V
Operating Temperature (Case) Power Supply
12.3
Characteristics
Parameter Standby Current Deep Power-down Current Condition HOLD VCC, inputs CMOS levels HOLD VCC, inputs CMOS levels MHz; IOUT VIL, MHz; IOUT VIL, Units
Symbol IDPD
ICC1
Active Current, Read Operation
MHz; IOUT VIL, MHz; IOUT VIL, MHz; IOUT VIL,
ICC2 ICC3
Active Current, Program Operation Active Current, Erase Operation Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage
VCC, VCC, CMOS levels VOUT CMOS levels
-100 0.2V
3668D-DFLASH-9/08
12.4
Characteristics
AT25DF041A (2.3V version) AT25DF041A Units V/ns V/ns
Symbol fSCK fRDLF tSCKH tSCKL tSCKR
Parameter Serial Clock (SCK) Frequency Frequency Read Array (Low Frequency opcode) High Time Time Rise Time, Peak-to-Peak (Slew Rate) Fall Time, Peak-to-Peak (Slew Rate) Chip Select High Time Chip Select Setup Time (relative SCK) Chip Select Hold Time (relative SCK) Chip Select High Setup Time (relative SCK) Chip Select High Hold Time (relative SCK) Data Setup Time Data Hold Time Output Disable Time Output Valid Time Output Hold Time HOLD Setup Time (relative SCK) HOLD Hold Time (relative SCK) HOLD High Setup Time (relative SCK) HOLD High Hold Time (relative SCK) HOLD Output High-Z HOLD High Output Low-Z Write Protect Setup Time Write Protect Hold Time Sector Protect Time (from Chip Select High) Sector Unprotect Time (from Chip Select High) Chip Select High Deep Power-down Chip Select High Standby Mode
tSCKF(1) tCSH tCSLS tCSLH tCSHS tCSHH tDIS(1) tV(2) tHLS tHLH tHHS tHHH tHLQZ(1) tHHQX(1) tWPS(1)(3) tWPH
(1)(3)
tSECP(1) tSECUP(1) tEDPD(1) tRDPD(1) Notes:
100% tested (value guaranteed design characterization). load MHz, load MHz. Only applicable constraint Write Status Register command when SPRL
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12.5
tPP(1) tBLKE(1) tCHPE(1)(2) tWRSR Note:
Program Erase Characteristics
Parameter Page Program Time (256 Bytes) Byte Program Time Kbytes Block Erase Time Kbytes Kbytes Chip Erase Time Write Status Register Time Maximum values indicate worst-case performance after 100,000 erase/program cycles. 100% tested (value guaranteed design characterization). Units
Symbol
12.6
tVCSL tPUW VPOR
Power-up Conditions
Parameter Minimum Chip Select Time Power-up Device Delay Before Program Erase Allowed Power-on Reset Voltage Units
Symbol
12.7
Input Test Waveforms Measurement Levels
DRIVING LEVELS
(10% 90%)
2.4V 1.5V 0.45V
MEASUREMENT LEVEL
12.8
Output Test Load
DEVICE UNDER TEST
3668D-DFLASH-9/08
Waveforms
Figure 13-1. Serial Input Timing
tCSH
tCSLS tSCKH tCSLH tSCKL tCSHH tCSHS
HIGH-IMPEDANCE
Figure 13-2. Serial Output Timing
tSCKH tSCKL tDIS
Figure 13-3. HOLD Timing Serial Input
tHHH tHLS tHLH tHHS
HOLD
HIGH-IMPEDANCE
AT25DF041A
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AT25DF041A
Figure 13-4. HOLD Timing Serial Output
tHHH tHLS tHLH tHHS
HOLD
tHLQZ tHHQX
Figure 13-5. Timing Write Status Register Command When SPRL
tWPS tWPH
WRITE STATUS REGISTER OPCODE
WRITE STATUS REGISTER DATA BYTE
NEXT OPCODE
HIGH-IMPEDANCE
3668D-DFLASH-9/08
Ordering Information
14.1 Ordering Code Detail
SSHF
Atmel Designator Shipping Carrier Option
Bulk (tubes) Trays Tape reel
Product Family
Operating Voltage
Blank 2.7V minimum (2.7V 3.6V) 2.3V minimum (2.3V 3.6V)
Device Density
4-megabit
Device Grade
Green, NiPdAu lead finish, industrial temperature range (-40°C +85°C)
Interface
Serial
Package Option
8-pad, UDFN 8-lead, 0.150" wide SOIC 8-lead, 0.208" wide SOIC
Device Revision
14.2
Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code Package 8MA1 8MA1 NiPdAu 2.3V 3.6V NiPdAu 2.7V 3.6V Industrial (-40°C +85°C) Lead Finish Operating Voltage fSCK (MHz) Operation Range
AT25DF041A-MH-Y AT25DF041A-MH-T AT25DF041A-SSH-B AT25DF041A-SSH-T AT25DF041A-SH-B AT25DF041A-SH-T AT25DF041A-MHF-Y AT25DF041A-MHF-T AT25DF041A-SSHF-B AT25DF041A-SSHF-T Note:
shipping carrier option code marked devices.
Package Type 8MA1 8-pad, Body, Thermally Enhanced Plastic Ultra Thin Dual Flat Lead Package (UDFN) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
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AT25DF041A
Packaging Information
15.1 8MA1 UDFN
SIDE VIEW
VIEW
0.45
Notch (0.20 (Option Option
Chamfer 0.35)
COMMON DIMENSIONS (Unit Measure SYMBOL 0.45 0.00 0.35 0.55 0.02 0.40 0.152 4.90 3.80 5.90 3.20 5.00 4.00 6.00 3.40 1.27 0.50 0.00 0.20 0.60 0.75 0.08 5.10 4.20 6.10 3.60 0.60 0.05 0.48 NOTE
BOTTOM VIEW
4/15/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 8MA1, 8-pad Body), Thermally Enhanced Plastic Ultra Thin Dual Flat Lead Package (UDFN) DRAWING 8MA1 REV.
3668D-DFLASH-9/08
15.2
JEDEC SOIC
VIEW VIEW
SYMBOL COMMON DIMENSIONS (Unit Measure NOTE
0.10
0.25
SIDE VIEW
Note: These drawings general information only. Refer JEDEC Drawing MS-012, Variation proper dimensions, tolerances, datums, etc.
3/17/05 1150 Cheyenne Mtn. Blvd. Colorado Springs, 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING REV.
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15.3 EIAJ SOIC
VIEW
SYMBOL
VIEW
COMMON DIMENSIONS (Unit Measure NOTE
1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 1.27
2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85
SIDE VIEW
Notes:
This drawing general information only; refer EIAJ Drawing EDR-7320 additional information. Mismatch upper lower dies resin burrs aren't included. Determines true geometric position. Values apply plated terminal. standard thickness plating layer shall measure between 0.007 .021
Package Drawing Contact: packagedrawings@atmel.com
TITLE 8S2, 8-lead, 0.208" Body, Plastic Small Outline Package (EIAJ)
4/15/08 DRAWING REV.
3668D-DFLASH-9/08
Revision History
Revision Level Release Date March 2007 History Initial release. Changed part number ordering code reflect NiPdAu lead finish. Changed AT25DF041A-SSU AT25DF041A-SSH. Changed AT25DF041A-SU AT25DF041A-SH. Changed AT25DF041A-MU AT25DF041A-MH. Added lead finish details Ordering Information table. Added 2.3V 3.6V operating range. Changed 8M1-A package 8MA1 UDFN package. Added Ordering Code Detail. Updated 8MA1 UDFN package drawing with current revision (Rev. Removed "Preliminary" designation from datasheet Changed Deep Power-Down Current values Increased typical value from Increased maximum value from Updated Features section Changed tVCSL minimum from Changed VPOR maximum from 2.5V 2.2V
November 2007
March 2008
September 2008
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3668D-DFLASH-9/08
Headquarters
Atmel Corporation 2325 Orchard Parkway Jose, 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
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Product Contact
Site www.atmel.com Technical Support dataflash@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
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3668D-DFLASH-9/08

Supports Modes Maximum Clock Frequency Flexible, Uniform Erase Ar

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