Copyright 2003 Altera® Corporation Altera FPGA Stratix, APEX
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Cyclone
Copyright 2003 Altera® Corporation
Altera
FPGA Stratix, APEX APEX 20K, FLEX FPGA Cyclone ACEX FPGA Clock Data Recovery Stratix Mercury CPLD 7000 3000
FPGA
NiosTM, Excalibur-
Copyright 2003 Altera® Corporation
APEX 20KE FLEX 10KE
LE(1)
FLEX 6000
APEX 20KC
ACEX
Stratix
Next Generation FPGA
Cyclone
1998
1999
2000
2002
2003
2004
Copyright 2003 Altera® Corporation
Copyright 2003 Altera® Corporation
ACEX
ACEX
Cyclone
Device
Logic Elements 2,910 4000 5,980 12,060 20,060
Memory Bits
LVDS Maximum User Compatible Channels
EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
(-6,
Copyright 2003 Altera® Corporation
Cyclone
FLASH LVTTL, LVCMOS, SSTL-2 SSTL-3 66-MhZ, 32-bit (311 MbPS) LVDS Global Clock SDRAM (133 MhZ), FCRAM Single Data Rate (SDR) SDRAM
Copyright 2003 Altera® Corporation
Device 100-Pin TQFP
144-Pin TQFP
240-Pin PQFP
256-Pin FBGA
324-Pin FBGA
400-Pin FBGA
EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
EP1C4 LVDS: Mbps
Copyright 2003 Altera® Corporation
Cyclone
EP1C20F324C6 EP1C Altera Cyclone 20,000 Logic Elements (LEs) Fineline (1.0 Commercial, Industrial
Copyright 2003 Altera® Corporation
Cyclone Industrial
Device/ Package
EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
T100
T144
Q240
F256
F324
F400
Copyright 2003 Altera® Corporation
Cyclone Extended Temp
Degrees Device Ordered: -7I, Performance:
Device/Package
EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
T100
T144
Q240
F256
F324
F400
Copyright 2003 Altera® Corporation
Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
total 2,910 4000 5,980 12,060 20,060
Copyright 2003 Altera® Corporation
EP1C20
IOEs: LVDS Logic Array Blocks Block
Phase-Locked Loops (PLLs)
Side IOEs: LVDS,
Side Elements (IOEs): LVDS,
Bottom IOEs: LVDS
Copyright 2003 Altera® Corporation
Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
Rows
Columns
Copyright 2003 Altera® Corporation
Source Local interconnect Destination
Register Chain
Column
Direct Link
Block
Chain
Chain Register Chain Local interconnect Direct Link Block Column
Copyright 2003 Altera® Corporation
Cyclone
3.3-V, 32-bit, 66-MhZ JTAG (Slew-rate) Bus-hold User Mode
Copyright 2003 Altera® Corporation
Standard 3.3-V LVTTL LVCMOS 2.5-V LVTTL LVCMOS 1.8-V LVTTL LVCMOS 1.5-V LVCMOS SSTL-3 Class SSTL-2 Class LVDS Differential SSTL-2 Type Single-Ended Single-Ended Single-Ended Single-Ended Single-Ended Voltage Referenced Voltage Referenced Differential Differential Bank
clock (PLL_OUT).
Copyright 2003 Altera® Corporation
VCCIO VCCIO VREF
Copyright 2003 Altera® Corporation
Cyclone Multivolt
Copyright 2003 Altera® Corporation
Standard LVTTL (3.3 LVCMOS (3.3 LVTTL (2.5 LVTTL (1.8 LVTLL (1.5
IOH/IOL Current Strength Setting (mA)
Copyright 2003 Altera® Corporation
4,608 Bits True Dual-port Memory Simple Dual-port Memory Single-port Memory Shift Register FIFO Buffer
Copyright 2003 Altera® Corporation
4608
True Dual-Port Simple Dual-Port Single-Port FIFO Shift Register Mode
Copyright 2003 Altera® Corporation
Device
EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
Copyright 2003 Altera® Corporation
Columns
Blocks
total Bits
59,904 78,336 92,160 239,616 294,912
Simple Dual-Port
Read Port
4Kx1 2Kx2 1Kx4 512x8 256x16 128x32 512x9 256x18 128x36
Copyright 2003 Altera® Corporation
Write Port
4Kx1 2Kx2 1Kx4 512x8 256x16 128x32 512x9 256x18 128x36
True Dual-Port
Port
4Kx1 4Kx1 2Kx2 1Kx4 512x8 256x16 512x9 256x18 2Kx2
Port
1Kx4 512x8 256x16 512x9 256x18
Copyright 2003 Altera® Corporation
Global Clock Dedicated Clock Pins Dual Purpose Clock Pins DPCLK[7:0]
Copyright 2003 Altera® Corporation
Global Clock
Cyclone Device
Copyright 2003 Altera® Corporation
Cyclone
CLK0 LVDSCLK1p
Global Clock Network
CP/LF CP/LF
CLK1 LVDSCLK1n
Buffer
Phase Selection
Post-Scale Counter
Copyright 2003 Altera® Corporation
Cyclone Clock
Copyright 2003 Altera® Corporation
Cyclone
Parameter input Frequency Output Frequency Maximum input Jitter Standards Clock Feedback Specification 9.38 (Peak-to-Peak) LVTTL, PCI, LVDS, SSTL-2 SSTL-3 Zero Delay Buffer Mode Normal Feedback Mode Compensation Mode Supported
Programmable Phase Shifting
Copyright 2003 Altera® Corporation
Device EP1C3 EPC14 EP1C6 EP1C12 EP1C20
100-Pin TQFP
144-Pin TQFP
240-Pin PQFP
256-Pin FBGA
324-Pin FBGA
400-Pin FBGA
Does Support LVDS input External Output Does Support External Output Right
Copyright 2003 Altera® Corporation
Copyright 2003 Altera® Corporation
LVDS
311-MbPS SERDES
Cyclone Device
Receiving Device
Copyright 2003 Altera® Corporation
LVDS
Device
EP1C3 100-pin TQFP LVDS
Copyright 2003 Altera® Corporation
Active Serial (AS)
Cyclone FPGAs
EPCS1 EPCS4
FPGA EPCS1 EPCS4 (DCLK), Serial Data Output (DATA), Data input (ASDI) Chip Select (Ncs). DCLK Cyclone FPGA (14-20 MhZ) EPCS1 EPCS4 EP1C3 EP1C6 Cyclone
8-Pin SOIC
Copyright 2003 Altera® Corporation
EPCS1(4) Flash Byteblastertm Download Cable Altera Programming Unit (APU).
Copyright 2003 Altera® Corporation
Three Types Configuration Devices: Serial (EPCS1, EPCS4) Configuration (EPC2) Enhanced (EPC4, EPC8, EPC16)
Serial Enhanced Non-enhanced
Copyright 2003 Altera® Corporation
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