Enable/Disable control individual requests Four, independent channels

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Enable/Disable control individual requests Four, independent channels

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Enable/Disable control individual requests Four, independent channels Independent auto-initialization channels Memory-to-Memory transfers Memory block initialization Address increment decrement Directly expandable number channels process input terminating transfers Software requests Independent polarity control DREQ DACK signals C8237 developed synthesizes approximately 5,500 gates depending technology used. Functionality based Intel 8237
C8237
Programmable Controller Altera Core
C8237 Programmable Controller core (C8237 core) peripheral interface circuit microprocessor systems. core designed with external, 8-bit address latch. contains four independent channels expanded number channels cascading additional controller chips. Each channel full address word count capability.
Applications
C8237 core designed improve system performance allowing external devices directly transfer information from system memory.
Block Diagram
RESET READY IORNIN IOWNIN EOPNIN ADSTB EOPNOUT MEMRN MEMWN IORNOUT IOWNOUT HLDA
Decrementor Temp Word Count Timing Control
Incrementor/ Decrementor Temp Address
AOUT[7:0]
Channel-3
Channel-2
C8237REG
Channel-1 Channel-0
State Machine
Read/Write Current Word Count Register Write Base Word Count Register Base Word Address Register Current Word Address Register
DBOUT(7:0)
DREQ(3:0) DACK(3:0)
Fixed Priority Rotating Priority Logic
Command Register Mask Register Request Register Mode Register Status Register Temporary Register
DBIN(7:0)
AIN[3:0]
January 2008
Functional Description
C8237 core partitioned into modules shown block diagram described below: Timing Control generates internal timing external control signals C8237. timing Control block derives internal timing from clock input. C8237 operates major cycles, idle cycle (Si) Active cycle (S0, S4). Memoryto-memory transfers require read-from write-tomemory complete each transfer. requires eight states single transfer. first four states (S11, S12, S13, S14) used read-from -memory half last four states (S21, S22, S23, S24) write-to-memory half transfer. Each state composed full clock period. Fixed Priority Rotating Priority Logic Fixed Priority fixes channels priority order based upon descending value their number. lowest priority channel highest priority channel With Rotating Priority, last channel service becomes lowest priority channel with others rotating accordingly. C8237 Registers C8237 contains bits internal memory form registers. must when microprocessor attempting write read internal registers C8237. Command Register Write Command Register Command:
IORN IOWN
Bit4: Bit5:
Fixed priority Rotating priority Late write Extended write bit3
Bit6: Bit7:
DREQ sense active high DREQ sense active DACK sense active DACK sense active high
Mode Register Write Mode Register Command:
IORN IOWN
Each channel 6-bit Mode register. programmed microprocessor.
Bit1 Bit0: Channel Channel Channel Channel Bit3 Bit2: Verify transfer (pseudo transfer) Write transfer (from memory) Read transfer (from memory I/O) Illegal bits Bit4: Auto initialization disable Auto initialization enable Bit5: Address increment select Address decrement select Bit7 Bit6: Demand mode Single mode Block mode Cascade mode Demand Transfer Mode: device will continue making transfers until external EOPN encountered until DREQ goes inactive. Single Transfer Mode: device makes transfer only. DREQ must held active until DACK becomes active order recognized. Block Transfer Mode: device active DREQ software request continue making transfers during service until external EOPN encountered. DREQ need only held active until DACK becomes active. Cascade Transfer Mode: This mode used cascade more than C8237 together simple system expansion. ready input ignored this cascade transfer mode.
This 8-bit register controls operation C8237. programmed microprocessor cleared Reset Master Clear instruction.
Bit0: Bit1:
Memory-to-memory disable Memory-to-memory enable Channel address hold disable Channel address hold enable bit0
Bit2: Bit3:
Controller enable Controller disable Normal timing Compressed timing
Cast, Inc.
Request Register Write Request Register Command:
IORN IOWN
Programming Single Mask Register Bits: Write Single Mask Register Command:
IORN IOWN
Each channel request associated with 4-bit Request register. These non-maskable subject prioritization Priority Encoder. Each register reset separately under software control cleared upon generation external EOPN. entire register cleared Reset. order make software request, channel must Block Mode.
Bit0: Clear channel mask channel mask Bit1: Clear channel mask channel mask Bit2: Clear channel 2-mask channel mask Bit3: Clear channel 3-mask channel mask Status Register Read Status Register Command:
IORN IOWN
Bit1 Bit0: Channel Channel Channel Channel Bit2: Reset request request Mask Register Each channel mask associated with which disable incoming DREQ. Each mask when associated channel produces EOPN channel programmed Auto initialize. Each 4-bit Mask register also cleared separately under software control. entire register also Reset. This disables requests until clear Mask register instruction allows them occur. Programming Mask Register Bits: Write Mask Register Bits Command:
IORN IOWN
This register available read C8237 microprocessor. contains information about status devices this point. Bits when that channel reaches external EOPN applied. These bits cleared upon Reset each Status Read. Bits whenever their corresponding channel requesting.
Bit0: Channel reached Bit1: Channel reached Bit2: Channel reached Bit3: Channel reached Bit4: Channel request Bit5: Channel request Bit6: Channel request Bit7: Channel request
Bit1 Bit0: Channel Channel Channel Channel Bit2: Clear mask mask
Cast, Inc.
Temporary Register Read Temporary Register Command:
IORN IOWN
Word Count Address Register Command Codes Write IORN IOWN Read IORN IOWN
Register Base Current Address Base Current Word Count Base Current Address Base Current Word Count Base Current Address Base Current Word Count Base Current Address Base Current Word Count DB0-DB7 A0-A7 A8-A15 W0-W7 W8-W15 A0-A7 A8-A15 W0-W7 W8-W15 A0-A7 A8-A15 W0-W7 W8-W15 A0-A7 A8-A15 W0-W7 W8-W15
This register used hold data during memory-to-memory transfers. Following completion transfers, last word moved read microprocessor. temporary register cleared Reset.
Current Address Register Each channel 16-bit Current Address register. This register holds value address used during transfers. address automatically incremented decremented after each transfer intermediate values address stored Current Address register during transfer. This register written read microprocessor. Current Word Register Each channel 16-bit Current Word Count register. This register determines number transfers performed. word count decremented after each transfer. When value register goes from zero FFFFH, will generated. This register loaded read microprocessor Program Condition. Base Address Base Word Count Registers Each channel 16-bit Base Address 16-bit Base Word Count register. These registers store original value, which will loaded current registers during Auto initialize.
Software Commands These three commands depend specific pattern data bus. Clear First/Last Flip-Flop Command:
IORN IOWN
This command must executed prior writing reading address word count information C8237. Master Clear Command:
IORN IOWN
This command same effect hardware Reset. Command, Status, Request, Temporary, Internal First/Last Flip-Flop registers cleared Mask register set. C8237 will idle cycle. Clear Mask Register Command:
IORN IOWN
This command clears mask bits four channels, enabling them accept requests
Cast, Inc.
Temporary Word Count Register Decrementor) will decrement word count after each transfer. When value register goes from zero FFFFH, Terminal Count (TC) will generated. Temporary Address Register Incrementor/Decrementor) Base mode address, address will decremented incremented after each transfer. intermediate values address stored Current Address register during transfer.
Support
core delivered warranted against defects ninety days from purchase. Thirty days phone email technical support included, starting with first interaction. Additional maintenance support options available.
Verification
core been verified through extensive simulation rigorous code coverage measurements.
Deliverables
core includes everything required successful implementation: Encrypted Licenses Post-synthesis EDIF netlist Assignment Configuration Symbol file Include file Wrapper matching original device Vectors testbench Source Licenses VHDL Verilog source code Testbench Wrapper matching original device Vectors testbench Expected results testbench Simulation synthesis script
Implementation Results
following typical performance utilization results using variety Altera devices.
Supported Family Cyclone Stratix Stratix-II Device Tested EP1C20-6 EP1S20-5 EP2S60-3 1,007 1,007 Utilization Memory Memory bits Performance Fmax
CAST, Inc. Stonewall Court Woodcliff Lake, 076747 201-391-8300 201-391-8694 Copyright CAST, Inc. 2008, Rights Reserved. Contents subject change without notice. July 2003

Enable/Disable control individual requests Four, independent channels

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