16-bit levels instruction decoder Three levels instruction queue

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16-bit levels instruction decoder Three levels instruction queue

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Control Unit
16-bit levels instruction decoder Three levels instruction queue
C68000-AHB
32-bit Microprocessor Core
Implements powerful 32-bit microprocessor derived from Motorola MC68000 microprocessor. core uses AMBA-compatible master interface, making ideal processor solution low-cost, AHB-based System Chip (SoC) applications. C68000-AHB microcode-free design developed reuse ASIC FPGA implementations. design strictly synchronous without internal tri-states with synchronous reset. Scan insertion straightforward. Native On-Chip Debugging Support (OCDS) available option facilitate embedded processor debugging.
instructions address
modes
Supervisor User mode
Independent stack pointer each mode Eight 32-bit data address registers 16-bit status register Integer 32-bit packet Independent data address buses GB-address space 32-bit address 32-bit data RETRY, SPLIT, ERROR responses served Only NONSEQ access used locking instruction Parameterizable endianess Seven Priority Levels Virtually unlimited number interrupt sources Vectored auto-vectored interrupt modes 32-bit arithmetic logic operations Boolean manipulations 16-bit multiplication (sign unsigned) 16-bit division (sign unsigned)
Users registers
Data format
Memory interface Master
Applications
C68000-AHB suitable variety applications, including: 32-bit data processing applications High speed control systems Embedded microcontroller systems Professional audio video Sensor applications
Block Diagram
Registers
data registers
Interrupt Controller
Execution Unit
Chip Debug Support
OCDS Interface data
address registers
shifter
Interface
address handshake
Arithmetic-Logic Unit
special registers
Program Counter
acknowledge information halt reset
avect
Interrupt Control
Control Unit
Operation execution same
data address registers
Interface On-Chip Debug
solution (optional)
Optional module
March 2008
Functional Description
C68000-AHB core partitioned into modules shown block diagram described below.
Implementation Results
C68000-AHB reference designs have been evaluated variety technologies. following sample ASIC results obtained using synthesis with layout process considered, with only clock constrained shown.
Device 0.13 0.18 Area 23,459 gates 24,214 gates Speed
Control Unit
Decodes opcodes controls instruction data flow. Contains main processor sequencer control unit inner resources.
[MHz]
hclk [MHz]
Interrupt control
Provides seven priority levels interrupt calculates internal vector during auto-vector interrupt. also holds internal state interrupt exception level.
Support
core delivered warranted against defects ninety days from purchase. Thirty days phone email technical support included, starting with first interaction. Additional maintenance support options available.
Registers
Contains eight 32-bit wide data register, eight 32-bit wide address registers, 32-bit user stack pointer 16-bit status register.
Verification
C68000-AHB core's functionality verified means proprietary hardware modeler. same stimulus applied hardware model that contained original Motorola MC68000 chip, results compared with core's simulation outputs.
Execution unit
Contains unit arithmetic logic operations, shifter shift operations.
Program counter
program counter (PC) bits wide. This register incremented loaded control unit during instruction execution. Interface This interface unit implements functionality master. compliant with AMBA specification rev. supports 32-bit address data busses. responses (OK, RETRY, SPLIT, ERROR) served, only NONSEQ access type implemented. clock faster than clock, major influence CPU's performance. Both clocks must synchronous, clock equal clock divided ratios 1:1; 1:2; 1:3; etc. OCDS (optinal) This unit provides interface optional On-Chip Debug support through IEEE1149.1 (JTAG) port. unit provides following functions: Run/stop control Single-step mode Software breakpoint Debugger program execution Hardware breakpoints Read/Write Access every memory space
Deliverables
core available ASIC (synthesizable HDL) FPGA (netlist) forms, includes everything required successful implementation. Xilinx version includes: source code Sophisticated Testbench including arbiter., analyzer, configurable interrupt controller, RAM. Simulation script, vectors, expected results, comparison utility Synthesis script Comprehensive user documentation, including detailed specifications system integration guide
CAST, Inc. Stonewall Court Woodcliff Lake, 07677 201-391-8300 201-391-8694 Copyright CAST, Inc. 2008, Rights Reserved. Contents subject change without notice. Trademarks property their respective owners.
This core developed processor experts Evatronix

16-bit levels instruction decoder Three levels instruction queue

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