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TECHNICAL REFERENCE MANUAL Document Trident 4DWAVE-DX Techni


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4DWAVE-DX
TECHNICAL REFERENCE MANUAL
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Trident 4DWAVE-DX Technical Reference Manual
Trident Microsystems, Inc.
4DWAVE-DX
TECHNICAL REFERENCE MANUAL
Document
NOTICE information this document subject change, Company make changes product order improve reliability, design, function, without prior written notice. part this manual reproduced transmitted form means without written permission company. EVENT WILL COMPANY LIABLE SPECIAL INCIDENTAL CONSEQUENTIAL DAMAGES, WHETHER ARISING DIRECTLY INDIRECTLY, SUCH LOSS PROFIT GOOD WILL, THAT SUFFERED CONNECTION WITH PURCHASE THIS PRODUCT FROM BREACH REPRESENTATION WARRANTY. November 1997, LIMITED WARRANTY This product warranted against defects materials workmanship period year from date purchase. During warranty period, product which Company determines fails meet warrant will repaired Company's option, replaced charge. eligible warranty service, product must returned Company Company authorized service center, costs shipping prepaid. This warranty does cover results accident, abuse, neglect, contrary specifications instructions, repair modification anyone other than Company. COMPANY SPECIFICALLY DISCLAIMS OTHER EXPRESS, IMPLIED STATUTORY WARRANTIES, INCLUDING IMPLIED WARRANTIES FITNESS PARTICULAR PURPOSE MERCHANTABILITY. SUCH DISCLAIMER IMPLIED WARRANTY PERMITTED LAW, DURATION SUCH IMPLIED WARRANTIES LIMITED DAYS FROM DATE DELIVERY. SOME JURISDICTIONS ALLOW EXCLUSION IMPLIED WARRANTIES LIMITATIONS LONG IMPLIED WARRANTY LAST, EXCLUSION LIMITATION INCIDENTAL CONSEQUENTIAL DAMAGES, SUCH LIMITATIONS EXCLUSIONS APPLY YOU. THIS WARRANTY GIVES SPECIFIC LEGAL RIGHTS ALSO HAVE OTHER RIGHTS WHICH VARY FROM JURISDICTION JURISDICTION. Trident Microsystems, Inc. assumes responsibility circuit other than circuits embodied Trident Microsystems, Inc. product. LICENSE Company grants customer non-exclusive, non-transferable license software, any, accompanying this product internal single computer system. user make single copy software solely backup purposes; otherwise, copies made software part thereof. other license kind granted part product intellectual property therein. TRADEMARK ACKNOWLEDGMENTS 4DWAVE-DX Technical Reference Manual, TridentMicrosystems, Inc. 1997. rights reserved. Trident Microsystems, Inc. registered trademark Trident Microsystems, Inc. VirtualFM, VirtualGM, VirtualGS Trident trademark registrations progress. Direct3D, DirectX, DirectSound, DirectSound3D, DirectMusic, DirectInput trademarks Microsoft Corporation; Windows, Windows 3.1, Windows Windows Windows registered trademarks Microsoft Corporation. OPL3 registered trademark Yahama Corporation. SoundBlaster SoundBlaster trademarks Creative Labs, Inc. other product names trademarks property their respective owners. Copyright protection claimed includes forms matters copyright table material information allowed statutory judicial hereinafter granted, including without limitation, material generated from software programs which displayed screen such icons, screen display looks, etc. Reproduction disassembly embedded computer programs algorithms prohibited.
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Table Contents
INTRODUCTION ADVANCED DIRECTSOUNDACCELERATOR FEATURE HIGHLIGHTS 1.2.1 Advanced DirectSound Accelerator 1.2.2 High Quality Wavetable Synthesizer 1.2.3 Full Legacy Games Compatibility 1.2.4 High Quality Audio Support 1.2.5 Advanced Streaming Architecture. 1.2.6 Microsoft® 1.2.7 Extras 1.2.8 Software Support. 1.2.9 Power Management 1.2.10 Testability 1.2.11 Process 1.2.12 Package Ordering REFERENCE DOCUMENTS. INTERFACE LEGACY. VOICE BUFFER/STREAM BUFFER ADDRESS ENGINE ENVELOPE ENGINE MIXER RECORDING ENGINE INTERFACE ASSIGNMENT TABLE SIGNAL DESCRIPTION 3.1.1 Interface 3.1.2 Interface. 3.1.3 MIDI/Game Port 3.1.4 Test Logic. 3.1.5 Power 3.1.6 Forward-Compatible Signal Group. PHYSICAL DIMENSIONS (MM) CONFIGURATION SPACE 4.1.1 Configuration Registers Description. 4.1.1.1 Vendor (Offset 00h) 4.1.1.2 Device (Offset 02h). 4.1.1.3 Command (Offset 04h). 4.1.1.4 Status (Offset 06h)
SYSTEM ARCHITECTURE OVERVIEW.
PACKAGE ASSIGNMENTS.
ADDRESS REGISTER DESCRIPTION.
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4DWAVE-DX
TECHNICAL REFERENCE MANUAL
4.1.1.5 4.1.1.6 4.1.1.7 4.1.1.8 4.1.1.9 4.1.1.10 4.1.1.11 4.1.1.12 4.1.1.13 4.1.1.14 4.1.1.15 4.1.1.16 4.1.1.17 4.1.1.18 4.1.1.19 4.1.2
Document
Revision (Offset 08h). Class Code (Offset 10h). Cache Line Size (Offset 0Ch). Latency Timer (Offset 0Dh). Header Type (Offset 0Eh) BIST (Offset 0Fh) Base Address (Offset 10h) Memory Base Address (Offset 14h) Subsystem Vendor (Offset 2Ch). Subsystem (Offset 2Eh). Capabilities Pointer (Offset 34h) Interrupt Line (Offset 3Ch). Interrupt (Offset 3Dh) Minimum Grant (Offset 3Eh) Maximum Latency (Offset 3Fh).
Legacy Configuration Registers Description 4.1.2.1 Distributed Configuration (Offset 40h). 4.1.2.2 Legacy Base (Offset 44h). 4.1.2.3 Legacy (Offset 45h). 4.1.2.4 Legacy Control (Offset 46h) Power Management Configuration. 4.1.3.1 Capabilities (Offset 48h) 4.1.3.2 Next Item Pointer (Offset 49h). 4.1.3.3 Power Management Capabilities (Offset 4Ah) 4.1.3.4 Power Management Control/Status (Offset 4Ch). Interrupt Snooping Configuration 4.1.4.1 Interrupt Snooping Control (Offset 50h)
4.1.3
4.1.4
WAVE ENGINE CONTROL REGISTERS 4.2.1 Address Wave Register Space 4.2.2 Legacy Registers Mapping Wave Engine Registers 4.2.2.1 Legacy Registers Address Wave Register Space Mapping 4.2.2.2 Wave Engine Registers. 4.2.2.3 Channel-Specific Registers 4.2.2.4 Global Volume Control Bank Envelope Control Registers. LEGACY COMPATIBILITY 4.3.1 Compatibility. 4.3.2 Compatibility 4.3.3 Legacy Functions Compatibility. 4.3.3.1 SoundBlasterPro/16 OPL3 4.3.3.2 SoundBlasterPro/16 Mixer. 4.3.3.3 MIDI MPU-401 UART 4.3.3.4 Game Port 4.3.3.5 SoundBlasterDMA
SYSTEM TEST FUNCTIONS.
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TEST MODE GLOBAL TRISTATE TREE PARAMETERS 6.1.1 Core (3.3V Only) 6.1.2 Signaling Environment 6.1.3 3.3V Signaling Environment PARAMETERS 6.2.1 Clocks. 6.2.1.1 Clock 6.2.2 6.2.3 6.2.3 6.2.4 Signals. Resets 6.2.3.1 Reset Reset (Cold Warm). Signals.
AC/DC PARAMETERS
REFERENCE SCHEMATIC 4DWAVE-DX REFERENCE BOARD BILL MATERIALS (REVISED: APRIL 1998).
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Introduction
Advanced DirectSoundAccelerator
4DWAVE-DX advanced audio accelerator providing full legacy compatibility, wavetable synthesis, DirectMusicTM, DirectSoundTM, DirectSound3Don single chip high-performance, cost-sensitive consumer market. supports full SoundBlastercompatibility fully PC97/PC98 compliant. named 4DWAVE adds time dimension interactive positional audio wave streams. time element includes such effects processing adding Doppler, Chorus, Reverb effects positional audio wavetable streams. 4DWAVE-DX integrates 64-voice wavetable engine with voice effect processing capability. supports upcoming Microsoft® DirectMusicAPI fully compatible with Level (downloadable samples) specification. 4DWAVEDX optimized Microsoft® Windows® Windows® NTTM5.0 streaming architecture with re-routable endpoint support. 4DWAVE-DX integrates DirectX5 positional audio accelerator incorporating QSound® Labs' QSoft3Dtechnology. includes DirectSound3Dacceleration hardware (Interaural Time Difference), (Interaural Intensity Difference), Pan, Delay, Doppler hardware. VirtualFMTMand VirtualGStechnologies maintain SoundBlasterPro/16 games compatibility while improving gaming audio quality. 4DWAVE-DX utilizes Digital Enhanced Game Port, when coupled with DirectInputdriver, save overhead nominally required conventional analog game port. 4DWAVE-DX employs high precision 26-bit digital mixer, providing accurate 20-bit output higher than 90dB signal-to-noise ratio when used with high quality codec. 4DWAVE-DX designed with aggressive power management mind well. both ACPI-compliant Power Management Interface (PPMI)-compliant. With power 3.3V process space conscious LQFP package, 4DWAVE-DX well suited Notebook systems well. 4DWAVE-DX delivers impressive combination features performance end-users without burdening them price. combining Mastering DirectSoundacceleration, Hardware Wavetable synthesizer, Digital Enhanced Game Port, interactive positional audio acceleration through QSoft3DTM, 4DWAVE-DX provides system level performance enhancement over equivalent audio controller. delivers high performance, high quality audio, highend features with efficient power management single-chip space-efficient LQFP package. forward socket-compatible with future 4DWAVE family products. This document will briefly describe signals future products enable system designers accommodate future 4DWAVE family products with design, substantially simplifying future design testing efforts.
4DWAVE-DX
Interface
AC-Link
Wavetable DirectSound Accelerator
AC'97 Audio Codec
Game Port
MIDI Port
Figure 1-1. 4DWAVE-DX High Level System Block Diagram
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1.2.1
Feature Highlights
Advanced DirectSound Accelerator
2.1-compliant with Mastering optimized multiple streams operation On-chip voice cache minimizes bandwidth improvement over bandwidth utilization Hardware multi-channel digital mixer
1.2.2
High Quality Wavetable Synthesizer
voices polyphony wavetable synthesizer supports combinations wavetable samples formats Stereo/mono 8-/16-bits Signed/unsigned
channel volume envelope control, pitch shift, tremolo, vibrato channel effect processing effect volume control reverb, chorus echo Microsoft® DirectMusicsupport (upcoming) with unlimited downloadable samples system memory DLS1-compliant Downloadable Samples support
1.2.3
Full Legacy Games Compatibility
Legacy game audio support with SoundBlasterPro/16 compatibility Legacy support with DDMA-enabled standard (non-DDMA) chipsets VirtualFMenhances audio experience through real-time FM-to-wavetable conversion MPU-401 compatible UART external internal synthesis VirtualGSprovides General MIDI/GS command interpretation wavetable effect synthesis
1.2.4
High Quality Audio Support
quality audio with better equal 90dB signal-to-noise ratio using external high quality codec support with full duplex, independent sample rate converter audio recording playback On-chip sample rate converter ensures internal operation 48KHz High precision internal 26-bit digital mixer with 20-bit digital audio output
1.2.5
Advanced Streaming Architecture
Microsoft® Streaming architecture compliant "Re-routable endpoint" support Three stereo capture channels stereo recording channel through AC-link
1.2.6
Microsoft®
voices DirectSoundchannels DirectSound3Daccelerator with IID, ITD, Doppler effects positional audio buffers DirectSoundaccelerator volume, pan, pitch shift control streaming static buffers QSound® QSoft3DTM-based interactive positional audio accelerator DirectX5
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Extras
Fully Plug Play controller software Digital Enhanced Game port enables analog joystick emulate digital joystick performance using Trident- provided DirectInputdriver. This eliminates overhead wasted joystick polling. DirectXtimer video/audio synchronization Forward pin-compatible with next generation audio accelerators
1.2.8
Software Support
Complete DirectXdriver suite (DirectSound3DTM, DirectSoundTM, DirectMusicTM, DirectInputTM) Windows® Windows® 98/NT 5.0® Configuration, installation, diagnostics under real mode DOS, Windows® 95/Windows® Windows® 3.1, NT4.0, Windows® 98/NT5.0 configuration, installation, mixer program Mbytes General MIDI (GM)/General Sound (GS) compliant sample Library
1.2.9
Power Management
Desktop ACPI PPMI Compatible Software Controls Codec Power States
1.2.10 Testability
NAND Tree test mode Tri-state I/Os test mode Loop-back modes Diagnostics Mixer Channels captured
1.2.11 Process
Advanced 0.35um process power 3.3V (5V-safe) operation
1.2.12 Package Ordering
LQFP (14mm 14mm 1.4mm) Ordering Part Number 7700
Reference Documents
Local Specification, Revision 2.1, June 1995 ACPI Advanced Configuration Power Interface Specification, Revision PPMI Power Management Interface Specification, Revision 1.0, March 1997 OnNow Device Class Power Management Reference Specification, Audio Device Class V1.0 Audio Codec Component Specification, Revision 1.03, September 1996 8237A High Performance Programmable Controller, October 1987 "PCIway", Revision SoundBlaster Programming Information V0.90, January 1995 Developer SoundBlaster Series, Edition, October 1993
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System Architecture Overview
4DWAVE-DX 64-Voice Wavetable/DirectSoundAudio Accelerator. packaged 100-pin LQFP package targeted desktop space-constrained applications such notebook handheld computer design. shown Figure above, 4DWAVE-DX will interface serial communication with Codec Digitally Enhanced Game Port
MIDI port 4DWAVE family devices designed enable single driver support current future generation devices. This approach allows stable, maintainable code base. hardware/software combinations provide following acceleration functions: DirectSoundacceleration 64-voice Wavetable synthesis Chorus effects Reverb effects Synthesis VirtualFMtechnology General MIDI/GS command interpreter VirtualGMTM/VirtualGStechnology
positional audio effects Figure shows major functional blocks 4DWAVE-DX. following sections provide architectural descriptions each functional blocks.
LEGACY
VOICE STREAM BUFFER INTERFACE
ADDRESS ENGINE
MIXER INTERFACE
ENVELOPE ENGINE
RECORDING ENGINE
Figure 1-2. 4DWAVE-DX Functional Block Diagram
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Interface
4DWAVE-DX interface fully Plug-n-Play compliant. consists separate master slave controllers that operate independently. Both master slave engine support burst cycles. slave programmed accept both Memory (memory mapped I/O) cycles 4DWAVE-DX registers. 4DWAVE-DX register space mapped configuring Configuration registers Memory base addressing. legacy register space only accessible through cycles cannot remapped. 4DWAVE-DX uses single interrupt. interrupts combined together internally form this single interrupt signal. Internal registers must accessed determine nature interrupt. This function programmed differently device legacy emulation mode not. emulation legacy operation, device configured either Distributed (DDMA, spec.) mechanism Trident proprietary snooping mechanism depending whether system core logic supports Distributed not.
Legacy
4DWAVE-DX supports both SoundBlasterPro SoundBlaster16 register sets. This includes Adlib, OPL3, MPU-401, Game Port. When configured support legacy operation, device will respond cycles legacy address regions. integrates on-chip SoundBlastercompatible command interpreter. OPL3 MPU-401 compatibility handled Trident's VirtualFMand based hardware/software combination provide emulation synthesis General MIDI/GS command interpretation DOS. hardware provides registers reads writes legacy locations while software provides interpretation emulation. 4DWAVE-DX supports legacy analog game port Digitally Enhanced Game Port. When using with bundled DirectInputdriver, Digitally Enhanced Game Port allows dramatic reduction both traffic utilization removing requirement "I/O polling" joystick position. This save overhead; this substantially enhances game performance gaming experience. MIDI port supported with MPU-401 compatible UART. This port also used emulation mode (VirtualGMTM/VirtualGSTM) support synthesis mode games.
Voice Buffer/Stream Buffer
voice buffer/stream buffer used buffer data streams between accelerator engine system memory. stream buffer supports channels with Dword-deep buffer channel. stream buffer used for: playback streams audio effects, support three capture channels WDM, chorus, reverb effects.
Address Engine
address engine supports voice channels. Stereo/mono, 8-/16-bit, signed/unsigned formats supported. voices optimized DirectXTM/WDM audio streams. Each channel sample rate converted 48KHz. address engine performs sample address calculations including using channel specific sample rate conversion factor.
Envelope Engine
envelope engine controls channel volume. first channels, supports global volumes, per/channel volume, left-right PAN, chorus volume, reverb volume. first also includes volume slope buffers allow MIDI ADSR (Attack-Decay-Sustain-Release) curve performed. second channels support per/channel volume, left-right PAN, chorus volume, reverb volume. volume controls operate (decibels) attenuation. This allows attenuations simply summed before sending composite mixer.
Mixer
4DWAVE-DX digital mixer supports high-precision 26-bit accumulators three separate stereo channels. hi-resolution accumulation allows voices mixed (accumulated) without degradations such "clipping". mixer supports both 16-bit 20-bit audio outputs, when coupled with high quality codec, provide higher than 90dB signal-to-noise ratio.
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There separate mixer channel each main stereo out), reverb, chorus output. main mixer channel data buffered FIFO before being accessed interface. This allows device buffer several samples ahead substantially increases tolerance latency others delays caused other system events.
Recording Engine
recording engine records data samples from codec. data sampled 48KHz recorded 16-bit stereo format. This requires 4-bytes sample 192Kbytes second record data. recording channel also supports independent down sampling format conversion. down sampling, bandwidth memory space reduced. instance, voice function using 8-bit mono samples 8KHz uses only bytes second.
Interface
interface supports 5-pin AC'Link interface codec. interface operates fixed 48KHz sample rate. provides 20-bit stereo output playback supports 16-bit stereo input recording. interface also includes register that allows access external codec registers. power management cold warm fully supported.
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Package Assignments
Interface Interface MIDI/Game Port Interface Test Logic Power/Ground Forward-Compatible signal group
4DWAVE-DX packaged space-efficient LQFP package (14mm 14mm 1.4mm). 4DWAVE-DX pins classified into five functional categories forward-compatible category:
Assignment Table Signal Description
following legends used characteristics "Type" column Sections 3.1.1 3.1.6. Input Output Tri-state Power Ground Internal Pull-Up "I/O Buffer" columns Section 3.1.1 3.1.6 indicate various buffer/cells used 4DWAVE-DX. Table shows detailed buffer characteristics each buffer type used. Table 3-1. Detailed Buffer Characteristics
Cell IBUFT_5S BT8_5S BT8OD_5S BT10U_5S BDT4U_5S BDT6U_5S BDT10U_5S BDT10_5S V5SFPAD VDD5SPAD VSS5SPAD Pull-up Voltage Level (mA) (mA) Voltage safe safe safe safe safe safe safe safe 3.3V
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3.1.1
Interface
Signal Name AD[31:0] Type T/I/O Buffer BDT10_5S Signal Description AD[31:0] (Address-Data) 32-bit multiplexed address data bus. used transmit address during "command" phase used send receive data during "data" phase. C/BE[3:0]# (Command/Byte Enable) 4-bit multiplexed command byte enable bus. used transmit command during "command" phase used send receive active data byte enables during "data" phase. (Parity) even parity across AD[31:0] C/BE[3:0]#. generated clock after address data phases. current master (delayed clock) drives parity. FRAME# (Cycle Frame) driven current master active indicate beginning transaction. also held indicate that master desires multiple data transaction. TRDY# (Target Ready) driven current target active indicate ready complete current data phase. IRDY# (Initiator Ready) driven current master active indicate ready complete current data phase. STOP# (Stop) driven current target indicate that desires stop current transaction. DEVSEL# (Device Select) driven active addressed target indicate that target current transaction. IDSEL (Initialization Device Select) active high signal driven system logic select device during configuration transaction. SERR# (System Error) active signal that used signal system parity (data address) other system errors. PERR# (Parity Error) active signal that used signal system only data parity errors. REQ# (Request) active signal that driven master when needs request transaction. GNT# (Grant) active signal that driven system arbitration logic signal master that been granted bus. INTA# (Interrupt "A") asynchronous active signal used signal processor/OS event that requires handling.
Number(s) 85-87,89-93, 9799,2-6,20-24, 2729,31, 33-37, 3940 95,8,18,30
C/BE[3:0]#
T/I/O
BDT10_5S
T/I/O
BDT10_5S
FRAME#
T/I/O
BDT10_5S
TRDY#
T/I/O
BDT10_5S
IRDY#
T/I/O
BDT10_5S
STOP# DEVSEL#
T/I/O T/I/O
BDT10_5S BDT10_5S
IDSEL
IBUFT_5S
SERR#
BDT10_5S
PERR# REQ# GNT#
BDT10_5S BT8_5S IBUFT_5S
INTA#
BT8OD_5S
(Continued next page)
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Interface (Cont'd)
Number(s) Signal Name RST# Type Buffer IBUFTS_5S Signal Description
Document
RST# (Reset) reset signal. active signal. This signal asynchronous CLK. bring sequencer outputs known defined state. reset control AC_RESET# will also activated. (Clock) operation clock. This clock used reference transactions used audio engine operational clock.
IBUFT_5S
3.1.2
Interface
Signal Name AC_SYNC AC_BITCLK Type Buffer BDT6U_5S IBUFT_5S Signal Description AC_SYNC Sync) used fixed 48kHz synchronization signal. AC_BITCLK Clock) 12.288MHz clock used serial data transfer between 4DWAVEDX. AC_SDATA_OUT Serial Data Out) serial, time division multiplexed, output data stream. AC0_SDATA_IN (Primary Serial Data serial, time division multiplexed, input data stream. (Note used differentiate with future secondary codecs such AC1, AC2, etc. multiple support.) AC_RESET# Reset) active master reset signal. This signal controlled RST# signal internal Power Management register.
Number(s)
AC_SDATA_OUT AC0_SDATA_IN
BDT6U_5S IBUFT_5S
AC_RESET#
BDT6U_5S
3.1.3
MIDI/Game Port
Signal Name MIDI_OUT MIDI_IN GAMEH[3:0] GAMEL[3:0] Type T/I/O Buffer BT10U_5S IBUFT_5S IBUFT_5S BDT10U_5S Signal Description MIDI_OUT (MIDI Out) MIDI UART serial output signal. MIDI_IN (MIDI MIDI UART serial input signal. GAMEH[3:0] MS-nibble Game Port. This nibble reads Button values input only. GAMEL[3:0] LS-nibble Game Port. This nibble "fires" game port timer applications poll current position reading GAMEL[3:0] through Enhanced Game Port Position Register 58-61
Number(s)
62,64-66
3.1.4
Test Logic
Signal Name TEST[1:0]# Type Buffer BDT4U_5S Signal Description TEST[1:0]# inputs that enable 4DWAVE-DX into test modes during low-to-high RST# transition. reserved Global Tristate NAND Tree test Normal Operation Test Data data NAND Tree test mode. 67,68
Number(s)
BDT4U_5S
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3.1.5
Power
Signal Name VCC_5V Type Power Power Power Buffer V5SFPAD VDD5SPAD VSS5SPAD Power (3.3V) Ground Signal Description Power Safe (Tolerant) Pads
Number(s) 1,19,26,38,51, 57,69,76,88 13,25,32,44, 50,63,75,82, 94,100
3.1.6
Forward-Compatible Signal Group
These pins Connects" 4DWAVE-DX defined future socket-compatible 4DWAVE family products. Trident will provide applications notes design assistance system designs intended accommodate future 4DWAVE family products same socket. These pins shown "shaded" pins Section 3.2, Assignment Diagram.
Number(s) Signal Name CLKRUN# Type Buffer Signal Description CLKRUN# (Clock Running) active signal that controls whether clock stopped should kept running. This intended Notebook "motherboard" design CLKRUN# available slot. PME# (Power Management Event) active signal that informs system core logic that event occurred that requires modification power management state system. This intended Notebook "motherboard" design PME# available slot. Serial Data signal. This should connected "data" 2-pin serial EEPROM. Serial transfer clock. This should connected "clock" 2-pin serial EEPROM. serial clock. This intended Notebook design should connected ZV-port SCLK pin. word select; Left Word; Right Word. This intended Notebook design should connected ZV-port LRCLK pin. I2S: Serial Data This intended Notebook design should connected ZV-port SDATA pin. AC1_SDATA_IN Secondary serial data This should connected secondary codec recommended spec. Crystal Ground Crystal Power Crystal Input Crystal Output
PME#
ROM_DATA ROM_CLK I2S_SCLK I2S_LRCLK
I2S_SDATA AC1_SDATA_IN
XVSS XVCC XTALI XTALO
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Note:
Figure 3-1. 4DWAVE-DX Assignment shaded pins functional signals 4DWAVE-DX belong "Forward-compatible Signal Group" future socket-compatible 4DWAVE family products. Refers Section 3.1.6 more details.
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AD10 C/BE0# ROM_CLK ROM_DATA I2S_SDATA I2S_LRCLK I2S_SCLK AC1_SDATA_IN AC_RESET_N AC_SYNC
AD20 AD19 AD18 AD17 AD16 VCC_5V C/BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# C/BE1# AD15 AD14 AD13 AD12 AD11
AD21 AD22 AD23 IDSEL C/BE3# AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 REQ# GNT# RST# CLKRUN# PME# INTA#
4DWAVE-DX
XVSS XTALO XTALI XVCC TEST0# TEST1# GAMEL0 GAMEL1 GAMEL2 GAMEL3 GAMEH0 GAMEH1 GAMEH2 GAMEH3 MIDI_IN MIDI_OUT AC_SDATA_OUT AC_BITCLK AC0_SDATA_IN
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Physical Dimensions (mm)
typ. typ. 12.00 typ.
12.00 typ.
typ.
typ.
LQFP
0.50
0.07 0.20 0.03
1.40 0.05
1.60 max. 0°7°
0.15 1.00 ref.
0.05 0.15
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Address Register Description
4DWAVE-DX standalone single function audio device. registers three address spaces: Configuration Header space, Space, Memory Space. These spaces initialized through Plug-n-Play system software routines configuring registers 256-byte Configuration Register space. 4DWAVE-DX three major groups registers described following sections Section Configuration Registers Section Wave Engine Control Registers Section Legacy Registers (SoundBlasterTM, Adlib, MPU-401, Game Port)
Configuration Space
Table 4-1. 4DWAVE-DX Configuration Register Space
Offset (Hex) 18-28h RSVD (Read Only 00h) LEGACY_CTRL MAX_LAT (Read Only 05h) BIST (Read Only 0000h) Byte Status Class Code (Read Only 040100h) Header Type (Read Only 00h) Latency Timer Byte Byte Command Revision (Read Only 00h) Cache Line Size (Read Only 0000h) Byte Device (Read Only 2000h) Vendor (Read Only 1023h)
device both PPMI DDMA compatible, which requires additional registers set-up. Cap_Ptr points offset where additional registers defines power management capabilities 4DWAVE-DX.
Audio Base Address Register Audio Memory Base Address Register RSVD (Read Only 00000000h) Subsystem (Read Only 2000h) RSVD (Read Only 000000h) RSVD (Read Only 00000000h) MIN_GNT (Read Only 02h) Interrupt (Read Only 01h) LEGACY_DMA Next_Ptr (Read Only 00h) Interrupt Line Subsystem Vendor (Read Only 1023h) Cap_Ptr (Read Only 48h) RSVD (Read Only 00000000h)
DDMA_CFG LEGACY_IOBASE Cap_ID (Read Only 01h)
Power Management Capabilities (Read Only 0601h) Power Value Data (Read Only 00h) PMCSR_BSE (Read Only 00h)
Power Management Control/Status Interrupt Snooping Control
RSVD (Read Only 0000h)
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4.1.1
4.1.1.1
Configuration Registers Description
Vendor (Offset 00h)
Bits [15:0] 1023h Read/Write Description Trident Microsystems' Vendor
4.1.1.2
Bits
Device (Offset 02h)
2000h Read/Write 4DWAVE-DX Device Description
[15:0]
4.1.1.3
Bits
Command (Offset 04h)
000000b Read/Write Reserved Fast Back-to-Back enable master transactions. 4DWAVE-DX does support this feature. This hardwired `0'. SERR# enable Disables SERR# Driver Enables SERR# Driver Address/Data stepping Wait cycle control. 4DWAVE-DX does support this feature. This hard wired `0'. Parity Enable Ignores parity errors. Report parity errors. palette snoop. 4DWAVE-DX does support this feature. This hard wired `0'. Enable "Memory Write Invalidate" command. 4DWAVE-DX does support this feature. This hard wired `0'. Enable device monitor Special Cycle commands. 4DWAVE-DX does support this feature. This hard wired `0'. Master Enable Disables Master Operation Enables Master Operation Memory Space Enable Disables device respond Memory Space cycles Enables device respond Memory Space cycles Space Enable Disables device respond Space cycles Enables device respond Space cycles Description
[15:10]
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4.1.1.4
Bits [15] [14] [13] [12] [11] [10:9]
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Status (Offset 06h)
Read/Write Clear Clear Clear Clear Clear Description Parity Error Detected. device sets this bit, whenever detects parity error, even when Command disabled. SERR# status. whenever this device asserts SERR#. Received Master-Abort status. whenever transaction this device terminated with Master-Abort. Received Target-Abort status. whenever transaction this device terminated with Target-Abort. Signaled Target-Abort status. whenever transaction this device terminated with Target-Abort. This will never happen 4DWAVE-DX. DEVSEL Timing. device supports "Medium" DEVSEL timing. Data Parity Error Detected. This Master device when detects data parity error, current Master, when Command enabled report parity errors. Capable Fast Back-to-Back cycles. 4DWAVE-DX does support this feature. This hard wired `0'. User Definable Features. 4DWAVE-DX does support this feature. This hard wired `0'. 66MHz Capable. 4DWAVE-DX does support this feature. This hard wired `0'. Capabilities List. 4DWAVE-DX supports "New Capabilities" structure. Reserved
[3:0]
0000b
4.1.1.5
Bits [7:0]
Revision (Offset 08h)
Read/Write Description
4DWAVE-DX Revision. First revision 00h.
4.1.1.6
Bits
Class Code (Offset 10h)
Read/Write Base Class. Multimedia Class. Audio Interface Class. None Defined Description
[23:16] [15:8] [7:0]
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4.1.1.7
Bits [7:0]
Cache Line Size (Offset 0Ch)
Read/Write Description
Cache Line Size. 4DWAVE-DX does support this feature. This hardwired `0'.
4.1.1.8
Bits [7:3] [2:0]
Latency Timer (Offset 0Dh)
00000b 000b Read/Write Description Latency Timer 8-PCI Clock increments. Latency Timer 3-bits. Always 000b. This forces latency incremented 8-PCI Clocks time.
4.1.1.9
Bits [6:0]
Header Type (Offset 0Eh)
0000000b Read/Write Description Multi-function device enable. 4DWAVE-DX multi-function device. Header Layout. 4DWAVE-DX uses "standard" configuration layout.
4.1.1.10 BIST (Offset 0Fh)
Bits [7:0] Read/Write Description 4DWAVE-DX does support this feature. These bits hardwired `00h'.
4.1.1.11 Base Address (Offset 10h)
Bits [31:8] [7:2] 000000h 000000b Read/Write Description Base Address [31:8]. Specifies 24-bits Audio base address. Base Address [7:2]. Forces alignment 256-byte block. Reserved. Base identifier.
4.1.1.12 Memory Base Address (Offset 14h)
Bits [31:12] [11:4] [2:1] 00000h Read/Write Description Memory Base Address [31:12]. Specifies 20-bits Audio Memory base address. Memory Base Address [11:4]. Forces alignment 4K-byte block. Prefetchable. 4DWAVE-DX uses this space Memory mapped I/Os. This prefetchable mergeable address space. Type. This located anywhere 32-bit address space. Memory Base identifier.
4.1.1.13 Subsystem Vendor (Offset 2Ch)
Bits [15:0] 1023h Read/Write R/(W) Description Trident Microsystems's Vendor used default. This register written Config [46h] enabled.
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4.1.1.14 Subsystem (Offset 2Eh)
Bits [15:0] 2000h Read/Write Description
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4DWAVE-DX does support this feature. These bits hardwired `2000h'.
4.1.1.15 Capabilities Pointer (Offset 34h)
Bits [7:0] Read/Write Description Capabilities Pointer. Absolute offset start extended capabilities configuration space.
4.1.1.16 Interrupt Line (Offset 3Ch)
Bits [7:0] Read/Write Description Interrupt Line. This used driver Plug-n-Play setup code identify interrupt used this device.
4.1.1.17 Interrupt (Offset 3Dh)
Bits [7:0] Read/Write Description Interrupt Pin. This used tell what device uses. 4DWAVE-DX uses INTA# pin.
4.1.1.18 Minimum Grant (Offset 3Eh)
Bits [7:0] Read/Write Description Minimum Latency. minimum time complete burst 500ns. 0.25us increment)
4.1.1.19 Maximum Latency (Offset 3Fh)
Bits [7:0] Read/Write Description Maximum Latency. maximum time between request cycles 1.25us 0.25us increment)
4.1.2
4.1.2.1
Legacy Configuration Registers Description
Distributed Configuration (Offset 40h)
Bits [31:4] 0000000h Read/Write DDMA Base Address [31:4] Legacy Extended Addressing Control (Fully Addressing) disabled enabled Legacy Transfer Size Control transfer, legacy DDMA Slave Channel Access Enable Control disabled enabled Description
[2:1]
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4.1.2.2
Bits
Legacy Base (Offset 44h)
Read/Write Description MPU-401 Legacy Address Space Enable MPU401Base disable MPU401Base enable MPU-401 Legacy Address Space Select MPU401Base 0330h-0333h MPU401Base 0300h-0303h Game Port Legacy Address Space Enable GAMEBase disable GAMEBase enable Game Port Legacy Address Space Select GAMEBase 0200h-0207h GAMEBase 0208h-020Fh Adlib Legacy Address Space Enable ADLIBBase disable ADLIBBase enable Adlib Legacy Address Space Select ADLIBBase 0388h-038Bh ADLIBBase 038Ch-038Fh SoundBlasterLegacy Address Space Enable SBBase disable SBBase enable SoundBlasterLegacy Address Space Select SBBase 0220h-022Fh SBBase 0240h-024Fh
4.1.2.3
Bits [7:4]
Legacy (Offset 45h)
Read/Write Reserved Reserved Reserved Enable Legacy Snooping/Trapping trapping disable trapping enable Snooping Channel Select channel trapping channel trapping Description
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4.1.2.4
Bits [7:3]
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Legacy Control (Offset 46h)
00000b Read/Write Reserved Audio Engine Reset Normal Reset Audio Registers Wave Engine State Machines When this `1', audio block (including wavetable legacy audio) will reset. must `0', exit reset. Sub-System Vendor Write Enable Sub-System Vendor Read Only Sub-System Vendor Read/Write Reserved Description
4.1.3
4.1.3.1
Power Management Configuration
Capabilities (Offset 48h)
Bits [7:0] Read/Write Description Identifies capability being Power Management Registers.
4.1.3.2
Bits [7:0]
Next Item Pointer (Offset 49h)
Read/Write Description being 00h, indicates linked-list extended capabilities.
4.1.3.3
Bits
Power Management Capabilities (Offset 4Ah)
00000b 000b 001b Read/Write Description Support 4DWAVE-DX does support PME# generation. Support 4DWAVE-DX supports power state. Support 4DWAVE-DX supports power state. Reserved Device Specific Initialization 4DWAVE-DX does require device specific initialization. Auxiliary Power Source 4DWAVE-DX does support separate internal power support. PME# generation.) Clock 4DWAVE-DX does support PME# generation and, therefore, does need clock generate PME#. Version 4DWAVE-DX support Revision Power Management Interface specification.
[15:11] [10] [8:6] [2:0]
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4.1.3.4
Bits [15]
Power Management Control/Status (Offset 4Ch)
0000b 000000b Read/Write Description Status 4DWAVE-DX does support generation. Data Scale 4DWAVE-DX does support Power value reporting through "Data" register. Data Select 4DWAVE-DX does support Power value reporting through "Data" register. PME# Enable 4DWAVE-DX does support PME# generation. Reserved Power State This used determine current power state. Software updates this register when changing power states 11b-D3hot
[14:13] [12:9] [7:2] [1:0]
4.1.4
4.1.4.1
Interrupt Snooping Configuration
Interrupt Snooping Control (Offset 50h)
Bits [15:8] Read/Write Description Interrupt Vector: Compared vector returned AD[7:0] during interrupt acknowledge cycle. matches, then disable INTA# until internal interrupts have been cleared. Reserved Interrupt Snoop Enable Disable Interrupt Snooping Enable Interrupt Snooping (During Interrupt Acknowledge)
[7:1]
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4.2.1
Wave Engine Control Registers
Address Wave Register Space
4DWAVE-DX configured respond separate legacy register addresses (SoundBlasterTM, Adlib, MPU401, Game Port), well combined Wave register space (AudioBase). Wave register space accessed through traditional cycle memory mapped cycles, legacy register space only accessible through cycles. Legacy registers mapped into bottom bytes Wave register address space. Figure below shows System Memory address space 4DWAVE-DX.
System Space
0000h 0003h 0008h 0087h 0083h GameBase 0200h 0208h SBBase 0220h 0240h MPUBase 0300h 0330h AdlibBase 0388h 38Ch DDMA Base Status Page Game Port Regs Regs Adlib Regs DDMA Regs 2-bytes 8-bytes 1-byte 8-bytes 16-bytes 4-bytes 4-bytes 16-bytes Memory Base MemBase+ 100h Wave Registers 4K-bytes Read Only 00000000h MemBase+ 1000h
System Memory Space
Wave Base
Wave Registers
256-bytes
Figure 4-1. System Memory Address Space 4DWAVE-DX Table details address 4DWAVE-DX internal register set. These Wave registers addressable using either Audio Base Address Audio Memory Base Address. legacy portion these registers available through their respective legacy addresses well. providing both memory aperture these registers, 4DWAVE-DX tuned both compatibility performance. Both Memory apertures enabled simultaneously. Wave registers consume 256-byte aligned address space. mapping only allows 256-byte space accessed. memory mapping consumes 4K-bytes, however, only bottom 256-bytes actually addresses Wave registers. register contents reside on-chip, however, some registers must accessed through base indexed manner. This true voice channel specific registers OPL3 locations. locations which defined will return H'00000000 when read. There affect when writing undefined registers. Wave registers indexed through global function specific particular voice channel. registers through voice channel specific each voice channels (0-63) channel index programmed through (Channel Index Register) offset A0h. Registers through implemented only first voice channels.
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Table 4-2. 4DWAVE-DX Internal Registers
Audio Base Offset (Hex) 24-2C 64-6C DMAR3 RSVD DMAR11 DMAR15
Byte DMAR2 DMAR6 DMAR10 DMAR14 SBR2 SBR6 SBR7 SBR9 MPUR2 RSVD
Byte DMAR1 DMAR5 RSVD DMAR13
Byte DMAR0 DMAR4 DMAR8 DMAR12 SBR0 SBR4 RSVD SBR8 MPUR0
Byte
SBR3/SBR1 SBR6 SBR7 SBR10 MPUR3 RSVD GAMER2 GAMER3
SBR1/SBR3 SBR5 RSVD SBR8 MPUR1 GAMER1
RSVD (Read Only h'00000000) GAMER0
RSVD (Read Only h'00000000) ACR0 ACR1 ACR2 RSVD (Read Only h'00000000) ASR0 RSVD ASR3 ASR6 AOPLSR0 RSVD (Read Only h'00000000) RSVD PSBVLD_A Channels 0-31 PSBVLD_B Channels 32-63 START_A Channels 0-31 STOP_A Channels 0-31 DLY_A SIGN_CSO_A CSPF_A Channels 0-31 CEBC_A AIN_A Channels 0-31 EINT_A RCI2 RCI1 RCI0 RSVD (Read Only h'00000000) ASR5 RSVD ASR4 ASR2 ASR1
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Table 4-2. 4DWAVE-DX Internal Registers (Cont'd.)
Audio Base Offset (Hex) Byte GC(12:8) +LFOCTRL_A AINTEN_A Channels 0-31 MUSICVOL SBDELTA MISCINT START_B Channels 32-63 STOP_B Channels 32-63 CSPF Channels 32-63 SBBL SBE2R RSVD LFOCTRL_B T_FIFO [FIFO(39:24)] T_DIGIMIXER [ADL(19:4)] AIN_B Channels 32-63 AINTEN_B Channels 32-63 Bank Address (Channels 0-31) PSBPTR[1:0] LBA[29:0] RSVD PSBPTR[1:0] LBA[29:0] RSVD GVSEL EBUF1 EBUF2 RSVD (Read Only h'00000000) RSVD Bank Envelope CTRL Ec(11:8) Ec(7:0) DELTA RVOL(6:1) RSVD DELTA RVOL(6:1) ALPHA(11:4) ALPHA(11:4) RSVD STIMER LFOCOUNT_B ROM_TEST T_FIFO [FIFO(19:4)] T_DIGIMIXER [ADR(19:4)] SBCL SBDD WAVEVOL DELTA_R Byte LFOCOUNT_A GC(7:0) Byte
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Byte (Channel Index Register)
SBCTRL
ALPHA(3:0)
RVOL(0) CVOL ALPHA(3:0)
Bank Address (Channel 32-63)
RVOL(0) CVOL
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4.2.2
4.2.2.1
Legacy Registers Mapping Wave Engine Registers
Legacy Registers Address Wave Register Space Mapping
Register Name Legacy Address Bits Description
AudioBase Offset
Legacy Channel Mapping Registers DMAR0 DMAR1 DMAR2 DMAR3 DMAR4 DMAR5 DMAR6 DMAR8 DMAR10 DMAR11 DMAR12 DMAR13 DMAR14 DMAR15 0000h/0002h 0000h/0002h 0087h/0083h -0001h/0003h 0001h/0003h -0008h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Legacy Playback Buffer Base Register Legacy Playback Buffer Base Register Legacy Playback Buffer Base Register Legacy Playback Buffer Base Register Legacy Playback Byte Count Register Legacy Playback Byte Count Register Legacy Playback Byte Count Register Legacy Command/Status Register Legacy Single Channel Mask Port Legacy Channel Operation Mode Register Legacy First/Last Flag Clear Port Legacy Master Clear Port Legacy Clear Mask Port Legacy Multi-Channel Mask Register Legacy Music Bank Register Index/Legacy Music Status Legacy Music Bank Register Data Port Legacy Music Bank Register Index Legacy Music Bank Register Data Port Legacy Mixer Register Index Port Legacy Mixer Register Data Port Legacy Reset Port Legacy Data Port Legacy Command/Status Port Legacy Data Ready/IRQ Port
Legacy Mapping Registers 16-17h 1A-1Bh 1C-1Dh SBR0 SBR1/SBR3 SBR2 SBR3/SBR1 SBR4 SBR5 SBR6 SBR7 SBR8 SBR9 SBBase+0h SBBase+1h/ SBBase+3h SBBase+2h SBBase+1h/ SBBase+3h SBBase+4h SBBase+5h SBBase+6h/ SBBase+7h SBBase+Ah/+Bh SBBase+Ch/+Dh SBBase+Eh [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] (R=FFh)
(Continued next page)
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AudioBase Offset
Register Name
Legacy Address
Bits
Description
Legacy Mapping Registers SBR10 SBBase+Fh [7:0] Legacy Data Ready/IRQ Port Legacy MPU-401 Data Port/IRQ Port Legacy MPU-401 Command/ Status Port MPU-401 Operation Control/ Status Register MPU-401 MIDI-IN FIFO Access Port Game Port Control Register Legacy Game Port Register Enhanced Game Port Position Register Enhanced Game Port Position Register
Legacy MPU-401 Mapping Registers MPUR0 MPUR1 MPUR2 MPUR3 GAMER0 GAMER1 GAMER2 GAMER3 MPU401Base+0h MPU401Base+1h MPU401Base+2h MPU401Base+3h -GameBase -[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [31:0] [31:0] FFFFFFFFh FFFFFFFFh [7:2] [1:0]
Legacy Game Port Mapping Digital Enhanced Game Port Registers
4.2.2.2
Wave Engine Registers
Register Name ACR0 ACR1 ACR2 ASR0 ASR1 ASR2 ASR3 ASR4 ASR5 ASR6 AOPLSR0 Bits Control Registers Description
AudioBase Offset
[31:0] [31:0] [31:0] [31:0] [15:0] [7:0] [31:0] [7:0] [7:0] [7:0] [31:0]
00000000h 00000000h 00000000h 00000000h AC44h 00000000h 00000000h
Codec Write Register Codec Read Register Command/Status Register 4DWAVE-DX Status Register Legacy Frequency Readback Register Legacy Time Constant Readback Register 4DWAVE-DX Scratch-pad Register 4DWAVE-DX Version Control Register Version High Byte Control Register Version Byte Control Register OPL3 Emulation Channel On/Off Trace Register Record Channel Index (Chorus), (Reverb), (Mixer) Register Bank Stream Buffer Valid Flags (for testing only) Bank Stream Buffer Valid Flags (for testing only)
Miscellaneous Status/Control Registers
OPL3 Channel Status Registers Recording Channel/Streaming Buffer Status Registers RCI[2:0] PSBVLD_A PSBVLD_B [31:0] [31:0] [31:0] 00000000h 00000000h 00000000h
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AudioBase Offset
Register Name START_A STOP_A DLY_A SIGN_CSO_A CSPF_A CEBC_A AIN_A EINT_A LFO_A AINTEN_A VOL_A DELTA MISCINT START_B STOP_B CSPF_B SBBL&SBCL SBCTRL STIMER ROM_TEST LFO_B T_FIFO T_DIGIMIXER AIN_B AINTEN_B
Bits
Description
4DWAVE-DX Wave Engine Registers [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [15:0] [15:0] [31:0] [31:0] [31:0] [31:0] 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00008080h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h XXXXh 0000h XXXXXXXXh XXXXXXXXh 00000000h 00000000h Bank START Command Status Register Bank STOP Command Status Register Delay Flag Register (Bank only) Sign (Bank only) Bank Current Sample Position Flag Current Envelope Buffer Control Register (Bank only) Bank Address Engine Interrupt Register Envelope Engine Interrupt Register (Bank only) Bank LFO, Global Control Channel Index Register Bank Address Engine Interrupt Enable Control Register Global Music Volume Global Wave Volume Control Register Sample Change Step Legacy Voice In/Out Recording Record/Playback Underrun/Record Overrun Interrupt Register Bank START Command Status Register Bank STOP Command Status Register Bank Current Sample Position Flag Base Length Current Length Register Control/SB Testing Byte/SB Direct Playback Data Sample Timer Test Register Bank Register Mixer FIFO Test Register Mixer Accumulator Test Register Bank Address Engine Interrupt Register Bank Address Engine Interrupt Enable Control Register
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4.2.2.3 Channel-Specific Registers
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There independent voice channels. first voice channels designated Bank second voice channels designated Bank Every voice channel it's parameter register set. Bank Bank parameters differs slightly. These register sets will share same space (offset EFh). global register (offset A0h) used select current accessible channel.
AudioBase Offset Register Name Alpha PPTR DELTA RVOL CVOL Bits [31:0] [31:0] [31:0] [31:0] XXXXXXXXh XXXXXXXXh XXXXXXXXh XXXXXXXXh Description Current Sample Offset Sample Interpolation Coefficient Frequency Modulation Step Pointer Loop Begin Address Sample Offset Delta Sample Rate Ratio Control, Reverb Volume Chorus Volume Control
4.2.2.4
Global Volume Control Bank Envelope Control Registers
Register Name GVSEL MISC EBUF1 EBUF2 Bits [31:0] [31:0] [31:0] XXXXXXXXh XXXXXXXXh XXXXXXXXh Description Global Volume Select, Volume Attenuation, Control Current Envelope Envelope Buffer Envelope Buffer
AudioBase Offset
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Legacy Compatibility
4DWAVE-DX supports aspects SoundBlasterlegacy compatibility. Including Compatibility, Address, Compatibility, Legacy Functions Compatibility (including, OPL3, SoundBlasterPro/16 Mixer, MPU-401, Game Port) which includes compatibility. following sections will briefly describe each compatibility achieved.
4.3.1
Compatibility
4DWAVE-DX supports major OSs. Each environment involves different levels types compatibility. type compatibility mechanism attain covered table below.
Application Real-mode Windows® 3.1/95 DOS-Box Windows® DOS-Box Compatibility Type Hardware register function compatibility SoundBlaster16, Adlib, OPL3, MIDI, Game Port Hardware register function compatibility SoundBlaster16, Adlib, OPL3, MIDI, Game Port Virtual register function compatibility SoundBlaster16, Adlib, OPL3, MIDI, Game Port
4.3.2
Compatibility
4DWAVE-DX supports legacy spaces 8-bit 8237A (Master Controller), Adlib OPL3, MIDI MPU-401 UART, SoundBlaster16 (except space), Game Port. These individually enabled selected through Config registers.
Legacy Function 8237A Controller Adlib MIDI/ MPU-401 UART SoundBlaster16 Game Port Space 0000h 000Fh Channel 0388h 038Bh 038Ch 038Fh 0330h 0333h 0300h 0303h 0220h 022Fh 0240h 024Fh 0200h 0207h 0208h 020Fh Enable Control Trapping Enable Config [45h].bit1 Address Decode Enable Config [44h].bit3 Address Decode Enable Config [44h].bit7 Address/Channel Select Channel Select Config [45h].bit0 Address Base Select Config [44h].bit2 Address Base Select Config [44h].bit6 Address Base Select Config [44h].bit0 Address Base Select Config [44h].bit4
Address Decode Enable Config [44h].bit1
Address Decode Enable Config [44h].bit5
4.3.3
Legacy Functions Compatibility
4DWAVE-DX provides legacy compatibility with SoundBlasterPro/16 OPL3, Mixer, MPU-401 UART Game Port well compatibility. Legacy Audio configured through Configuration registers. These registers include setting control Distributed Trident proprietary emulation mechanism.
4.3.3.1
SoundBlasterPro/16 OPL3
4DWAVE-DX uses proprietary VirtualFMtechnology perform emulation OPL3 function through combination hardware software. complete OPL3 register implemented VirtualFMdriver uses several additional status control register assist OPL3 emulation. Some registers implemented with complete function OPL3. Other registers just hold data VirtualFMdriver 4DWAVE-DX added AOPLSR0 register. This register used hold status which OPL3 keys, music rhythm, have been turned This register automatically clears itself once read.
4.3.3.2
SoundBlasterPro/16 Mixer
SoundBlasterPro/16 Mixer used control various volume levels. 4DWAVE-DX uses CT1745 mixer register set. complete SoundBlaster16 SoundBlasterPro mixer register sets implemented. mixer registers implemented
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hardware. 4DWAVE-DX performs emulation mixer function through combination hardware software. driver will convert command program mixer register accordingly.
4.3.3.3
MIDI MPU-401 UART
There ways MIDI SoundBlasterTM-compatible implementation. MPU-401 UART MIDI Synthesizer. Applications using MPU-401 UART mode send/receive MIDI command/data through UART with standard 2-pin interface (MIDI-IN MIDI-OUT). protocol based bits data with 1-start 1-stop bit. This mode used user connecting external keyboard organ with MIDI IN/OUT capability playback record. MIDI Synthesizer mode also uses MPU-401 UART, however, rather than transferring MIDI data through UART. data captured processed VirtualGMTM/VirtualGSdriver. driver interprets MIDI command/data converts corresponding instruments wavetable sample playback.
4.3.3.4
Game Port
Digital Enhanced Game Port 4DWAVE-DX completely backward compatible with legacy game port 8-bit register. legacy compatibility mode (either Windows® without DirectInputdriver loaded), works with joysticks intended legacy game port. With DirectInputdriver loaded, Digital Enhanced Game Port will substantially enhance system gaming performance eliminating most polling overhead CPU).
4.3.3.5
SoundBlasterDMA
SoundBlasteruses 8-bit channel. typical system configuration, channels available. SoundBlasterwill default channel 4DWAVE-DX, channel selected. 4DWAVE-DX supports legacy compatibility mechanisms first type based industry Distributed (DDMA Rev. 6.0) standard which requires system chipset contain DDMA Master logic, second type legacy requires DDMA support system chipset also founded DDMA concept. With "fair arbiter" design system core logic, both mechanisms assume that when legacy cycle "retried" PCI, that different Master will allocated Master issuing legacy cycle. Distributed industry standard mechanism supporting legacy cycles Bus. requires DDMA-compliant system chipset support DDMA Master function (responsible redirecting gathering control bits from trapped legacy cycles). 4DWAVE-DX implements corresponding logic support DDMA Slave function (responsible sending receiving control information with DDMA Master). system chipset does support DDMA, 4DWAVE-DX will Mechanism above provide both "slave" "master" functionality which specifically limited audio sub-system.
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System Test Functions
Test Mode
4DWAVE-DX test modes assist board debugging trouble-shooting during manufacturing. test modes "Global Tristate" "XOR tree."
4DWAVE-DX uses TEST[1:0]# pins conjunction with RST# enter "test mode". When RST# transitions from (active) high (inactive), TEST[1:0]# both logical (high), device enters test mode.
Enter "Test Mode" RST# enter Leave "Test Mode"
TEST[0]#
TEST[1]#
Select "Test Mode"
device uses TEST[1:0]# pins determine which test mode selected.
Test Mode Normal Tree Global Tristate Reserved TEST[1]# TEST[0]#
leave Test Mode, device must reset with both TEST[1:0]# pins logical `1'. Both TEST[1:0]# pins have internal Pull-Up pad.
Global Tristate
Global Tristate test mode will outputs into high impedance state that driving trace. This allows system designers check board trace connectivity inject input test patterns other on-board devices (such '97) without interference from 4DWAVE-DX.
Tree
tree test mode will signals into input mode with single pin, TDO, output. inputs chained together into single tree. This test mode used determine pads have been correctly attached board. When toggling input pins, output will also toggle. (Pin used tree output. RST# TEST[1:0]# pins connected tree. other signals inputs this test mode.
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AC/DC Parameters
Parameters
Tambient Vcc=5.0V 3.3V CVcc= 3.3V CVss
6.1.1
Core (3.3V Only)
Symbol CVcc CVss Core Ground Parameter Core Supply Voltage Condition 3.15 3.45 Units Notes
6.1.2
Signaling Environment
Symbol Supply Voltage Ground Input High Voltage Input Voltage Output High Voltage Output Voltage 0.55 Parameter Condition 4.75 5.25 Units Notes
Note: Consistent with both 1.13 specifications.
6.1.3
3.3V Signaling Environment
Symbol Supply Voltage Ground Input High Voltage Input Voltage Output High Voltage Output Voltage 2.97 0.33 Parameter Condition Units Notes
Note Consistent with both 1.13 specifications.
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6.2.1
6.2.1.1
Parameters
Clocks
Clock
Symbol Tcyc Thigh Tlow Tskew Cycle Time High Time Time Skew Parameter Condition Units Notes
Note general, components must work with clock frequency between 33MHz.
Volt Clock
2.0V 1.5V 0.8V 0.4V
2.4V
p-tp minimum
Volt Clock
0.5V 0.4V 0.3V 0.2V
Tcyc Thigh 0.6V
p-tp minimum
Tlow
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Inputs: AD[31:0], C_BE_N[3:0], FRAME_N, IRDY_N, TRDY_N, STOP_N, DEVSEL_N, IDSEL, PAR, GNT_N Outputs: AD[31:0], C_BE_N[3:0], FRAME_N, IRDY_N, TRDY_N, STOP_N, DEVSEL_N, PAR, REQ_N, INTA_N, PERR_N, SERR_N Point-to-Point Signals: REQ_N, GNT_N Symbol Tval_bus Tval_ptp Toff Tsu_bus Tsu_gnt Tsu_gnt Parameter Output Valid Delay bussed signals Output Valid Delay point point signals Output float active Output active float Input time bussed signals Input time GNT_N Input time REQ_N Input hold time from Condition Units Notes
Tval OUTPUT DELAY Tri-State OUTPUT Toff
INTPUT
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6.2.3
6.2.3.1
Resets
Reset
Parameter RST# time after power stable RST# time after stable Condition Units Notes
Symbol Trst_low Trst_clk
Power
RST# Trst_clk Trst_low
6.2.3
Reset (Cold Warm)
Parameter AC_RESET# time AC_RESET# inactive AC_BITCLK starts AC_SYNC high time AC_SYNC inactive AC_BITCLK starts Condition Units controlled Notes controlled linked PCIRST#
Symbol Trst_low Trst2clk Tsync_high Tsync2clk
AC_RESET# Trst_low AC_SYNC Tsync_high AC_BITCLK Tsync2clk Trst2clk
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6.2.4
Signals
Parameter Setup from edge AC_BITCLK Falling Edge AC0_SDATA_IN AC_SDATA_OUT Rising Edge SYNC Hold from edge AC0_BITCLK Falling Edge AC0_SDATA_IN AC_SDATA_OUT Rising Edge SYNC Condition Units Notes
Symbol Tsetup
Thold
AC_BITCLK Tsetup AC_SYNC Tsetup AC0_SDATA_IN AC_SDATA_OUT Thold Thold
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Document
4DWAVE-DX
TECHNICAL REFERENCE MANUAL
VCC3 VCC3 0.1uF 0.1uF VCC3 0.1uF
Reference Schematic
VCC3 0.1uF VCC3 0.1uF 0.1uF 0.1uF VCC5 VCC3 VCC3 VCC3
VCC3
VCC3
0.1uF
0.1uF
TEST1#
PME# AC1_SDATA_IN
VCC_5V
TEST0#
VSS0
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
NX-ONLY PINOUTS
Game Port
MIDI_IN I2S_SCLK MIDI_OUT I2S_LRCLK I2S_SDATA GAMEH3 GAMEH2 CLKRUN# OM_DATA ROM_CLK XTALOUT GAMEL1 GAMEL0 4.7K XVCC XVSS REQ# GNT# C/BE0# C/BE1# C/BE2# C/BE3# IDSEL PCICLK RESET# FRAME# STOP# IRDY# INTR# DEVSEL# TRDY# PERR# SERR# AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AC97_RESET# AC97D_OUT AC97_SYNC GAMEH1 GAMEH0 GAMEL3 GAMEL2
MIDI_IN MIDI_OUT GD[4.7] GD[0.3]
MIDI_IN MIDI_OUT
GD[4.7]
4.7K
GD[0.3]
AC97_DIN
AC97_CLK
4DWAVE AC97_RESET# AC97_SY AC_BITCLK AC97D_OUT AC97D_IN
AC97_RESET# AC97_SY AC_BITCLK AC97D_OUT AC97D_IN
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10
TRDY# DEVSEL# INTR# IRDY# STOP# FRAME# RESET# PCICLK IDSEL C/BE#3 C/BE#2 C/BE#1 C/BE#0
AD[0.31] GNT# C/BE#[0.3] IDSEL PCICLK ESET# STOP# IRDY# INTR# DEVSEL# PERR#
AD[0.31] GNT# C/BE#[0.3] IDSEL PCICLK ESET# STOP# IRDY# INTR# DEVSEL#
|LINK |BUS.SCH |LINEOUT.SCH |VIDEO.SCH |AC97.SCH
PERR#
SERR#
SERR#
PRELIMINARY
This application example. Trident Microsystems, Inc. bears responsibility errors drawing these schematics. Copyright 1998 Trident Microsystems, Inc. Schematics subject change without notice.
Trident Microsystems, Inc. 4DWAVE 2-layer Schematics converted ORCADWIN 7.01) changes from Schematics Dated 2/17/98 Title 4DWAVE 2-LAYER REFERENCE Size Date: Document Number 4DWAVE MAIN Tuesday, February 1998 Sheet
Trident Microsystems, Inc.
4DWAVE-DX
TECHNICAL REFERENCE MANUAL
Document
LOCAL
AD[0.31] CON1 -12V INTB INTD PRSNT1 RSRV104 PRSNT2 RSRV108 +5V_IO AD31 AD29 AD27 AD25 +3.3V C/BE3 AD23 AD21 AD19 +3.3V AD17 C/BE2 IRDY +3.3V EVSEL LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 AD12 AD10 +3.3V +5V_IO ACK64 PCI32 TRST +12V INTA INTC RSRV9 +5V_IO +5V_IO AD30 +3.3V AD28 AD26 AD24 IDSEL +3.3V AD22 AD20 AD18 AD16 +3.3V FRAME STOP +3.3V SDONE AD15 +3.3V AD13 AD11 C/BE0 +3.3V +5V_IO REQ64 +12V +12V 4.7K INTR# INTR# 10uF 0.1uF ESET# GNT# AD30 AD28 AD26 AD24 IDSEL AD22 AD20 AD18 AD16 FRAME STOP# FRAME STOP# Optional 3.3V Regulator GNT# AME86133-UP GNT# VOUT ESET# ESET# 100uF LT1587CM-3.3 VOUT AD[0.31] VOLTAGE REGULATOR
PCICLK
PCICLK AD31 AD29 AD27 AD25 C/BE#3 AD23 AD21 AD19 AD17 C/BE#2
IDSEL
IRDY# DEVSEL# PERR# SERR#
IRDY# DEVSEL# PERR# SERR# C/BE#1 AD14 AD12 AD10
AD15 AD13 AD11 C/BE#0
C/BE#E[0.3] C/BE#0 C/BE#[0.3]
C/BE#1
C/BE#2
C/BE#3
10uF
10uF
10uF
10uF
PRELIMINARY
This application example. Trident Microsystems, Inc. bears responsibility errors drawing these schematics. Copyright 1998 Trident Microsystems, Inc. Schematics subject change without notice.
Trident rosystems, Inc. Title 4DWAVE 2-LAYER REFERENCE Size ate: Document Number 4DWAVE INTERFACE Tuesday, February 1998 Sheet
4DWAVE 2-layer Schematics converted ORCADWIN 7.01) changes from Schematics Dated 2/17/98 NOTE: Added optioonal second Regulator
Trident Microsystems, Inc.
Document
4DWAVE-DX
TECHNICAL REFERENCE MANUAL
spkr1
spkr1
spkr2 Note: Removed Jumpers
spkr2
100UF AUDIO_R AUDIO_R 100UF AGND 1.2K 1.2K 100UF AGND AGND AGND +12V +12V 1N4001 100UF 0.1UF 1N4001 100UF PGND KA2206 100UF Power Amp. Bead AGND AGND OUT1 470UF OUT2 BTLOUT AGND FB20 470UF AUDIO_L AUDIO_L 100UF/25V 0.1UF AGND NOTE: THIS OPTIONAL AMPLIFIER SPEAKER Trident Microsystems, Inc. POPULATED BOARD Title 4DWAVE 2-LAYER REFERENCE 4DWAVE 2-layer Schematics converted ORCADWIN 7.01) changes from Schematics Dated 2/17/98 Size Date: Document Number POWER AMPLIFIER/ SPEAKER Tuesday, February 1998 Sheet
Trident Microsystems, Inc.
4DWAVE-DX
TECHNICAL REFERENCE MANUAL
PRELIMINARY
This application example. Trident Microsystems, Inc. bears responsibility errors drawing these schematics. Copyright 1998 Trident Microsystems, Inc. Schematics subject change without notice.
Document
MIDI_IN
VCC5
VCC5
.01U .01U .01U .01U GD[4.7] GD[0.7] VCC5
MIDI_OUT
GD[0.3] GD[0.7]
GAMEH3 GAMEH2 GAMEH1 GAMEH0
GAMEL3 GAMEL2 GAMEL1 GAMEL0
This type DE15 Connector Joystick
JOYSTICK/ MIDI PORT CONNECTS JOYSTICK
NOTE: 2.2K R84,R85,R86,R87 NOTE: Reflects Recommendations 4DWAVE 2-layer Schematics converted ORCADWIN 7.01) changes from Schematics Dated 2/17/98
BODY CONNECTOR GROUNDED Trident Microsystems, Inc. Title 4DWAVE 2-LAY REFERENCE Size Date: Document Number JOYSTICK /MIDI PORT Tuesday, February 1998 Sheet
Trident Microsystems, Inc.
Document
4DWAVE-DX
TECHNICAL REFERENCE MANUAL
LINEINPUT AGND
FERB FERB
LINE_INR
PRELIMINARY
This application example. Trident Microsystems,Inc. bears responsibility errors drawing these schematics. Copyright 1997 Trident Microsystems, Inc. Schematics subject change without notice. OPTION 3.3V AC97 CODECS STUFF REMOVE 3.3V STUFF REMOVE
LINE_INL FERB FERB
0.1UF
FERB
FERB AC97_RESET#
FERB
CD_R AGND AGND CD_L SPEAKER
AC97_RESET#
EADER FERB FERB VREFOUT FERB 470pf 2.2K CD_GND
100n
100n
100n
AC97D_OUT 100n AC97D_OUT
EADER
AC97D_IN# AC97D_IN
DVSS1
DVDD1
DVSS2
AVSS2
AVSS1
DVDD2
AVDD2
AVDD1
AC97D_IN
_BEEP LINE_IN_R LINE_IN_L MIC1 MIC2 CD_R CD_L CD_GND VIDEO_L VIDEO_R PHONE MONO_OUT LINE_OUT_R LINE_OUT_L
EADER
ESET# SDATA_OUT SDATA_IN T_CLK
AC97_SY AC_BITC AC97_SY
NOTE: 4-Pin connector Molex 705-53-0003 equivalent
CHAIN_IN LOCK_OUT
AC_BITC
Input Connectors
XTL_IN XTL_OUT VREFOUT 24.576MHz 10UF 0.1UF
spkr2
spkr2
EADER
FERB
LINE_OUTR
AFILT1
AFILT2
FILT_R
FILT_L
CX3D
RX3D
VREF
LINEOUTPUT SPEAKER VREFOUT
AC97#1
NOTE:Symbols Different
Used Digital Analog Ground Identification purpose AGND
EADER
FERB
LINE_OUTL
270p
100n
100n
270p
AGND spkr1 spkr1
AUDIO_R AUDIO_L AUDIO_R AUDIO_L AGND
SCHEMATIC REFLECTS CHANGES AD1819A CODEC- MARK BRASFILED 2/11/98
4DWAVE 2-layer Schematics converted ORCADWIN 7.01) changes from Schematics Dated 2/17/98 NOTE: Added Ferrite Beads VCC5/VCC3 options AC97 CODECS
Title 4DWAVE 2-LAY ENCE Size ate: Number AC97 CODEC Tues day, February 1998 Sheet
Trident Microsystems, Inc.
4DWAVE-DX
TECHNICAL REFERENCE MANUAL
Document
4DWave-DX reference board Bill Materials (Revised: April 1998)
CON1 Reference Part DB15 PCI32 Type/ Package Joystick Connector Edge Connector ceramic 0805 ceramic 0805 Radial ThruHole Radial ThruHole Radial ThruHole Thru-Hole ceramic 0805 ceramic 0805 ceramic 0805 ceramic 0805 Comments/ Assembly
Item
C1,C2,C3,C4,C7,C8,C9,C10, 0.1uF C11,C21,C151,C154 C28,C36, 0.1uF
Load Amplifier. Default LOAD
C12,C13,C14,C15,C22, C153
10UF
C25,C31,C32,C33,C34, C35, 100UF
Load Amplifier. Default LOAD
C41,C153
100UF
C26,C27,
470uF
Load Amplifier. Default LOAD
C29,C30,C105,C107, C110,C111,C116,C117, C118,C121,C122,C135, C155 C42,C43,C44,C45,C46,C47, C48,C49 C113,C112
.01uF
22pF
C119,C120
270pF
Trident Microsystems, Inc.
Document
4DWAVE-DX
TECHNICAL REFERENCE MANUAL
Item
Reference C123,C125,C131,C132, C133,C134 C124
Part 100nF
C126,C127,C128,C129, C130 C136
10uF
C142
470pf 1N4001
D1,D2
Type/ Package ceramic 0805 ceramic 0805 Radial Tantalum Thru Hole ceramic 0805 ceramic 0805 Thru Hole axial Axial Ferrite Bead Axial Ferrite Bead Header
Comments/ Assembly
FB3,FB5,1 FB10,FB11,FB12,FB13, FB14,FB15,FB16,FB17, FB18,FB19,FB20
FERB FERB
Load Amplifier. Default LOAD Load only. Default Load Amplifier. Default LOAD
JP2,JP3,JP4 JP7,JP8
SPEAKER Header HEADER HEADER LINEOUT LINEINPU
Header Jumper with Shunt Audio Jack Audio Jack Audio Jack
CD-ROM Selecting Lineout/ SPKR Line Out/ SPKR Microphone Jack Line input Jack
Only Load Depends CODEC. Default Only
Trident Microsystems, Inc.
4DWAVE-DX
TECHNICAL REFERENCE MANUAL Item Reference Part Bead Type/ Package Axial
Document
Comments/ Assembly Load Amplifier. Default LOAD
R3,R4,R7,R20,R61,R74,R75 ,R76,R77,R78,R79, R80,R81,R98,R99
4.7K
R14,R16
R15,R17,
R28,R64,R88,R89,R90, R91,R100,R1012 R18,R19
1.2K
R27,R29
R49,R50,R53,R54,R57,
R68,R71
Resistor 1/10W 0805 Resistor 1/10W 0805 Resistor 1/10W 0805 Resistor 1/10W 0805 Resistor 1/10W 0805 Resistor 1/10W 0805 Resistor 1/10W 0805 Resistor 1/10W 0805 Resistor 1/10W 0805 Resistor 1/10W 0805 Resistor 1/10W 0805
Load Amplifier. Default LOAD
Load Amplifier. Default LOAD Load Amplifier. Default LOAD
Load Amplifier. Default LOAD
R100,R101 required only CODEC that Support VREFOUT. (Note These reflected current gerbers Rev.
Trident Microsystems, Inc.
Document
4DWAVE-DX
TECHNICAL REFERENCE MANUAL Reference R84,R85,R86,R87, Part 2.2K Type/ Package Resistor 1/10W 0805 LQFP Voltage Regulator Voltage Regulator Power 1819A Cardinal Crystal Comments/ Assembly
Item
NOTE:
4DWAVE LT1587C M-3.3 AME8613 3-UP KA2206 AC97#1 24.576MH
Trident Audio Chip Load Load LOAD AC97 CODEC Trident Approved
Items BOLD Italics components associated with Power Amplifier. recommend populating these.
Trident Microsystems, Inc.

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