20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technolo
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PIC16F631/677/685/687/689/690 Data Sheet
20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
2008 Microchip Technology Inc.
DS41262E
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, MATE, rfPIC SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2008, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS41262E-page
2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
High-Performance RISC CPU:
Only Instructions Learn: single-cycle instructions except branches Operating Speed: oscillator/clock input instruction cycle Interrupt Capability 8-Level Deep Hardware Stack Direct, Indirect Relative Addressing modes
Low-Power Features:
Standby Current: 2.0V, typical Operating Current: kHz, 2.0V, typical MHz, 2.0V, typical Watchdog Timer Current: 2.0V, typical
Special Microcontroller Features:
Precision Internal Oscillator: Factory calibrated Software selectable frequency range Software tunable Two-Speed Start-up mode Crystal fail detect critical applications Clock mode switching during operation power savings Power-Saving Sleep mode Wide Operating Voltage Range (2.0V-5.5V) Industrial Extended Temperature Range Power-on Reset (POR) Power-up Timer (PWRTE) Oscillator Start-up Timer (OST) Brown-out Reset (BOR) with Software Control Option Enhanced Low-Current Watchdog Timer (WDT) with On-Chip Oscillator (Software selectable nominal Seconds with Full Prescaler) with Software Enable Multiplexed Master Clear/Input Programmable Code Protection High Endurance Flash/EEPROM Cell: 100,000 write Flash endurance 1,000,000 write EEPROM endurance Flash/Data EEPROM retention: years Enhanced USART Module: Supports RS-485, RS-232 Auto-Baud Detect Auto-wake-up Start
Peripheral Features:
Pins Input-Only Pin: High current source/sink direct drive Interrupt-on-Change Individually programmable weak pull-ups Ultra Low-Power Wake-up (ULPWU) Analog Comparator Module with: analog comparators Programmable on-chip voltage reference (CVREF) module VDD) Comparator inputs outputs externally accessible Latch mode Timer Gate Sync Latch Fixed 0.6V VREF Converter: 10-bit resolution channels Timer0: 8-bit Timer/Counter with 8-bit Programmable Prescaler Enhanced Timer1: 16-bit timer/counter with prescaler External Timer1 Gate (count enable) Option OSC1 OSC2 mode Timer1 oscillator INTOSC mode selected Timer2: 8-bit Timer/Counter with 8-bit Period Register, Prescaler Postscaler Enhanced Capture, Compare, PWM+ Module: 16-bit Capture, resolution 12.5 Compare, resolution 10-bit with output channels, programmable "dead time", frequency output steering control Synchronous Serial Port (SSP): mode (Master Slave) I2C(Master/Slave modes): I2Caddress mask In-Circuit Serial Programming(ICSPTM) Pins
2008 Microchip Technology Inc.
DS41262E-page
PIC16F631/677/685/687/689/690
Program Memory Flash (words) 1024 2048 4096 2048 4096 4096 Data Memory SRAM EEPROM (bytes) (bytes) 10-bit Comparators (ch) Timers 8/16-bit
Device
ECCP+ EUSART
PIC16F631 PIC16F677 PIC16F685 PIC16F687 PIC16F689 PIC16F690
PIC16F631 Diagram
20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC4/C2OUT RC3/C12IN3RC6 RA0/C1IN+/ICSPDAT/ULPWU RA1/C12IN0-/ICSPCLK RA2/T0CKI/INT/C1OUT RC0/C2IN+ RC1/C12IN1RC2/C12IN2RB4
TABLE
Note
PIC16F631 SUMMARY
Analog AN0/ULPWU Comparators C1IN+ C12IN0C1OUT C2IN+ C12IN1C12IN2C12IN3C2OUT Timers T0CKI T1CKI Interrupt IOC/INT Pull-up Y(1) Basic ICSPDAT ICSPCLK MCLR/VPP OSC2/CLKOUT OSC1/CLKIN
Pull-up enabled only with external MCLR configuration.
PIC16F631
DS41262E-page
2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
PIC16F677 Diagram
20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC4/C2OUT RC3/AN7C12IN3RC6/AN8/SS RC7/AN9/SDO RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RB5/AN11 RB6/SCK/SCL
TABLE
Note
PIC16F677 SUMMARY
Analog AN0/ULPWU AN1/VREF AN10 AN11 Comparators C1IN+ C12IN0C1OUT C2IN+ C12IN1C12IN2C12IN3C2OUT Timers T0CKI T1CKI SDI/SDA SCL/SCK Interrupt IOC/INT Pull-up
PIC16F677
Basic ICSPDAT ICSPCLK MCLR/VPP OSC2/CLKOUT OSC1/CLKIN
Pull-up activated only with external MCLR configuration.
2008 Microchip Technology Inc.
DS41262E-page
PIC16F631/677/685/687/689/690
PIC16F685 Diagram
20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/C12IN3-/P1C RC6/AN8 RC7/AN9 RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RB4/AN10 RB5/AN11
TABLE
Note
PIC16F685 SUMMARY
Analog AN0/ULPWU AN1/VREF AN10 AN11 Comparators C1IN+ C12IN0C1OUT C2IN+ C12IN1C12IN2C12IN3C2OUT Timers T0CKI T1CKI ECCP CCP1/P1A Interrupt IOC/INT Pull-up
PIC16F685
Basic ICSPDAT ICSPCLK MCLR/VPP OSC2/CLKOUT OSC1/CLKIN
Pull-up activated only with external MCLR configuration.
DS41262E-page
2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
PIC16F687/689 Diagram
20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC4/C2OUT RC3/AN7/C12IN3RC6/AN8/SS RC7/AN9/SDO RB7/TX/CK RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RB5/AN11/RX/DT RB6/SCK/SCL
TABLE
PIC16F687/689 SUMMARY
Analog AN0/ULPWU AN1/VREF AN10 AN11 Comparators C1IN+ C12IN0C1OUT C2IN+ C12IN1C12IN2C12IN3C2OUT Timers T0CKI T1CKI EUSART RX/DT TX/CK SDI/SDA SCL/SCK Interrupt Pull-up IOC/INT Y(1) MCLR/VPP OSC2/CLKOUT OSC1/CLKIN Basic ICSPDAT ICSPCLK
Note Pull-up activated only with external MCLR configuration.
2008 Microchip Technology Inc.
PIC16F687/689
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PIC16F631/677/685/687/689/690
PIC16F690 Diagram (PDIP, SOIC, SSOP)
20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/C12IN3-/P1C RC6/AN8/SS RC7/AN9/SDO RB7/TX/CK RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RB4/AN10/SDI/SDA RB5/AN11/RX/DT RB6/SCK/SCL
TABLE
PIC16F690 SUMMARY
Analog AN0/ULPWU AN1/VREF AN10 AN11 Comparators Timers C1IN+ C12IN0C1OUT C2IN+ C12IN1C12IN2C12IN3C2OUT T0CKI T1CKI ECCP CCP1/P1A TX/CK EUSART RX/DT SDI/SDA SCL/SCK Interrupt IOC/INT Pull-up Y(1) MCLR/VPP OSC2/CLKOUT OSC1/CLKIN Basic ICSPDAT ICSPCLK
Note Pull-up activated only with external MCLR configuration.
PIC16F690
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2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
PIC16F631/677/685/687/689/690 Diagram (QFN)
20-pin
RA0/AN0/C1IN+/ICSPDAT/ULPWU PIC16F631/677/ 685/687/689/690 RA4/AN3/T1G/OSC2/CLKOUT
RA5/T1CKI/OSC1/CLKIN
RA3/MCLR/VPP RC5/CCP1/P1A
RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+
RC4/C2OUT/P1B
RC3/AN7/C12IN3-/P1C(1) RC6/AN8/SS
RC7/AN9/SDO(2)
RB6/SCK/SCL(2)
RB5/AN11/RX/DT(3)
Note
CCP1/P1A, P1B, available PIC16F685/PIC16F690 only. SDO, SDI/SDA SCL/SCK available only. RX/DT TX/CK available PIC16F687/PIC16F689/PIC16F690 only.
2008 Microchip Technology Inc.
RB4/AN10/SDI/SDA(2)
RB7/TX/CK
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PIC16F631/677/685/687/689/690
Table Contents
Device Overview Memory Organization Oscillator Module (With Fail-Safe Clock Monitor). Ports Timer0 Module Timer1 Module with Gate Control. Timer2 Module Comparator Module. Analog-to-Digital Converter (ADC) Module 10.0 Data EEPROM Flash Program Memory Control 11.0 Enhanced Capture/Compare/PWM Module 12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) 13.0 Module Overview 14.0 Special Features 15.0 Instruction Summary 16.0 Development Support. 17.0 Electrical Specifications. 18.0 Characteristics Graphs Tables 19.0 Packaging Information. Appendix Data Sheet Revision History. Appendix Migrating from other PIC® Devices.
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Most Current Data Sheet
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Errata
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DS41262E-page
2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
DEVICE OVERVIEW
PIC16F631/677/685/687/689/690 devices covered this data sheet. They available 20-pin PDIP, SOIC, TSSOP packages. Block Diagrams pinout descriptions devices follows: PIC16F631 (Figure 1-1, Table 1-1) PIC16F677 (Figure 1-2, Table 1-2) PIC16F685 (Figure 1-3, Table 1-3) PIC16F687/PIC16F689 (Figure 1-4, Table 1-4) PIC16F690 (Figure 1-5, Table 1-5)
FIGURE 1-1:
PIC16F631 BLOCK DIAGRAM
Configuration Program Counter Flash Program Memory 8-Level Stack (13-bit) bytes File Registers Addr PORTB Data PORTA
Program Instruction Direct Addr
Addr Indirect Addr
STATUS PORTC Instruction Decode Control OSC1/CLKI OSC2/CLKO Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Internal Oscillator Block MCLR ULPWU T0CKI T1CKI EEDAT Bytes Data EEPROM Timer0 Timer1 EEADR
C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
Ultra Low-Power Wake-up
Analog Comparators Reference
2008 Microchip Technology Inc.
DS41262E-page
PIC16F631/677/685/687/689/690
FIGURE 1-2: PIC16F677 BLOCK DIAGRAM
Configuration Program Counter Flash Program Memory Program Instruction Direct Addr 8-Level Stack (13-bit) bytes File Registers Addr PORTB Data PORTA
Addr Indirect Addr
STATUS PORTC Instruction Decode Control OSC1/CLKI OSC2/CLKO Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Internal Oscillator Block MCLR ULPWU T0CKI T1CKI
SDI/ SCK/
Ultra Low-Power Wake-up
Timer0
Timer1
Synchronous Serial Port
AN10 AN11 EEDAT Analog Comparators Reference Bytes Data EEPROM EEADR
Analog-to-Digital Converter
VREF C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
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PIC16F631/677/685/687/689/690
FIGURE 1-3: PIC16F685 BLOCK DIAGRAM
Configuration Program Counter Flash Program Memory Program Instruction Direct Addr 8-Level Stack (13-bit) bytes File Registers Addr PORTB Data PORTA
Addr Indirect Addr
STATUS PORTC Instruction Decode Control OSC1/CLKI OSC2/CLKO Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Internal Oscillator Block MCLR ULPWU T0CKI T1CKI
CCP1/
Ultra Low-Power Wake-up
Timer0
Timer1
Timer2
ECCP+
AN10 AN11 EEDAT Analog Comparators Reference Bytes Data EEPROM EEADR
Analog-to-Digital Converter
VREF C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690
FIGURE 1-4: PIC16F687/PIC16F689 BLOCK DIAGRAM
Configuration Program Counter Flash 2K(1)/4K Program Memory Program Instruction Direct Addr 8-Level Stack (13-bit) 128(1)/256 bytes File Registers Addr PORTB Data PORTA
Addr Indirect Addr
STATUS PORTC Instruction Decode Control OSC1/CLKI OSC2/CLKO Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Internal Oscillator Block MCLR ULPWU T0CKI T1CKI TX/CK RX/DT
SDI/ SCK/
Ultra Low-Power Wake-up
Timer0
Timer1
EUSART
Synchronous Serial Port
AN10 AN11 EEDAT Analog Comparators Reference Bytes Data EEPROM EEADR
Analog-to-Digital Converter
VREF C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT Note PIC16F687 only.
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PIC16F631/677/685/687/689/690
FIGURE 1-5: PIC16F690 BLOCK DIAGRAM
Configuration Program Counter Flash Program Memory Program Instruction Direct Addr 8-Level Stack (13-bit) bytes File Registers Addr PORTB Data PORTA
Addr Indirect Addr
STATUS PORTC Instruction Decode Control OSC1/CLKI OSC2/CLKO Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Internal Oscillator Block MCLR ULPWU T0CKI T1CKI TX/CK RX/DT CCP1/
SDI/ SCK/
Ultra Low-Power Wake-up
Timer0
Timer1
Timer2
EUSART
ECCP+
Synchronous Serial Port
AN10 AN11 EEDAT Analog Comparators Reference Bytes Data EEPROM EEADR
Analog-to-Digital Converter
VREF C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690
TABLE 1-1: PINOUT DESCRIPTION PIC16F631
Function C1IN+ ICSPDAT ULPWU RA1/C12IN0-/ICSPCLK C12IN0ICSPCLK RA2/T0CKI/INT/C1OUT T0CKI C1OUT RA3/MCLR/VPP MCLR RA4/T1G/OSC2/CLKOUT OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN T1CKI OSC1 CLKIN RC0/C2IN+ Legend: C2IN+ C12IN1RC2 C12IN2RC3 C12IN3RC4 C2OUT Analog input output compatible input High Voltage Input Type XTAL Output Type Description Name RA0/C1IN+/ICSPDAT/ULPWU
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Comparator non-inverting input. Ultra Low-Power Wake-up input. CMOS ICSPData I/O. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Comparator inverting input. ICSPclock.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Timer0 clock input. External interrupt pin. General purpose input. Individually controlled interrupt-onchange. Master Clear with internal pull-up. Programming voltage.
CMOS Comparator output.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. XTAL Timer1 gate input. Crystal/Resonator.
CMOS FOSC/4 output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Timer1 clock input. Crystal/Resonator. External clock input/RC oscillator connection.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS General purpose I/O. Comparator non-inverting input. Comparator inverting input. Comparator inverting input. Comparator inverting input. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS Comparator output. CMOS General purpose I/O.
CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels XTAL Crystal
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PIC16F631/677/685/687/689/690
TABLE 1-1: PINOUT DESCRIPTION PIC16F631 (CONTINUED)
Function Analog input output compatible input High Voltage Input Type Power Power Output Type CMOS General purpose I/O. CMOS General purpose I/O. Ground reference. Positive supply. Description Name Legend:
CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels XTAL Crystal
2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690
TABLE 1-2: PINOUT DESCRIPTION PIC16F677
Function C1IN+ ICSPDAT ULPWU RA1/AN1/C12IN0-/VREF/ ICSPCLK C12IN0VREF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT T0CKI C1OUT RA3/MCLR/VPP MCLR RA4/AN3/T1G/OSC2/CLKOUT OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN T1CKI OSC1 CLKIN RB4/AN10/SDI/SDA AN10 RB5/AN11 AN11 RB6/SCK/SCL Legend: Analog input output compatible input High Voltage Input Type XTAL Output Type Description
Name RA0/AN0/C1IN+/ICSPDAT/ ULPWU
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel input. Comparator non-inverting input. Ultra Low-Power Wake-up input.
CMOS ICSPData I/O. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel input. Comparator inverting input. External Voltage Reference A/D. ICSPclock.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel input. Timer0 clock input. External interrupt pin. General purpose input. Individually controlled interrupt-onchange. Master Clear with internal pull-up. Programming voltage.
CMOS Comparator output.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. XTAL Channel input. Timer1 gate input. Crystal/Resonator.
CMOS FOSC/4 output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Timer1 clock input. Crystal/Resonator. External clock input/RC oscillator connection.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel input. data input. I2Cdata input/output.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel input. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS clock. I2Cclock.
CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels XTAL Crystal
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TABLE 1-2: PINOUT DESCRIPTION PIC16F677 (CONTINUED)
Function C2IN+ RC1/AN5/C12IN1RC1 C12IN1RC2/AN6/C12IN2RC2 C12IN2RC3/AN7/C12IN3RC3 C12IN3RC4/C2OUT RC6/AN8/SS C2OUT RC7/AN9/SDO Legend: Analog input output compatible input High Voltage Input Type Power Power Output Type Description Name RC0/AN4/C2IN+
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS General purpose I/O. Channel input. Comparator non-inverting input. Channel input. Comparator inverting input. Channel input. Comparator inverting input. Channel input. Comparator inverting input.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O. CMOS Comparator output. CMOS General purpose I/O. CMOS General purpose I/O. Channel input. Slave Select input. Channel input. Ground reference. Positive supply.
CMOS General purpose I/O. CMOS data output.
CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels XTAL Crystal
2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690
TABLE 1-3: PINOUT DESCRIPTION PIC16F685
Name RA0/AN0/C1IN+/ICSPDAT/ ULPWU Function C1IN+ ICSPDAT ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK C12IN0VREF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT T0CKI C1OUT RA3/MCLR/VPP MCLR RA4/AN3/T1G/OSC2/CLKOUT OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN T1CKI OSC1 CLKIN RB4/AN10 AN10 RB5/AN11 AN11 RC0/AN4/C2IN+ C2IN+ Legend: Analog input output compatible input High Voltage Input Type XTAL Output Type Description
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. Comparator positive input. Ultra Low-Power Wake-up input.
CMOS ICSPData I/O. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. Comparator negative input. External Voltage Reference A/D. ICSPclock.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. Timer0 clock input.
External interrupt pin.
General purpose input. Individually controlled interrupt-onchange. Master Clear with internal pull-up. Programming voltage.
CMOS Comparator output.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. XTAL Channel input. Timer1 gate input. Crystal/Resonator.
CMOS FOSC/4 output. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Timer1 clock input. Crystal/Resonator. External clock input/RC oscillator connection.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. CMOS General purpose I/O. Channel input. Comparator positive input.
CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels XTAL Crystal
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PIC16F631/677/685/687/689/690
TABLE 1-3: PINOUT DESCRIPTION PIC16F685 (CONTINUED)
Name RC1/AN5/C12IN1Function C12IN1RC2/AN6/C12IN2-/P1D C12IN2P1D RC3/AN7/C12IN3-/P1C C12IN3P1C RC4/C2OUT/P1B C2OUT RC5/CCP1/P1A CCP1 RC6/AN8 RC7/AN9 Legend: Analog input output compatible input High Voltage Input Type Power Power Output Type CMOS General purpose I/O. Channel input. Comparator negative input. Channel input. Comparator negative input. Description
CMOS General purpose I/O.
CMOS output. CMOS General purpose I/O. Channel input. Comparator negative input.
CMOS output. CMOS General purpose I/O. CMOS Comparator output. CMOS output. CMOS General purpose I/O. CMOS Capture/Compare input. CMOS output. CMOS General purpose I/O. Channel input. Channel input. Ground reference. Positive supply. CMOS General purpose I/O.
CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels XTAL Crystal
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TABLE 1-4: PINOUT DESCRIPTION PIC16F687/PIC16F689
Name RA0/AN0/C1IN+/ICSPDAT/ ULPWU Function C1IN+ ICSPDAT ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK C12IN0VREF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT T0CKI C1OUT RA3/MCLR/VPP MCLR RA4/AN3/T1G/OSC2/CLKOUT OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN T1CKI OSC1 CLKIN RB4/AN10/SDI/SDA AN10 RB5/AN11/RX/DT AN11 Legend: Analog input output compatible input High Voltage Input Type XTAL Output Type Description
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. Comparator positive input. Ultra Low-Power Wake-up input.
CMOS ICSPData I/O. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. Comparator negative input. External Voltage Reference A/D. ICSPclock.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. Timer0 clock input. External Interrupt. General purpose input. Individually controlled interrupt-on-change. Master Clear with internal pull-up. Programming voltage.
CMOS Comparator output.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. XTAL Channel input. Timer1 gate input. Crystal/Resonator.
CMOS FOSC/4 output. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Timer1 clock input. Crystal/Resonator. External clock input/RC oscillator connection.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. data input. I2Cdata input/output.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. EUSART asynchronous input.
CMOS EUSART synchronous data.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels XTAL Crystal
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TABLE 1-4: PINOUT DESCRIPTION PIC16F687/PIC16F689 (CONTINUED)
Name RB6/SCK/SCL Function RB7/TX/CK RC0/AN4/C2IN+ C2IN+ RC1/AN5/C12IN1RC1 C12IN1RC2/AN6/C12IN2RC2 C12IN2RC3/AN7/C12IN3RC3 C12IN3RC4/C2OUT RC6/AN8/SS C2OUT RC7/AN9/SDO Legend: Analog input output compatible input High Voltage Input Type Power Power Output Type Description
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. CMOS clock. I2Cclock. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. CMOS EUSART asynchronous output. CMOS EUSART synchronous clock. CMOS General purpose I/O. Channel input. Comparator positive input. Channel input. Comparator negative input. Channel input. Comparator negative input. Channel input. Comparator negative input.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O. CMOS Comparator output. CMOS General purpose I/O. CMOS General purpose I/O. Channel input. Slave Select input. Channel input. Ground reference. Positive supply.
CMOS General purpose I/O. CMOS data output.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels XTAL Crystal
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TABLE 1-5: PINOUT DESCRIPTION PIC16F690
Name RA0/AN0/C1IN+/ICSPDAT/ ULPWU Function C1IN+ ICSPDAT ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK C12IN0VREF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT T0CKI C1OUT RA3/MCLR/VPP MCLR RA4/AN3/T1G/OSC2/CLKOUT OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN T1CKI OSC1 CLKIN RB4/AN10/SDI/SDA AN10 RB5/AN11/RX/DT AN11 Legend: Analog input output compatible input High Voltage Input Type XTAL Output Type Description
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. Comparator positive input. Ultra Low-Power Wake-up input.
CMOS ICSPData I/O. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. Comparator negative input. External Voltage Reference A/D. ICSPclock.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. Timer0 clock input. External interrupt. General purpose input. Individually controlled interrupt-onchange. Master Clear with internal pull-up. Programming voltage.
CMOS Comparator output.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. XTAL Channel input. Timer1 gate input. Crystal/Resonator.
CMOS FOSC/4 output. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Timer1 clock input. Crystal/Resonator. External clock input/RC oscillator connection.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. data input. I2Cdata input/output.
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. Channel input. EUSART asynchronous input.
CMOS EUSART synchronous data.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels XTAL Crystal
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TABLE 1-5: PINOUT DESCRIPTION PIC16F690 (CONTINUED)
Name RB6/SCK/SCL Function RB7/TX/CK RC0/AN4/C2IN+ C2IN+ RC1/AN5/C12IN1RC1 C12IN1RC2/AN6/C12IN2-/P1D C12IN2P1D RC3/AN7/C12IN3-/P1C C12IN3P1C RC4/C2OUT/P1B C2OUT RC5/CCP1/P1A CCP1 RC6/AN8/SS RC7/AN9/SDO Legend: Analog input output compatible input High Voltage Input Type Power Power Output Type Description
CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. CMOS clock. I2Cclock. CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. CMOS EUSART asynchronous output. CMOS EUSART synchronous clock. CMOS General purpose I/O. Channel input. Comparator positive input. Channel input. Comparator negative input. Channel input. Comparator negative input.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS output. CMOS General purpose I/O. Channel input. Comparator negative input.
CMOS output. CMOS General purpose I/O. CMOS Comparator output. CMOS output. CMOS General purpose I/O. CMOS Capture/Compare input. CMOS output. CMOS General purpose I/O. Channel input. Slave Select input. Channel input. Ground reference. Positive supply.
CMOS General purpose I/O. CMOS data output.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels XTAL Crystal
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NOTES:
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MEMORY ORGANIZATION
Program Memory Organization
FIGURE 2-2:
PROGRAM MEMORY STACK PIC16F685/689/690
PC<12:0>
PIC16F631/677/685/687/689/690 13-bit program counter capable addressing program memory space. Only first (0000h-03FFh) physically implemented PIC16F631, first (0000h-07FFh) PIC16F677/PIC16F687, first (0000h-0FFFh) PIC16F685/PIC16F689/ PIC16F690. Accessing location above these boundaries will cause wraparound. Reset vector 0000h interrupt vector 0004h (see Figures through 2-3).
CALL, RETURN RETFIE, RETLW Stack Level Stack Level
Stack Level Reset Vector 0000h
FIGURE 2-1:
PROGRAM MEMORY STACK PIC16F631
PC<12:0> On-Chip Program Memory
Interrupt Vector Page Page
0004h 0005h 07FFh 0800h 0FFFh 1000h
CALL, RETURN RETFIE, RETLW Stack Level Stack Level
Access 0-FFFh 1FFFh
Stack Level
FIGURE 2-3:
Reset Vector 0000h
PROGRAM MEMORY STACK PIC16F677/PIC16F687
PC<12:0>
Interrupt Vector On-Chip Memory Page
0004h 0005h 03FFh 0400h CALL, RETURN RETFIE, RETLW Stack Level Stack Level
Access 0-3FFh 1FFFh
Stack Level Reset Vector 0000h
Interrupt Vector On-Chip Memory Page
0004h 0005h 07FFh 0800h
Access 0-7FFh 1FFFh
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Data Memory Organization
data memory (see Figures through 2-8) partitioned into four banks which contain General Purpose Registers (GPR) Special Function Registers (SFR). Special Function Registers located first locations each bank. General Purpose Registers, implemented static RAM, located last locations each Bank. Register locations F0h-FFh Bank 170h-17Fh Bank 1F0h-1FFh Bank point addresses 70h-7Fh Bank actual number General Purpose Resisters (GPR) each Bank depends device. Details shown Figures through 2-8. other unimplemented returns when read. RP<1:0> STATUS register bank select bits: Bank selected Bank selected Bank selected Bank selected
2.2.1
GENERAL PURPOSE REGISTER FILE
register file organized PIC16F687 PIC16F685/PIC16F689/PIC16F690. Each register accessed, either directly indirectly, through File Select Register (FSR) (see Section "Indirect Addressing, INDF Registers").
2.2.2
SPECIAL FUNCTION REGISTERS
Special Function Registers registers used peripheral functions controlling desired operation device (see Tables through 2-4). These registers static RAM. special registers classified into sets: core peripheral. Special Function Registers associated with "core" described this section. Registers related operation peripheral features described section that peripheral feature.
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FIGURE 2-4: PIC16F631 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON
PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE
PCLATH INTCON EEDAT EEADR
PCLATH INTCON EECON1 EECON2(1)
WPUA IOCA WDTCON
WPUB IOCB VRCON CM1CON0 CM2CON0 CM2CON1
ANSEL
SRCON
General Purpose Registers Bytes Bank
accesses 70h-7Fh Bank
accesses 70h-7Fh Bank
16Fh 170h 17Fh
accesses 70h-7Fh Bank
1EFh 1F0h 1FFh
Note
Unimplemented data memory locations, read `0'. physical register.
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FIGURE 2-5: PIC16F677 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON
PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE
PCLATH INTCON EEDAT EEADR
PCLATH INTCON EECON1 EECON2(1)
SSPBUF SSPCON
SSPADD(2) SSPSTAT WPUA IOCA WDTCON
WPUB IOCB VRCON CM1CON0 CM2CON0 CM2CON1
ADRESH ADCON0
ADRESL ADCON1 General Purpose Register Bytes
ANSEL ANSELH
SRCON
General Purpose Register Bytes Bank
16Fh 170h 17Fh 1EFh 1F0h 1FFh
accesses 70h-7Fh Bank
accesses 70h-7Fh Bank
accesses 70h-7Fh Bank
Note
Unimplemented data memory locations, read `0'. physical register. Address also accesses Mask (SSPMSK) register under certain conditions. Registers 13-2 13-3 more details.
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FIGURE 2-6: PIC16F685 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON
PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE
PCLATH INTCON EEDAT EEADR EEDATH EEADRH
PCLATH INTCON EECON1 EECON2(1)
CCPR1L CCPR1H CCP1CON
WPUA IOCA WDTCON
WPUB IOCB VRCON CM1CON0 CM2CON0 CM2CON1
PWM1CON ECCPAS ADRESH ADCON0
ADRESL ADCON1
ANSEL ANSELH
PSTRCON SRCON
General Purpose Register Bytes Bank
General Purpose Register Bytes accesses 70h-7Fh Bank
General Purpose Register Bytes accesses 70h-7Fh Bank 16Fh 170h 17Fh accesses 70h-7Fh Bank 1F0h 1FFh
Note
Unimplemented data memory locations, read `0'. physical register.
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FIGURE 2-7: PIC16F687/PIC16F689 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON
PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE
PCLATH INTCON EEDAT EEADR EEDATH(3) EEADRH
PCLATH INTCON EECON1 EECON2(1)
SSPBUF SSPCON
RCSTA TXREG RCREG
SSPADD(2) SSPSTAT WPUA IOCA WDTCON TXSTA SPBRG SPBRGH BAUDCTL
WPUB IOCB VRCON CM1CON0 CM2CON0 CM2CON1
ADRESH ADCON0
ADRESL ADCON1 General Purpose Register Bytes Bytes (PIC16F689 only) accesses 70h-7Fh Bank
ANSEL ANSELH General Purpose Register Bytes (PIC16F689 only) accesses 70h-7Fh Bank
SRCON
General Purpose Register Bytes Bank Note
170h 17Fh
accesses 70h-7Fh Bank
1F0h 1FFh
Unimplemented data memory locations, read `0'. physical register. Address also accesses Mask (SSPMSK) register under certain conditions. Registers 13-2 13-3 more details. PIC16F689 only.
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FIGURE 2-8: PIC16F690 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG PWM1CON ECCPAS ADRESH ADCON0
PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPADD(2) SSPSTAT WPUA IOCA WDTCON TXSTA SPBRG SPBRGH BAUDCTL
PCLATH INTCON EEDAT EEADR EEDATH EEADRH
PCLATH INTCON EECON1 EECON2(1)
WPUB IOCB VRCON CM1CON0 CM2CON0 CM2CON1
ADRESL ADCON1
ANSEL ANSELH
PSTRCON SRCON
General Purpose Register Bytes Bank
General Purpose Register Bytes accesses 70h-7Fh Bank
General Purpose Register Bytes accesses 70h-7Fh Bank 16Fh 170h 17Fh accesses 70h-7Fh Bank 1F0h 1FFh
Note
Unimplemented data memory locations, read `0'. physical register. Address also accesses Mask (SSPMSK) register under certain conditions. Registers 13-2 13-3 more details.
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TABLE 2-1:
Addr Bank INDF TMR0 STATUS PORTA(7) PORTB(7) PORTC(7) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2(3) T2CON(3) SSPBUF(5) SSPCON(5, CCPR1L(3) CCPR1H
PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
Name
Addressing this location uses contents address data memory (not physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer
xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx xxxx -xxxx xxxx
44,205 81,205 44,205 36,205 44,205 59,205 69,205 76,205 44,205 38,205 41,205 42,205 86,205 86,205 88,205 91,205 92,205 182,205 181,205 128,205 128,205 127,205 161,205 145,205 142,205 115,205 113,205
Unimplemented Unimplemented OSFIF PEIE ADIF(4) C2IF T0IE RCIF(2) C1IF Write Buffer upper bits Program Counter INTE TXIF(2) EEIF RABIE SSPIF(5) T0IF INTF RABIF(1) TMR1IF CCP1IF(3) TMR2IF(3)
0000 0000 000x -000 0000 0000 -xxxx xxxx xxxx xxxx
Holding Register Least Significant Byte 16-bit TMR1 Register Holding Register Most Significant Byte 16-bit TMR1 Register T1GINV TMR1GE TOUTPS3 T1CKPS1 TOUTPS2 T1CKPS0 TOUTPS1 T1OSCEN TOUTPS0 T1SYNC TMR2ON TMR1CS T2CKPS1 Timer2 Module Register Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN SSPM3 SSPM2 SSPM1 SSPM0
TMR1ON 0000 0000 0000 0000 T2CKPS0 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx
Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) P1M1 SPEN P1M0 DC1B1 SREN DC1B0 CREN CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D
CCP1CON(3) RCSTA(2) TXREG(2) RCREG PWM1CON(3) ECCPAS(3) ADRESH(4) ADCON0(4)
0000 0000 0000 000x 0000 0000 0000 0000
EUSART Transmit Data Register EUSART Receive Data Register Unimplemented PRSEN PDC6 PDC5 ECCPAS1 CHS3 PDC4 ECCPAS0 CHS2 PDC3 PSSAC1 CHS1 PDC2 PSSAC0 CHS0 PDC1 PSSBD1 GO/DONE PDC0 PSSBD0 ADON
0000 0000 0000 0000 xxxx xxxx 0000 0000
ECCPASE ECCPAS2 ADFM VCFG
Result Register High Byte
Legend: Note
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented MCLR Reset affect previous value data latch. RABIF will cleared upon Reset will again mismatch exists. PIC16F687/PIC16F689/PIC16F690 only. PIC16F685/PIC16F690 only. only. only. When SSPCON register bits SSPM<3:0> 1001, reads writes SSPADD address accessed through SSPMSK register. Registers 13-2 13-3 more detail. Port pins with analog functions controlled ANSEL ANSELH registers will read immediately after Reset even though data latches either undefined (POR) unchanged (other Resets).
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TABLE 2-2:
Addr Bank INDF OPTION_REG STATUS TRISA TRISB TRISC PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE PR2(3) SSPADD(5, SSPMSK(5, SSPSTAT WPUA(6) IOCA WDTCON TXSTA(2) SPBRG(2) SPBRGH(2) BAUDCTL(2) ADRESL(4) ADCON1(4)
PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
Name
Addressing this location uses contents address data memory (not physical register) RABPU TRISB7 TRISC7 INTEDG TRISB6 TRISC6 T0CS TRISA5 TRISB5 TRISC5 T0SE TRISA4 TRISB4 TRISC4 TRISA3 TRISC3 TRISA2 TRISC2 TRISA1 TRISC1 TRISA0 TRISC0 Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer
xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 -1111 1111
44,205 37,205 44,205 36,205 44,205 59,205 70,206 76,205 44,205 38,205 39,206 40,206 43,206 48,206 52,206 91,206 188,206 191,206 180,206 62,206 62,206 213,206 160,206 163,206 163,206 162,206 115,206 114,206
Unimplemented Unimplemented OSFIE Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register MSK7 CSRC BRG7 BRG15 ABDOVF MSK6 BRG6 BRG14 RCIDL MSK5 WPUA5 IOCA5 TXEN BRG5 BRG13 MSK4 WPUA4 IOCA4 WDTPS3 SYNC BRG4 BRG12 SCKP MSK3 IOCA3 WDTPS2 SENDB BRG3 BRG11 BRG16 MSK2 WPUA2 IOCA2 WDTPS1 BRGH BRG2 BRG10 MSK1 WPUA1 IOCA1 WDTPS0 TRMT BRG1 BRG9 MSK0 WPUA0 IOCA0 SWDTEN TX9D BRG0 BRG8 ABDEN PEIE ADIE IRCF2
T0IE RCIE
Write Buffer upper bits Program Counter INTE TXIE
0000 0000 000x -000 0000 0000 -110 q000 0000 1111 1111 0000 0000 1111 1111 0000 0000 -111 0000 1000 0000 0010 0000 0000 0000 0000 01-0 0-00 xxxx xxxx
RABIE SSPIE OSTS TUN3
T0IF CCP1IE TUN2
INTF TMR2IE TUN1
RABIF(1) TMR1IE TUN0
C2IE
C1IE IRCF1
EEIE IRCF0 TUN4
ULPWUE SBOREN
Unimplemented Unimplemented Result Register Byte ADCS2 ADCS1 ADCS0
-000
Legend: Note
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented MCLR Reset affect previous value data latch. RABIF will cleared upon Reset will again mismatch exists. PIC16F687/PIC16F689/PIC16F690 only. PIC16F685/PIC16F690 only. only. only. pull-up enabled when configured MCLR Configuration Word. Accessible only when SSPCON register bits SSPM<3:0> 1001.
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TABLE 2-3:
Addr Bank 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h INDF TMR0 STATUS PORTA(4) PORTB(4) PORTC(4) Addressing this location uses contents address data memory (not physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte Unimplemented Unimplemented EEDAT7 EEADR7(3) Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented WPUB7 IOCB7 VRCON CM1CON0 CM2CON0 CM2CON1 ANSEL ANSELH(3) C1VREN C1ON C2ON MC1OUT WPUB6 IOCB6 C2VREN C1OUT C2OUT MC2OUT WPUB5 IOCB5 C1OE C2OE WPUB4 IOCB4 VP6EN C1POL C2POL C1CH1 C2CH1 T1GSS C1CH0 C2CH0 C2SYNC PEIE EEDAT6 EEADR6 T0IE EEDAT5 EEADR5 Write Buffer upper bits Program Counter INTE EEDAT4 EEADR4 RABIE EEDAT3 EEADR3 EEDATH3 T0IF EEDAT2 EEADR2 EEDATH2 INTF EEDAT1 EEADR1 EEDATH1 RABIF(1) EEDAT0 EEADR0 Indirect Data Memory Address Pointer xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx xxxx -xxxx xxxx 0000 0000 000x 0000 0000 0000 0000 44,205 81,205 44,205 36,205 44,205 59,205 69,205 76,205 44,205 38,205 120,206 120,206 120,206 120,206 70,206 70,206 105,206 98,206 99,206 101,206 61,206 115,206 Name
PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
10Ah PCLATH 10Bh INTCON 10Ch EEDAT 10Dh EEADR 10Eh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh IOCB EEDATH(2) WPUB 10Fh EEADRH(2)
EEDATH5 EEDATH4
EEDATH0 0000
EEADRH3 EEADRH2 EEADRH1 EEADRH0 0000 1111 -0000 0000 0000 0000 -000 0000 -000
Unimplemented
Unimplemented Unimplemented ANS7 ANS6 ANS5 ANS4 ANS3(3) ANS11 ANS2(3) ANS10 ANS1 ANS9 ANS0 ANS8
1111 1111 1111
Legend: Note
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented MCLR Reset does affect previous value data latch. RABIF will cleared upon Reset will again mismatch exists. PIC16F685/PIC16F689/PIC16F690 only. only. Port pins with analog functions controlled ANSEL ANSELH registers will read immediately after Reset even though data latches either undefined (POR) unchanged (other Resets).
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TABLE 2-4:
Addr Bank 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note INDF OPTION_REG STATUS TRISA TRISB TRISC PCLATH INTCON EECON1 EECON2 PSTRCON(2) SRCON Addressing this location uses contents address data memory (not physical register) xxxx xxxx RABPU TRISB7 TRISC7 INTEDG TRISB6 TRISC6 T0CS TRISA5 TRISB5 TRISC5 T0SE TRISA4 TRISB4 TRISC4 TRISA3 TRISC3 TRISA2 TRISC2 TRISA1 TRISC1 TRISA0 TRISC0 1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 -1111 1111 PEIE T0IE Write Buffer upper bits Program Counter INTE RABIE WRERR T0IF WREN INTF RABIF(1) 0000 0000 000x x000 C1SEN STRSYNC C2REN STRD PULSS STRC PULSR STRB STRA 0001 0000 Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer 44,205 37,205 44,205 36,205 44,205 59,205 70,206 76,206 44,205 38,205 121,206 119,206 146,206 103,206 Name
PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
Unimplemented Unimplemented EEPGD(2) Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
EEPROM Control Register (not physical register)
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented MCLR Reset does affect previous value data latch. RABIF will cleared upon Reset will again mismatch exists. PIC16F685/PIC16F690 only.
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2.2.2.1 STATUS Register
STATUS register, shown Register 2-1, contains: arithmetic status Reset status bank select bits data memory (GPR SFR) STATUS register destination instruction, like other register. STATUS register destination instruction that affects bits, then write these three bits disabled. These bits cleared according device logic. Furthermore, bits writable. Therefore, result instruction with STATUS register destination different than intended. example, CLRF STATUS, will clear upper three bits bit. This leaves STATUS register `000u u1uu' (where unchanged). recommended, therefore, that only BCF, BSF, SWAPF MOVWF instructions used alter STATUS register, because these instructions affect Status bits. other instructions affecting Status bits, Section 15.0 "Instruction Summary" Note bits operate Borrow Digit Borrow bit, respectively, subtraction. SUBLW SUBWF instructions examples.
REGISTER 2-1:
R/W-0 Legend: Readable Value
STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-x R/W-x DC(1) R/W-x C(1)
Writable
Unimplemented bit, read cleared unknown
IRP: Register Bank Select (used indirect addressing) Bank (100h-1FFh) Bank (00h-FFh) RP<1:0>: Register Bank Select bits (used direct addressing) Bank (00h-7Fh) Bank (80h-FFh) Bank (100h-17Fh) Bank (180h-1FFh) Time-out After power-up, CLRWDT instruction SLEEP instruction time-out occurred Power-down After power-up CLRWDT instruction execution SLEEP instruction Zero result arithmetic logic operation zero result arithmetic logic operation zero Digit Carry/Borrow (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) carry-out from low-order result occurred carry-out from low-order result Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) carry-out from Most Significant result occurred carry-out from Most Significant result occurred Borrow, polarity reversed. subtraction executed adding two's complement second operand. rotate (RRF, RLF) instructions, this loaded with either high-order low-order source register.
Note
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2.2.2.2 OPTION Register
Note: achieve prescaler assignment Timer0, assign prescaler setting OPTION register `1'. Section "Timer1 Prescaler". OPTION register, shown Register 2-2, readable writable register, which contains various control bits configure: Timer0/WDT prescaler External RA2/INT interrupt Timer0 Weak pull-ups PORTA/PORTB
REGISTER 2-2:
R/W-1 RABPU Legend: Readable Value
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 R/W-1 R/W-1 R/W-1
Writable
Unimplemented bit, read cleared unknown
RABPU: PORTA/PORTB Pull-up Enable PORTA/PORTB pull-ups disabled PORTA/PORTB pull-ups enabled individual PORT latch values INTEDG: Interrupt Edge Select Interrupt rising edge RA2/INT Interrupt falling edge RA2/INT T0CS: Timer0 Clock Source Select Transition RA2/T0CKI Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select Increment high-to-low transition RA2/T0CKI Increment low-to-high transition RA2/T0CKI PSA: Prescaler Assignment Prescaler assigned Prescaler assigned Timer0 module PS<2:0>: Prescaler Rate Select bits
Value Timer0 Rate Rate
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2.2.2.3 INTCON Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable global enable bit, INTCON register. User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. INTCON register, shown Register 2-3, readable writable register, which contains various enable flag bits TMR0 register overflow, PORTA change external RA2/AN2/T0CKI/INT/C1OUT interrupts.
REGISTER 2-3:
R/W-0 Legend: Readable Value
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RABIE(1,3) R/W-0 T0IF(2) R/W-0 INTF R/W-x RABIF
Writable
Unimplemented bit, read cleared unknown
GIE: Global Interrupt Enable Enables unmasked interrupts Disables interrupts PEIE: Peripheral Interrupt Enable Enables unmasked peripheral interrupts Disables peripheral interrupts T0IE: Timer0 Overflow Interrupt Enable Enables Timer0 interrupt Disables Timer0 interrupt INTE: RA2/INT External Interrupt Enable Enables RA2/INT external interrupt Disables RA2/INT external interrupt RABIE: PORTA/PORTB Change Interrupt Enable bit(1,3) Enables PORTA/PORTB change interrupt Disables PORTA/PORTB change interrupt T0IF: Timer0 Overflow Interrupt Flag bit(2) TMR0 register overflowed (must cleared software) TMR0 register overflow INTF: RA2/INT External Interrupt Flag RA2/INT external interrupt occurred (must cleared software) RA2/INT external interrupt occur RABIF: PORTA/PORTB Change Interrupt Flag When least PORTA PORTB general purpose pins changed state (must cleared software) None PORTA PORTB general purpose pins have changed state IOCA IOCB register must also enabled. T0IF when Timer0 rolls over. Timer0 unchanged Reset should initialized before clearing T0IF bit. Includes ULPWU interrupt.
Note
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2.2.2.4 PIE1 Register
Note: PEIE INTCON register must enable peripheral interrupt. PIE1 register contains interrupt enable bits, shown Register 2-4.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER
R/W-0 ADIE(5) R/W-0 RCIE(3) R/W-0 TXIE(3) R/W-0 SSPIE(4) R/W-0 CCP1IE(2) R/W-0 TMR2IE(1) R/W-0 TMR1IE
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
Unimplemented: Read ADIE: Converter (ADC) Interrupt Enable bit(5) Enables interrupt Disables interrupt RCIE: EUSART Receive Interrupt Enable bit(3) Enables EUSART receive interrupt Disables EUSART receive interrupt TXIE: EUSART Transmit Interrupt Enable bit(5) Enables EUSART transmit interrupt Disables EUSART transmit interrupt SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit(4) Enables interrupt Disables interrupt CCP1IE: CCP1 Interrupt Enable bit(2) Enables CCP1 interrupt Disables CCP1 interrupt TMR2IE: Timer2 Match Interrupt Enable bit(1) Enables Timer2 match interrupt Disables Timer2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable Enables Timer1 overflow interrupt Disables Timer1 overflow interrupt PIC16F685/PIC16F690 only. PIC16F685/PIC16F689/PIC16F690 only. PIC16F687/PIC16F689/PIC16F690 only. only. only.
Note
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2.2.2.5 PIE2 Register
Note: PEIE INTCON register must enable peripheral interrupt. PIE2 register contains interrupt enable bits, shown Register 2-5.
REGISTER 2-5:
R/W-0 OSFIE Legend: Readable Value
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER
R/W-0 C2IE R/W-0 C1IE R/W-0 EEIE
Writable
Unimplemented bit, read cleared unknown
OSFIE: Oscillator Fail Interrupt Enable Enables oscillator fail interrupt Disables oscillator fail interrupt C2IE: Comparator Interrupt Enable Enables Comparator interrupt Disables Comparator interrupt C1IE: Comparator Interrupt Enable Enables Comparator interrupt Disables Comparator interrupt EEIE: Write Operation Interrupt Enable Enables write operation interrupt Disables write operation interrupt Unimplemented: Read
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2.2.2.6 PIR1 Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable global enable bit, INTCON register. User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. PIR1 register contains interrupt flag bits, shown Register 2-6.
REGISTER 2-6:
Legend: Readable Value
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER
R/W-0 ADIF(5) RCIF
TXIF
R/W-0 SSPIF
R/W-0 CCP1IF
R/W-0 TMR2IF
R/W-0 TMR1IF
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read ADIF: Converter Interrupt Flag bit(5) conversion complete (must cleared software) conversion completed been started RCIF: EUSART Receive Interrupt Flag bit(3) EUSART receive buffer full (cleared reading RCREG) EUSART receive buffer full TXIF: EUSART Transmit Interrupt Flag bit(3) EUSART transmit buffer empty (cleared writing TXREG) EUSART transmit buffer full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit(4) Transmission/Reception complete (must cleared software) Waiting Transmit/Receive CCP1IF: CCP1 Interrupt Flag bit(2) Capture mode: TMR1 register capture occurred (must cleared software) TMR1 register capture occurred Compare mode: TMR1 register compare match occurred (must cleared software) TMR1 register compare match occurred mode: Unused this mode TMR2IF: Timer2 Interrupt Flag bit(1) Timer2 match occurred (must cleared software) Timer2 match occurred TMR1IF: Timer1 Overflow Interrupt Flag TMR1 register overflowed (must cleared software) TMR1 register overflow PIC16F685/PIC16F690 only. PIC16F685/PIC16F689/PIC16F690 only. PIC16F687/PIC16F689/PIC16F690 only. only. only.
Note
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2.2.2.7 PIR2 Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable global enable bit, INTCON register. User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. PIR2 register contains interrupt flag bits, shown Register 2-7.
REGISTER 2-7:
R/W-0 OSFIF Legend: Readable Value
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER
R/W-0 C2IF R/W-0 C1IF R/W-0 EEIF
Writable
Unimplemented bit, read cleared unknown
OSFIF: Oscillator Fail Interrupt Flag System oscillator failed, clock input changed INTOSC (must cleared software) System clock operating C2IF: Comparator Interrupt Flag Comparator output (C2OUT bit) changed (must cleared software) Comparator output (C2OUT bit) changed C1IF: Comparator Interrupt Flag Comparator output (C1OUT bit) changed (must cleared software) Comparator output (C1OUT bit) changed EEIF: Write Operation Interrupt Flag Write operation completed (must cleared software) Write operation completed started Unimplemented: Read
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2.2.2.8 PCON Register
Power Control (PCON) register (see Register 2-8) contains flag bits differentiate between Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
PCON register also controls Ultra Low-Power Wake-up software enable BOR.
REGISTER 2-8:
Legend: Readable Value
PCON: POWER CONTROL REGISTER
R/W-0 ULPWUE R/W-1 SBOREN(1) R/W-0 R/W-x
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read ULPWUE: Ultra Low-Power Wake-up Enable Ultra Low-Power Wake-up enabled Ultra Low-Power Wake-up disabled SBOREN: Software Enable bit(1) enabled disabled Unimplemented: Read POR: Power-on Reset Status Power-on Reset occurred Power-on Reset occurred (must software after Power-on Reset occurs) BOR: Brown-out Reset Status Brown-out Reset occurred Brown-out Reset occurred (must software after Brown-out Reset occurs) BOREN<1:0> Configuration Word register this control BOR.
Note
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PCLATH
2.3.2 STACK
Program Counter (PC) bits wide. byte comes from register, which readable writable register. high byte (PC<12:8>) directly readable writable comes from PCLATH. Reset, cleared. Figure shows situations loading upper example Figure shows loaded write (PCLATH<4:0> PCH). lower example Figure shows loaded during CALL GOTO instruction (PCLATH<4:3> PCH). PIC16F631/677/685/687/689/690 devices have 8-level 13-bit wide hardware stack (see Figures 2-3). stack space part either program data space Stack Pointer readable writable. PUSHed onto stack when CALL instruction executed interrupt causes branch. stack POPed event RETURN, RETLW RETFIE instruction execution. PCLATH affected PUSH operation. stack operates circular buffer. This means that after stack been PUSHed eight times, ninth push overwrites value that stored from first push. tenth push overwrites second push (and on). Note There Status bits indicate stack overflow stack underflow conditions. There instructions/mnemonics called PUSH POP. These actions that occur from execution CALL, RETURN, RETLW RETFIE instructions vectoring interrupt address.
FIGURE 2-9:
LOADING DIFFERENT SITUATIONS
Instruction with Destination Result
PCLATH<4:0>
PCLATH PCLATH<4:3> GOTO, CALL OPCODE<10:0>
Indirect Addressing, INDF Registers
PCLATH
INDF register physical register. Addressing INDF register will cause indirect addressing. Indirect addressing possible using INDF register. instruction using INDF register actually accesses data pointed File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing INDF register indirectly results operation (although Status bits affected). effective 9-bit address obtained concatenating 8-bit STATUS register, shown Figure 2-10. simple program clear location 20h-2Fh using indirect addressing shown Example 2-1.
2.3.1
MODIFYING
Executing instruction with register destination simultaneously causes Program Counter PC<12:8> bits (PCH) replaced contents PCLATH register. This allows entire contents program counter changed writing desired upper bits PCLATH register. When lower bits written register, bits program counter will change values contained PCLATH register those being written register. computed GOTO accomplished adding offset program counter (ADDWF PCL). Care should exercised when jumping into look-up table program branch table (computed GOTO) modifying register. Assuming that PCLATH table start address, table length greater than instructions lower bits memory address rolls over from 0xFF 0x00 middle table, then PCLATH must incremented each address rollover that occurs between table beginning target location within table. more information refer Application Note AN556, "Implementing Table Read" (DS00556).
EXAMPLE 2-1:
MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE
INDIRECT ADDRESSING
0x20 INDF FSR,4 NEXT ;initialize pointer ;clear INDF register ;inc pointer ;all done? clear next ;yes continue
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FIGURE 2-10: DIRECT/INDIRECT ADDRESSING PIC16F631/677/685/687/689/690
Indirect Addressing File Select Register Direct Addressing From Opcode
Bank Select
Location Select
Bank Select 180h
Location Select
Data Memory
Bank Bank Bank Bank
1FFh
memory detail, Figures 2-6, 2-8.
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NOTES:
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OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)
Overview
Oscillator module configured eight clock modes. External clock with OSC2/CLKOUT. Low-Power Crystal mode. Medium Gain Crystal Ceramic Resonator Oscillator mode. High Gain Crystal Ceramic Resonator mode. External Resistor-Capacitor (RC) with FOSC/4 output OSC2/CLKOUT. RCIO External Resistor-Capacitor (RC) with OSC2/CLKOUT. INTOSC Internal oscillator with FOSC/4 output OSC2 OSC1/CLKIN. INTOSCIO Internal oscillator with OSC1/CLKIN OSC2/CLKOUT.
Oscillator module wide variety clock sources selection features that allow used wide range applications while maximizing performance minimizing power consumption. Figure illustrates block diagram Oscillator module. Clock sources configured from external oscillators, quartz crystal resonators, ceramic resonators Resistor-Capacitor (RC) circuits. addition, system clock source configured from internal oscillators, with choice speeds selectable software. Additional clock features include: Selectable system clock source between external internal software. Two-Speed Start-up mode, which minimizes latency between external oscillator start-up code execution. Fail-Safe Clock Monitor (FSCM) designed detect failure external clock source (LP, modes) switch automatically internal oscillator.
Clock Source modes configured FOSC<2:0> bits Configuration Word register (CONFIG). internal clock generated from internal oscillators. HFINTOSC calibrated highfrequency oscillator. LFINTOSC uncalibrated low-frequency oscillator.
FIGURE 3-1:
SIMPLIFIED PIC® CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0> (Configuration Word Register) SCS<0> (OSCCON Register)
External Oscillator OSC2 Sleep OSC1
RCIO, INTOSC
IRCF<2:0> (OSCCON Register) Internal Oscillator Postscaler HFINTOSC LFINTOSC
System Clock (CPU Peripherals)
Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
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Oscillator Control
Oscillator Control (OSCCON) register (Figure 3-1) controls system clock frequency selection options. OSCCON register contains following bits: Frequency selection bits (IRCF) Frequency Status bits (HTS, LTS) System clock control bits (OSTS, SCS)
REGISTER 3-1:
Legend: Readable Value
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 OSTS(1) R/W-0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read IRCF<2:0>: Internal Oscillator Frequency Select bits (default) (LFINTOSC) OSTS: Oscillator Start-up Time-out Status bit(1) Device running from clock defined FOSC<2:0> CONFIG register Device running from internal oscillator (HFINTOSC LFINTOSC) HTS: HFINTOSC Status (High Frequency kHz) HFINTOSC stable HFINTOSC stable LTS: LFINTOSC Stable (Low Frequency kHz) LFINTOSC stable LFINTOSC stable SCS: System Clock Select Internal oscillator used system clock Clock source defined FOSC<2:0> CONFIG register resets with Two-Speed Start-up selected Oscillator mode Fail-Safe mode enabled.
Note
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Clock Source Modes
3.4.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
Clock Source modes classified external internal. External Clock modes rely external circuitry clock source. Examples are: Oscillator modules mode), quartz crystal resonators ceramic resonators (LP, modes) Resistor-Capacitor (RC) mode circuits. Internal clock sources contained internally within Oscillator module. Oscillator module internal oscillators: High-Frequency Internal Oscillator (HFINTOSC) Low-Frequency Internal Oscillator (LFINTOSC). system clock selected between external internal clock sources System Clock Select (SCS) OSCCON register. Section "Clock Switching" additional information.
Oscillator module configured modes, Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following Power-on Reset (POR) when Power-up Timer (PWRT) expired configured), wake-up from Sleep. During this time, program counter does increment program execution suspended. ensures that oscillator circuit, using quartz crystal resonator ceramic resonator, started providing stable system clock Oscillator module. When switching between clock sources, delay required allow clock stabilize. These oscillator delays shown Table 3-1. order minimize latency between external oscillator start-up code execution, Two-Speed Clock Start-up mode selected (see Section "TwoSpeed Clock Start-up Mode").
TABLE 3-1:
Switch From Sleep/POR Sleep/POR
OSCILLATOR DELAY EXAMPLES
Switch LFINTOSC HFINTOSC HFINTOSC Frequency Oscillator Delay Oscillator Warm-up Delay (TWARM) cycles cycle each 1024 Clock Cycles (OST) (approx.)
LFINTOSC kHz) Sleep/POR LFINTOSC kHz)
3.4.2
MODE
FIGURE 3-2:
External Clock (EC) mode allows externally generated logic level system clock source. When operating this mode, external clock source connected OSC1 input OSC2 available general purpose I/O. Figure shows connections mode. Oscillator Start-up Timer (OST) disabled when mode selected. Therefore, there delay operation after Power-on Reset (POR) wake-up from Sleep. Because PIC® design fully static, stopping external clock input will have effect halting device while leaving data intact. Upon restarting external clock, device will resume operation time elapsed.
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC® OSC2/CLKOUT(1)
Clock from Ext. System
Note
Alternate functions listed Section "Device Overview".
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3.4.3 MODES
modes support quartz crystal resonators ceramic resonators connected OSC1 OSC2 (Figure 3-3). mode selects low, medium high gain setting internal inverteramplifier support various resonator types speed. Oscillator mode selects lowest gain setting internal inverter-amplifier. mode current consumption least three modes. This mode designed drive only 32.768 tuning-fork type crystals (watch crystals). Oscillator mode selects intermediate gain setting internal inverter-amplifier. mode current consumption medium three modes. This mode best suited drive resonators with medium drive level specification. Oscillator mode selects highest gain setting internal inverter-amplifier. mode current consumption highest three modes. This mode best suited resonators that require high drive setting. Figure Figure show typical circuits quartz crystal ceramic resonators, respectively. Note Quartz crystal characteristics vary according type, package manufacturer. user should consult manufacturer data sheets specifications recommended application. Always verify oscillator performance over temperature range that expected application. oscillator design assistance, reference following Microchip Applications Notes: AN826, "Crystal Oscillator Basics Crystal Selection rfPIC® PIC® Devices" (DS00826) AN849, "Basic PIC® Oscillator Design" (DS00849) AN943, "Practical PIC® Oscillator Analysis Design" (DS00943) AN949, "Making Your Oscillator Work" (DS00949)
FIGURE 3-4:
FIGURE 3-3:
QUARTZ CRYSTAL OPERATION (LP, MODE)
PIC®
OSC1/CLKIN
CERAMIC RESONATOR OPERATION MODE)
PIC®
OSC1/CLKIN Internal Logic RP(3) RF(2) Sleep
Quartz Crystal RF(2)
Internal Logic Sleep
Ceramic RS(1) Resonator OSC2/CLKOUT
OSC2/CLKOUT
RS(1)
Note
series resistor (RS) required ceramic resonators with drive level.
Note
series resistor (RS) required quartz crystals with drive level. value varies with Oscillator mode selected (typically between
value varies with Oscillator mode selected (typically between additional parallel feedback resistor (RP) required proper ceramic resonator operation.
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3.4.4 EXTERNAL MODES
Internal Clock Modes
external Resistor-Capacitor (RC) modes support external circuit. This allows designer maximum flexibility frequency choice while keeping costs minimum when clock accuracy required. There modes: RCIO. mode, circuit connects OSC1. OSC2/ CLKOUT outputs oscillator frequency divided This signal used provide clock external circuitry, synchronization, calibration, test other application requirements. Figure shows external mode connections.
Oscillator module independent, internal oscillators that configured selected system clock source. HFINTOSC (High-Frequency Internal Oscillator) factory calibrated operates MHz. frequency HFINTOSC user-adjusted software using OSCTUNE register (Register 3-2). LFINTOSC (Low-Frequency Internal Oscillator) uncalibrated operates kHz.
FIGURE 3-5:
REXT
EXTERNAL MODES
PIC®
system clock speed selected software using Internal Oscillator Frequency Select bits IRCF<2:0> OSCCON register. system clock selected between external internal clock sources System Clock Selection (SCS) OSCCON register. Section "Clock Switching" more information.
OSC1/CLKIN CEXT FOSC/4 I/O(2) OSC2/CLKOUT
Internal Clock
3.5.1
INTOSC INTOSCIO MODES
Recommended values: REXT REXT 3-5V CEXT 2-5V Note Alternate functions listed Section "Device Overview". Output depends upon RCIO Clock mode.
INTOSC INTOSCIO modes configure internal oscillators system clock source when device programmed using oscillator selection FOSC<2:0> bits Configuration Word register (CONFIG). INTOSC mode, OSC1/CLKIN available general purpose I/O. OSC2/CLKOUT outputs selected internal oscillator frequency divided CLKOUT signal used provide clock external circuitry, synchronization, calibration, test other application requirements. INTOSCIO mode, OSC1/CLKIN OSC2/CLKOUT available general purpose I/O.
RCIO mode, circuit connected OSC1. OSC2 becomes additional general purpose pin. oscillator frequency function supply voltage, resistor (REXT) capacitor (CEXT) values operating temperature. Other factors affecting oscillator frequency are: threshold voltage variation component tolerances packaging variations capacitance user also needs take into account variation tolerance external components used.
3.5.2
HFINTOSC
High-Frequency Internal Oscillator (HFINTOSC) factory calibrated internal clock source. frequency HFINTOSC altered software using OSCTUNE register (Register 3-2). output HFINTOSC connects postscaler multiplexer (see Figure 3-1). seven frequencies selected software using IRCF<2:0> bits OSCCON register. Section 3.5.4 "Frequency Select Bits (IRCF)" more information. HFINTOSC enabled selecting frequency between setting IRCF<2:0> bits OSCCON register 000. Then, System Clock Source (SCS) OSCCON register enable Two-Speed Start-up setting IESO Configuration Word register (CONFIG) `1'. Internal Oscillator (HTS) OSCCON register indicates whether HFINTOSC stable not.
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3.5.2.1 OSCTUNE Register
HFINTOSC factory calibrated adjusted software writing OSCTUNE register (Register 3-2). default value OSCTUNE register `0'. value 5-bit two's complement number. When OSCTUNE register modified, HFINTOSC frequency will begin shifting frequency. Code execution continues during this shift. There indication that shift occurred. OSCTUNE does affect LFINTOSC frequency. Operation features that depend LFINTOSC clock source frequency, such Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) peripherals, affected change frequency.
REGISTER 3-2:
Legend: Readable Value
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read TUN<4:0>: Frequency Tuning bits 01111 Maximum frequency 01110 00001 00000 Oscillator module running factory-calibrated frequency. 11111 10000 Minimum frequency
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3.5.3 LFINTOSC 3.5.5
Low-Frequency Internal Oscillator (LFINTOSC) uncalibrated internal clock source. output LFINTOSC connects postscaler multiplexer (see Figure 3-1). Select kHz, software, using IRCF<2:0> bits OSCCON register. Section 3.5.4 "Frequency Select Bits (IRCF)" more information. LFINTOSC also frequency Power-up Timer (PWRT), Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM). LFINTOSC enabled selecting (IRCF<2:0> bits OSCCON register 000) system clock source (SCS OSCCON register when following enabled: Two-Speed Start-up IESO Configuration Word register IRCF<2:0> bits OSCCON register Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) Internal Oscillator (LTS) OSCCON register indicates whether LFINTOSC stable not.
HFINTOSC LFINTOSC CLOCK SWITCH TIMING
When switching between LFINTOSC HFINTOSC, oscillator already shut down save power (see Figure 3-6). this case, there delay after IRCF<2:0> bits OSCCON register modified before frequency selection takes place. bits OSCCON register will reflect current active status LFINTOSC HFINTOSC oscillators. timing frequency selection follows: IRCF<2:0> bits OSCCON register modified. clock shut down, clock start-up delay started. Clock switch circuitry waits falling edge current clock. CLKOUT held clock switch circuitry waits rising edge clock. CLKOUT connected with clock. bits OSCCON register updated required. Clock switch complete.
Figure more details. internal oscillator speed selected between kHz, there start-up delay before frequency selected. This because frequencies derived from HFINTOSC postscaler multiplexer. Start-up delay specifications located oscillator tables Section 17.0 "Electrical Specifications".
3.5.4
FREQUENCY SELECT BITS (IRCF)
output HFINTOSC LFINTOSC connects postscaler multiplexer (see Figure 3-1). Internal Oscillator Frequency Select bits IRCF<2:0> OSCCON register select frequency output internal oscillators. eight frequencies selected software: (Default after Reset) (LFINTOSC) Note: Following Reset, IRCF<2:0> bits OSCCON register `110' frequency selection MHz. user modify IRCF bits select different frequency.
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FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC HFINTOSC
LFINTOSC (FSCM disabled)
Start-up Time
2-cycle Sync
Running
LFINTOSC IRCF <2:0> System Clock
HFINTOSC HFINTOSC
LFINTOSC (Either FSCM enabled)
2-cycle Sync
Running
LFINTOSC IRCF <2:0> System Clock
LFINTOSC LFINTOSC
HFINTOSC
LFINTOSC turns unless FSCM enabled
Start-up Time
2-cycle Sync
Running
HFINTOSC IRCF <2:0> System Clock
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Clock Switching
system clock source switched between external internal clock sources software using System Clock Select (SCS) OSCCON register. When Oscillator module configured modes, Oscillator Start-up Timer (OST) enabled (see Section 3.4.1 "Oscillator Start-up Timer (OST)"). will suspend program execution until 1024 oscillations counted. Two-Speed Start-up mode minimizes delay code execution operating from internal oscillator counting. When count reaches 1024 OSTS OSCCON register set, program execution switches external oscillator.
3.6.1
SYSTEM CLOCK SELECT (SCS)
System Clock Select (SCS) OSCCON register selects system clock source that used peripherals. When OSCCON register system clock source determined configuration FOSC<2:0> bits Configuration Word register (CONFIG). When OSCCON register system clock source chosen internal oscillator frequency selected IRCF<2:0> bits OSCCON register. After Reset, OSCCON register always cleared. Note: automatic clock switch, which occur from Two-Speed Start-up Fail-Safe Clock Monitor, does update OSCCON register. user monitor OSTS OSCCON register determine current system clock source.
3.7.1
TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode configured following settings: IESO Configuration Word register) Internal/External Switchover (Two-Speed Startup mode enabled). OSCCON register) FOSC<2:0> bits Configuration Word register (CONFIG) configured mode. Two-Speed Start-up mode entered after: Power-on Reset (POR) and, enabled, after Power-up Timer (PWRT) expired, Wake-up from Sleep. external clock oscillator configured anything other than mode, then Twospeed Start-up disabled. This because external clock oscillator does require stabilization time after exit from Sleep.
3.6.2
OSCILLATOR START-UP TIME-OUT STATUS (OSTS)
Oscillator Start-up Time-out Status (OSTS) OSCCON register indicates whether system clock running from external clock source, defined FOSC<2:0> bits Configuration Word register (CONFIG), from internal clock source. particular, OSTS indicates that Oscillator Start-up Timer (OST) timed modes.
3.7.2
TWO-SPEED START-UP SEQUENCE
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power savings minimizing latency between external oscillator start-up code execution. applications that make heavy Sleep mode, Two-Speed Start-up will remove external oscillator start-up time from time spent awake reduce overall power consumption device. This mode allows application wake-up from Sleep, perform instructions using INTOSC clock source back Sleep without waiting primary oscillator become stable. Note: Executing SLEEP instruction will abort oscillator start-up time will cause OSTS OSCCON register remain clear.
Wake-up from Power-on Reset Sleep. Instructions begin execution internal oscillator frequency IRCF<2:0> bits OSCCON register. enabled count 1024 clock cycles. timed out, wait falling edge internal oscillator. OSTS set. System clock held until next falling edge clock (LP, mode). System clock switched external clock source.
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3.7.3 CHECKING TWO-SPEED CLOCK STATUS
Checking state OSTS OSCCON register will confirm microcontroller running from external clock source, defined FOSC<2:0> bits Configuration Word register (CONFIG), internal oscillator.
FIGURE 3-7:
TWO-SPEED START-UP
HFINTOSC TOST OSC1 1022 1023
OSC2 Program Counter
System Clock
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Fail-Safe Clock Monitor
3.8.3 FAIL-SAFE CONDITION CLEARING
Fail-Safe Clock Monitor (FSCM) allows device continue operating should external oscillator fail. FSCM detect oscillator failure time after Oscillator Start-up Timer (OST) expired. FSCM enabled setting FCMEN Configuration Word register (CONFIG). FSCM applicable external Oscillator modes (LP, RCIO). Fail-Safe condition cleared after Reset, executing SLEEP instruction toggling OSCCON register. When toggled, restarted. While running, device continues operate from INTOSC selected OSCCON. When times out, Fail-Safe condition cleared device will operating from external clock source. Fail-Safe condition must cleared before OSFIF flag cleared.
FIGURE 3-8:
FSCM BLOCK DIAGRAM
Clock Monitor Latch
3.8.4
RESET WAKE-UP FROM SLEEP
External Clock
LFINTOSC Oscillator (~32
FSCM designed detect oscillator failure after Oscillator Start-up Timer (OST) expired. used after waking from Sleep after type Reset. used with Clock modes that FSCM will active soon Reset wake-up completed. When FSCM enabled, Two-Speed Start-up also enabled. Therefore, device will always executing code while operating. Note:
Clock Failure Detected
Sample Clock
3.8.1
FAIL-SAFE DETECTION
FSCM module detects failed oscillator comparing external oscillator FSCM sample clock. sample clock generated dividing LFINTOSC Figure 3-8. Inside fail detector block latch. external clock sets latch each falling edge external clock. sample clock clears latch each rising edge sample clock. failure detected when entire halfcycle sample clock elapses before primary clock goes low.
wide range oscillator start-up times, Fail-Safe circuit active during oscillator start-up (i.e., after exiting Reset Sleep). After appropriate amount time, user should check OSTS OSCCON register verify oscillator start-up that system clock switchover successfully completed.
3.8.2
FAIL-SAFE OPERATION
When external clock fails, FSCM switches device clock internal clock source sets flag OSFIF PIR2 register. Setting this flag will generate interrupt OSFIE PIE2 register also set. device firmware then take steps mitigate problems that arise from failed clock. system clock will continue sourced from internal clock source until device firmware successfully restarts external oscillator switches back external operation. internal clock source chosen FSCM determined IRCF<2:0> bits OSCCON register. This allows internal oscillator configured before failure occurs.
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FIGURE 3-9:
Sample Clock System Clock Output Clock Monitor Output OSCFIF Oscillator Failure
FSCM TIMING DIAGRAM
Failure Detected
Test Note:
Test
Test
system clock normally much higher frequency than sample clock. relative frequencies this example have been chosen clarity.
TABLE 3-2:
Name CONFIG(2) OSCCON OSCTUNE PIE1 PIR1 Legend: Note
SUMMARY REGISTERS ASSOCIATED WITH CLOCK SOURCES
IRCF2 ADIE ADIF MCLRE IRCF1 RCIE RCIF PWRTE IRCF0 TUN4 TXIE TXIF WDTE OSTS TUN3 SSPIE SSPIF FOSC2 TUN2 CCP1IE CCP1IF FOSC1 TUN1 TMR2IE TMR2IF FOSC0 TUN0 TMR1IE TMR1IF Value POR, -110 x000 0000 -000 0000 -000 0000 Value other Resets(1) -110 x000 uuuu -000 0000 -000 0000
unknown, unchanged, unimplemented locations read `0'. Shaded cells used oscillators. Other (non Power-up) Resets include MCLR Reset Watchdog Timer Reset during normal operation. Configuration Word register (Register 14-1) operation register bits.
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PORTS
There many eighteen general purpose pins available. Depending which peripherals enabled, some pins available general purpose I/O. general, when peripheral enabled, associated used general purpose pin. port pins read, this value modified then written PORT data latch. reads when MCLRE TRISA register controls PORTA output drivers, even when they being used analog inputs. user should ensure bits TRISA register maintained when using them analog inputs. pins configured analog input always read `0'. Note: ANSEL register must initialized configure analog channel digital input. Pins configured analog inputs will read `0'.
PORTA TRISA Registers
PORTA 6-bit wide, bidirectional port. corresponding data direction register TRISA (Register 4-2). Setting TRISA will make corresponding PORTA input (i.e., disable output driver). Clearing TRISA will make corresponding PORTA output (i.e., enables output driver puts contents output latch selected pin). exception RA3, which input only TRIS will always read `1'. Example shows initialize PORTA. Reading PORTA register (Register 4-1) reads status pins, whereas writing will write PORT latch. write operations read-modify-write operations. Therefore, write port implies that
EXAMPLE 4-1:
CLRF CLRF MOVLW MOVWF STATUS,RP0 STATUS,RP1 PORTA STATUS,RP1 ANSEL STATUS,RP0 STATUS,RP1 TRISA STATUS,RP0
INITIALIZING PORTA
;Bank ;Init PORTA ;Bank ;digital ;Bank ;Set RA<3:2> inputs ;and RA<5:4,1:0> outputs ;Bank
REGISTER 4-1:
Legend: Readable Value
PORTA: PORTA REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read RA<5:0>: PORTA Port Port
REGISTER 4-2:
Legend: Readable Value
TRISA: PORTA TRI-STATE REGISTER
R/W-1 TRISA5 R/W-1 TRISA4 TRISA3 R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read TRISA<5:0>: PORTA Tri-State Control PORTA configured input (tri-stated) PORTA configured output TRISA<3> always reads `1'. TRISA<5:4> always reads Oscillator modes.
Note
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Additional Functions
4.2.3 INTERRUPT-ON-CHANGE
Every PORTA this device family interrupt-on-change option weak pull-up option. also Ultra Low-Power Wake-up option. next three sections describe these functions. Each PORTA individually configurable interrupt-on-change pin. Control bits IOCAx enable disable interrupt function each pin. Refer Register 4-6. interrupt-on-change disabled Power-on Reset. enabled interrupt-on-change pins, values compared with value latched last read PORTA. `mismatch' outputs last read OR'd together PORTA Change Interrupt Flag (RABIF) INTCON register (Register 2-6). This interrupt wake device from Sleep. user, Interrupt Service Routine, clears interrupt read write PORTA. This will mismatch condition, then, Clear flag RABIF.
4.2.1
ANSEL ANSELH REGISTERS
ANSEL ANSELH registers used disable input buffers pins, which allow analog voltages applied those pins without causing excessive current. Setting ANSx corresponding will cause digital reads that return also permit analog functions that operate correctly. state ANSx effect digital output function corresponding pin. with TRISx clear ANSx will operate digital output, together with analog input function that pin. Pins with ANSx always read `0', which cause unexpected behavior when executing read write operations port read-modify-write sequence such operations.
4.2.2
WEAK PULL-UPS
Each PORTA pins, except RA3, individually configurable internal weak pull-up. Control bits WPUAx enable disable each pull-up. Refer Register 4-4. Each weak pull-up automatically turned when port configured output. pull-ups disabled Power-on Reset RABPU OPTION register. weak pull-up automatically enabled when configured MCLR disabled when I/O. There software control MCLR pull-up.
mismatch condition will continue flag RABIF. Reading PORTA will mismatch condition allow flag RABIF cleared. latch holding last read value affected MCLR Reset. After these Resets, RABIF flag will continue mismatch present. Note: change should occur when read operation being executed (start cycle), then RABIF interrupt flag set.
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REGISTER 4-3:
R/W-1 ANS7 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ANSEL: ANALOG SELECT REGISTER
R/W-1 ANS6 R/W-1 ANS5 R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0
ANS<7:0>: Analog Select bits Analog select between analog digital function pins AN<7:0>, respectively. Analog input. assigned analog input(1). Digital I/O. assigned port special function. Setting analog input automatically disables digital input circuitry, weak pull-ups interrupt-on-change available. corresponding TRIS must Input mode order allow external control voltage pin.
Note
REGISTER 4-4:
Legend: Readable Value
ANSELH: ANALOG SELECT HIGH REGISTER(2)
R/W-1 ANS11 R/W-1 ANS10 R/W-1 ANS9 R/W-1 ANS8
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read ANS<11:8>: Analog Select bits Analog select between analog digital function pins AN<7:0>, respectively. Analog input. assigned analog input(1). Digital I/O. assigned port special function. Setting analog input automatically disables digital input circuitry, weak pull-ups interrupt-on-change available. corresponding TRIS must Input mode order allow external control voltage pin. only.
Note
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REGISTER 4-5:
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
WPUA: PORTA REGISTER
R/W-1 WPUA5 R/W-1 WPUA4 R/W-1 WPUA2 R/W-1 WPUA1 R/W-1 WPUA0
Unimplemented: Read WPUA<5:4>: Weak Pull-up Register Pull-up enabled Pull-up disabled Unimplemented: Read WPUA<2:0>: Weak Pull-up Register Pull-up enabled Pull-up disabled Global RABPU OPTION register must enabled individual pull-ups enabled. weak pull-up device automatically disabled Output mode (TRISA pull-up enabled when configured MCLR disabled Configuration Word. WPUA<5:4> always reads Oscillator modes.
Note
REGISTER 4-6:
Legend: Readable Value
IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
R/W-0 IOCA5 R/W-0 IOCA4 R/W-0 IOCA3 R/W-0 IOCA2 R/W-0 IOCA1 R/W-0 IOCA0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read IOCA<5:0>: Interrupt-on-change PORTA Control Interrupt-on-change enabled Interrupt-on-change disabled Global Interrupt Enable (GIE) must enabled individual interrupts recognized. IOCA<5:4> always reads Oscillator modes.
Note
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4.2.4 ULTRA LOW-POWER WAKE-UP
Ultra Low-Power Wake-up (ULPWU) allows slow falling voltage generate interrupt-on-change without excess current consumption. mode selected setting ULPWUE PCON register. This enables small current sink, which used discharge capacitor RA0. Follow these steps this feature: Charge capacitor configuring output Configure input. Enable interrupt-on-change RA0. ULPWUE PCON register begin capacitor discharge. Execute SLEEP instruction. series resistor between external capacitor provides overcurrent protection RA0/AN0/C1IN+/ICSPDAT/ULPWU allow software calibration time-out (see Figure 4-1). timer used measure charge time discharge time capacitor. charge time then adjusted provide desired interrupt delay. This technique will compensate affects temperature, voltage component accuracy. Ultra Low-Power Wake-up peripheral also configured simple Programmable Low-Voltage Detect temperature sensor. Note: more information, refer Application Note AN879, "Using Microchip Ultra Low-Power Wake-up Module" (DS00879).
When voltage drops below VIL, interrupt will generated which will cause device wake-up execute next instruction. INTCON register set, device will then call interrupt vector (0004h). Section 4.4.2 "Interrupt-on-change" Section 14.3.3 "PORTA/PORTB Interrupt" more information. This feature provides low-power technique periodically waking device from Sleep. time-out dependent discharge time circuit RA0. Example initializing Ultra Low-Power Wake-up module.
EXAMPLE 4-2:
CALL MOVLW MOVWF SLEEP
ULTRA LOW-POWER WAKE-UP INITIALIZATION
;Bank ;Set data latch ;Bank ;RA0 digital ;Bank ;Output high ;charge capacitor ;Enable Wake-up ;Select ;RA0 input ;Enable interrupt ;and clear flag ;Bank ;Wait
STATUS,RP0 STATUS,RP1 PORTA,0 STATUS,RP1 ANSEL,0 STATUS,RP0 STATUS,RP1 TRISA,0 CapDelay PCON,ULPWUE IOCA,0 TRISA,0 B'10001000' INTCON STATUS,RP0
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4.2.5 DESCRIPTIONS DIAGRAMS 4.2.5.1 RA0/AN0/C1IN+/ICSPDAT/ULPWU
Each PORTA multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions such comparator Converter (ADC), refer appropriate section this data sheet. Figure shows diagram this pin. RA0/AN0/C1IN+/ICSPDAT/ULPWU configurable function following: general purpose analog input (except PIC16F631) analog input Comparator In-Circuit Serial Programmingdata analog input Ultra Low-Power Wake-up
FIGURE 4-1:
BLOCK DIAGRAM
Analog(1) Input Mode Data WPUA WPUA RABPU Weak
PORTA
TRISA TRISA PORTA IOCA IOCA Interrupt-on-Change IULP Analog(1) Input Mode ULPWUE
PORTA Comparator Converter(2)
Note
ANSEL determines Analog Input mode. implemented PIC16F631.
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4.2.5.2 RA1/AN1/C12IN0-/VREF/ICSPCLK 4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT
Figure shows diagram this pin. RA1/AN1/C12IN0-/VREF/ICSPCLK configurable function following: general purpose analog input (except PIC16F631) analog input Comparator voltage reference input In-Circuit Serial Programming clock Figure shows diagram this pin. RA2/AN2/T0CKI/INT/C1OUT configurable function following: general purpose analog input (except PIC16F631) clock input Timer0 external edge triggered interrupt digital output from Comparator
FIGURE 4-2:
Data WPUA WPUA
BLOCK DIAGRAM
Analog(1) Input Mode Weak RABPU
FIGURE 4-3:
Data WPUA WPUA
BLOCK DIAGRAM
Analog(1) Input Mode Weak RABPU C1OUT Enable
PORTA
PORTA
C1OUT
TRISA TRISA PORTA IOCA IOCA
Analog(1) Input Mode TRISA TRISA PORTA IOCA IOCA
Analog(1) Input Mode
Interrupt-onChange PORTA Comparator Converter(2) Note
Interrupt-onChange
PORTA Timer0 Converter(2)
ANSEL determines Analog Input mode. implemented PIC16F631.
Note
ANSEL determines Analog Input mode. implemented PIC16F631.
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4.2.5.4 RA3/MCLR/VPP 4.2.5.5 RA4/AN3/T1G/OSC2/CLKOUT
Figure shows diagram this pin. RA3/MCLR/VPP configurable function following: general purpose input Master Clear Reset with weak pull-up Figure shows diagram this pin. RA4/AN3/T1G/OSC2/CLKOUT configurable function following: general purpose analog input (except PIC16F631) Timer1 gate input crystal/resonator connection clock output
FIGURE 4-4:
BLOCK DIAGRAM
MCLRE Weak
FIGURE 4-5:
Input
BLOCK DIAGRAM
Analog(3) Input Mode
Data TRISA PORTA IOCA IOCA
Reset
MCLRE
Data WPUA WPUA
CLK(1) Modes Weak
RABPU Oscillator Circuit CLKOUT Enable
MCLRE
OSC1
PORTA
FOSC/4
Interrupt-onChange
PORTA TRISA TRISA PORTA IOCA IOCA
CLKOUT Enable INTOSC/ RC/EC(2) CLKOUT Enable Analog Input Mode
Interrupt-onChange Converter(4)
PORTA
Note modes LPTMR1 CLKOUT Enable. With CLKOUT option. ANSEL determines Analog Input mode. implemented PIC16F631.
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4.2.5.6 RA5/T1CKI/OSC1/CLKIN
Figure shows diagram this pin. RA5/T1CKI/OSC1/CLKIN configurable function following: general purpose Timer1 clock input crystal/resonator connection clock input
FIGURE 4-6:
BLOCK DIAGRAM
INTOSC Mode
Data WPUA WPUA
TMR1LPEN(1) Weak
RABPU Oscillator Circuit OSC2
PORTA
TRISA TRISA PORTA IOCA IOCA INTOSC Mode
Interrupt-onChange
PORTA TMR1 CLKGEN
Note
Timer1 Oscillator enabled. When using Timer1 with oscillator, Schmitt Trigger bypassed.
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TABLE 4-1:
Name ADCON0 ANSEL CM1CON0 INTCON IOCA OPTION_REG PORTA SSPCON T1CON TRISA WPUA Legend:
SUMMARY REGISTERS ASSOCIATED WITH PORTA
ADFM ANS7 C1ON RABPU WCOL T1GINV VCFG ANS6 C1OUT PEIE INTEDG SSPOV TMR1GE CHS3 ANS5 C1OE T0IE IOCA5 T0CS SSPEN TRISA5 WPUA5 CHS2 ANS4 C1POL INTE IOCA4 T0SE TRISA4 WPUA4 CHS1 ANS3 RABIE IOCA3 SSPM3 TRISA3 CHS0 ANS2 T0IF IOCA2 SSPM2 T1SYNC TRISA2 WPUA2 GO/DONE ANS1 C1CH1 INTF IOCA1 SSPM1 TMR1CS TRISA1 WPUA1 ADON ANS0 C1CH0 RABIF IOCA0 SSPM0 TMR1ON TRISA0 WPUA0 Value POR, 0000 0000 1111 1111 0000 -000 0000 000x 0000 1111 1111 xxxx 0000 0000 0000 0000 1111 -111 Value other Resets 0000 0000 1111 1111 0000 -000 0000 000x 0000 1111 1111 uuuu 0000 0000 uuuu uuuu 1111 -111
T1CKPS1 T1CKPS0 T1OSCEN
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTA.
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PORTB TRISB Registers
4.4.1 WEAK PULL-UPS
PORTB 4-bit wide, bidirectional port. corresponding data direction register TRISB (Register 4-6). Setting TRISB will make corresponding PORTB input (i.e., corresponding output driver High-Impedance mode). Clearing TRISB will make corresponding PORTB output (i.e., enable output driver contents output latch selected pin). Example shows initialize PORTB. Reading PORTB register (Register 4-5) reads status pins, whereas writing will write PORT latch. write operations read-modify-write operations. Therefore, write port implies that port pins read, this value modified then written PORT data latch. TRISB register controls PORTB output drivers, even when they being used analog inputs. user should ensure bits TRISB register maintained when using them analog inputs. pins configured analog input always read `0'. Each PORTB pins individually configurable internal weak pull-up. Control bits WPUB<7:4> enable disable each pull-up (see Register 4-9). Each weak pull automatically turned when port configured output. pull-ups disabled Power-on Reset RABPU OPTION register.
4.4.2
INTERRUPT-ON-CHANGE
Four PORTB pins individually configurable interrupt-on-change pin. Control bits IOCB<7:4> enable disable interrupt function each pin. Refer Register 4-10. interrupt-on-change feature disabled Power-on Reset. enabled interrupt-on-change pins, present value compared with value latched last read PORTB determine which bits have changed mismatch value. `mismatch' outputs OR'd together PORTB Change Interrupt flag (RABIF) INTCON register (Register 2-3). This interrupt wake device from Sleep. user, Interrupt Service Routine, clears interrupt read write PORTB. This will mismatch condition. Clear flag RABIF.
EXAMPLE 4-3:
CLRF MOVLW MOVWF STATUS,RP0 STATUS,RP1 PORTB STATUS,RP0 TRISB STATUS,RP0
INITIALIZING PORTB
;Bank ;Init PORTB ;Bank ;Set RB<7:4> inputs ;Bank
Note:
ANSELH register must initialized configure analog channel digital input. Pins configured analog inputs will read `0'.
mismatch condition will continue flag RABIF. Reading writing PORTB will mismatch condition allow flag RABIF cleared. latch holding last read value affected MCLR Brown-out Reset. After these Resets, RABIF flag will continue mismatch present. Note: change should occur when read operation being executed (start cycle), then RABIF interrupt flag set. Furthermore, since read write port affects bits that port, care must taken when using multiple pins Interrupt-on-Change mode. Changes seen while servicing changes another pin.
Additional PORTB Functions
PORTB pins RB<7:4> device family device have interrupt-on-change option weak pull-up option. following three sections describe these PORTB functions.
REGISTER 4-7:
R/W-x Legend: Readable Value
PORTB: PORTB REGISTER
R/W-x R/W-x R/W-x
Writable RB<7:4>: PORTB Port Port Unimplemented: Read
Unimplemented bit, read cleared unknown
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REGISTER 4-8:
R/W-1 TRISB7 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
TRISB: PORTB TRI-STATE REGISTER
R/W-1 TRISB6 R/W-1 TRISB5 R/W-1 TRISB4
TRISB<7:4>: PORTB Tri-State Control PORTB configured input (tri-stated) PORTB configured output Unimplemented: Read
REGISTER 4-9:
R/W-1 WPUB7 Legend: Readable Value
WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 WPUB6 R/W-1 WPUB5 R/W-1 WPUB4
Writable
Unimplemented bit, read cleared unknown
WPUB<7:4>: Weak Pull-up Register Pull-up enabled Pull-up disabled Unimplemented: Read Global RABPU OPTION register must enabled individual pull-ups enabled. weak pull-up device automatically disabled Output mode (TRISB<7:4>
Note
REGISTER 4-10:
R/W-0 IOCB7 Legend: Readable Value
IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 IOCB6 R/W-0 IOCB5 R/W-0 IOCB4
Writable
Unimplemented bit, read cleared unknown
IOCB<7:4>: Interrupt-on-Change PORTB Control Interrupt-on-change enabled Interrupt-on-change disabled Unimplemented: Read
DS41262E-page
2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
4.4.3 DESCRIPTIONS DIAGRAMS 4.4.3.1 RB4/AN10/SDI/SDA
Each PORTB multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions such SSP, I2Cor interrupts, refer appropriate section this data sheet. Figure shows diagram this pin. RB4/AN10/SDI/SDA(1) configurable function following: general purpose analog input (except PIC16F631) data data Note available 16F690 only.
FIGURE 4-7:
Data WPUB WPUB
BLOCK DIAGRAM
Analog(1) Input Mode Weak RABPU
PORTB
SSPEN SSPSR
TRISB TRISB PORTB IOCB IOCB
From
Analog(1) Input Mode
Interrupt-onChange PORTB SSPSR Converter(2)
Available only. Note ANSEL determines Analog Input mode. implemented PIC16F631.
2008 Microchip Technology Inc.
DS41262E-page
PIC16F631/677/685/687/689/690
4.4.3.2 RB5/AN11/RX/DT(1, FIGURE 4-8:
Data WPUB WPUB
BLOCK DIAGRAM
Analog(1) Input Mode Weak RABPU SYNC SPEN
Figure shows diagram this pin. RB5/AN11/RX/DT configurable function following: general purpose analog input (except PIC16F631) asynchronous serial input synchronous serial data Note available PIC16F687/PIC16F689/PIC16F690 only. AN11 implemented PIC16F631.
PORTB
EUSART
TRISB TRISB PORTB IOCB IOCB
From EUSART Analog(1) Input Mode
Interrupt-onChange PORTB EUSART RX/DT Converter(2)
Available PIC16F687/PIC16F689/PIC16F690 only. Note ANSEL determines Analog Input mode. implemented PIC16F631.
DS41262E-page
2008 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
4.4.3.3 RB6/SCK/SCL FIGURE 4-9:
Data WPUB WPUB
BLOCK DIAGRAM
Weak RABPU
Figure shows diagram this pin. RB6/SCK/SCL(1) configurable function following: general purpose clock I2Cclock Note available PIC16F677/PIC16F687/PIC16F689/ PIC16F690 only.
PORTB
SSPEN Clock
From
TRISB TRISB PORTB IOCB IOCB
Interrupt-onChange PORTB
Available only.
2008 Microchip Technology Inc.
DS41262E-page
PIC16F631/677/685/687/689/690
4.4.3.4 RB7/TX/CK
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