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Split Transaction Feature Intel® PXA27x Processor Family
Order Number: 280142
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Split Transaction Feature Intel® PXA27x Processor Family
Introduction
Intel® PXA27x Processor Family (PXA27x processor) contains device called directmemory access (DMA) controller bridge unit. Most developers understand portion unit rarely think about bridge portion unit. controller move blocks data from peripherals without intervention from core. bridge performs read/writes from peripheral units that core initiated, core released continue processing subsequent tasks while read/write occurring across internal buses. Developers using Intel® PXA27x processor often consider internal controller only controller initiate direct-memory access between peripherals aware that controller serve bridge read writes issued from Intel XScale® core. Some developers think that once write issued peripheral they issue another read write command another peripheral, they aware potential problems because split-transaction feature. Other developers aware difference between system-bus peripheral peripheral-bus peripheral. This application note addresses these topics that developers using PXA27x processor fully aware bridge feature split-transaction feature, understand ensure safe split transactions explore maximum utilization.
Description
Bulverde Architecture
Figure block diagram typical system using Intel® PXA27x processor.
Split Transaction Feature Intel® PXA27x Processor Family
Figure Intel® PXA27x Processor Block Diagram Typical System
PX27x system allows access following clients:
Intel XScale® core host controller controller Internal SRAM Camera interface controller bridge Memory controller
system programmed operate maximum frequency achieve processor's highest level performance. These system-bus clients high-speed devices that require fast access time. Rather than using three-state approach, multiplexed clients request without limitations. More peripherals accessible through peripheral bus, which itself accessed through bridge. Regardless system-bus speed, peripheral always runs accommodate low-speed peripherals. interrupt controller accessible through low-speed peripheral bus. Because interrupt latency critical system performance, there another interface exposed allowing Intel XScale® core access interrupt controller Coprocessor quickly. With exception ICCR IPR, interrupt controller registers accessible through both peripheral Coprocessor interfaces.
Split Transaction Feature Intel® PXA27x Processor Family
What Split Transaction?
Processor accesses peripheral default split posted operations (refer Section 5.5.11, "DPCSR[BrgSplit]" Intel® PXA27x Processor Family Developers Manual). other words, read operation requires system-bus transactions: initial transaction send request, separate data transfer return read data. During between these transactions, system relinquished other devices. However, core stalled while waiting read transaction complete; therefore, core inadvertently process something that order. write operation, system-bus transaction completes when write operation transferred over bridge rather than wait until reaches actual peripheral. Therefore, core continue execute other reads/writes without knowledge completion previous write. both cases, operations complete peripheral strict order issue system bus. However, writes-in particular completion write seen processor)-this does mean that write operation taken effect. guarantee this write operation taken effect before allowing core proceed with additional execution, read peripheral location required (once read operation completed, previous write operations have taken effect). Rather than concerned about out-of-order sequences, developers using PXA27x processor want disable split-transaction feature.
Should Split Transaction Enabled?
split transaction feature should enabled principal reasons: improve peripheral client accesses, avoid system client underruns.
Improving Peripheral Client Access
With system high MHz, peripheral always MHz; throughput system eight times that peripheral bus. With split transaction, transaction requests across peripheral posted bridge, which makes parallel accesses peripheral space feasible.
Avoid System Client Underun
When split transaction disabled read write operations, system always owned XScale core until read write operation completed, which causes underruns system-bus clients such LCD, camera, others. Without split transaction enabled, highresolution camera images (such 1280x960x16bpp) corrupted.
Split Transaction Feature Intel® PXA27x Processor Family
Split Transaction Achieved
When Split Transaction Disabled Reads
read transaction system completed only after bridge receives data from across peripheral bus. There split responses, split completions, retries this mode. following step-by-step description read transaction with split transaction disabled: Core acquires system Core issues read command bridge Core stalls Data returned from peripheral register bridge, then core Core activates releases system
When Split Transaction Disabled Writes
write transaction system completed only after write data sent across peripheral bus. targeted address location guaranteed updated time transaction completes system bus. following step-by-step description write transaction with split transaction disabled: Core acquires system Core issues write command data bridge Core stalls Data arrives peripheral register bridge bridge indicates core that write transaction complete Core activates releases system
When Split Transaction Enabled Reads
transaction (PIO transaction transaction read from peripheral register write peripheral register) read from peripheral-address domain, split responds read instruction. bridge releases system bus, then uses micro-coded instructions read data from peripheral bus. Once read completes across peripheral bus, controller completes split transaction re-capturing system completing read transaction. core stalled until read returned because this programmed I/O. transactions (reads writes) that occur while current read transaction between split response split completion will retried. following step-by-step description read transactions with split transaction enabled: Core acquires system
Split Transaction Feature Intel® PXA27x Processor Family
Core issues read command bridge Core releases system stalls Data returned from peripheral register bridge bridge acquires system bridge returns data back core Core activates releases system
When Split Transaction Enabled Writes
programmed transaction write instruction peripheral address domain, posts write instruction. bridge indicates system that write complete then releases system bus. actual write transaction then sent across peripheral using micro-coded instructions. instructions (reads writes) between time write gets posted system when actual write completes cross peripheral retried. following step-by-step description write transactions with split transaction enabled: Core acquires system Core issues write command data bridge bridge notifies core that write completed Core releases system Data arrives peripheral register bridge
System Impact
System Impact
Following system-bus impact with split-transaction feature disabled/enabled.
Read
disabled, system released only when data returns core (that core system stalled). enabled, system released once read command reaches bridge (that core stalled system stalled).
Write
disabled, system released only when data reaches peripheral space, disabled (that core system both stalled). enabled, system released once write command data reach bridge (that core system stalled).
Summary
Split Transaction Feature Intel® PXA27x Processor Family
Peripherals underun split transaction feature disabled. System shared more efficiently between multiple clients (USB host, LCD, core, camera, internal SRAM, memory controller), enabled.
Core Execution Impact
Following core-execution impact with split-transaction feature disabled/enabled.
Read
Core continues executing only after data returns core, whether enabled disabled.
Write
disabled, core continues executing only after data reaches peripheral space. enabled, core continues executing once command data reach bridge.
Summary
Read/write always stalls core until complete. Read always stalls core until data returns core. core continue executing instructions without waiting write complete.
Split Transaction
Ensure Earlier Write Takes Effect
previously stated, when split transaction enabled, write safe-the core continue execution assuming previous write peripheral space took effect, when fact not. ensure earlier write peripheral-bus space takes effect, read back from same address. write-only registers, read from location same peripheral address range. driver writes registers time, just readback from peripheral space enough ensure previous writes take effect. Note: Usually readback from location same peripheral address range enough ensure that previous writes take effect except peripherals whose write fairly slow (RTC keypad, example). such cases, readback from same address sufficient.
Avoid Side Effects During Development
Disable split transaction first when debugging
default reset value split transaction "enabled." disable this feature, after each reset entry (power-on reset entry, wakeup-reset entry, etc.). Enable split transaction debug camera high resolution.
Enable split transaction when stable gain performance
Split Transaction Feature Intel® PXA27x Processor Family
Carefully check driver code side effects writing peripheral space
Examine code that operates with assumption that peripheral-bus write completed before executing next line code. necessary read back after each write achieve maximum parallelism. Analyze writes peripheral case-by-case basis.
Disable split-transaction feature when problems encountered.
Write-back Sample Code
code:
base address memory controller xlli_MSC2_value value into MSC2 xlli_MSC2 offset offset from memory controller MSC2 =xlli_MSC2_value [r0, #xlli_MSC2_offset] [r0, #xlli_MSC2_offset] MSC2 setting Write value Read back ensure earlier write takes effect
code:
volatile unsigned_int32 *prt=(volatile unsigned_int32*)0x48000010; unsigned_int32 dummy; *ptr=MSC2_VALUE; dummy=*ptr;
Vulnerable Areas
Interrupt Controller
Some registers accessible co-processor peripheral bus; some accessible only through peripheral bus. Always same interface access same registers.
GPIO
typical assumption during initialization that GPIO pins have been programmed appropriate functionality (which includes configuring GPIO pins their alternate functionality, required) well levels/directions before peripheral starts Because GPIO controller peripheral-bus peripheral (due split-transaction feature), earlier write GPIO registers take effect while relevant peripherals have started. example, when configuring controller, driver must first configure GPIO pins
Split Transaction Feature Intel® PXA27x Processor Family
functionality. Once associated GPIOs configured, driver enables controller soon write GPIO operation returned-even though GPIO operation have completed. System-bus clients (USBH, LCD, etc.) more likely start earlier relative their associated GPIO state.
When peripheral-bus clients operate mode, they must operate their registers registers. Because system-bus client, previous peripheral-register write still take effect while write register started.
Interrupt Handler
Ensure that register operation correct within interrupt handler; otherwise, vulnerable improper operation.
Sample Code Disable Split Transaction
Programmed Control Status Register (DPCSR) Physical Address: 0x4000_00a4 This register used activating monitoring posted writes split reads, when software uses programmed instructions access peripheral address domain bridge. DPCSR[BrgSplit] Setting DPCSR[BrgSplit] activates split behavior. Note: This control must modified only when DPCSR[BrgBusy] clear pending peripheral transactions). Modifying this control when transaction still pending might lead unpredictable results therefore, recommended.
format
=0x400000a4 [r0] ands [r0] ;judge busy ;physical address DPCSR
;clear brgsplit
format
=0x400000a4 [r0] ands judge busy physical address DPCSR
Split Transaction Feature Intel® PXA27x Processor Family
[r0]
clear brgsplit
Split Transaction Feature Intel® PXA27x Processor Family

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