PEELTM18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable

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PEELTM18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable

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Commercial/ Industrial
PEELTM18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device
Multiple Speed, Power, Temperature Options Speeds ranging from 25ns Power 37mA 25MHz Commercial Industrial versions available CMOS Electrically Erasable Technology Superior factory testing Reprogrammable plastic package Reduces retrofit development costs Development/Programmer Support Third party software programmers PLACE Development Software PDS-3 programmer PLD-to-PEEL JEDEC file translator Architectural Flexibility product term input array inputs pins possible macrocell configurations Synchronous preset, asynchronous clear Independent Output enables 20-pin DIP, PLCC, SOIC TSSOP packages Application Versatility Replaces random logic Super-sets standard PLDs (PAL, GAL, EPLD) Enhanced Architecture fits more logic than ordinary PLDs
General Description
PEEL18CV8 Programmable Electrically Erasable Logic (PEEL) device providing attractive alternative ordinary PLDs. PEEL18CV8 offers performance, flexibility, ease design production practicality needed logic designers today. PEEL18CV8 available 20-pin DIP, PLCC, SOIC TSSOP packages (see Figure with speeds ranging from 25ns with power consumption 37mA. EE-reprogrammability provides convenience instant reprogramming development reusable production inventory minimizing impact programming changes errors. EE-reprogrammability Configuration (Figure
I/CLK
also improves factory testability, thus assuring highest quality possible. PEEL18CV8 architecture allows replace over standard 20-pin PLDs (PAL, GAL, EPLD, etc.). also provides additional architecture features more logic into every design. ICT's JEDEC file translator instantly converts PEEL18CV8 existing 20pin PLDs without need rework existing design. Development programming support PEEL18CV8 provided popular third-party programmers development software. also offers free PLACE development software lowcost development system (PDS-3).
Block Diagram (Figure
TSSOP
PLCC
SOIC
PEEL18CV8
Figure PEEL18CV8 Logic Array Diagram
PEEL18CV8
Function Description PEEL18CV8 implements logic functions sum-of-products expressions programmableAND/fixed-OR logic array. User-defined functions created programming connections input signals into array. User-configurable output structures form macrocells further increase logic flexibility. Architecture Overview PEEL18CV8 architecture illustrated block diagram Figure dedicated inputs I/Os provide inputs outputs creation logic functions. core device programmable electrically-erasable array which drives fixed array. With this structure PEEL18CV8 implement sum-ofproducts logic expressions. Associated with each functions macrocell which independently programmed different configurations. programmable macrocells allow each create sequential combinatorial logic functions activehigh active-low polarity, while providing three different feedback paths into array. AND/OR Logic Array programmable array PEEL18CV8 (shown Figure formed input lines intersecting product terms. input lines product terms used follows: Input Lines: input lines carry true complement signals applied input pins additional lines carry true complement values feedback input signals from I/Os product terms: product terms (arranged groups used form product functions output enable terms (one each I/O) global synchronous preset term global asynchronous clear term each input-line/product-term intersection there EEPROM memory cell which determines whether there logical connection that intersection. Each product term essentially 36input gate. product term which connected both true complement input signal will always FALSE thus will affect function that drives. When connections product term opened, "don't care" state exists that term will always TRUE. When programming PEEL18CV8, device programmer first performs bulk erase remove previous pattern. erase cycle opens every logical connection array. device configured perform user-defined function programming selected connections array. (Note that PEEL device programmers automatically program connections unused product terms that they will have effect output function). Programmable Macrocell unique twelve-configuration output macrocell provides complete control over architecture each output. ability configure each output independently permits users tailor configuration PEEL18CV8 precise requirements their designs. Macrocell Architecture Each macrocell, shown Figure consists D-type flip-flop signal-select multiplexers. configuration each macrocell determined four EEPROM bits controlling these multiplexers. These bits determine: output polarity, output type (registered non-registered) input/feedback path (bi-directional I/O, combinatorial feedback register feedback). Refer Table details. Equivalent circuits twelve macrocell configurations illustrated Figure addition emulating four PAL-type output structures (configurations macrocell provides eight additional configurations. When creating PEEL device design, desired macrocell configuration generally specified explicitly design file. When design assembled compiled, macrocell configuration bits defined last lines JEDEC programming file. Output Type signal from array directly output (combinatorial function) latched D-type flip-flop (registered function). D-type flip-flop latches data rising edge clock controlled global preset clear terms. When synchronous preset term satisfied, output register will HIGH next rising edge clock input. Satisfying asynchronous clear term will LOW, regardless clock state. both terms satisfied simultaneously, clear will override preset. Output Polarity Each macrocell configured implement active-high active-low logic. Programmable polarity eliminates need external inverters. Output Enable output each macrocell enabled disabled under control associated programmable output enable product term. When logical conditions programmed output enable term satisfied, output signal propagated pin. Otherwise, output buffer driven into high-impedance state.
PEEL18CV8
Under control output enable term, function dedicated input, dedicated output, bi-directional I/O. Opening every connection output enable term will permanently enable output buffer yield dedicated output. Conversely, every connection intact, enable term will always logically false will function dedicated input. Input/Feedback Select PEEL18CV8 macrocell also provides control over feedback path. input/feedback signal associated with each macrocell obtained from three different locations: from (bi-directional I/O), directly from output flip-flop (registered feedback) directly from gate (combinatorial feedback). Bi-directional input/feedback signal taken from when using dedicated input bi-directional I/O. (Note that possible create registered output function with bi-directional I/O.) Combinatorial Feedback signal-select multiplexer gives macrocell ability feedback output gate, bypassing output buffer, regardless whether output function registered combinatorial. This feature allows creation asynchronous latches, even when output must disabled. (Refer configurations Figure Registered Feedback Feedback also taken from register, regardless whether output function combinatorial registered. When implementing combinatorial output function, registered feedback allows internal latching states without giving external output. Design Security PEEL18CV8 provides special EEPROM security that prevents unauthorized reading copying designs programmed into device. security programmer, either conclusion programming cycle separate step, after device been programmed. Once security set, impossible verify (read) program PEEL until entire device first been erased with bulk-erase function.
Figure Block Diagram PEEL18CV8 Macrocell
PEEL18CV8
Figure Equivalent Circuits Twelve Configurations PEEL18CV8 Macrocell.
Configuration
Input/Feedback Select Bi-Directional Combinatorial Feedback Register Feedback
Output Select Register Combinatorial Register Combinatorial Register Combinatorial Active Active High Active Active High Active Active High Active Active High Active Active High Active Active High
Table PEEL18CV8 Macrocell Configuration Bits
PEEL18CV8
Absolute Maximum Ratings
Symbol Parameter
Supply Voltage Voltage Applied Pin2 Output Current Storage Temperature Lead Temperature Soldering seconds This device been designed tested specified operating ranges. Proper operation outside these levels guaranteed. Exposure absolute maximum ratings cause permanent damage.
Conditions
Relative Ground Relative Ground1 (IOL, IOH)
Rating
-0.5 -0.5 +150 +300
Unit
Operating Ranges
Symbol Parameter
Supply Voltage
Conditions
Commercial Industrial
4.75
5.25
Unit
TRVCC
Ambient Temperature Clock Rise Time Clock Fall Time Rise Time
Commercial Industrial Note Note Note
D.C. Electrical Characteristics Over operating range
Symbol Parameter
VOHC VOLC Output HIGH Voltage Output HIGH Voltage CMOS Output Voltage Input Voltage CMOS Input HIGH Voltage Input Voltage Input, Leakage Current Max, Input, Leakage Current HIGH Max, Output Short Circuit Current 0.5V 25°C ICC10 Current (See CR-1 typical ICC) 25MHz outputs disabled4 -10/I-10 -15/I-15 -25/I-25
Conditions
Min, -4.0mA Min, -10µA Min, 16mA/24mA14 Min, 10µA
Unit
0.15 -0.3 (Typ) (Typ) -135 110/115 45/55 37/50
CIN7 COUT7
Input Capacitance Output Capacitance
25°C, 5.0V 1MHz
PEEL18CV8
A.C. Electrical Characteristics
Symbol Parameter
tCO1 tCO2 tCL, fMAX1 fMAX2 fMAX3 tRESET Input5 non-registered output Input5 output enable6 Input output disable Clock output Clock comb. output delay internal registered feedback Clock Feedback Input feedback setup clock Input hold after clock Clock time, Clock high time8 clock period, (tSC tCO1) Internal Feedback (1/tSC+tCF)
Over Operating Range
166.7
I-10
83.3
I-15
41.6
I-25
28.5 28.5 33.3
Unit
117.6 83.3 142.8
External frequency External (1/tCP)12 Feedback (1/tCL+tCH)
166.7
Asynchronous Reset pulse width Input Asynchronous Reset Asynchronous Reset Recovery Time Power-on reset time registers clear state
Switching Waveforms
Inputs, I/O, Registered Feedback, Synchronous Preset Clock Asynchronous Reset Registered Outputs Combinatorial Outputs
Notes
Minimum input -0.5V, however inputs Test conditions assume: signal transition times
undershoot -2.0V periods less than 20ns. specified program/verify operation. Test points Clock referenced levels. pins "Input" refers Input signal. measured from input transition VREF 0.1V, measured from input transition 0.1V 0.1V; VREF test loads Section this Data Book. Capacitances tested sample basis.
less from points, timing reference levels 1.5V (unless otherwise specified). Test output time duration less than sec. typical application: This parameter tested with device programmed 8-bit Counter. PEEL Device test loads specified Section this Data Book. Parameters 100% tested. Specifications based initial characterization tested after design process modification which affect operational frequency.
PEEL18CV8
Ordering Information
PART NUMBER PEEL18CV8J-5 PEEL18CV8P-7 PEEL18CV8J-7 PEEL18CV8S-7 PEEL18CV8P-10 PEEL18CV8PI-10 PEEL18CV8J-10 PEEL18CV8JI-10 PEEL18CV8S-10 PEEL18CV8SI-10 PEEL18CV8T-10 PEEL18CV8TI-10 PEEL18CV8P-15 PEEL18CV8PI-15 PEEL18CV8J-15 PEEL18CV8JI-15 PEEL18CV8S-15 PEEL18CV8SI-15 PEEL18CV8T-15 PEEL18CV8TI-15 PEEL18CV8P-25 PEEL18CV8PI-25 PEEL18CV8J-25 PEEL18CV8JI-25 PEEL18CV8S-25 PEEL18CV8SI-25 PEEL18CV8T-25 PEEL18CV8TI-25 SPEED 7.5ns 7.5ns 7.5ns 10ns 10ns 10ns 10ns 15ns 15ns 15ns 15ns 25ns 25ns 25ns 25ns TEMPERATURE PACKAGE
Contact availability speed grades TSSOP packages.
Part Number
Device Suffix
PEEL18CV8P-25
Speed
Package Plastic 300mil Plastic Leaded Chip Carrier (PLCC) SOIC TSSOP
7.5ns 10ns 15ns 25ns
Temperature Range (Blank) Commercial +70oC Industrial +85oC

PEELTM18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable

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