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3120® 3150® Smart Transceiver Data Book
005-0139-01D
Echelon, LON, LONWORKS, Neuron, 3120, 3150, LonTalk, NodeBuilder, LNS, LonMaker, i.LON, Echelon logo trademarks Echelon Corporation registered United States other countries. Other brand product names trademarks registered trademarks their respective holders. Smart Transceivers, Neuron Chips, other Products were designed equipment systems which involve danger human health safety risk property damage Echelon assumes responsibility liability Smart Transceivers Neuron Chips such applications. Parts manufactured vendors other than Echelon referenced this document have been described illustrative purposes only, have been tested Echelon. responsibility customer determine suitability these parts each application. ECHELON MAKES RECEIVE WARRANTIES CONDITIONS, EXPRESS, IMPLIED, STATUTORY COMMUNICATION WITH YOU, ECHELON SPECIFICALLY DISCLAIMS IMPLIED WARRANTY MERCHANTABILITY FITNESS PARTICULAR PURPOSE. part this publication reproduced, stored retrieval system, transmitted, form means, electronic, mechanical, photocopying, recording, otherwise, without prior written permission Echelon Corporation. Printed United States America. Copyright ©2002-2006 Echelon Corporation. Echelon Corporation www.echelon.com
Table Contents
Chapter Introduction Introduction Audience Product Overview Free Topology Technology Overview Related Documentation Chapter Hardware Resources Overview Neuron Processor Architecture Memory Allocation 3120 Smart Transceiver 3150 Smart Transceiver EEPROM Static Preprogrammed External Memory 3150 Smart Transceiver Input/Output Eleven Bidirectional Pins 16-Bit Timer/Counters Clock Input Clock Generation Additional Functions Reset Function RESET Power Sequence Software Controlled Reset Watchdog Timer Considerations Reset Processes Timing SERVICE Integrity Mechanisms Memory Integrity Using Checksums Reboot Integrity Options Word Reset Processing Signatures Chapter Input/Output Interfaces Overview Hardware Considerations Timing Issues Scheduler-Related Timing Information Firmware Hardware-Related Timing Information
3120 3150 Smart Tranceiver Data Book
Table Contents
Direct Objects Input/Output Byte Input/Output Leveldetect Input Nibble Input/Output Parallel Objects Muxbus Input/Output Parallel Input/Output Master/Slave Mode Slave Mode Token Passing Handshaking Data Transferring Serial Objects Bitshift Input/Output Input/Output Magcard Input Magtrack1 Input Neurowire (SPI Interface) Input/Output Object Neurowire Master Mode Neurowire Slave Mode Serial Input/Output Touch Input/Output Wiegand Input Timer/Counter Input Objects Dualslope Input Edgelog Input Infrared Input Ontime Input Period Input Pulsecount Input Quadrature Input Totalcount Input Timer/Counter Output Objects Edgedivide Output Frequency Output Oneshot Output Pulsecount Output Pulsewidth Output Triac Output Triggered Count Output Notes
3120 3150 Smart Tranceiver Data Book
Chapter Hardware Design Considerations Introduction Quick Start Users Familiar With FTT-10A Transceiver Interface Between Smart Transceivers Network Board Layout Guidelines Design Issues Design Issues .101 Lightening Protection .102 Building Entrance Protection .102 Network Line Protection .102 Shield Protection .103 Suggested Discharge Arresters .103 61000-4 Electromagnetic Compatibility (EMC) Testing .104 Chapter Network Cabling Connections .109 Network Connection .110 Network Topology Overview .110 System Performance Cable Selection .111 System Specifications .112 Transmission Specifications .112 Cable Termination Shield Grounding .113 Free Topology Network Segment .113 Doubly Terminated Topology Segment .113 Grounding Shielded Twisted Pair Cable .114 Chapter Programming Considerations .115 Application Program Development Export .116 LonBuilder Developers .116 Development Hardware Setup .116 Release Hardware Setup .118 NodeBuilder Development Tool .118 Development Hardware Setup .118 Release Hardware Setup .119 Appendix Smart Transceiver Design Checklist .121 Introduction .122 Device Checklist .122 Appendix Qualified TP/FT-10 Cable Specifications Sources .125 Introduction .126 Qualified Cables .126 Category Cable Specifications .126 NEMA Level Cable Specifications .126 16AWG/1.3mm "Generic" Cable Specifications .128
3120 3150 Smart Tranceiver Data Book
Table Contents
Appendix Design Handling Guidelines .129 Application Considerations .130 Termination Unused Pins .130 Avoidance Damaging Conditions .130 Power Supply, Ground, Noise Considerations .132 Decoupling Capacitors .133 Board Soldering Considerations .134 Soldering Through-hole Parts (FT-X1) .134 Soldering Surface Mount (SMT) Parts (Free Topology Transceivers) .135 Handling Precautions Electrostatic Discharge .135 Electrostatic Discharge .138 Recommended Reading .139 Power Distribution Decoupling Capacitors .139 Recommended Bypass Capacitor Placement .140 Appendix Reference Design Schematics Layout .141 Mini Evaluation Board .142 3150 Evaluatin Board Core .143 3150 Evaluation Board Peripheral Circuitry.144 3150 Evaluation Board Composite Layer.145 3150 Evaluation Board Layer .146 3150 Evaluation Board Internal Ground Layer.147 3150 Evaluation Board Internal Power Layer.148 3150 Evaluation Board Bottom Layer .149 3150 Evaluation Board Composite Bottom Layer .150
3120 3150 Smart Tranceiver Data Book
Introduction
3120 3150 Smart Transceiver Data Book
Chapter Introduction
Introduction
This manual provides detailed technical specifications electrical interfaces, mechanical interfaces, operating environment characteristics 3120® 3150® Smart Transceivers. This manual also provides guidelines migrating applications Smart Transceiver-based device using LonBuilder® NodeBuilder®development tool. some cases, vendor sources included this manual simplify task integrating Smart Transceivers with application electronics. There list related documentation this chapter section Related Documentation. documents listed that section found Echelon website (www.echelon.com) unless otherwise noted.
Audience
This manual provides specifications user instructions Smart Transceiver customers, users network interfaces based Smart Transceivers.
Product Overview
Smart Transceivers integrate Neuron® 3120 Neuron 3150 network processor core, respectively, with free topology (FT) twisted-pair transceiver create cost, smart transceiver chip. Combined with Echelon high performance FT-X1 FT-X2 Communication Transformer, Smart Transceivers benchmarks performance, robustness, cost. Ideal LONWORKS® devices designed building, industrial, transportation, home, utility automation applications, Smart Transceivers used both product designs means cost reducing existing devices. integral transceiver fully compatible with TP/FT-10 channel communicate with devices using Echelon FTT-10A Free Topology Transceiver, with addition suitable isolation capacitors, LPT-10 Link Power Transceiver. free topology transceiver supports polarity insensitive cabling using star, bus, daisychain, loop, combined topologies. This frees installer from need adhere strict wiring rules. Free topology wiring reduces time expense device installation allowing wiring installed most expeditious cost-effective manner. also simplifies network expansion eliminating restrictions wire routing, splicing, device placement. 3120 Smart Transceiver complete system-on-a-chip that targeted cost-sensitive small form factor designs that require 4Kbytes application code. Neuron 3120 core operates 40MHz, includes 4Kbytes EEPROM 2Kbytes RAM. Neuron firmware pre-programmed on-chip ROM. application code stored embedded EEPROM memory updated over network. 3120 Smart Transceiver offered 32-lead SOIC package well compact 44-lead TQFP package. 3150 Smart Transceiver includes 20MHz Neuron 3150 core, 0.5Kbytes EEPROM 2Kbytes RAM. Through external memory bus, 3150 Smart Transceiver address 58Kbytes external memory, which 16Kbytes external non-volatile memory dedicated Neuron system firmware. 3150 Smart Transceiver supplied 64-lead TQFP package. embedded EEPROM written 10,000 times with data loss. Data stored EEPROM will retained least years. Three different versions Smart Transceivers available meet wide range applications packaging requirements. table below product offerings descriptions.
3120/FT 3150 Smart Transceiver Data Book
Product Overview
Table Smart Transceiver Product Offerings
Smart Transceiver Product Number 3120-E4S40 3120-E4P40 3150-P20 External memory interface
Model Number 14212R-500 14222R-800 14230R-450
Maximum input clock 40MHz 40MHz 20MHz
EEPROM (Kbytes) 4Kbytes 4Kbytes 0.5Kbytes
(Kbytes) 2Kbytes 2Kbytes 2Kbytes
(Kbytes) 12Kbytes 12Kbytes
Package SOIC TQFP TQFP
Smart Transceivers provide pins which configured operate more predefined standard input/output modes. Combining wide range models with on-board timer/counters enables Smart Transceivers interface application circuits with minimal external logic software development. Smart Transceivers easily interfaced other host MCUs Echelon ShortStackor firmware. When used with ShortStack firmware, Smart Transceiver enables product with host microcontroller quickly inexpensively become networked, Internet-accessible device. ShortStack firmware uses serial interface communicate between host Smart Transceiver. firmware uses high performance parallel dual-ported interface. Smart Transceivers supplied with either FT-X1or FT-X2 transformer, patent-pending external communication transformers. transformer enables operation presence high frequency common mode noise unshielded twisted pair networks. Properly designed devices meet rigorous Level requirements 61000-4-6 without need network isolation choke. transformer also offers outstanding immunity from magnetic field noise, eliminating need protective magnetic field shields most applications. transformer provided potted, 6-pin, through-hole plastic package. typical Smart Transceiver-based device requires power source, crystal, circuitry. Figure typical Smart Transceiver-based device. Smart Transceivers compatible withthe Echelon LPT-10 Link Power Transceiver, they communicate with each other single twisted pair cable. This capability provides inexpensive means interfacing devices whose current voltage requirements would otherwise exceed capacity link power segment. When equipped with Smart Transceiver blocking capacitors, these devices operated from local power supply without need additional electrical isolation from link power network.
LONWORKS Device
Sense Control Devices, e.g., Motors, Valves, Encoders, Lights, Relays, Switches
Smart Transceiver
Communication Transformer FT-X1 FT-X2 Data Rate kbps
Crystal
Power Source
Free Topology Twisted Pair Network
Figure Typical Smart Transceiver-based Device
3120/FT 3150 Smart Transceiver Data Book
Chapter Introduction
Smart Transceivers also provide electrical isolation devices that grounded, allowing such devices used link power network segment. many applications, some devices grounded, either meet functional requirements safety regulations. FT-X1or FT-X2 transformer electrically isolates device from segment, allowing circuitry grounded without impairing communications. twisted pair channel composed multiple segments separated 709.1 routers physical layer repeaters. physical layer repeater designed using FTT-10A transceivers (the Smart Transceivers cannot used physical layer repeaters). FTT-10A transceiver includes physical layer repeater feature that allows LONWORKS data exchanged between network segments interconnecting more FTT-10A transceivers. This allows twisted pair network grow inexpensively encompass many more devices longer wire distances than would otherwise possible. Refer LONWORKS FTT-10A Free Topology Transceiver User's Guide more information this. Smart Transceivers designed comply with both 55022 requirements, minimizing time-consuming expensive testing.
Free Topology Technology Overview
conventional control system using topology wiring (such RS-485) consists network sensors actuators that interconnected using shielded twisted wire pair. accordance with RS-485 guidelines, devices must wired topology limit electrical reflections ensure reliable communications. There high cost associated with installing maintaining cable plant that links together devices RS-485-based control system. topology wiring more time consuming expensive install, because installer unable branch star wiring where convenient. devices must connected directly main bus. best solution reduce installation maintenance costs simplify system modifications free topology communications system. Echelon's free topology transceiver technology offers such solution, providing elegant inexpensive method interconnecting different elements distributed control system. free topology architecture allows installer wire control devices with virtually topology restrictions. Power supplied local +5VDC power supply located each device shown Figure 1.2.
Sensor Actuator +5VDC power Smart Transceiver Device
Smart Transceiver Device Smart Transceiver Device Smart Transceiver Device Termination Smart Transceiver Device additional 3120 3150 Smart Transceiver devices
Smart Transceiver Device
Figure Free Topology Transceiver System
3120/FT 3150 Smart Transceiver Data Book
Related Documentation
Unlike wiring designs, free topology Smart Transceivers wiring scheme that supports star, loop, and/ wiring (see Figure 1.3). This design many advantages:
installer free select method wiring that best suits installation, reducing need advanced planning allowing last minute changes installation site. installers have been trained style wiring installations, free topology technology introduced without requiring retraining. Retrofit installations with existing wiring plants accommodated with minimal, any, rewiring. This capability ensures that Smart Transceiver technology adapted both projects. Free topology permits Smart Transceiver systems expanded future simply tapping into existing wiring where most convenient This reduces time expense system expansion, from customer's perspective, keeps down life cycle cost free topology network.
Singly Terminated Topology
Star Topology
Doubly Terminated Topology
Loop Topology
Mixed Topology
Termination. actual termination circuit will vary topology.)
Figure Typical Wiring Topologies Supported Smart Transceivers System Content
Related Documentation
following Echelon documents suggested reading: LONWORKS Transceiver Datasheet (003-0336-01) LonBuilder User's Guide (078-0001-01) NodeBuilder User's Guide (078-0141-01) Neuron Programmer's Guide (078-0002-01) LonBuilder Hardware Guide (078-0003-01)
3120/FT 3150 Smart Transceiver Data Book
Chapter Introduction
LONMARKLayers Interoperability Guidelines (078-0014-01) LONMARKApplication Layer Interoperability Guidelines (078-0120-01) 3120 3150 Smart Transceiver Datasheet (003-0337-01) LONWORKS FTT-10A Free Topology Transceiver data sheet (003-0312-01) LONWORKS Custom Node Development engineering bulletin (005-0024-01) LPI-10 Link Power Interface Module User's Guide (078-0104-01) LPT-10 Link Power Transceiver User's Guide (078-0105-01) Junction Wiring Guidelines Twisted Pair LONWORKS Networks engineering bulletin (005-0023-01) EIA-709.1 Control Network Protocol Specification (distibuted Global Engineering Documents: global.ihs.com).
3120/FT 3150 Smart Transceiver Data Book
Hardware Resources
3120 3150 Smart Transceiver Data Book
Chapter Hardware Resources
Overview
3150 Smart Transceiver supports external memory more complex applications, while 3120 Smart Transceiver complete system chip. major hardware blocks both processors same, except where noted table figure below. Table Comparison Smart Transceivers
Characteristic Bytes Bytes EEPROM Bytes 16-Bit Timer/Counters External Memory Interface Package 3150 Smart Transceiver 2,048 TQFP 3120 Smart Transceiver 2,048 12,288 4,096 SOIC TQFP
Figure Smart Transceiver Block Diagram
Neuron Processor Architecture
Neuron core composed three processors. These processors assigned following functions Neuron firmware. Processor layer processor that handles layers 7-layer LonTalk® protocol stack. This includes driving communications subsystem hardware executing media access control algorithm. Processor communicates with Processor using network buffers located shared memory.
3120 3150 Smart Transceiver Data Book
Neuron Processor Architecture
Processor network processor that implements layers through LonTalk protocol stack. handles network variable processing, addressing, transaction processing, authentication, background diagnostics, software timers, network management, routing functions. Processor uses network buffers shared memory communicate with Processor application buffers communicate with Processor These buffers also located shared memory. Access them mediated with hardware semaphores resolve contention when updating shared data.
Communications Port Input/Output
Proces-
Network Proces-
Application
Network Buffers
Application Buffers
Shared
Figure Processor Organization Memory Allocation Processor application processor. executes code written user, together with operating system services called user code. primary programming language used applications Neuron derivative ANSI language optimized enhanced LONWORKS distributed control applications. major enhancements following (see Neuron Programmer's Guide details):
network communication model, based functional blocks network variables, that simplifies promotes data sharing between like disparate devices. network configuration model, based functional blocks configuration properties, that facilitates interoperable network configuration tools. type model based standard user resource files that expands market interoperable devices simplifying integration devices from multiple manufacturers. extensive drivers that support capabilities Neuron core. Powerful event driven programming extensions that provide easy handling network, I/O, timer events.
support these capabilities part Neuron firmware, does need written programmer. Each three identical processors register (Table 2.2), three processors share data, ALUs (arithmetic logic units) memory access circuitry (Figure 2.3). 3150 Smart Transceiver, internal
3120 3150 Smart Transceiver Data Book
Chapter Hardware Resources
address, data, signals reflected corresponding external lines when utilized internal processors. Each minor cycle consists three system clock cycles, phases; each system clock cycle input clock cycles. minor cycles three processors offset from another system clock cycle, that each processor access memory ALUs once during each instruction cycle. Figure shows active elements each processor during three phases minor cycle. Therefore, system pipelines three processors, reducing hardware requirements without affecting performance. This allows execution three processes parallel without time-consuming interrupts context switching. Table Register
Mnemonic FLAGS Bits Contents Number, Fast Select, Carry Next Instruction Pointer Address 256-Byte Base Page Data Stack Pointer Within Base Page Return Stack Pointer Within Base Page Data Stack, Input
Processor Registers
Processor Registers
Processor Registers
ALUs
Active elements Processor Latch Active elements Processor Memory Active elements Processor
Latch
Figure Processor/Memory Activity During Three System Clock Cycles Minor Cycle architecture stack-oriented; 8-bit wide stack used data references, operates (Top Stack) register next entry data stack which RAM. second stack stores return
3120 3150 Smart Transceiver Data Book
Neuron Processor Architecture
addresses CALL instructions, also used temporary data storage. This stack architecture leads very compact code. Tables 2.3, 2.42.4, outline instruction set. Figure shows layout base page, which bytes long. Each three processors uses different base page, whose address given contents register that processor. data stack 8-bit register, next element data stack location within base page offset given contents register. data stack grows from memory towards high memory. assembler shorthand symbol NEXT refers contents location (BP+DSP) memory, which actual processor register. Pushing byte data onto data stack involves following steps: incrementing register, storing current contents address (BP+DSP) memory, moving byte data TOS. Popping byte data from data stack involves following steps: moving destination, moving contents address (BP+DSP) memory TOS, decrementing register. return stack grows from high memory towards memory. Executing subroutine call involves following steps: storing high byte instruction pointer register address (BP+RSP) memory, decrementing RSP, storing byte address (BP+RSP) memory, decrementing RSP, moving destination address register. Similarly, returning from subroutine involves following steps: incrementing RSP, moving contents (BP+RSP) byte register, incrementing RSP, moving contents (BP+RSP) high byte
Return Stack BP+RSP BP+DSP NEXT Data Stack BP+0x18 BP+0x17 Sixteen Byte Registers BP+0x8 BP+0x7 Four 16-bit Pointer Registers
Base Page.
Figure Base Page Memory Layout processor instruction cycle three system clock cycles, input clock (CLK1) cycles. Most instructions take between seven processor instruction cycles. input clock rate 40MHz, instruction times vary between 0.15 1.05 Execution time scales inversely with input clock rate. formula instruction time <Instruction Time> Cycles> <Input Clock> Tables 2.3, 2.42.4, list processor instructions, their timings cycles) sizes bytes). This provided purposes calculating execution time size code sequences. programming Smart Transceiver done with Neuron using LonBuilder NodeBuilder development tool. Neuron compiler optionally produce assembly listing, examining this listing help programmer optimize his/her Neuron source code.
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Chapter Hardware Resources
Table Program Control Instructions
Mnemonic BR/BRC/ BRNC SBRZ/SBRNZ BRZ/BRNZ BRNEQ DBRNZ Cycles Size (bytes) Description operation Short unconditional branch Branch, branch (not) carry Short branch (not) zero Unconditional branch Branch (not) zero Return from subroutine Branch equal (taken/not taken) Decrement [RSP] branch zero Call subroutine relative Call subroutine Call subroutine Offset Offset -128 +127 Offset Drops Absolute address Offset -128 +127. Drops Drops bytes from return stack Offset -128 +127. Drops equal Offset -128 +127. taken, drops byte from return stack Offset -128 +127. Pushes bytes return stack Address 8KB. Pushes bytes return stack Absolute address. Pushes bytes return stack Comments
CALLR CALL CALLF
Table Memory/Stack Instructions
Mnemonic PUSH DROP DROP_R PUSH (NEXT, DSP, RSP, FLAGS) (DSP, RSP, FLAGS) DROP NEXT DROP_R NEXT PUSH/POP PUSH !TOS !TOS PUSH [RSP] DROP [RSP] PUSHS #literal PUSH #literal PUSHPOP POPPUSH LDBP address PUSH/POP [DSP][-D] PUSHD #literal PUSHD [PTR] Cycles Size (bytes) Comments Effective Address (EA) Increment DSP, duplicate into NEXT Move NEXT TOS, decrement Move NEXT TOS, decrement DSP, return from call Push processor register processor register Decrement Decrement return from call Byte register TOS, push byte NEXT TOS, byte from NEXT Push from return stack data stack, unchanged Increment Push short literal value Push 8-bit literal value 255] from return stack, push data stack from data stack, push return stack Load base page pointer with 16-bit value displacement 16-bit literal value (high byte first) Push from 16-bit pointer high byte first
3120 3150 Smart Transceiver Data Book
Memory Allocation POPD [PTR] PUSH/POP [PTR][TOS] PUSH/POP [PTR][D] PUSH/POP absolute IN/OUT Mnemonic INC/DEC/NOT ROLC/RORC SHL/SHR SHLA/SHRA ADD/AND/OR/XOR/ADC ADD/AND/OR/XOR #literal (ADD/AND/OR/XOR)_R ALLOC #literal DEALLOC_R #literal NEXT,TOS NEXT, TOS,NEXT [PTR] Cycles Size (bytes) 16-bit pointer byte first (16-bit pointer) (16-bit pointer) displacement 255] Absolute memory address Fast instruction, transfer bytes Operation Increment/decrement/negate Rotate left/right through carry Unsigned left/right shift TOS, clear carry Signed left/right shift into carry Operate with NEXT TOS, drop NEXT Operate with literal Operate with NEXT TOS, drop NEXT return data stack pointer Subtract from data stack pointer return NEXT TOS, drop NEXT NEXT carry, drop NEXT NEXT, drop NEXT Exchange NEXT Increment 16-bit pointer
Table Instructions
Memory Allocation
3120 Smart Transceiver
Figure memory 3120 Smart Transceiver.
4,096 bytes in-circuit programmable EEPROM that store: Network configuration addressing information. Unique 48-bit Neuron (written factory). User-written application code read-mostly data.
2,048 bytes static that store following: Stack segment, application, system data. Network buffers application buffers.
12,288 bytes that store following: Neuron firmware, including system firmware executed network processors, executive supporting application program.
3150 Smart Transceiver
Figure memory 3150 Smart Transceiver.
bytes in-circuit programmable EEPROM that store following: Network configuration addressing information.
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Chapter Hardware Resources
Unique 48-bit Neuron (written factory). User-written application code read-mostly data. Table available EEPROM space.
2,048 bytes static that store following: Stack segment, application, system data. Network application buffers.
processor access 59,392 bytes available 65,536 bytes memory address space external memory interface. remaining 6,144 bytes memory address space mapped internally. 16,384 bytes external memory (59,392 bytes total) required store following: Neuron firmware, including system firmware executed Network processors, executive supporting application program.
rest external memory (43,008 bytes) available for: User-written application code. Additional application read/write non-volatile data. Additional network buffers application buffers.
FFFF FC00 FBFF
Reserved Space Memory Mapped 2.5K Reserved Space
FFFF FC00 FBFF
Reserved Space Memory Mapped
F200 F1FF F000 EFFF
Internal 0.5K EEPROM EEPROM F000 EFFF Internal
E800 E7FF Memory Space Available User External 4000 3FFF Neuron Firmware Reserved Space 4FFF EEPROM 4C00 Unavailable E800 Unavailable
2FFF 0000 Neuron Firmware (ROM)
0000
Figure 3150 Smart Transceiver Memory
Figure 3120 Smart Transceiver Memory
EEPROM
Both versions Smart Transceiver have internal EEPROM containing:
Network configuration addressing information.
3120 3150 Smart Transceiver Data Book
Memory Allocation
Unique 48-bit Neuron Optional user-written application code data tables.
bytes EEPROM written under program control using on-chip charge pump generate required programming voltage. charge pump operation transparent user. remaining bytes written during manufacture, contain unique 48-bit identifier each part called Neuron plus bits device code chip manufacturer. Each byte EEPROM region written 10,000 times. both Smart Transceivers, EEPROM stores installation-specific information such network addresses communications parameters. 3120 Smart Transceiver, EEPROM also stores application program generated LonBuilder NodeBuilder development tools. application code 3150 Smart Transceiver stored either on-chip EEPROM memory off-chip external memory depending size application code. Table available EEPROM space. write operations internal EEPROM, Neuron firmware automatically compares value EEPROM location with value written. same, write operation performed. This prevents unnecessary write cycles EEPROM, reduces average EEPROM write cycle latency. When Smart Transceiver within specified power supply voltage range, pending on-going EEPROM write guaranteed. Smart Transceiver contains built-in low-voltage interruption (LVI) circuit that holds chip reset when below certain voltage. 3120 3150 Smart Transceiver Datasheet trip points. This prevents EEPROM data corruption, although some cases, additional external protection appropriate. section RESET Pin, more information circuitry. event fault, on-chip EEPROM 3150 Smart Transceiver reset factory default state executing EEBLANK program. program EEBLANK.NRI file into external memory device, temporarily replace external flash application with chip that EEBLANK.NRI loaded, power device. After some time, service device should come solid, indicating that EEPROM been blanked. Then replace original application flash. EEBLANK.NRI file distributed with LonBuilder 3.01 (Service Pack NodeBuilder (Service Pack greater), NodeBuilder (Service Pack greater) development tools. file also downloaded from developer's toolbox located Echelon website (www.echelon.com). Versions EEBLANK.NRI distributed before these Service Packs should used with 3150 Smart Transceiver. set_eeprom_lock() function also used additional protection against accidental EEPROM data corruption. This function allows application program state lock checksummed portion EEPROM. Refer Neuron Reference Guide more information. internal EEPROM Smart Transceiver will contain fixed amount overhead network image (configuration), addition user code user data. following table shows maximum amount EEPROM space available user code user data assuming minimally-sized network image. Also shown minimum segment size user data. Constant data assumed part code space. Table Memory Usage
Device 3120 Smart Transceiver 3150 Smart Transceiver Firmware Version EEPROM Space (Bytes) 3969 Segment Size (Bytes)
EEPROM must allocated increments device's segment size, smallest unit EEPROM that allocated variable space. example, there three 3-byte variables used, there must bytes variable space. 3120 Smart Transceiver, this would result allocation bytes variable space, bytes lowest increment device segment size bytes) that store three 3-byte variables. 3150 Smart Transceiver, this would result allocation bytes variable space, bytes lowest increment device segment size bytes) that store three 3-byte variables.
3120 3150 Smart Transceiver Data Book
Chapter Hardware Resources
Static
Both Smart Transceivers contain 2048 bytes static RAM. used store following:
Stack segment, application, system data Network buffers application buffers
state retained long power applied device. After reset, releasing Smart Transceiver initialization sequence will clear (see section Reset Processes Timing, later this chapter).
Preprogrammed
3120 Smart Transceiver contains 12,288 bytes pre-programmed ROM. This memory contains Neuron firmware, including LonTalk protocol stack, real time task scheduler, system function libraries. Neuron firmware 3150 Smart Transceiver stored external memory. object code supplied with LonBuilder NodeBuilder tools.
External Memory 3150 Smart Transceiver
External memory support only 3150 Smart Transceiver. memory interface supports 42Kbytes external memory space additional user program data. total address space 64Kbytes. However, upper address space reserved internal RAM, EEPROM, memory-mapped (see Figure Figure 2.6), leaving external address space. this space, used Neuron firmware reserved other specific functions. external memory space populated with RAM, ROM, PROM, EPROM, EEPROM, flash memory increments bytes. memory 3150 Smart Transceiver shown Figure 2.5. bidirectional data lines address lines driven processor. interface lines (R/W used external memory access. Refer 3120 3150 Smart Transceiver Datasheet required access times external memory used. input clock scaled down, slower memory used. input clock rates supported 3150 Smart Transceiver 20MHz, 10MHz, 5MHz. Enable Clock runs system clock rate, which one-half input clock rate. memory, both internal external, accessed three processors appropriate phase instruction cycle. Since instruction cycles three processors offset one-third cycle with respect each other, memory used only processor time. Neuron 3150 Chip External Memory Interface engineering bulletin provides guidelines interfacing 3150 Smart Transceiver different types memory. minimum hardware configuration would external (PROM EPROM), containing both Neuron firmware user application code. This configuration would allow system engineer change application code after installation. network image (network address connection information) however, could altered because this information resides internal EEPROM. application downloads over network requirement maintenance upgrade application code will into internal EEPROM, then external EEPROM flash will necessary. Refer Neuron Programmer's Guide guidelines reduce code size. pins used external memory interfacing listed Table 2.7. clock signal used generate read write) signals external memory. (address line programmable array logic (PAL) decoded signal gated with used generate read signals external memory.
3120 3150 Smart Transceiver Data Book
Input/Output
Table External Memory Interface Pins
Designation Direction Output Input/Output Output Output Function Address Pins Data Pins Enable Clock Read/Write Select
preferred method interfacing Smart Transceiver another through pins using serial parallel connection, through dual-ported device such Cypress CY7C144, CY7C138, CY7C1342. There pre-defined serial parallel models this purpose which easily implemented using Neuron programming language, short stack firmware used simplify interface. more details dual-ported interfacing, Appendix LONWORKS Microprocessor Interface Program User's Guide (Echelon 078-0017-01).
Input/Output
Eleven Bidirectional Pins
These pins usable several different configurations provide flexible interfacing external hardware access internal timer/counters. logic level output pins read back application processor. Section detailed electrical characteristics. Pins have programmable pull-up current sources. They enabled disabled with compiler directive (see Neuron Reference Guide). Pins have high current sink capability others have standard sink capability (1.4 pins (IO0 IO10) have level inputs with hysteresis. Pins also have level detect latches.
16-Bit Timer/Counters
timer/counters implemented load register writable processor, 16-bit counter, latch readable processor. 16-bit registers accessed byte time. Both 3120 3150 Smart Transceivers have timer/counter whose input selectable among pins IO7, whose output IO0, second timer/counter with input from output (Figure 2.7). pins dedicated timer/counter functions. example, Timer/Counter used input signals only, then available other input output functions. Timer/counter clock enable inputs from external pins, from scaled clocks derived from system clock; clock rates timer/counters independent each other. External clock actions occur optionally rising edge, falling edge, both rising falling edges input.
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Chapter Hardware Resources
System Clock Divide Chain
System Clock Divide Chain
Control Logic
Timer/Counter
Control Logic
Timer/Counter
Figure Timer/Counter Circuits
Clock Input
Smart Transceivers operate with input clock 20MHz. 3120 Smart Transceiver also supports 40MHz operation. Developers using LonBuilder 3.0.1 NodeBuilder tools upgrading clock speed higher than 10MHz should refer readme.txt file included latest Service Pack LonBuilder 3.01, NodeBuilder tools in-depth discussion about software considerations each platform. NodeBuilder later) development tool contains built-in support these higher clock speeds.
Clock Generation
Smart Transceiver divides input clock factor provide symmetrical on-chip system clock. input clock generated either external free-running oscillator on-chip oscillator Smart Transceiver using external parallel-mode resonant crystal. accuracy input clock frequency Smart Transceiver must ±200ppm better; this requirement with suitable crystal, cannot with ceramic resonator. Smart Transceiver includes oscillator that used generate input clock using external crystal. MHz, 10MHz, 20MHz, either external clock source on-chip crystal oscillator used. 40MHz operation 3120 Smart Transceiver, external oscillator must used. When externally generated clock used drive CLK1 CMOS input Smart Transceiver, CLK2 must left unconnected used drive more than external CMOS load. accuracy clock frequency must 0.02% (200 ppm) better, ensure that devices correctly synchronize their clocks. Figure shows crystal oscillator circuit. load capacitance resistor values recommended manufacturer crystal this circuit. 60/40 duty cycle better required when using external oscillator shown Figure 2.9. external oscillator must provide CMOS voltage levels CLK1 pin.
3120 3150 Smart Transceiver Data Book
Additional Functions
CLK1 EXTERNAL CRYSTAL
Figure Smart Transceiver Clock Generator Circuit
PWHIGH
PWLOW
Figure Test Point Levels CLK1 Duty Cycle Measurements 3120 Smart Transceiver designed frequencies 40MHz using external clock oscillator. External oscillators generally take several milliseconds stabilize after power-up. 3120 Smart Transceiver operating 40MHz must held reset until externally-generated input stable, external poweron-reset-pulse stretching chip/circuit required. Check specification oscillator vendor more information about startup stabilization times.
Additional Functions
Reset Function
reset function critical operation embedded microcontroller. case theFT 3120 3150 Smart Transceivers, reset function plays role following conditions:
Initial power (ensures proper initialization Smart Transceiver). power fluctuations (manages proper recovery Smart Transceiver after stabilizes). Program recovery application gets lost corruption address data, external reset used recovery watchdog timer could timeout, causing watchdog reset). power down (ensures proper shut down). Helps protect EEPROM from major corruption.
Smart Transceivers have four mechanisms initiate reset: RESET pulled then returned high. Watchdog timeout occurs during application execution (the timeout period 210ms 40MHz; this figure scales inversely with clock frequency).
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Chapter Hardware Resources
Software command either from application program from network. circuit detects drop power supply below level.
During reset functions, when RESET state, Smart Transceiver pins states described list below. Figure 2.11 also illustrates condition pins during reset Smart Transceivers initialization sequence after reset returned high again.
Oscillator continues processor functions stop SERVICE goes high impedance pins high impedance output address pins 0xFFFF 3150 Smart Transceiver only) data pins become outputs with high states 3150 Smart Transceiver only) clock goes high 3150 Smart Transceiver only) goes 3150 Smart Transceiver only)
When RESET released back high state, Smart Transceiver begins initialization procedure starting address 0x0001. time takes Smart Transceiver complete initialization differs between Smart Transceivers, different firmware versions that being run, memory space used application (code data). This will discussed later this section.
RESET
RESET both input output. input, RESET internally pulled high current source acting pull-up resistor. RESET becomes output when following events occur:
Watchdog Timer event. Software reset initialization. Internal detects voltage. RESET drops below internal trip point.
Power Sequence During power sequences, RESET should held until power supply stable, prevent start-up malfunctioning. Likewise, when powering down, Smart Transceiver RESET should state before power supply goes below minimum operating voltage Smart Transceiver. WARNING: proper reset recovery circuitry used, Smart Transceiver applicationless unconfigured. applicationless unconfigured state occurs when checksum error verification routine detects corruption memory which could have falsely been detected improper reset sequence noise power supply. Several options exist LonBuilder NodeBuilder tools allow reboot checksum failure. Figure 2.11 shows typical external RESET components. total capacitance directly connected RESET pin, including stray external device input capacitance, must exceed 1000 This ensures that Smart Transceiver successfully output reset down below 0.8V. minimum capacitance required noise immunity.
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Additional Functions
Software Controlled Reset When watchdog timer expires, software command reset occurs, RESET pulled CLK1 clock cycles. RESET external capacitor (100 1000 allowed begin charging provide required duration reset.
Smart Transceiver
Other Devices
RESET
Switch
RESET
using flash, external pulse-stretching must used (Dallas DS1233-10).
(100 1000 Max)
Figure 2.10 Example Reset Circuit Watchdog Timer Smart Transceivers protected against malfunctioning software memory faults three watchdog timers, each processor that makes Neuron core. application system software fails reset these timers periodically, entire Smart Transceiver automatically reset. watchdog period approximately 40MHz input clock rate scales inversely with input clock rate. Considerations 3120 3150 Smart Transceivers include internal ensure that they only operate above minimum voltage threshold. 3120 3150 Smart Transceiver Datasheet trip points. circuit operates below this voltage, improper operation could occur. example, Smart Transceiver writing internal external EEPROM flash memory when reset event initiated, then that data could corrupted. When using external flash memory 3150 Smart Transceiver device, external pulse-stretching greater than should used (Echelon recommends using Dallas Semiconductor Part DS1233-5). When using external oscillator drive CLK1 either Smart Transceivers, power-on-pulse-stretching needed ensure that external oscillator stabilized before Smart Transceiver released from reset. Since RESET Smart Transceiver bidirectional, external must have open-drain opencollector output. external actively drives RESET high, then Smart Transceiver will able reliably assert RESET (low) during internal resets. This contention Smart Transceiver RESET cause anomalous behavior, from applicationless errors physical damage Smart Transceiver reset circuitry.
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Chapter Hardware Resources
Reset Processes Timing
During reset period, pins high-impedance state. 3150 Smart Transceiver address lines forced 0xFFFF, forced forced data lines undetermined driven high low, they will float draw excess current. SERVICE high impedance during reset. Reset overrides effect clock data lines that, normal operations data only driven write cycle during clock portion cycle, while reset forces data driven. steps followed preparing Smart Transceiver execute application code discussed below. These steps summarized Figure 2.11. After RESET released, Smart Transceiver performs hardware firmware initialization before executing application programs. These tasks are:
Oscillator start-up Oscillator stabilization Stack initialization built-in self-test (BIST) SERVICE initialization State initialization
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Additional Functions
Specified Application
Specified Application
Scheduler Init One-Second Timer Init Checksum Init Comm Port Init System Setup
Stable Address Reflecting Firmware Execution
Random Number Seed Calc
Stable Data Reflecting Firmware Execution Stable Reflecting Firmware Execution
Off-Chip
Oscillates Divide CLK1
State Init
Pull-Ups Enabled
SERVICE Init Stack Init BIST Oscillator Stabilization* Oscillator Start-Up*
Oscillates
Output High
Reset
3150 ONLY
DATA [7:0]
[7:4]
*NOTE: power oscillator will start running before RESET released.
Figure 2.11 RESET Timeline 3120 3150 Smart Transceivers
Off-chip initialization Random number seed calculation System setup Communication port initialization Checksum initialization
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[10:8, 3:0]
ADDR [15:0]
SERVICE
RESET
WARNING: SCALE
Chapter Hardware Resources
One-second timer initialization Scheduler initialization
During internal oscillator start (after power up), Smart Transceiver waits oscillator signal amplitude grow before using oscillator waveform system clock. This period depends type oscillator used frequency, begins soon power applied oscillator independent RESET pin. oscillator start-up period before after RESET released, depending duration reset time required oscillator start After oscillator started Smart Transceiver counts additional transitions CLK1 allow frequency oscillator stabilize. From time RESET asserted until oscillator stabilization period, pins high-impedance state. signal goes inactive (high) immediately after reset goes low, address becomes high (0xFFFF) deselect external devices. stack initialization BIST task tests on-chip RAM, timer/counter logic, counter logic. test pass, three processors must functioning. flag indicate whether Smart Transceiver passed failed BIST. cleared this step. beginning this task, pull-ups IO[7:4] enabled, that weak high state observed these pins. SERVICE oscillates between solid weak high. memory interface signals reflect execution these tasks. self-test fails, device goes offline, service comes solid, error logged status structure device. Self-test results available first byte (0xE800) follows:
Value Description Failure failure Timer/counter failure Counter failure Configured input clock rate exceeds chip maximum
SERVICE initialization task turns SERVICE (high state). state initialization task determines Smart Transceiver boot required 3150 Smart Transceiver only), performs boot required. Smart Transceiver decides perform boot blank, boot does match boot ROM. off-chip initialization task checks memory determine off-chip present then either tests clears off-chip optionally, clears application area only. This choice controlled application program Neuron compiler directive. This task applies only 3150 Smart Transceiver. random number seed calculation task creates seed random number generator. system setup task sets internal system pointers well linked lists system buffers. checksum initialization task generates checks checksums nonvolatile writable memories. boot process executed configured unconfigured states, state initialization task, then checksums generated; otherwise, they checked. This process includes on-chip EEPROM, off-chip EEPROM, flash, offchip nonvolatile RAM. There checksums, configuration image application image. each case, checksum negated two's complement values image. one-second timer initialization task initializes one-second timer. this point, network processor available accept incoming packets. scheduler initialization task allows application processor perform application-related initialization follows:
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Additional Functions
State wait wait device leave applicationless state. Pointer initialization perform global pointer initialization. Initialization step execute initialization task, which created compiler/linker handle initialization static variables timer/counters. initialization step initialize pins based application definition. Prior this point, pins high impedance. State wait wait device leave unconfigured hard-offline state. waiting required, flag indicate that device should come offline. Parallel synchronization devices using parallel attempt execute master/slave synchronization protocol this point. Reset task execute application reset task (when (reset{})).
offline flag set, offline execute offline task. BIST flag indicated failure, then SERVICE turned offline task executed. Otherwise, scheduler starts normal task scheduling loop. amount time required perform these steps depends many factors, including: Smart Transceiver model; input clock rate; whether device performs boot process; whether device applicationless, configured, unconfigured; amount off-chip RAM; whether off-chip tested simply cleared; number buffers allocated; application initialization. Table Table summarize number input clock cycles (CLK1) required each these steps 3120 3150 Smart Transceivers. times approximate given functions most significant application variables. Table 3120 Smart Transceiver Reset Sequence Time
Step Stack Initialization BIST SERVICE Initialization State Initialization Off-Chip Initialization Random Number Seed Calculation System Set-up Communication Port Initialization Checksum Initialization One-Second Timer Initialization Scheduler Initialization Number CLK1 Cycles 386,000 1000 (for boot) 2,275,000 (for boot) 21,000 600*B 3400 175*M 6100 7400 Notes
Notes: Note These tasks parallel with other tasks. Note number application and/or network buffers allocated. Note number bytes checksummed. Note Assumes trivial initialization task, reset task configured state.
example, timing each these steps shown 3120 Smart Transceiver application with following parameters: 10MHz input clock, crystal oscillator, boot required, least application and/or network buffers, bytes EEPROM checksummed. Stack Initialization BIST SERVICE Initialization State Initialization Off-Chip Initialization Random Number Seed Calculation
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38.6 0.025
Chapter Hardware Resources
System Setup Communication Port Initialization Checksum Initialization One-Second Timer Initialization Scheduler Initialization Total
10.8 0.61 0.74 53.7
Table 3150 Smart Transceiver Reset Sequence Time
Step Stack Initialization BIST SERVICE Initialization State Initialization Off-Chip Initialization Random Number Seed Calculation System Setup Communication Port Initialization Checksum Initialization One-Second Timer Initialization Scheduler Initialization Number CLK1 Cycles 425,000 1000 1300 (for boot) 70,000 ms*E (for boot) 24,000 214*R (for test clear) 24,000 152*Ra (for clear only) 50,000 27,000 1500*B 7200 175*M (for boot) 82,000 175*M (for boot) 6100 7400 Notes
Notes: Note number non-zero bytes being written (ranges from 504). Note number off-chip bytes. Note number non-system off-chip bytes. Note number application and/or network buffers allocated. Note These tasks parallel with other tasks. Note number bytes checksummed. Note Only booting configured unconfigured state; booting applicationless state, boot" equation. Note Assumes trivial initialization task, reset task, configured state.
example, timing each these steps shown 3150 Smart Transceiver application with following parameters: 10MHz input clock, crystal oscillator, boot required, external RAM, test clear external RAM, least application and/or network buffers, bytes EEPROM checksummed. Stack Initialization BIST SERVICE Initialization State Initialization Off-Chip Initialization Random Number Seed Calculation System Setup Communication Port Initialization Checksum Initialization One-Second Timer Initialization Scheduler Initialization Total 42.5 0.13 12.5 0.61 0.74
following compiler directive disable testing off-chip RAM: pragma ram_test_off
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SERVICE
SERVICE alternates between input open-drain output rate with duty cycle. When output, sink driving LED. When used exclusively input, optional onchip pull-up bring input inactive-high state when pull-up resistor connected. Under control Neuron firmware, this used during configuration, installation, maintenance device containing Smart Transceiver. firmware flashes 1/2-Hz rate when Smart Transceiver been configured with network address information. Grounding SERVICE causes Smart Transceiver transmit network management message containing unique 48-bit Neuron program application network. This information then used network tool install configure device. typical circuit SERVICE push-button shown Figure 2.12. During reset SERVICE state indeterminate. default state SERVICE pull-up enabled. 3120/3150 Smart Transceiver
Config Pull-Up
SERVICE
Broadcast
Sink
Drive
driving duty cycle output. Waveform sampled external ground condition.
ThreeState SERVICE Signal
ThreeState
ThreeState
Firmware Samples
Figure 2.12 Smart Transceiver SERVICE Circuit
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Table 2.10 Service Behavior During Different States
Device State Applicationless Unconfigured Unconfigured (but with Application) Configured, Hard Offline Configured 3150 Defective External Memory 0xF015 State Code Service Flashing
SERVICE active service message sent once maximum SERVICE transition. service message goes into next available priority non-priority output network buffer.
Integrity Mechanisms
Memory Integrity Using Checksums
ensure integrity memory Smart Transceiver Neuron firmware maintains number checksums. Each checksum single byte two's complement bytes covers. These checksums verified during reset processing also continual basis background diagnostic process. There three main checksums used verify integrity memory Smart Transceiver:
Configuration image checksum Application image checksum System image checksum (off-chip system image only)
configuration image checksum covers network configuration information communication parameters residing on-chip EEPROM. default behavior that configuration checksum error causes device unconfigured state. Refer Table 2.12 other options. application image checksum covers application code both on-chip EEPROM application code off-chip EEPROM, NVRAM, flash memory. This checksum optionally extended cover application code off-chip well. default behavior that application checksum error causes device applicationless state. Application read/write data residing EEPROM, NVRAM, flash checksummed. Refer Table 2.12 other options. Table 2.11 Checksum Coverage Smart Transceiver Memory Areas
Memory Area Checksum System Application Application Application Configuration Application
System image (optionally covered application checksum 3150) off-chip code (optionally covered Application checksum 3150) off-chip flash, EEPROM, NVRAM code off-chip code Configuration image on-chip EEPROM code
3150 Smart Transceiver, memory areas listed Figure 2.11 except on-chip EEPROM code have their checksum that checksum errors further isolated. unconfigured configured device continually checks application checksum background rate byte iteration through main loop network processor bytes millisecond when running 10MHz with network activity).
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Integrity Mechanisms
system image checksum covers system image. only available when system image resides off-chip memory optional. system image checksum error always forces device applicationless state. checksum computed device applicationless state. checksums verified during reset processing network processor part background diagnostic process. background diagnostic process causes device reset when error detected; state change occurs. assumed that persistent error will found reset processing. Upon detecting checksum error, reset process will force appropriate state error error log. 3150 Smart Transceiver, checksum must fail twice during reset processing order deemed bad.
Reboot Integrity Options Word
3150 Smart Transceiver number options actions taken following checksum error other memory related fatal errors. 16-bit word resides system image defined part export options device LonBuilder NodeBuilder tools. recovery process relies fact that initial on-chip EEPROM image application, configuration, communication parameter data reside off-chip system image. During initial power system image data copied (booted) on-chip EEPROM. recovery process recopies reboots suspect areas dictated error recovery options. changes made on-chip EEPROM (e.g., network application load network tool initiated reconfiguration) after initial boot lost recovery process. recovery action defined setting combination bits defined following masks (Table 2.12). Table 2.12 Recovery Action Masks
Recovery Word 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 Description Reboot application application fatal error. Always reboot application reset (see NOTE Reboot configuration configuration checksum fails. Reboot configuration application fatal error. Always reboot configuration reset. Reboot communication parameters configuration checksum fails. Reboot communication parameters type rate mismatch. Always reboot communication parameters reset. Reboot EEPROM variables when rebooting application. Applicationless state considered application fatal error. option 0x0001 0x0008 set, applicationless state will result reboot. Application fatal errors defined below (see NOTE Checksum code, including system image.
0x0400
NOTE Applications exported with these options cannot loaded over network.
above options, "configuration" does include communication parameters since their recovery governed separately. Also, fatal application errors refer application image checksum errors, memory allocation failures, memory failures. Refer Programming 3150 Chip Memory LonBuilder User's Guide (Revision 3.0) Loading Application Image NodeBuilder User's Guide (Release Revision more information. configuration will rebooted independently application only configuration table sizes match between EEPROM ROM. This avoids situation where application with different table sizes loaded over network, reboot configuration corrupts program.
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When EEPROM recovery occurs checksum failure other error, event will logged error table Smart Transceiver. test command will show EEPROM recovery occurred last error logged.
Reset Processing
During reset processing, configuration checksum checked first. bad, configuration recovery options set, then configuration checksum error logged, checksum repaired, device state changed unconfigured. configuration recovery option set, configuration recovered. Next, application checksum checked. bad, checksum error system image, then system image checksum error logged device state changed applicationless. application checksum bad, application recovery options set, application checksum error logged device state changed applicationless. application checksum application recovery option boot application does contain references off-chip ROM, flash, EEPROM, NVRAM, code, there checksum errors these regions, then application recovered. Otherwise, application checksum error logged device goes applicationless.
Signatures
off-chip code areas have 2-byte cyclic redundancy check (CRC) called signature, immediately following area checksum. Signatures stored area memory map. Mismatches between area signature memory copy signature result device going applicationless. This mechanism prevents partial application load over network which incompatible with unloaded code (such code ROM).
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Input/Output Interfaces
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Chapter Input/Output Interfaces
Overview
3120 3150 Smart Transceivers connect application-specific external hardware pins, named IO0-IO10. These pins configured numerous ways provide flexible input output functions with minimal external circuitry. programming model (Neuron language) allows programmer declare more pins objects. object provides programmable access driver specified on-chip hardware configuration specified input output waveform definition. program then refer these objects io_in io_out() system calls perform actual input/output function during execution program. Certain events associated with changes input values. task scheduler thus execute associated application code when these changes occur. There different objects available with Smart Transceivers. Most Objects available Smart Transceiver system images default. object included default system image required application, development tool will link appropriate objects into available memory space. 3120 Smart Transceiver designs, this means that internal EEPROM space must used additional object. 3150 Smart Transceiver designs, object will added external flash region beyond 16KB space reserved system image. Smart Transceivers have 16-bit timer/counters on-chip (see Figure 2.7). input timer/counter also called multiplexed timer/counter, selectable among pins IO7, programmable multiplexer (mux) output connected IO0. input timer/counter also called dedicated timer/counter, connected output IO1. timer/counters implemented 16-bit load register writable CPU, 16-bit counter, 16-bit latch readable CPU. load register latch accessed byte time. pins dedicated timer/counter functions. example, timer/counter used input signals only, then available other input output functions. Timer/counter clock enable inputs from external pins, from scaled clocks derived from system clock; clock rates timer/counters independent each other. External clock actions occur optionally rising edge, falling edge, both rising falling edges input. Multiple timer/counter input objects declared different pins within single application. calling io_select() function, application first timer/counter implement four different input objects. timer/counter configured implement output objects, configured quadrature input object, then reassigned another timer/counter object same application program.
IO10
Timer/Counter
Timer/Counter
System Clock Divide Chain
Sink Capability
Programmable Pull-Up Capability
Figure Smart Transceiver Timer/Counter External Connections
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Hardware Considerations
Hardware Considerations
Tables through list different objects available. Various objects different types used simultaneously. Figure summarizes configuration each objects. electrical characteristics these pins, refer 3120 3150 Smart Transceiver Datasheet. following sections contain detailed descriptions objects. application program optionally specify initial values digital outputs. Pins configured outputs also read inputs, returning value last written. Pins have optional pull-up current sources that like pull-up resistors (see Figure 3.1). These enabled with Neuron compiler directive (#pragma enable_io_pullups). Pins have high sink capability. others have standard sink capability. Pins have low-level detect latches. latency timing values described later this section typical 10MHz. accuracy these values 10%. Most latency values scale down higher input clock rates scale lower input clock rates. pull-ups always enabled during stack initialization BIST task. This cause problem some applications, example driving relay. best solution that does have pull-up. However, with pull-up must used, pull-down resistor could used overcome effects pull-up. Typically, pull-down range 2.4k 2.7k adequate.
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Table Summary Direct Objects
Object Input Output Byte Input Byte Output Leveldetect Input Nibble Input Nibble Output Applicable Pins IO10 IO10 adjacent adjacent Input/Output Value binary data binary data binary data binary data Logic level detected binary data binary data Page
Table Summary Parallel Objects
Object Muxbus Parallel Applicable Pins IO10 IO10 Input/Output Value Page
Parallel bidirectional port using mul- tiplexed addressing Parallel bidirectional handshaking port
Table Summary Serial Objects
Object Bitshift Input Bitshift Output Magcard Input Applicable Pins adjacent pair (except IO8) adjacent pair (except IO8) (one IO7) Input/Output Value bits clocked data bits clocked data bytes bidirectional serial data Encoded ISO7811 track data stream from magnetic card reader Encoded ISO3554 track data stream from magnetic card reader bits bidirectional serial data 8-bit characters 8-bit characters Page
Magtrack1
(one IO7)
Neurowire Serial Input Serial Output Touch Wiegand Input
IO10 (one IO7) IO10 adjacent pair
2048 bits input output bits Encoded data stream from Wiegand card reader
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Hardware Considerations Table Summary Timer/Counter Input Objects
Object Dualslope Input Edgelog Input Infrared Input Ontime Input Period Input Pulsecount Input Quadrature Input Totalcount Input Applicable Pins IO0, (one IO7) IO5, Input Signal Comparator output dualslope converter logic stream input transitions Encoded data stream from infrared demodulator Pulse width 1.678 Signal period 1.678 65,535 input edges during 0.839 16,383 binary Gray code transitions 65,535 input edges Page
Table Summary Timer/Counter Output Objects
Object Edgedivide Output Applicable Pins IO0, (one IO7) Output Signal Output frequency input frequency divided user-specified number Square wave 2.5MHz Pulse duration 1.678 65,535 pulses 100% duty cycle pulse train Page
Frequency Output Oneshot Output Pulsecount Output Pulsewidth Output Triac Output Triggeredcount Output
IO0, IO0, IO0, IO0, IO0, (one IO7) IO0, (one IO7)
Delay output pulse with respect input edge Output pulse controlled counting input edges
maintain provide consistent behavior external events prevent metastability, pins Smart Transceiver, when configured inputs, passed through hardware synchronization block sampled internal system clock. This always input clock divided (e.g. 10MHz 5MHz). signal reliably synchronized with 10MHz input clock, must least duration (see Figure 3.2). inputs software sampled during when statement processing. latency sampling dependent object which being executed (see timing specification Neuron Programmer's Guide more information). These latency values scale inversely with input clock. Thus, event that lasts longer than will synchronized hardware, there will latency software sampling resulting delay detecting event. state changes faster rate than software sampling occur, then interim changes will undetected. There exceptions synchronization block. First, chip select (CS) input used slave mode parallel object; this input will recognize rising edges asynchronously (see page 45). Second, leveldetect input latched flip flop with 200ns clock. leveldetect transition event will latched, there will delay software detection (see page 43). input timer/counter functions also different, that events pins will accurately measured value returned register, regardless state application processor. However, application processor delayed reading register. Consult Neuron Programmer's Guide detailed programming information.
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tsetup
thold
Input IO_0 IO_10 Internal System Clock
(200 pulse with 10MHz Input Clock)
Figure Synchronization External Signals
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Timing Issues
DIRECT OBJECTS
Input, Output Byte Input, Byte Output Leveldetect Input Nibble Input, Nibble Output Four Adjacent Pins Data Pins Data Pins Data Pins Optional Timeout Optional Timeout Optional Chip Select Optional Timeout Muxbus Master/Slave Slave Pins
PARALLEL OBJECTS Parallel
Notes: Clock, Data Bitshift, I2C, Magcard, Magtrack, Neurowire Timer/Counter Devices IO_6 input quadrature IO_4 input edgelog IO_0 output [triac triggeredcount edgedivide] sync(IO_4.7) IO_0 output [frequency oneshot pulsecount pulsewidth] four IO_4 input [ontime period pulsecount totalcount dualslope infrared] IO_5.7 input [ontime period pulsecount totalcount dualslope infrared] Timer/Counter Devices IO_4 input quadrature IO_4 input edgelog IO_1 output [triac triggeredcount edgedivide] sync(IO_4) IO_1 output [frequency oneshot pulsecount pulsewidth] IO_4 input [ontime period pulsecount totalcount dualslope infrared]
Bitshift Input, Bitshift Output Magcard Input Magtrack1 Input
SERIAL OBJECTS
Neurowire
Master Slave
Serial Input Serial Output Wiegand Input Dualslope Input Edgelog Input Infrared Input Pins (Optional Timeout) Control
TIMER/COUNTER INPUT OBJECTS
Ontime Input Period Input
Pulsecount Input
Quadrature Input Totalcount Input Edgedivide Output Sync Input
TIMER/ COUNTER OUTPUT OBJECTS
Frequency Output Oneshot Output Pulsecount Output Pulsewidth Output Triac Output Triggeredcount Output Control Control Sync Input Sync Input
High Sink
Pull
Standard
Figure Summary Objects
Timing Issues
Smart Transceiver timing influenced three separate, overlapping areas overall chip architecture:
scheduler firmware object
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Chapter Input/Output Interfaces
Smart Transceiver hardware
contribution scheduler overall timing characteristic approximately uniform across function blocks since contribution overall timing relatively high functional level. contribution firmware hardware varies from object another (e.g., versus Neurowire I/O), with area generally being dominant factor.
Scheduler-Related Timing Information
part Smart Transceiver firmware, scheduler provides orderly predictable means facilitate evaluation user-defined events. when clause, provided Neuron language, used specify such events. more information operation scheduler, refer Neuron Programmer's Guide. There finite latency associated with operation scheduler. time required scheduler evaluate same when clause particular user application code large extent, function size user code, total number when clauses, state events associated with those when clauses. Therefore, impossible specify nominal value this latency, each application will have distinct behavior under different circumstances. best case latency viewed several ways, each exposing different aspect scheduler operation. simple example consists having application program consisting when clauses, both which always evaluate TRUE, shown below.
IO_0 output testbit; when (TRUE) io_out(testbit, when (TRUE) io_out (testbit,
Processing when clauses done round-robin fashion; therefore, Neuron code above performs alternating activation order isolate extract timing parameters associated with scheduler. waveform seen Smart Transceiver, result above code, shown Figure 3.4.
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Timing Issues
IO_out call
IO_out call
IO_out call
tsol
IO_0
TIME
when clause end-of-loop processing begins when clause when clause
(Not scale)
Symbol tsol
Description when-clause when-clause latency Scheduler overhead latency (see text)
10MHz
Figure when-Clause when-Clause Scheduler Overhead Latency when-clause when-clause latency, tww, this case includes execution time io_out() function latency 10MHz) event that always evaluates TRUE. actual given application driven actual task within when statement well when event which evaluated. above example only measures best-case minimum latency between consecutive when clauses (whose events evaluate TRUE), tww, also reveals that end-of-loop overhead latency scheduler tsol. shown Figure 3.4, off-time period output waveform tsol on-time output waveform, minus tww. This shows that scheduler overhead latency, scheduler end-of-loop latency, occurs just before execution last when clause program. latency associated with return from io_out() function small, relative that execution function call itself. NOTE: Some objects suspend application processing until task complete. This because they firmware-driven. These bitshift, Neurowire, parallel, serial objects, I2C, magcard, magtrack, Touch I/O, Wiegand. They suspend network communication this handled network processor media access processor.
Firmware Hardware-Related Timing Information
updates Smart Transceiver performed Neuron firmware using system image function calls. total latency given function call, from start end, broken down into separate parts. first processing time required before actual hardware update (read write) occurs. second delay associated with time required finish current function call return application program. Overall accuracy always related accuracy CLK1 input Smart Transceiver. Timing diagrams provided non-trivial cases clarify parameters given. more information operation each objects, refer Neuron Reference Guide.
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Chapter Input/Output Interfaces
Direct Objects
timing numbers shown this section valid both explicit call implicit call through when clause, assumed Smart Transceiver running 10MHz.
Input/Output
Pins IO10 individually configured single-bit input output ports. Inputs used sense TTLlevel compatible logic signals from external logic, contact closures, like. Outputs used drive external CMOS level compatible logic, switch transistors very current relays actuate highercurrent external devices such stepper motors lights. high (20mA) current sink capability pins allows these pins drive many devices directly (refer Figure 3.5). Figures show input output latency times, respectively. These times from which io_in() io_out() called, until value returned. direction ports changed between input output dynamically under application control.
IO10
IO10 Optional Pull-Up Resistors
High Current Sink Drivers
Figure WARNING: After Reset, Smart Transceiver performs self-test which includes enabling 104-107 pullup resistors. This could cause positive level change.
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Direct Objects
tfin INPUT TIME START io_in()
tret
INPUT SAMPLED
io_in()
Symbol tfin tret
Description Function call sample IO10 Return from function IO10
10MHz 23.4 27.9 32.3 36.7 41.2 45.6 23.4 27.9
Figure Input Latency Values
tfout
tret
OUTPUT TIME START io_out() OUTPUT UPDATED io_out()
Symbol tfout
Description Function call update others Return from function IO10
10MHz
tret
Figure Output Latency Values
Byte Input/Output
Pins configured byte-wide input output port, which read written using integers range 255. This useful driving devices that require ASCII data, other data, eight bits time. example, alphanumeric display panel byte function data, pins IO10 function
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Chapter Input/Output Interfaces
control addressing. Figures 3.8, 3.9, 3.10. represents data. direction byte port changed between input output dynamically under application control.
IO10
IO10 Optional Pull-Up Resis-
High Current Sink Drivers
Figure Byte
tfin INPUT TIME START io_in()
tret
INPUT SAMPLED
io_in()
Symbol tfin tret
Description Function call input sample Return from function
10MHz
Figure Byte Input Latency Values
tfout
tret
OUTPUT TIME START io_out() OUTPUT UPDATED io_out()
Symbol tfout tret
Description Function call update Return from function
10MHz
Figure 3.10 Byte Output Latency Values
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Direct Objects
Leveldetect Input
Pins individually configured leveldetect input pins, which latch negative-going transition input level with minimal pulse width 200ns, with Smart Transceiver clocked 10MHz. application therefore detect short pulses input which might missed software polling. This useful reading devices, such proximity sensors. This only direct object which latched before sampled. latch cleared during when statement sampling again immediately after, another transition should occur. Figure 3.11.
tfin INPUT 200ns SYSTEM CLOCK 10MHz) INPUT LATCH TIME NEGATIVE TRANSITION LATCHED START io_in() INPUT LATCH SAMPLED THEN CLEARED
tret
IO10 Optional Pull-Up Resistors
io_in() NEGATIVE TRANSITION LATCHED
Symbol tfin
Description Function call sample Return from function
10MHz 39.4 43.9 48.3 52.7 57.2 61.6
tret
Figure 3.11 Leveldetect Input Latency Values
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Chapter Input/Output Interfaces
Nibble Input/Output
Groups four consecutive pins between configured nibble-wide input output ports, which read written using integers range This useful driving devices that require data, other data four bits time. example, switch matrix scanned using nibble generate output (row select four rows), nibble read input from columns switch matrix. Figures 3.12, 3.13, 3.14. direction nibble ports changed between input output dynamically under application control (see Neuron Programmer's Guide). input data determined object declaration pins.
IO10
High Current Sink Drivers Optional Pull-Up Resistors
Figure 3.12 Nibble
tfin INPUT TIME START io_in()
tret
INPUT SAMPLED
io_in()
Symbol tfin tret
Description Function call sample Return from function
10MHz 22.8 27.5 32.3
Figure 3.13 Nibble Input Latency Values
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Parallel Objects
tfout
tret
OUTPUT TIME START io_out() OUTPUT UPDATED io_out()
Symbol tfout
Description Function update Return from function
10MHz 89.8 101.5 113.3
tret
Figure 3.14 Nibble Output Latency Values
Parallel Objects
Muxbus Input/Output
This object provides means performing parallel data transfers between Smart Transceiver attached peripheral device processor (see Figure 3.15). Unlike parallel input/output object, which makes token-passing scheme ensuring synchronization, muxbus input/output enables Smart Transceiver essentially control read write operations times. This relieves burden protocol handling from attached device results easier-to-use interface expense data throughput capacity. data remains last state used.
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ADDR/ DATA IO10 C_WS (IO9) C_RS (IO10) C_ALS (IO8)
ADDR
DATA
ADDR
DATA
trset
twas
tahw
tadrs
tahr
tdws C_ALS C_WS C_RS
TIME START io_out()
twhold
twrs
trhold
tfout
twws
twret
tfin
trret
io_in()
io_out()
START io_in()
NOTE: Data latched after falling edge C_RS. Symbol tfout tahw tahr twas twrs twws tdws trset twhold trhold tadrs tfin trret twret Description io_out() valid address Address valid address strobe Address hold write Address hold read Address strobe width Read strobe width Write strobe width Data valid write strobe Read setup time Write hold time Read hold time Address disable read strobe io_in() valid address Function return from read Function return from write 10.8 26.4 10.8 10.8 10.8 26.4
Figure 3.15 Muxbus Object
Parallel Input/Output
Pins IO10 configured bidirectional 8-bit data 3-bit control port connecting external processor. other processor computer, microcontroller, another Smart Transceiver (for gateway applications). parallel interface configured master, slave slave mode. Typically, Smart Transceivers interface master/slave mode Smart Transceiver interfaces with another microprocessor
3120 3150 Smart Transceiver Data Book
Parallel Objects slave configuration, with other microprocessor master. Handshaking used both modes control instruction execution, application processing suspended duration transfer bytes/ transfer). Consult Neuron Reference Guide detailed programming instructions. Upon reset condition, master processor monitors transition handshake (HS) line from slave, then passes CMD_RESYNC (0x5A) synchronization purposes. This must done within 0.84 seconds after reset goes high with Smart Transceiver slave running 10MHz, avoid watchdog reset error condition (see Neuron Programmer's Guide). CMD_RESYNC followed slave acknowledging with CMD_ACKSYNC (0x07). This synchronization ensures that both processors properly reset before data transfer occurs. When interfacing Smart Transceivers, these characters passed automatically (refer flow table illustrated later this section). However, when using parallel interface Smart Transceiver another microprocessor, that microprocessor must duplicate interface signals characters that automatically generated parallel function Smart Transceiver. additional information, Parallel Interface Neuron Chip engineering bulletin. timing numbers shown this section valid both explicit call implicit call through when clause, assumed Smart Transceiver running 10MHz. Master/Slave Mode This mode recommended when interfacing Smart Transceivers. master/slave configuration, master drives chip select specify read write cycle, slave drives IO10 handshake (HS) acknowledgment (see Figure 3.16). maximum data transfer rate byte processor instruction cycles, byte 40MHz input clock rate. data transfer rate scales proportionally input clock rate master write slave read). Timing case where Smart Transceiver master (Figure 3.17), refers measured output timing 10MHz. After every byte write byte read, line monitored master, verify slave completed processing (when slave ready next byte transfer. This done automatically Smart Transceiver-to-FT Smart Transceiver (master/slave mode) data transfers. line should pulled (inactive) with resistor ensure proper resynch behavior after slave resets. Slave timing shown Figure 3.18.
IO10 PARALLEL MASTER
IO10
PARALLEL SLAVE
Figure 3.16 Parallel Master Slave
3120 3150 Smart Transceiver Data Book
Chapter Input/Output Interfaces
tmhscs tmcspw tmhsh tmrws tmrwh tmrws tmcspw
tmhsv
tmhsh
tmhsv
tmhsdv tmrdz
DATA tmrds DATA READ CYCLE WRITE CYCLE tmwdh tmwds
tmwdd
tmrdh
Symbol tmrws tmrwh tmcspw tmhsh tmhsv tmrdz tmrds tmhscs tmrdh tmwdd tmhsdv tmwds tmwdh
Description setup before falling edge hold after rising edge pulse width hold after falling edge checked firmware after rising edge Master three-state DATA after rising edge (Notes Read data setup before falling edge (Note falling edge (Note Read data hold after falling edge Master drive DATA after falling edge (Note data valid (Note Write data setup before rising edge Write data hold after rising edge (Note
CLK1 Note
CLK1 CLK1 CLK1 CLK1 CLK1 CLK1
Notes: Refer 3120 3150 Smart Transceiver Datasheet detailed measurement information. Smart Transceiver-to-FT Smart Transceiver operation, contention (tmrdz, tsawdd) eliminated firmware, ensuring that zero state present when token passed between master slave. Parallel Interface Neuron Chip engineering bulletin further information. high used slave busy flag. held low, maximum data transfer rate CLK1s (2.4 10MHz) byte. used flag, caution should taken ensure master does initiate data transfer before slave ready. Parameters were added order interface design with Smart Transceiver. Master will hold output data valid during write until Slave device pulls low. CLK1 represents period Smart Transceiver input clock (100 10MHz). master read, pulsing acts like handshake flag slave that data been latched
Figure 3.17 Master Mode Timing
3120 3150 Smart Transceiver Data Book
Parallel Objects
tsacspw tsahsh tsarws tsarwh
tsahsv
tsacspw tsahsh
tsahsv
tsarws
tsawd
DATA tsawds DATA WRITE CYCLE (MASTER READ) tsawdh
tsards
tsardh
tsardz
READ CYCLE (MASTER WRITE)
Symbol tsarws tsarwh tsacspw tsahsh tsahsv tsawdd tsawds tsawdh tsardz tsards
Description setup before falling edge hold after rising edge pulse width hold after rising edge valid after rising edge Slave drive DATA after rising edge (Notes Write data valid before falling edge Write data valid after rising edge Slave three-state DATA after falling edge (Note Read data setup before rising edge
(Note
CLK1 CLK1
tsardh Read data hold after rising edge Notes: Refer 3120 3150 Smart Transceiver Datasheet detailed measurement information. Smart Transceiver-to-FT Smart Transceiver operation, contention (tmrdz, tsawdd) eliminated firmware, ensuring that zero state present when token passed between master slave. Parallel Interface Neuron Chip engineering bulletin further information. tsarwh then tsawdh tsarwh. CLK1 represents period Smart Transceiver input clock (100 10MHz). slave mode, signal high minimum CLK1 periods. typical time high during consecutive data reads consecutive data writes also CLK1 periods.
Figure 3.18 Slave Mode Timing following pair example programs that transfer data parallel master/slave configuration. code LonBuilder emulators hardwired shown Figure 3.16. master program writes test_data input bufferof slave master owns token after reset first option write bus) slave then outputs data input buffer master. buffers viewed through LonBuilder debugger verify transfer complete. master transmits [5,1,1,1,1,1] slave slave transmits [7,1,2,3,4,5,6,7,0,0,0,0,0,0] master. first byte indicates number bytes being passed; following non-zero valued bytes this example actual data transferred. remaining length array, any,
3120 3150 Smart Transceiver Data Book
Chapter Input/Output Interfaces
filled with master program writes once slave reads once from slave. implement continuous writes reads, io_out_request() function call after io_in() function call master program.
This master program. After reset, buffer filled with then buffer written slave. master then reads slave's buffer. master's output buffer should contain [5,1,1,1,1,1]; input buffer should contain [7,1,2,3,4,5,6,7,0,0,0,0,0,0]. IO_0 parallel master parallel_bus; #define TEST_DATA data written output buffer #define MAX_IN maximum length input data expected #define OUT_LEN output length equal less than #define MAX_OUT maximum array length struct parallel_out output structure unsigned len; actual length data output unsigned buffer[MAX_OUT]; array setup length data output }p_out; output structure name struct parallel_in input structure unsigned len; actual buffer length input unsigned buffer[MAX_IN]; maximum input array }p_in; unsigned when (reset) p_out.len=OUT_LEN; for(i=0; i<OUT_LEN; ++i) p_out.buffer[i]=TEST_DATA; io_out_request(parallel_bus); when (io_out_ready(parallel_bus)) io_out(parallel_bus, &p_out); when (io_in_ready(parallel_bus)) p_in.len=MAX_IN; io_in(parallel_bus, &p_in); input structure name
assign output length fill output buffer with request output buffer
output buffer when slave ready
declare maximum input buffer acceptable store input data buffer program
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This slave program. After reset, output buffer filled with data then slave reads from master. slave then writes master. slave's input buffer should contain [5,1,1,1,1,1]; output buffer should contain [7,1,2,3,4,5,6,7,0,0,0,0,0,0]. IO_0 parallel slave parallel_bus; #define MAX_IN maximum length input data expected #define OUT_LEN output length equal less than #define MAX_OUT maximum array length struct parallel_out output structure unsigned len; actual length data output unsigned buffer[MAX_OUT]; array setup length data output }p_out; struct parallel_in unsigned len; unsigned buffer[MAX_IN]; }p_in; unsigned when (reset) p_out.len=OUT_LEN; for(i=0; i<OUT_LEN; ++i) p_out.buffer[i]=i+1; when (io_out_ready(parallel_bus)) io_out(parallel_bus, &p_out); when (io_in_ready(parallel_bus)) p_in.len=MAX_IN; io_in(parallel_bus, &p_in); io_out_request(parallel_bus); output structure name input structure actual length buffer input maximum input array input structure name
assign output length fill output buffer with
output buffer
declare maximum input buffer acceptable store input data buffer request output buffer program
Debugging Above Programs: watchdog timeout occurs either LonBuilder emulator, simultaneously reset emulators using reset pushbutton switches face emulators. Both emulator boards should disconnected this application. Slave Mode slave mode recommended interfacing Smart Transceiver acting slave another microprocessor acting master. When configured slave mode, Smart Transceiver accepts chip select specify whether master will read write, accepts IO10 register select input. When asserted either IO10 IO10 high low, pins form bidirectional data bus. When IO10 high, high, asserted, driven acknowledgment signal master.
3120 3150 Smart Transceiver Data Book
Chapter Input/Output Interfaces
Smart Transceiver appear registers address space master; registers being read/write data register, other being read-only status register. Therefore, reads master address access status register handshaking acknowledgments other reads writes access data register transfers. control register, which read through IO0, bit. master reads after every master read write. D0/HS line should pulled (inactive) with resistor ensure proper resynch behavior after resets. When acting slave different microprocessor, Smart Transceiver slave mode handles handshaking token passing automatically. However, master microprocessor must read after each transaction must also internally track token passing. This mode designed with master processor that uses memorymapped I/O, address master typically connected IO10 Smart Transceiver. This illustrated Figures 3.19 3.20.
READ ONLY STATUS REGISTER IO10
READ/WRITE DATA REGISTER IO10 IO10
SLAVE D0/HS
IO10
HS/D0
Figure 3.19 Parallel Master/Slave 3120/FT 3150 Smart Transceiver Memory-Mapped Device) Token Passing Virtual token passing implemented eliminate possibility data contention. token owned master after synchronization passed between master slave devices. After each data transfer completed, token owner writes message (EOM) (0x00) indicate that transfer complete. never read. Instead, "processing EOM" indicates passing token. Token passing achieved executing either data packet NULL transfer. Only owner token write bus. Therefore, when master performs writes data bytes each) dummy read cycle (NULL character 0x00) must inserted between them order pass token. Token passing executed automatically Smart Transceiverto-FT Smart Transceiver interface. Refer section Data Transferring, master/slave flow transactions.
3120 3150 Smart Transceiver Data Book
Parallel Objects Handshaking Handshaking allows master monitor slave between every byte transfer, ensuring that both processors ready byte transferred. master owns token, master waits from slave before writing data bus. slave owns token, master monitors transition before reading bus. master slave mode, Smart Transceiver line IO10. slave mode, Smart Transceiver monitored which corresponds least significant data status register.
3120 3150 Smart Transceiver Data Book
Chapter Input/Output Interfaces
MASTER tsbcspw
tsbcspw tsbah
MASTER tsbas MASTER tsbrws tsbrwh tsbrws
LATCH
MASTER DATA tsbwdv WRITE CYCLE (MASTER READ)
tsbrds
tsbrdh
tsbwdz tsbwdh
READ CYCLE (MASTER WRITE)
SLAVE DATA
Symbol tsbrws tsbrwh tsbcspw tsbas tsbah tsbwdv tsbwdh tsbwdz tsbrds
Description setup before falling edge 3120 3150 Smart Transceivers hold after rising edge pulse width setup falling edge hold after rising edge write data valid Write data hold after rising edge (Notes rising edge Slave release data (Note Read data setup before rising edge
Note
tsbrdh Read data hold after rising edge Notes: slave write cycle (master read) pulse width directly related slave write data valid parameter master read setup parameter. calculate write cycle duration needed special application use: tsbcspw tsbwdv master's read data setup before rising edge Refer master's specification data book master read setup parameter. slave read cycle minimum pulse width Refer 3120 3150 Smart Transceiver Datasheet detailed measurement information. data hold parameter, tsbwdh, measured disable levels shown 3120 3150 Smart Transceiver Datasheet, rather than traditional data invalid levels. slave write cycle timing parameters same control register (HS) write data write. Special applications: Both state determine slave write cycle. used data transfer, then toggling line used with changes hardware. other words, held during slave write cycle, positive pulse (low high low) execute data transfer. high transition causes slave drive data with same timing parameters tsbwdv (redefined write data valid). Likewise, falling edge causes slave release data with same timing limits rising edge tsbwdz. This scenario only true slave write cycle applicable slave read cycle slave data transitions. This application helpful master separate read write signals signal. Caution must taken ensure free before transfers avoid contention.
Figure 3.20 Slave Mode Timing Data Transferring data transfer operation between master slave accomplished through virtual write tokenpassing protocol. write token passed alternatively between master slave infinite ping-pong fashion. owner token option writing series data bytes, alternatively, passing write token without data. Figure 3.21 illustrates sequence operations this token passing protocol.
3120 3150 Smart Transceiver Data Book
Parallel Objects
SMART TRANSCEIVERS
MASTER TOKEN
MASTER
WRITE DATA
PASS TOKEN
CMP_ RESYNC
SLAVE TOKEN
SLAVE
WRITE DATA
PASS TOKEN
CMP_ACK RESYNC
Figure 3.21 Handshake Protocol Sequence Between Master Slave Once possession write token, device Smart Transceiver host processor) transfer bytes data. stream data bytes preceded command length bytes. token holder keeps possession token until data bytes have been written, after which token passed attached device. same process repeated other side alternatively, token passed back without data. timing relationship between various Smart Transceiver signals involved this process shown following timing diagrams. Resynchronization Procedure: following procedure applies master/slave master/slave configuration. master initiates resynchronization with RESYNC (0x5A) command, slave acknowledges with ACKSYNC (0x07). slave does respond, master continues send RESYNC until slave responds correctly.
MASTER (Owns Token) Write RESYNC Write Process Write ACKSYNC Read ACKSYNC Write Process (Owns Token) master owns token when reset SLAVE master initiates resynchronization (0x5A) Read RESYNC message (EOM=0x00) slave acknowledges resynching (0x07)
Master writes buffer slave: Enter RD/_WR=0. MASTER SLAVE (Owns Token) Write XFER Read XFER Write (length)
master data write (XFER=0x01) length=number bytes data
3120 3150 Smart Transceiver Data Book
Chapter Input/Output Interfaces Read (length) Write (data_0) Write (data_n) Write Read (data_0) last byte data transferred Read (data_n) data transfer (EOM=0x00) Process EOM// exchange token (Owns Token) master begins data transfer slave
Slave writes buffer master: Enter RD/_WR=1. MASTER SLAVE (Owns Token) Write XFER Read XFER Write (length) Read (length) Write (data_0) Read (data_0) Write (data_n) Read (data_n) Write Process (Owns Token)
slave data write (XFER=0x01) length=number bytes data slave begins writing data master
last byte data transferred data transfer exchange token
Master passes token slave: Entry same when master writes buffer slave. MASTER SLAVE (Owns Token) Write NULL master data send slave Read NULL NULL=0x00 Write message (EOM=0x00) Process exchange token (Owns Token)
Slave passes token master: Entry same when slave writes buffer master. MASTER SLAVE (Owns Token) Write NULL slave data send master Read NULL NULL=0x00 Write message (EOM=0x00) Process exchange token (Owns Token)
3120 3150 Smart Transceiver Data Book
Serial Objects
Serial Objects
timing numbers shown this section valid both explicit call implicit call through when clause, assumed Smart Transceiver running 10MHz.
Bitshift Input/Output
Pairs adjacent pins configured serial input output lines. first pair IO0-IO6, IO8, IO9, used clock (driven Smart Transceiver). adjacent higher-numbered then used bits serial data. data rate configured 1kbps, 10kbps, 15kbps 10MHz input clock rate. data rate scales proportionally input clock rate, example: 4kbps, 40kbps, 60kbps 40MHz input clock rate. active clock edge specified either rising falling. This object useful transferring data external logic employing shift registers. This function suspends application processing until operation complete. Figures 3.22, 3.23, 3.24.
IO10 BITSHIFT OUTPUT
Data Data Data Data Data
IO10 BITSHIFT INPUT
Data Data Data Data Data
Figure 3.22 Bitshift Examples
bitshift input, clock output deasserted inactive level) same time start first data. bitshift output, clock output initially inactive prior first data (unless overridden output overlay).
3120 3150 Smart Transceiver Data Book
Chapter Input/Output Interfaces
INPUT SAMPLED
thold tfin OUTPUT CLOCK taet ttae
tret
DATA
START io_in()
io_in()
Active clock edge assumed positive above diagram
Symbol tfin tret thold
Description Function call first edge Return from function Active clock edge sampling input data kbps rate kbps rate kbps rate Active clock edge next clock transition kbps rate kbps rate kbps rate Clock transition next active clock edge kbps rate kbps rate kbps rate Clock frequency 1/(taet ttae) kbps rate kbps rate kbps rate
10MHz 156.6 40.8 938.2 31.8 63.6 14.4 14.4 14.4 21.6 12.8 1.03
taet
ttae
Figure 3.23 Bitshift Input Latency Values
3120 3150 Smart Transceiver Data Book
Serial Objects
tsetup tfin OUTPUT CLOCK taet ttae
tret
DATA
START io_in()
io_in()
Active clock edge assumed positive above diagram
Symbol tfin
Description Function call first data stable 16-bit shift count 1-bit shift count Return from function Data stable active clock edge kbps rate kbps rate kbps rate Active clock edge next clock transition kbps rate kbps rate kbps rate Clock transition next active clock edge kbps rate kbps rate kbps rate Clock frequency 1/(taet ttae) kbps rate kbps rate kbps rate
10MHz 185.3 337.6 10.8 10.8 10.8 10.8 10.2 939.5 34.8 34.8 34.8 1.02
tret tsetup
taet
ttae
Figure 3.24 Bitshift Output Latency Values
Input/Output
This object used interface Smart Transceiver device which adheres Philips Semiconductor Inter-Integrated Circuit (I2C) protocol. Smart Transceiver always master, with being serial clock (SCL) serial data (SDA). These lines operated open-drain mode order accommodate special requirements protocol. With exception pull-up resistors, additional external components necessary interfacing Smart Transceiver device. bytes data transferred time. start transfers, right-justified 7-bit address argument sent immediately after "start condition." more information this protocol, refer Philips Semiconductor documentation.
3120 3150 Smart Transceiver Data Book
Chapter Input/Output Interfaces
IO10 tdch tchcl tchd tdcl TIME INPUT DATA SAMPLED TRANSFER TIMING
Clock Serial Data
tcld
tstart
tcla
tstop
tclch
TIME START io_in() io_out()
tret
io_in() io_out() START STOP TIMING
Parameter
Description call start condition io_in() io_out() start condition io_in() io_out() start start address io_in() io_out() data io_out() Data high io_out() Clock high clock io_out() high data sampling io_in() Data sample io_in() Clock clock high io_in() Clock high data io_in() io_out() high return from function io_in() io_out()
24.0 24.0 24.6 12.6 13.2 24.0 12.6 12.6
54.6 43.4
tstart
tcla
tcld tdch tchcl tchd tdcl tclch tstop
tret
Figure 3.25 Object
Magcard Input
This object used transfer synchronous serial data from 7811 Track magnetic stripe card reader real time. data presented data signal input IO9, clock, data strobe, signal input IO8. data clocked just following falling (negative) edge clock signal IO8, with
3120 3150 Smart Transceiver Data Book
Serial Objects first. addition, pins used timeout prevent lockup case abnormal abort input stream during input process. characters read time. Both parity Longitudinal Redundancy Check (LRC) checked Smart Transceiver.
IO10
Timeout
Clock Serial Data
DATA (IO9)
thold
tsetup CLOCK (IO8) tclk tlow TIMEOUT tret TIME START io_in()
thigh
twto
tfin
ttret
io_in()
Symbol tfin thold tsetup tlow thigh twto tclk ttret tret
Description Function call first clock input Data hold Data setup Clock width Clock high width Width timeout pulse Clock period Return from timeout Return from function
21.6
45.0
81.6 301.8
Figure 3.26 Magcard Input Object Smart Transceiver operating 10MHz process rate 8334 bits/second density bits/inch). This equates card velocity inches/second. Most magnetic card stripes contain 15-bit sequence zero data start card, allowing time application start card reading function. 8334 bits/ second, this period about scheduler latency greater than value, io_in() function will miss front data stream. rate processing capability scales with input clock rate. example: rate 33,336 40MHz.
3120 3150 Smart Transceiver Data Book
Chapter Input/Output Interfaces
Magtrack1 Input
This input object type used read synchronous serial data from ISO3554 magnetic stripe card reader. data input IO9, clock, data strobe, presented input IO8. data clocked just following falling edge clock signal IO7, with first.
IO10 (IO9)
Timeout
Clock Serial Data
thold tsetup
CLOCK (IO8) tlow tclk TIMEOUT
thigh
twto
tfin
TIME START io_in()
tret ttret
io_in()
Symbol tfin thold tsetup tlow thigh twto tclk ttret tret
Description Function call first clock input Data hold Data setup Clock width Clock high width Width timeout pulse Clock period Return from timeout Return from function
tlow 21.6
45.0
tclk 81.6 301.8
Figure 3.27 Magtrack1 Input Object minimum period entire cycle (tclk) greater than thigh. tsetup hold times should such that data stable duration tlow.
3120 3150 Smart Transceiver Data Book
Serial Objects Data recognized IATA format series 6-bit characters plus even parity character. process begins when start sentinel (hex recognized, continues until sentinel (0x0F) recognized. more than characters, including sentinels character, will read. data stored right-justified bytes buffer space pointed buffer pointer argument io_in() function with parity stripped, includes start sentinels. This buffer should bytes long. magtrack1 input object optionally uses pins timeout/abort pin. this feature suggested since io_in() function will update watchdog timer during clock wait states, could result lockup card were stop moving middle transfer process. logic level detected timeout pin, io_in() function will abort. This input oneshot timer counter output, circuit, DATA_VALID signal from card reader. Smart Transceiver with clock rate 10MHz process incoming rate 7246 bits/second when strobe signal duty cycle (thigh tlow µs). density bits/inch, this translates card speed 34.5 inches/second. rate processing capability scales with Smart Transceiver input clock rate, example: rate 28,984bps 40MHz.
Neurowire (SPI Interface) Input/Output Object
Neurowire object implements full-duplex synchronous transfer data some peripheral device. operate master (drive clock out) slave (accept clock in). both master slave modes, bits data transferred time. Neurowire suspends application processing until operation completed. Neurowire object useful external devices, such A/D, converters, display drivers incorporating serial interfaces that conform with Motorola National Semiconductor Microwaveinterfaces. Figure 3.28.
IO10 Neurowire MASTER
Select
Timeout
Clock Data Data
Clock Data Data
IO10
Neurowire SLAVE
Figure 3.28 Neurowire Neurowire Master Mode Neurowire master mode, clock (driven Smart Transceiver), serial data output, IO10 serial data input. Serial data clocked same time data clocked from IO10. Data clocked rising edge clock signal default. clockedge(-) keyword changes active edge clock negative. addition, more pins used chip select, allowing multiple Neurowire devices connected three-wire bus. clock rate specified 1kbps, 10kbps, 20kbps input clock rate 10MHz; these scale proportionally with input clock, example: 4kbps, 40kbps, 80kbps input clock rate 40MHz. Figure 3.29.
3120 3150 Smart Transceiver Data Book
Chapter Input/Output Interfaces
tsetup
thold
thigh tlow
CLOCK
DATA
DATA INPUT SAMPLED
tfin tcs_clock
CLOCK
tclock_cs
tret
SELECT START io_in() io_out() io_in() io_out()
Parameter tfin tret thold
Description Function call active Return from function Active clock edge sampling input data kbps rate kbps rate kbps rate Period, clock high (active clock edge kbps rate kbps rate kbps rate Period, clock (active clock edge Data output stable active clock edge Select active first active clock edge Last clock transition select inactive Clock frequency 1/(thigh tlow) kbps rate kbps rate kbps rate
69.9 11.4 53.4 960.6 25.8 67.8 975.0 33.0 91.2 81.6 17.0 9.92
thigh
tlow tsetup clock tclock
Figure 3.29 Neurowire (SPI) Master Timing Neurowire Slave Mode Neurowire slave mode, clock (driven external master), serial data output, IO10 serial data input. Serial data clocked same time data clocked from IO10. Data clocked rising edge clock signal (default), which 18kbps 10MHz. This data rate scales with Smart Transceiver input clock rate, example: 72kbps 40MHz. clockedge(-) keyword changes
3120 3150 Smart Transceiver Data Book
Serial Objects active edge clock negative. pins designated timeout pin. logic level timeout causes Neurowire slave operation terminated before specified number bits been transferred. This prevents Smart Transceiver watchdog timer from resetting chip event that fewer than requested number bits transferred external clock. Figure 3.30.
tret tcklodo
tfin
tcklo
tdocki
INPUT CLOCK
DATA
DATA
TIME START io_in() CLOCK DATA SAMPLED CLOCK DATA SAMPLED OUTPUT io_in()
DATA OUTPUT
Parameter tfin tret tdocki tcklo tcklodo
Description Function call data Return from function Data input clock data sampled Data sampled clock sampled Clock sampled data output Clock frequency (max)
41.4 19.2 24.0 25.8 18.31
Figure 3.30 Neurowire (SPI) Slave Timing algorithm each output/input Neurowire slave objects described below. this description, default active clock edge (positive) assumed; invert keyword used, clock levels stated should reversed.
next output value. Test IO8, clock input, high level. This test rising edge input clock. input clock still low, sample timeout event abort high. When input clock high, store next data input sampled IO10. Test input clock input level. This test falling edge input clock. input clock still high, sample timeout event abort high. When input clock low, return step there more bits processed. Else return number bits processed.
When either clock input test fails (that clock sampled before next transition), there additional timeout check time 19.8 (wait clock high) 19.2 (wait clock low) added that stage algorithm.
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Chapter Input/Output Interfaces
chip select logic Neurowire slave handled user through separate input object, along with appropriate handshaking algorithm implemented user application program. order prevent unnecessary timeouts, setup hold times chip select line, relative start external clock, must satisfied. timeout input either connected external timer output Smart Transceiver that declared oneshot object.
Serial Input/Output
configured asynchronous serial input line, IO10 configured asynchronous serial output line. rates input output independently specified 600, 1200, 2400, 4800 bits/second 10MHz input clock rate. data rate scales proportionally input clock rate. example, 40MHz, rates would 2400, 4800, 9600, 19,200 bits/second. frame format fixed start bit, data bits, stop bit; bytes transferred time. Either serial input serial output operation (but both) effect time. interface halfduplex only. This function suspends application processing until operation completed. input, io_in() request will time after character times start received. stop wrong polarity should input operation terminated with error. application code pins flow control handshaking required. This function us
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