software version About This Guide Programming Using VHDL Introduction
|
|
|
Top Searches for this datasheet
Metamor User's Guide Contents
software version About This Guide Programming Using VHDL Introduction VHDL Programming Combinational Logic Programming Sequential Logic Programming Finite State Machines Some Common Examples VHDL Synthesis VHDL Types Managing Large Designs
Copyright 1992 1996, Metamor, Inc. rights reserved.
Logic Metalogic XBLOX Synthesis Attributes Synthesis Coding Issues VHDL Quick Reference Prep Examples Error Messages Compile Options VHDL Information Resources
About This Guide
This guide intended engineer familiar with principles hardware design, little experience designing with language-based synthesis system. describes general concepts synthesis, general organization usage VHDL, provides specific information Metamor tool used this environment. does attempt present VHDL language depth, does provide example-based summary VHDL syntax that serves helpful reference user.
Notation Conventions
VHDL case-sensitive, design description contain UPPERCASE lowercase text. this guide, examples lowercase. VHDL reserved words both text examples bold, example entity counter port (clk, reset: bit; sum: integer); counter
bold
examples, bold type indicates reserved word. example above, entity, port, out, reserved words. Regular plain type represents user-definable identifier another VHDL construct. Reserved words cannot used user-defined identifiers. example above, name "sum" user-defined identifier.
plain-text
About this Guide
Copyright Notice
Metamor software documentation produced Metamor, Inc. Metamor software includes software developed Department Electrical Engineering Computer Sciences, University California Berkeley. Unauthorized copying, duplication, other reproduction contents prohibited without written consent Metamor, Inc. information this guide subject change without notice does represent commitment part Metamor. program described this guide furnished under license agreement used copied except accordance with terms agreement. Metamor trademark Metamor, Inc. ABEL registered trademark Data Corporation. MS-DOS, Windows Windows95 registered trademarks Microsoft Corporation. Copyright 1992 1996, Metamor., Inc. rights reserved.
About this Guide
Programming Using VHDL VHDL Designers
VHDL large language. impractical task learn whole language before trying Fortunately, necessary learn whole language order VHDL same true computer even human language). This section presents view VHDL that should familiar users classic programming languages. Just programming, describe design I/O, combinational logic, sequential logic, state machines. Initially will only consider signals type std_logic std_logic_vector dimensional array std_logic). These types allow logical operations (and, or.) relational operations (equal, greater than,.).
Also
summary syntax VHDL: VHDL Quick Reference more detail contents this section: Programming Combinational Logic Programming Sequential Logic Programming Finite State Machines some VHDL examples: Some Common Examples VHDL
Programming Using VHDL
Design
Design described using port statement. Ports have mode INOUT BUFFER. mode describes direction data flow. default mode port Values assigned ports mode INOUT BUFFER, read from ports mode INOUT BUFFER. Port statements occur within entity. example entity ent1 port (a0,a1,b0,b1 std_logic; ent1; std_logic)
entity ent2 port (a,b std_logic_vector(0 std_logic; std_logic_vector(0 ent2; INOUT BUFFER used specify routing ports. INOUT port specifies bi-directional dataflow, BUFFER port unidirectional that read from. INOUT describes signal path that runs through back into design: "pin feedback" PLDs block some FPGAs. BUFFER describes signal path that drives output buffer internal logic: "register feedback" PLDs internal routing FPGAs. INOUT required specify feedback. Register feedback specified using BUFFER using extra signal. also convention another standard, IEEE 1164. this standard, write following lines before each entity package) provide visibility definition 'std_logic'. This required, it's just convention. library ieee; ieee.std_logic_1164.all; will these definitions Combinational Logic section.
Programming Using VHDL
Combinational Logic
Combinational logic described using concurrent statements, just like equations languages. Concurrent statements occur within architecture. Note that architecture references entity. equations assign values signals. Ports examples signals; other signals must declared before they used. could describe adder using boolean equations architecture adder ent1 signal std_logic; begin (not a0); (not adder; also perform conditional assignment. Here conditional assignment used build mux: architecture mux1 ent2 begin when else mux1; Note that omitting 'else above would specify latch: when '1'; because this would then have same meaning when else meaning different some languages, which assume default else 'zero', perhaps 'dont care'. VHDL'93 also different from VHDL'87 which required else present.
Programming Using VHDL
Generate concurrent looping structure. This construct allows another possible implementation mux. This example also illustrates selecting elements arrays: architecture mux2 ent2 begin generate c(i) (a(i) sel) (b(i) sel); generate; mux2; Further detail combinational logic described Programming Combinational Logic. Also look Seven-Segment Decoder which uses another concurrent statement: selected signal assignment.
Programming Using VHDL
Registers Tri-state
VHDL does contain register assignment operator; registers inferred from usage. Therefore, latch could described when '1'; flip flop when clk'event flip flop with asynchronous reset: when else when clk'event practice, clk'event expression little cumbersome. improve this using rising_edge() function from std_logic_1164. following example output registers combinational adder: library ieee; ieee.std_logic_1164.all; entity counter port (a0,a1,b0,b1,clk std_logic; counter; architecture adder_ff counter signal std_logic; begin (not a0); (not when rising_edge(clk); when rising_edge(clk); adder_ff; more detailed explanation register inference occurs Programming Sequential Logic.
std_logic)
Programming Using VHDL
tristates much same flip flops, using conditional assignment (here controlled input oe):. architecture adder_ff_tri counter signal std_logic; begin (not a0); (not when rising_edge(clk); when rising_edge(clk); when else 'Z'; when else 'Z'; adder_ff_tri;
Programming Using VHDL
procedures make intent design little clearer, such moving combinational logic into procedure. Notice that procedures contain programming language like 'sequential statements' that intermediate values example below held variables. Notice also that signals assigned with "<=", variables with ":=". Like programming languages, order sequential statements important. architecture using_procedure counter signal std_logic; procedure (signal a0,a1,b0,b1 std_logic; signal c0,c1 std_logic) variable std_logic; begin (not a0); (not end; begin when rising_edge(clk); when rising_edge(clk); using_procedure;
Programming Using VHDL
State Machines
There state transition view VHDL, however, does support behavioral view. This allows design description programming-language-like way, introduced procedures Registers Tri-state Sequential statements also occur processes. have already seen flip-flop described using concurrent statement. when rising_edge(clk); exactly equivalent statement process(clk) begin rising_edge(clk) then process; process statement contain many sequential statements. This simple behavioral description very like state machine description classic language. library ieee; ieee.std_logic_1164.all; entity ent5 port (clk,reset std_logic; buffer std_logic_vector(1 downto 0)); ent5
Programming Using VHDL
architecture counter1 ent4 begin process (clk, rst) begin reset then "00"; elsif rising _edge(clk) then case when "00" "01"; when "01" "10"; when "10" "11"; when "11" "00"; case; process counter1 Although we've introduced process statement describe state machines, more generally allows behavioral modeling both combinational sequential logic. There several examples state machines Some Common Examples VHDL, these slightly larger examples illustrate application process statements. strongly recommended that read Programming Sequential Logic Programming Finite State Machines before attempting write process statements; important understand impact wait statement signals variables process statement.
Programming Using VHDL
Types
types other than 'std_logic' 'std_vector_logic' make your design much easier read. good programming practice your type definitions package, make package contents visible with clause. example, counter1 State Machines could described: package type_defs subtype very_short integer range type_defs; library ieee; ieee.std_logic_1164.all; work.type_defs.all; entity counter2 port (clk, reset std_logic; buffer very_short); counter2 architecture using_ints counter2 begin process(clk,reset) begin reset then elsif rising_edge(clk) then process; counter2 this example used type integer because operator defined integers, std_logic_vectors, which have been using now.
2-10
Programming Using VHDL
Sometimes there other packages written third parties that use, such Synopsys packages included with Metamor. these packages defines operation between std_logic_vector integer. Using this package rewrite example: library ieee; ieee.std_logic_1164.all; ieee.std_logic_unsigned.all; entity counter2 port (clk, reset std_logic; buffer std_logic_vector(1 downto 0)); counter2 architecture using_ counter2 begin process(clk,reset) begin reset then "00"; elsif rising_edge(clk) then process; counter2 convention that Synopsys packages placed IEEE library, however, they IEEE standard. these packages IEEE library alias compile option specify ieee.vhd synopsys.vhd. Further discussion VHDL types occurs VHDL Types
Programming Using VHDL
2-11
Debugging
very personal issue here some suggestions debugging specification implementation your design.
System level simulation
Simulate your VHDL design before synthesis using third party VHDL simulator. This allows verify specification your design. don't have VHDL simulator, Metamor with compile option optimize zero minimize compile time), simulate output with your equation gate level simulator.
Hierarchy
Partition your design into entity/architecture references components. Compile each entity separately. Simulate using third party equation netlist simulator verify functionality. Check size logic this module. about what expected? Using hierarchy represent modules your design will result faster better optimization, allow reuse these design units future designs.
Attribute 'critical'
Critical forces signal retained output description. This allows trace VHDL signal using your third party equation netlist simulator. name VHDL signal will maintained prefixed with instance, block labels, package names, suffixed with "_n", represents more than wire.
2-12
Programming Using VHDL
Verbose option
This compile option enables printing additional information about inferred logic structures. information printed process basis, indicating inferred structure, type control signals, name. flip flop latch tristate critical comb macrocell type] type] <name> <name> [bit <name> [bit <name> [bit <name> [bit <name>
This information lists inferred structure. name field represents name inferred logic element. name will local signal variable name from within VHDL source code. name structure output file will derived within larger context different. user recognizable name exists, name field will contain "[anonymous]". field optional. macrocell name will predefined Xblox name. Note that design statistics printed compile same process inference information. There three possible reasons this: Optimization remove change inferred structures. Additional combinational feedback paths explicitly specified (i.e. inferred) between processes. Additional instantiated macrocells.
Programming Using VHDL
2-13
Report assert statements
VHDL report statement specifies logic useful following execution compiler perhaps when functions called iterations loop. example: entity loop_stmt port std_logic_vector std_logic_vector 3)); loop_stmt; architecture example loop_stmt begin process variable integer; begin while loop report "Loop number integer'image(b); loop; process; example; assert statement used place report statement, value assert condition must false order message written. synthesis, value condition depends upon signal, possible compiler evaluate either true false. this case message written (i.e. true). This lead confusion during debugging. best plan signals variables assert condition. more detailed discussion variables depending signals discussion metalogic expressions Logic Metalogic.
2-14
Programming Using VHDL
Happy
important understand that synthesis tools design you. Synthesis tools handle design details enable more productive. single most productive thing aware what, much hardware describing using HDL. This guide attempts provide with information will need. With this approach expect happy with results. Conversely, writing without considering hardware, expecting synthesis tool design' recipe disaster. common mistake create design description, validate with simulator, assume that correct specification must also good specification.
Programming Using VHDL
2-15
2-16
Programming Using VHDL
Introduction VHDL VHDL
VHDL hardware description language (HDL). contains features conventional programming language, classical programming language, netlist, well design management features. VHDL large language provides many features. This guide does attempt describe full language rather introduces enough language enable useful design. Metamor supports most VHDL language, however, some sections language have meanings that unclear context logic design -the file operations package "textio", example. exceptions constraints Metamor's VHDL support listed Unsupported Constructs, Ignored Constructs Constrained Constructs. Metamor uses VHDL'93 version VHDL. This version basically superset previous standard VHDL'87.
Introduction VHDL
Structure VHDL Design Description
basic organization VHDL design description shown following figure:
structure VHDL design description.
Introduction VHDL
package optional statement shared declarations. entity contains declarations design I/O, architecture contains description design. design contain number package, entity architecture statements. Most examples this guide single entity-architecture pair. more information Managing Large Designs. architecture contains concurrent statements. Concurrent statements (like netlists classic programming languages) evaluated independently order which they appear. Values passed between statements signals; assignment signal implies driver. signal thought physical wire bundle wires). most powerful VHDL constructs occur within sequential statements. These must placed inside particular concurrent statement, process statement, inside function procedure. Sequential statements very similar programming language statements: they executed order they written (subject statements, return statements, etc.). Values held variables constants. Signals used pass values process, from other concurrent statements same statement). Several concepts important understanding VHDL. They include: distinction between concurrent statements sequential statements, understanding that signals pass values between concurrent statements, variables pass values between sequential statements. Later will discuss sequential logic (logic with memory elements such flip-flops). Sequential statements VHDL refer statement ordering, type logic compiled. Sequential statements used compile both combinational sequential logic. VHDL written three levels abstraction: structural, data flow, behavioral. These three levels mixed. following subsections: Structural VHDL Data Flow VHDL ,and Behavioral VHDL introduce structural, data flow, behavioral design methods show VHDL code fragments that written each level abstraction.
Introduction VHDL
Variations following design used illustrate differences: entity hello port (clock, reset boolean; hello; char character)
architecture behavioral hello constant char_sequence string "hello world"; signal step integer range char_sequence'high begin Counter process (reset,clock) begin reset then step elsif clock clock'event then step char_sequence'high then step else step step process Output Decoder char char_sequence(step); behavioral This design compiles simple waveform generator with inputs (clock reset) eight outputs. output sequences through ASCII codes each eleven characters string "hello world". codes change some logic delay after each rising edge clock. When circuit reset, output code reset asynchronous.
Introduction VHDL
Structural VHDL
structural VHDL design description consists component instantiation statements, which concurrent statements. example: port (a_2, b_5); This netlist-level description. such, probably want type many statements structural level. Schematic capture long been known easier enter netlists. Structural VHDL simply describes interconnection hierarchy. Description function requires data flow behavioral levels. Component instantiation statements useful sections design that reused, integrating designs. design following example been partitioned into instantiated components. Note that components declared defined example. components would defined entity/architecture discussed Managing Large Designs. entity hello port (clock, reset boolean; hello; char character
architecture structural hello constant char_sequence string "hello world"; subtype short integer range char_sequence'high; signal step short; component counter port (clock reset boolean; short component; component decoder port (num short character) component; begin counter port (clock,reset,step); decoder port (step,char); structural;
Introduction VHDL
This useful counter decoder been previously created compiled into PALs. availability larger allows integrate design instantiating these components compiling larger device.
Introduction VHDL
Data Flow VHDL
Another concurrent statement signal assignment. example: when else in2; Assignments this level referred data flow descriptions. They sometimes referred (register-transfer-level) descriptions. This example could rewritten entity hello port (clock reset: boolean; hello; char character
architecture data_flow hello constant char_sequence string "hello world"; signal step0, step1 :integer range char_sequence'high begin Output decoder char char_sequence(step1); Counter logic step1 when step0 char_sequence'high else step0 Counter flip flops step0 when reset else step1 when clock clock'event; data_flow; data flow descriptions combinational logic described with signal assignment There register assignment operator; sequential logic inferred from incomplete specification step0) example above.
Introduction VHDL
Behavioral VHDL
most powerful concurrent statement process statement. process statement contains sequential statements allows designs described behavioral level abstraction. example process (insig) variable var1: integer; variable declaration begin var1:= insig; variable assignment var1:= function_name(var1 function call process; hardware design process statement ways: combinational logic sequential logic. describe combinational logic general form process statement process (signal_name, signal_name, signal_name,.) begin process; general forms sequential logic process (clock_signal) begin clock_signal clock_signal'event then process; combinational logic there list process input signals after keyword process. sequential logic there either: sensitivity list there wait statement; sensitivity list containing clock statements within statement. illegal VHDL process have both sensitivity list wait statement. have neither implies logic. Combinatorial logic discussed Programming Combinational Logic, sequential logic Programming Sequential Logic.
Introduction VHDL
example could viewed processes: sequential counter, combinatorial decoder entity hello port (clock, reset boolean; hello; char character)
architecture behavioral hello constant char_sequence string "hello world"; signal step integer range char_sequence'high begin counter process (reset, clock) begin reset then step elsif clock clock'event then step char_sequence'high then step else step step process decoder :process (step) begin char char_sequence(step); process behavioral
Introduction VHDL
VHDL Types
VHDL contains usual programming language data types, such boolean character integer real string
These types have their usual meanings. addition, VHDL types: bit_vector
type have value '1'. bit_vector array bits. (Similarly, string array characters VHDL just Pascal). Most electrical engineers IEEE 1164-standard-logic types place bit_vector. std_logic std_logic_vector
These declared IEEE library package std_logic_1164 make these declarations visible, entity that uses these types prefixed with library declaration clause: library ieee; ieee.std_logic_1164.all;
example Fifo. more info VHDL Design Libraries Metamor VHDL Libraries. Definitions predefined types found file std.vhd, which contains package standard. type variable, signal, constant (which collectively called objects) determines operators that predefined that object. 3-10 Introduction VHDL
hardware design, type also determines number possibly encoding scheme used wires that implemented that object. Type-checking performed during analysis. Types used resolve overloaded subprograms. Users define their types, which scalars, arrays, records. VHDL also allows subtypes. This simply mechanism define subset type. More information impact types subtypes synthesis contained Synthesis VHDL Types section.
Introduction VHDL
3-11
model simulates, but.
This section primarily experienced VHDL simulation users have VHDL code that been developed using VHDL simulator. VHDL standard, there problem Many VHDL models suitable synthesis, such high level performance models, environment models stimulus/response, system models including software, hardware, physical aspects. Synthesis assumes that VHDL code describes logic design, some model design. This assumption puts additional constraints programmer. Most remainder this guide describes program VHDL within these constraints. design description correctly specified English, have practical hardware implementation (e.g. H.G.Wells' Time Machine). same true design specified VHDL, which have practical implementation. Just because written Hardware Description Language doesn't mean describes hardware! example, suppose have VHDL simulation model PAL, lets model configures itself from JEDEC file during simulation initialization. model actually simulates programming logic PAL. describes more than just hardware, model also describes manufacturing step when programmed. synthesizable VHDL model would only describe component function earlier manufacturing step. Some other issues: Hardware design adds several additional constraints such gated clocks. These constraint simulation where values written computer memory without concern electrical glitches. Hardware design requires care taken controlling clocking memory elements. simulation model also describe timing characteristics design. These ignored synthesis tool, which considers timing result hardware realization design. VHDL model that depends timing correct operation synthesize expected result.
3-12
Introduction VHDL
simulation model enumerated types represent encoding group wires (e.g. load store execute), perhaps part state machine description represent electrical characteristic single wire e.g. high impedance, resistive, strong), well state simulation (unknown, uninitialized)
Within VHDL, synthesis system distinguish meaning each case. Metamor assumes encoding representation enumerated types unless encoding explicitly specified using attribute 'enum_encoding'.
Introduction VHDL
3-13
3-14
Introduction VHDL
Programming Combinational Logic
This section shows relationship between basic VHDL statements combinational logic. resulting logic represented schematics (one possible representation design), provided illustrate this relationship. actual implementation created Metamor depends upon other VHDL statements design that affect logic minimization, target technology, which affects available gate types. Most operators statements used describe combinational logic same those found programming language. Some VHDL operators more expensive compile because they require more gates implement like programming languages where some operators take more cycles execute). need aware these factors. This section describes relative costs associated with various operators. operand constant, less logic will generated. both operands constants, logic collapsed during compilation, cost operator zero gates. Using constants more generally metalogic expressions) wherever possible means that design description will contain extra functionality. result will compile faster produce smaller implementation. Certain operators generally restricted with specific types. Logical Operators Arithmetic Operators more information. VHDL, operators also redefined type. This known operator overloading, outside scope this guide.
Programming Combinational Logic
Logical Operators
VHDL provides following logical operators: nand xnor
These operators defined types bit, boolean arrays boolean (for example, bit_vector). compilation logic fairly direct from language construct, implementation gates, shown following examples: entity logical_ops_1 port bit; bit); logical_ops_1; architecture example logical_ops_1 signal bit; begin -concurrent signal assignments example; entity logical_ops_2 port bit_vector bit_vector 3)); logical_ops_2 architecture example logical_ops_2 begin example;
Programming Combinational Logic
Relational Operators
VHDL provides following relational operators: Equal Greater than Less than
equal
Greater than equal Less than equal equality operators defined types. ordering operators defined numeric types, enumerated types, some arrays. resulting type these operators boolean. simple comparisons, equal equal, cheaper implement terms gates) than ordering operators. illustrate, first example below uses equal operator second uses greater-than-or-equal-to operator. from schematic, second example uses more than twice many gates first. entity relational_ops_1 port bit_vector boolean); relational_ops_1; architecture example relational_ops_1 begin example; entity relational_ops_2 port integer range boolean); relational_ops_2; architecture example relational_ops_2 begin example;
Programming Combinational Logic
a>=b
Arithmetic Operators
are: Addition Subtraction Multiplication Division Modulus Remainder Absolute Value Exponentiation arithmetic operators VHDL defined numeric types. These
While adding operators fairly expensive terms gates, multiplying operators mod, rem) very expensive. Metamor does make special optimizations, however, when right hand operator constant even power absolute (abs) operator inexpensive implement. operator only supported when arguments constants. following example illustrates logic addition operator (and package type declaration): package example_arithmetic type small_int range example_arithmetic; work.example_arithmetic.all; entity arithmetic port small_int; small_int); arithmetic; architecture example arithmetic begin example;
Programming Combinational Logic
Control Statements
VHDL provides following concurrent statements creating conditional logic: conditional signal assignment selected signal assignment
VHDL provides following sequential statements creating conditional logic: case
Examples concurrent control statements are, conditional signal assignments: entity control_stmts port boolean; boolean); control_stmts; architecture example control_stmts begin when else example; possible cases must used selected signal assignments. certain this using others case: entity control_stmts port (sel: bit_vector a,b,c,d bit; bit); control_stmts; architecture example control_stmts begin with select when b"00", when b"01", when b"10", when others; example;
Programming Combinational Logic
same functions implemented using sequential statements occur inside process statement. condition statement must evaluate true false (that must boolean type). following example illustrates statement: entity control_stmts port boolean; boolean); control_stmts; architecture example control_stmts begin process variable boolean; begin then else process; example; Using case statement selected signal assignment will generally compile faster produce logic with less propagation delay than using nested statements large selected signal assignment). same true programming language, more significant context logic synthesis. statements selected signal assignments also used infer registers. Programming Sequential Logic. VHDL requires that possible conditions represented condition case statement. ensure this, others clause case statement cover unspecified conditions.
Programming Combinational Logic
following example illustrates case statement: entity control_stmts port (sel: bit_vector a,b,c,d bit; bit); control_stmts; architecture example control_stmts begin process (sel,a,b,c,d) begin case when b"00" when b"01" when b"10" when others case; process; example;
4-10
Programming Combinational Logic
case
sel_1 sel_0
Subprograms Loops
VHDL provides following constructs creating replicated logic: generate loop loop while loop function procedure
Functions procedures collectively referred subprograms. Generate concurrent loop statement. These constructs synthesized produce logic that replicated once each subprogram call, once each iteration loop. possible, loop generate ranges should expressed constants. Otherwise, logic inside loop replicated possible values loop ranges. This very expensive terms gates. entity loop_stmt port bit_vector bit_vector 3)); loop_stmt; architecture example loop_stmt begin process variable b:bit; begin '1'; loop a(3-i) m(i) loop; process; example;
-don't need declare
4-12
Programming Combinational Logic
loop statement replicates logic, therefore, must possible evaluate number iterations loop compile time. This requirement adds constraint synthesis while loop unconstrained loop (but loop These loops must completed statement whose execution depends only upon metalogic expressions. example, loop completion depends signal (i.e. metalogic expression infinite loop will result. Placing report statement within loop useful technique debugging. message will reported screen each iteration loop. entity loop_stmt port bit_vector bit_vector 3)); loop_stmt; architecture example loop_stmt begin process variable integer; begin while loop report "Loop number integer'image(b); loop; process; example; Loop statements terminated with exit statement, specific iterations loop statement terminated with next statement. When simulating, exit next used speed simulation time. synthesis, where each loop iteration replicates logic, there probably speedup. addition, exit next synthesizes logic that gates following loop logic. This result carry-chain-like structure with long propagation delay resulting hardware.
Programming Combinational Logic
4-13
function always terminated return statement, which returns value. return statement also used procedure, never returns value. entity subprograms port bit_vector bit_vector 2)); subprograms; architecture example subprograms function simple bit) return begin return end; begin process begin m(0) simple(a(0), a(1), a(2)); m(1) simple(a(2), a(0), a(1)); m(2) simple(a(1), a(2), a(0)); process; example
4-14
Programming Combinational Logic
loop
subprogram
Shift Rotate Operators
VHDL provides following shift rotate operators:
left operand dimensional array whose element type either BOOLEAN, right operand type INTEGER. right operand constant metalogic expression), these operations imply logic. entity sr_1 port b,c: bit_vector downto integer range 2**5 w,x,y: bit_vector downto sr_1 architecture example sr_1 begin ctl; shift left fill with ctl; shift right, fill with a'left a(5) ctl; rotate left example; Note that negative right argument means shift rotate opposite direction. right argument constant (not metalogic expression), subtype which range that includes negative number, bidirectional shift rotate structure will constructed. This very expensive. example function to_natural bit_vector) return natural; function to_integer bit_vector) return integer; to_natural (bv); to_integer (bv); 4-16
EXPENSIVE Programming Combinational Logic
Tristates
There possible methods describe tristates: either using type std_logic defined ieee.std_logic_1164, using assignment NULL turn driver. first method applies type std_logic only, second method applies type. first method commonly used. library ieee; ieee.std_logic_1164.all; entity tbuf2 port (enable boolean; std_logic_vector(0 std_logic_vector(0 4)); tbuf2; architecture example tbuf2 begin process (enable, enable then else 'Z'; process; end; equivalent concurrent statement architecture example2 tbuf2 begin when enable else 'Z'; end;
Programming Combinational Logic
4-17
internal tristate described following example. Note that constraint Metamor requires tristate buffers driving this same architecture. architecture example3 tbuf3 begin when enable0 else 'Z'; when enable1 else 'Z'; when enable2 else 'Z'; end; assignment null signal kind turns driver. When embedded statement, null assignment synthesized tristate buffer. package example_bus subtype bundle bit_vector example_bus; work.example_bus.all; entity tbuf port (enable: boolean; bundle; bundle bus); tbuf; architecture example tbuf begin process (enable, begin enable then else null; process; example;
4-18
Programming Combinational Logic
Programming Sequential Logic
Programming sequential logic VHDL like programming conventional programming language, unlike programming using traditional programming language. There register assignment operator, special attributes specifying clock, reset, etc. VHDL program behavior sequential logic element, such latch flip-flop, well behavior more complex sequential machines. This section shows program simple sequential elements such latches flip-flops VHDL. This extended behavior Reset (synchronous asynchronous). These techniques expanded upon Some Common Examples VHDLwhere will show examples more complex machines. behavior sequential logic element described using process statement equivalent procedure call, concurrent signal assignment statement). behavior sequential logic element (latch flipflop) save value signal over time. This section shows such behavior programmed. techniques shown here extended specify Reset, both synchronous asynchronous, shown later sections. There often several ways describe particular behavior, following examples typically show styles each, however, there particular 'right' style. choice style simply that which helps programmer specify clearest description particular design. example, designer choose copy procedures latches flip-flops from following examples, describe design terms equations procedure calls shown Registers Tri-State. Alternatively designer choose describe design more behavioral form show examples Some Common Examples VHDL. There three major methods program this register behavior: using conditional specification using wait statement, using guarded blocks. Conditional specification most common method.
Programming Sequential Logic
Conditional Specification
This relies behavior statement, assigning only condition: then else nothing This describes behavior latch, clock high output gets value, output retains previous value. Note that assigned both conditions, behavior would that mux: then else specification latch flip-flop incomplete assignment using statement; there particular significance signal names used code fragments. Note, however, that incomplete assignment within context whole process statement. could describe latch transparent low: then nothing else more concisely: then
Programming Sequential Logic
rising edge Flip-flop created making latch edge sensitive: clk'event then these cases number registers width determined type signal "y";
Programming Sequential Logic
Wait Statement
second method uses wait statement: wait until expression; This suspends evaluation (over time) until expression evaluates "true". flip-flip programmed: wait until possible describe latches using wait statement.
Guarded Blocks
latch.: block (clk) begin guarded block; possible describe flip-flops using guarded blocks. guard expression block statement used specify
Programming Sequential Logic
Latches
following examples describe level sensitive latch with function connected input. these cases signal retains it's current value unless clock true: Process statement process (clk, list signals used process begin then process; Procedure declaration, creates latch when used concurrent procedure call procedure my_latch (signal clk, boolean; signal boolean) begin then end; example such calls: label_1: my_latch clock, input1, input2, outputA label_2: my_latch clock, input1, input2, outputB concurrent conditional signal assignment, note that both used driven when else when clk;
Programming Sequential Logic
Flip-Flops
following examples describe edge sensitive flip-flop with function connected input. these cases signal retains it's current value unless clock changing Process statement process (clk) list signals that result propagation delay begin clk'event then clock rising process; Process statement containing wait statement: process list signals used process begin wait until clock falling process; Procedure declaration, this creates flip-flop when used concurrent procedure call procedure my_ff (signal clk, boolean; signal boolean) begin clk'event then clock falling end; concurrent conditional signal assignment, note that both used driven when 'event else when 'event last else required
Programming Sequential Logic
sometimes clearer write function detect rising edge function rising_edge (signal return boolean begin return s'event; end; Using this function, flip flop written when rising_edge(clk);
Programming Sequential Logic
Gated Clocks Clock Enable
examples this section assume clock simple signal. principle, complex boolean expression could used specify clocking. However, complex expression implies gated clock. with kind hardware design, there risk that gated clocks cause glitches register clock, hence produce unreliable hardware. need aware constraints target hardware and, general rule, only simple logic expression. possible specify gated clock with statement such clk1 then register assignments here which implies logical clock line. specify clock enable nested statements: clk1 then then register assignments here This will connect 'ena' register clock enable clock enable compile option used. clock enable option used then data path will gated with 'ena'. neither case will 'ena' gate 'clk1' line. also Compile Options.
Programming Sequential Logic
Synchronous Set/Reset
behavior synchronous reset simply conditional assignment constant immediately inside clock specification. Set: process (clk) begin clk'event then- clock rising then true; type boolean else process; bits reset bits init process begin wait until clock rising init then type integer else process;
Programming Sequential Logic
Asynchronous Reset
describe behavior asynchronous reset initialization longer within control clock. simply conditional assignment constant immediately outside clock specification. Reset using concurrent statement statement: false when reset else when 'event else using function rising_edge described earlier false when reset else when rising_edge(clk Reset using sequential statements: process (clk, reset) begin reset then false; type boolean else clk'event then clock rising process; procedure ff_async_set (signal clk, set: boolean; signal boolean) begin then true; elsif clk'event then clock rising input end;
5-10
Programming Sequential Logic
Asynchronous Reset
describe behavior both asynchronous reset simply second conditional assignment constant immediately outside clock specification. Reset using concurrent statement false when reset else true when preset else when 'event; Reset using sequential statements process (clk, reset, preset) begin reset then false; elsif preset then true else clk'event then process;
type boolean
clock rising
Programming Sequential Logic
5-11
Asynchronous Load
describe behavior asynchronous load, replace constant used reset with signal expression. Asynchronous load actually implemented using both flip flop asynchronous preset flip flop asynchronous reset. Load using concurrent statement load_data when load_ctl else when rising_edge(clk); Load using sequential statements process (clk, load_ctl,load_data) begin load_ctl then load_data; elsif rising_edge(clk) then process;
5-12
Programming Sequential Logic
Register Inference Rules
Storage elements inferred statement. Register control signals specified with expression statement, control signal function specified assignments lack assignments) branches statement. expression then then branch else else branch Multiple nested statements combined specify multiple register control signals. execution first statement conditional other statements, unless condition metalogic expression. scope register inference single concurrent statement.
Reset/Preset
branch statement assigns constant (metalogic expression) register. other branch assigns input register.
Clock
branch statement assigns register, other branch does assign register assigns register output). register inferred because value incompletely specified.
Clock Enable
branch statement assigns register input clock expression, other branch does assign register. Must occur immediately within clock statement.
Programming Sequential Logic
5-13
Inference priority
Control signals inferred with following priority, listed with highest priority first (not combinations supported) Asynchronous reset preset Clock Clock Enable Synchronous reset
5-14
Programming Sequential Logic
Programming Finite State Machines
Finite state machines (FSMs) classified Moore Mealy machines. Moore machine, output function current state only; thus change only clock edge. Whereas Mealy machine output function current state current inputs, change when input changes. This section shows relationship between these machines VHDL code. Each example illustrates single machine. This constraint, just simplification. there were multiple machines, they could have different clocks. this case, synchronization would responsibility designer. find additional examples Some Common Examples VHDL.
Programming Finite State Machines
Feedback Mechanisms
There ways create feedback using signals using variables. With addition feedback build state machines. This will discussed later this section. possible describe both combinational sequential (registered) feedback systems. When using combinational feedback create asynchronous state machines often helpful, required, mark feedback signal with Metamor user attribute 'critical' discussed Programming using VHDL).
Feedback signals
architecture example some_entity signal bit; function rising_edge (signal return boolean begin return s'event; end; begin process (clk, reset) begin reset then '0'; elsif rising_edge(clk) process; process combinational process begin process; example;
Programming Finite State Machines
more concise version same feedback shown following example: work.my_functions.all; package containing user function rising_edge architecture example some_entity begin process(clk,reset) begin reset then '0'; elsif rising_edge(clk) process; example;
Programming Finite State Machines
reset
Feedback variables
Variables exist within process, processes suspend reactivate. variable passes value from process back beginning, feedback implied. other words, feedback created when variables used (placed right hand side expression, statement, etc.) before they assigned (placed left hand side expression). Feedback paths must contain registers, need insert wait statement. process variable bit; begin wait until '1'; reset then '0'; else used before assigned process; flip-flop inserted feedback path because wait statement. This also specifies registered output signal variable declared inside function procedure, variable exists only within scope subprogram. Since wait statement only placed within process statement Metamor constraint), variables inside subprograms never persist over time never specify registers.
Programming Finite State Machines
reset
Moore Machine
following architecture, combinational logic functions. simple implementation maps each block VHDL process.
Moore
entity system port (clock: boolean; some_type;.d: some_type); system; architecture moore1 system signal some_type; begin process begin F1(a, process; process begin F2(c); process; process begin wait until clock; process; moore1;
Programming Finite State Machines
more compact description this architecture could written follows: architecture moore2 system signal some_type; begin process (c)- combinational logic begin F2(c); process; process sequential logic begin wait until clock; F1(a, process; moore2; fact, Moore Machine often specified process.
Programming Finite State Machines
Output registers
system timing requires logic between registers output (the shortest output propagation delay desired), following architecture could used:
Moore
architecture moore3 system begin process begin wait until clock; F(a,d) process; moore3;
Programming Finite State Machines
Input Registers
system timing requires logic between registers input short setup time desired), following architecture could used:
Moore
architecture moore4 system signal some_type; begin process begin wait until clock; process; process (a1, begin F(a1,d1) process; moore4;
6-10
Programming Finite State Machines
Mealy Machine
Mealy Machine always requires processes, since timing function both clock data inputs.
Mealy
architecture mealy system signal some_type; begin process combinational logic begin F2(a, process; process sequential logic begin wait until clock; F1(a, process; mealy;
Programming Finite State Machines
6-11
6-12
Programming Finite State Machines
Some Common Examples VHDL Seven-Segment Decoder
package seven subtype segments bit_vector type range seven; work.seven.all; entity decoder port (input: bcd; drive: segments); decoder; architecture simple decoder segment -encoding:
begin with input select drive b"1111110" when b"0110000" when b"1101101" when b"1111001" when b"0110011" when b"1011011" when b"1011111" when b"1110000" when b"1111111" when b"1111011" when b"0000000" when others just case simple;
Some Common Examples VHDL
Craps Game
package gamble type dice range gamble; work.gamble.all; entity craps port (roll, new_game: boolean; number: dice; win, loss: boolean); craps; architecture no_cheating craps begin process (roll, new_game,number) variable first_roll: boolean; variable point: dice; constant snake_eyes: dice begin newgame then async reset first_roll true; false; loss false; point elsif roll roll'event then clock first_roll then first_roll false; number number then true; elsif number snake_eyes then loss true; else point number;
Some Common Examples VHDL
else number number then loss true; elsif number point then true; else roll again process; no_cheating; This example state machine with asynchronous reset ("new_game") clocked input "roll". Output signals "win" "loss" registered reset, state "first_roll" registered set, state bits "point" reset. input number used rising edge "roll".
Some Common Examples VHDL
Blackjack
entity blackjack port (new_card,clk new_game: boolean; card integer range say_card,say_hold,say_bust boolean) blackjack; architecture no_cheating blackjack type play signal action play begin state_machine process variable total integer range variable boolean; begin wait until clk; new_game then action hit_me. total false; else case action when hit_me new_card then total total card; (card ace; action got_im; when got_im new_card then action test16;
Some Common Examples VHDL
when test16 total then action test21; else action hit_me; when test21 total then action hold; elsif then total total action test16; else action bust; when others null; case; process; decode outputs say_card action hit_me; say_bust action bust; say_hold action hold; end;
Some Common Examples VHDL
Traffic Light Controller
entity port (clk, reset, farm_traffic: boolean; farmroad_green_on, farmroad_yellow_on, farmroad_red_on, highway_green_on, highway_yellow_on, highway_red_on: boolean); tlc; architecture a_classic type states (highway_green, highway_yellow, farmroad_green, farmroad_yellow); type time range 100; signal short_timer, long_timer: time; signal tlc_state: states; signal set_timer, short_timeout, long_timeout: boolean; procedure timer (signal set, clk, set_timer boolean; signal timer inout time; constant load time; signal timeout boolean) begin set_timer then gated reset timer load; timeout false; elsif timer then timout true; else timer timer end;
Some Common Examples VHDL
begin timer reset, clk, set_timer, short_timer, short_timeout); timer reset, clk, set_timer, long_timer, 100, long_timeout); process begin clk'event then reset then tlc_state highway_green; set_timer false; else set_timer false; case tlc_state when highway_green farm_traffic long_timeout then tlc_state highway_yellow; set_timer true; when highway_yellow short_timeout then tlc_state farmroad_green; set_timer true; when farmroad_green farm_traffic long_timeout then tlc_state farmroad_yellow; set_timer true; when farmroad_yellow short_timeout then tlc_state highway_green; set_timer true; case; process; Some Common Examples VHDL
Decode states drive lights. farmroad_green_on tlc_state farmroad_green; farmroad_yellow_on tlc_state farmroad_yellow; farmroad_red_on tlc_state highway_green tlc_state highway_yellow; highway_green_on tlc_state highway_green; highway_yellow_on tlc_state highway_yellow; highway_red_on tlc_state farmroad_green tlc_state farmroad_yellow; a_classic;
Some Common Examples VHDL
Simple
package alu_types type (add, nop, load, loadc, op_and, op_or, shl, shr); subtype data_path bit_vector alu_types; work.alu_types.all; entity port buffer data_path; instr: ops; clk: boolean; data_path); alu; architecture simple begin process function bit_vector) return bit_vector variable sum: bit_vector a'high); variable bit:= '0'; begin a'high loop sum(i) a(i) b(i) (a(i) or(a(i) b(i)); loop; return sum; end; function shiftl(a: bit_vector) return bit_vector variable shifted: bit_vector a'high); begin Shift_left shift_right coded differently only sake example. a'high loop shifted(i a(i); loop; return shifted; end;
Some Common Examples VHDL
function shiftr(a: bit_vector) return bit_vector constant highbit: integer a'high; variable shifted: bit_vector highbit); begin Shift_left shift_right coded differently only sake example. shifted(0 highbit highbit); return shifted; end; begin wait until clk; case instr when Uses function. when null; null statement, when op_and when op_or when shiftl(a); when shiftr(a); when load when loadc case; process; simple;
7-10
Some Common Examples VHDL
Hello
This first design compiles simple waveform generator with input (the clock) eight outputs. output sequences through ASCII codes each eleven characters string "hello world." codes change some logic delay after each rising edge clock. When circuit reset, output code 'h'. design four flip-flops that make counter. entity hello port (clock, reset: boolean; char: character); hello; architecture simple hello constant char_sequence:string "hello world"; signal step:integer range char_sequence'high; begin counter process begin wait until clock; reset then step else step char_sequence'high then step else step step process; decoder char char_sequence(step); simple;
Some Common Examples VHDL
7-11
This example variant previous design; this case outputs registered well. state maintained counter there flipflops. Note counter "step" initialized (set reset) signal "reset", wraparound counter (step char_sequence'high) will loaded using data input. entity hello port (clock, reset: boolean; char: character); hello; architecture second hello begin process constant char_sequence:string "hello world"; variable step:integer range char_sequence'high; begin wait until clock; reset then step elsif step char_sequence'high then step else step step char char_sequence(step); process; second;
7-12
Some Common Examples VHDL
This final implementation optimal specifies more flip-flops that really required however, what code specifies). third architecture longer uses counter, uses output current state. situation complicated repeated characters, therefore, variable keep track these. This design flip-flops. entity hello port (clock reset: boolean; hello; char character)
architecture third hello begin process type rpt_char first, second, third, fourth variable rpt_char; begin wait until clock; case char when char 'e'; when char 'l'; when first then char 'l'; second; elsif second then char 'o'; third; else char 'd'; first; when third then char fourth; else char 'r'; first;
Some Common Examples VHDL
7-13
when char 'w'; when char 'o'; when char 'l'; when others char 'h'; case; reset then another implement reset char 'h'; process third
7-14
Some Common Examples VHDL
Fifo
Parameterized Fifo uses 'one hot' std_logic_vector counters shows techniques more efficient implementation based designers knowledge that counters hot. library ieee; ieee.std_logic_1164.all; entity fifo4 change size fifo changing vales generics generic(FifoDepth integer FifoWidth integer port(D std_logic_vector(FifoWidth downto std_logic; std_logic; Ldclk std_logic; Unclk std_logic; Empty buffer std_logic; these outputs back Full buffer std_logic; flip-flop clock enable Full_2 std_logic; Empty_2 std_logic; std_logic_vector(FifoWidth downto 0)); fifo4; architecture dataflow fifo4 types subtype data_path std_logic_vector(0 FifoWidth -1); subtype fifo_ptr std_logic_vector(1 FifoDepth); type fifo_type array (fifo_ptr'range) data_path; constant constant tristate data_path (others 'Z'); constant dont_care data_path (others '-');
Some Common Examples VHDL
7-15
signals signal Fifo fifo_type; signal ReadPtr, WritePtr fifo_ptr; signal Qint data_path; rotate, logic when constant function "rol"(l: std_logic_vector; integer) return std_logic_vector begin return To_StdLogicVector( To_bitvector(l) ring counter, fast register greedy, 'one hot' uses std_logic_vector "rol" above procedure ring_counter (signal clk, clkena std_logic; signal count inout std_logic_vector) constant one_hot fifo_ptr others '0');
7-16
Some Common Examples VHDL
begin then count one_hot; elsif rising_edge(clk) then clkena then count count end; ring counters coded 'one hot', write faster compare, because predefined "/=" doesnt know std_logic_vector this case (l'length r'length) test never true fifo example function "/="(l,r: std_logic_vector) return std_logic normalize ranges because loop below assumes same range alias std_logic_vector (l'length downto alias std_logic_vector (r'length downto begin l'length r'length then return '1'; ll'reverse_range loop same then args equal, returns zero (ll(i) lr(i)) then return '0'; loop; return '1'; end;
Some Common Examples VHDL
7-17
begin FifoDepth flip-flops with clock enable, preset, rest reset read_ring_counter: ring_counter (Rst, Unclk, Empty, ReadPtr); FifoDepth flip-flops with clock enable, preset, rest reset write_ring_counter: ring_counter (Rst, Ldclk, Full, WritePtr); read_fifo: process(ReadPtr, Fifo) begin Qint dont_care; because ReadPtr ReadPtr'range loop ReadPtr(i) then Qint Fifo(i); loop; process read_fifo; (FifoWidth FifoDepth) flip-flops with clock enable write_fifo: process (Ldclk) begin rising_edge(Ldclk) then Full then WritePtr'range loop WritePtr(i) then Fifo(i) loop; process write_fifo; FifoWidth tristate buffers Qint when else tristate; 7-18 Some Common Examples VHDL
active control signals "/=" "rol" overloaded functions defined above Full Full_2 Empty Empty_2 dataflow; ReadPtr ReadPtr ReadPtr ReadPtr WritePtr WritePtr WritePtr; WritePtr;
Some Common Examples VHDL
7-19
7-20
Some Common Examples VHDL
Synthesis VHDL Types
VHDL, types used type-checking overload resolution. logic design, each type declaration also defines encoding number wires produced. subtypes, checking overloading base type subtype. Each subtype declaration defines subset type specify number wires, possibly encoding scheme. During compilation Metamor, ports with types that compile multiple wires renamed appending "_n", where incremented integer starting from zero.
Synthesis VHDL Types
Default Encoding
default, enumerated types binary encoding. Elements assigned numeric values from left right, value leftmost element zero. number wires will smallest possible where: number elements 2**n type synthesized wire. type character synthesized eight wires.
Don't Cares
Unused encodings implicitly compiled "don't care" conditions; these allow Metamor perform additional logic optimizations. Subtypes element encodings their base, types define additional "don't care" conditions. Dont care explicitly specified using 'enum_encoding' described next section. also Std_logic_1164. example: declaration: type direction (left, right, down); type cpu_op (execute, load, store); synthesized wires. wires; encoding "don't care." wires; encodings "don't cares."
subtype mem_op cpu_op range load store;
example below, logic will generated with inputs "dont care" conditions evaluating output_var. variable operation: mem_op; case operation load output_var :=.; store output_var :=.; case;
Synthesis VHDL Types
User Defined Encoding
Users redefine encoding enumerated type using attribute 'enum_encoding'. example, cpu_op might redefined with encoding: attribute enum_encoding enum_t type "001 100"; type "one hot"; type "1-hot"; kept bits with different encoding: attribute enum_encoding enum_t type 11"; definition encoding contain string consisting '-', delimited encoding each enumerated element must have same number characters. Each encoding should unique. encoding represents high impedance, encoding represents dont care, encoding represents metalogic value. Users must aware that enum_encoding attribute allows user redefine semantics enumerated type. certain cases this results synthesis creating logic that does have same behavior original VHDL source! general, this problem; however, pitfall aware explained below. Enumerated types programming languages defined having unique ascending values. order maintain behavior enum_encoding specified user should unique ascending. Non-unique encoding should avoided. non-ascending encoding, user must overload ordering operators re-encoded type each ordering operator used. example enum_encoding first Prep (Using enum encoding) implementation.
Synthesis VHDL Types
Std_logic_ll64
library 'ieee' contains package 'std_logic_1164'; this turn declares enumerated type 'std_ulogic': type std_ulogic 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', This type derivatives 'std_logic' 'std_logic_vector' often used VHDL simulation. This allows user maintain information about simulation model itself well describe design. values referred metalogical values because they represent state model rather than logic design. object type std_logic encoded wire because library file ieee.vhd (supplied with Metamor) contains encoding definition: attribute enum_encoding std_ulogic type attribute defines semantics each element: Logic value Logic value Logic value tristate Metalogic value Don't care value values have same synthesis semantics except arguments IEEE Standard 1076.3 function STD_MATCH. semantics defined 1076.3 allow dont care logic optimization evaluation results assigning metalogic value dont care value. These semantics designed compatibility with simulation; propagates simulation, there dont care optimization. Note that some operations don't propagate unknowns: with metalogic argument always false. "/=" with metalogic argument always true. ordering operator with metalogic argument illegal. case choice containing metalogic always ignored. Synthesis VHDL Types Uninitialized Forcing Unknown Forcing Forcing High Impedance Weak Unknown Weak Weak Don't care
function ieee.numeric_std.std_match provides wildcard matching dont care value. example std_logic second Prep (Using std_logic_1164) implementation.
Synthesis VHDL Types
Encoding
User defined encoding used specify encoding. instance, Prep enumerated type 'state_type' could redefined simply changing enum_encoding attribute. There possible forms: type state_type either attribute enum_encoding state_type type "one hot"; attribute enum_encoding state_type type "0000000000000001 "0000000000000010 -st1 "0000000000000100 "0000000000001000 "0000000000010000 "0000000000100000 "0000000001000000 "0000000010000000 "0000000100000000 "0000001000000000 "0000010000000000 "0000100000000000 "0001000000000000 "0010000000000000 "0100000000000000 "1000000000000000"; st15 encoding specified ascending order ordering operators "<=" ">=" function expected, writing additional functions define these operations needed. Dont care conditions handled automatically transparently user. alternative method describe encoding arrays 'std_logic' even 'bit' This method slower compile require additional explicit dont care specification. recommended style enumerated types enum_encoding.
Synthesis VHDL Types
Numeric Types
Numeric types consist integer, floating point, physical types. encoding schemes used Metamor numeric types: Numeric types subtypes that contain negative number their range definition encoded complement numbers. Numeric types subtypes that contain only positive numbers encoded binary numbers.
number wires that synthesized depends value subtype declaration that largest magnitude. smallest magnitude assumed zero numeric types. Floating point numbers constrained have same possible values integers even though they represented using floating point format with positive exponent. Numeric types subtypes synthesized follows: declaration: type int0 range type int1 range type int2 range subtype int3 int2 range synthesized binary encoding having bits. binary encoding having 7bits complement encoding having bits (including sign). binary encoding having bits.
Warning take great care when using signed scalar numbers. These encoded twos-complement, which fixed width encoding. This problem when mixing objects that have different signed subtypes each will have different widths result unexpected behavior. This problem during simulation since these objects always encoded fixed width. probably safest unsigned scalar types. Another option array bits explicitly specify width; this approach taken Synopsys IEEE 1076.3 synthesis package.
Synthesis VHDL Types
type object which result assigned more bits than either operands, result numeric operations automatically sign zero extended. Sequential encoded types zero extended two's compliment numbers sign extended. type object which result assigned fewer bits than either operands, result numeric operations truncated. numeric operation result that larger than either operands, size evaluated before above rules applied. example, generates carry that will truncated used sign zero) extended, according type object which result assigned. type short integer 255; subtype shorter short range subtype shortest short range signal op1,op2,res1 shortest; signal res2 shorter; signal res3 short begin res1 op2; truncate carry res2 op2; carry res3 op2; carry zero extend Note that shorter been declared subtype shorter short range encoding integers rounded nearest power would have same result.
Arrays Records
Composite types (arrays records) treated collections their elements. Subtypes composite types treated collections elements subtype only.
Synthesis VHDL Types
Managing Large Designs Using Hierarchy
Many VHDL design descriptions this guide consist single entity (the design I/O) architecture (the design functionality). This view sufficient many users, your designs larger will also want consider issues partitioning design management. This section introduces some additional VHDL constructs partitioning sharing code modules. These block, component, package, library statements. these, only component special meaning context synthesis, refer standard VHDL texts detailed descriptions. VHDL entity have multiple architectures. particular entity/architecture pair (referred design entity) also referenced from another architecture VHDL component. Instantiating components within another design provides mechanism integrating partitioned designs using other designs current design. Metamor, component also used tell logic optimizer about hierarchy your design. Using components large design will result design that optimizes faster produces more efficient results. This because using components adds designer's knowledge hierarchy design description, this turn used compiler specify domain logic optimizer. Hierarchy also useful debugging large designs, reusing design units. manage relationship between component declaration various design entities using configuration specifications. Because default configurations these specifications required.
Managing Large Designs
Blocks
Designs partitioned using block statements component statements. These constructs have same meaning blocks components schematic capture. Block statements used partition concurrent statements, following example: architecture partitioned some_design begin a_block: block begin concurrent statements here block; another: block begin concurrent statements here block; partitioned;
Direct Instantiation
Each element design hierarchy (each entity architecture combination) directly instantiated within another. example design leaf entity child port bit; bit); child; architecture stupid child begin stupid;
Managing Large Designs
design root entity parent port bit; bit); parent architecture family parent signal bit; begin huey: entity child port luey: entity child port duey: entity child port family;
-direct instantiations
more powerful method instantiation using components described following section.
Managing Large Designs
Components Configurations
VHDL allows number entity-architecture pairs, which referred design entities. These design entities referenced from another architecture components. mapping design entities managed using configuration specification, which associates particular component instances with specified design entity. first example contains three component instantiations: component definition entity goose port bit; bit); goose; architecture snow_goose goose begin snow_goose; design definition entity flock port bit; bit); flock; architecture three_geese flock signal bit; component goose -component declaration port bit; bit); component; begin one: goose port -component instantiations two: goose port three: goose port three_geese; this example, architecture three_geese contains declaration component goose three instantiations that component, definition component's configuration. default, VHDL uses entity same name component this case goose), which defined beginning design.
Managing Large Designs
override default component definition using configuration specification. example, configuration specification could have been used describe another architecture entity flock, follows: architecture three_birds flock signal bit; component bird -component declaration port bit; bit); component; all: bird work.goose; -configuration specification begin one: bird port -component instantiations two: bird port three: bird port three_birds; configuration specification, instantiation labels this example, "one," "two," "three") used instead reserved word indicate that configuration applies particular instances specified component. Configurations have many other capabilities that described standard VHDL texts. design contains multiple design entities, need specify which used root (top level) design. Metamor's default last entity analyzed. override this default using elaborate compile option.
Managing Large Designs
Package Declarations Clauses
package declaration used declare common types subprograms. example: package example_package type shared_enum (first, second, third, last); example_package; order contents package visible from inside entity architecture, need place clause before entity declaration. example: work.example_package.all; entity design_io design_io; Placing clause before entity causes contents specified package visible that entity architecture(s), nowhere else. work library default name current library. now, just treat template always include clause. Since VHDL visibility rules ignore file boundaries, package might file, clause entity declaration another, architecture third file. VHDL requires that these units have already been analyzed when they referenced code, order files command line important. required that design units placed different files. define common subprograms, package body used. information this construct, other applications clause, refer standard VHDL texts.
Managing Large Designs
VHDL Design Libraries
VHDL, design library defined implementation-dependent storage facility previously analyzed design units" (LRM, Section 11.2). library "work" special case, alias current library. Metamor, library simply external VHDL file files, files specified command line library "work". Some files stored Metamor directory also saved pre-analyzed binary ".mm0" files, Libraries made visible within source code library statement. make library units within library visible outside library, necessary statements: library stuff; stuff.all; useless.all; Makes visible design units stuff. Makes declarations design unit named useless visible.
enter following statement each design unit: stuff.useless.all; There mechanisms associating VHDL libraries with source files. first assumes library statement directly specifies file name, second uses compile option associate more files with library name. Power users will probably want second mechanism. first mechanism provides simple default support libraries.
Direct association
library defined file same name.The library statement above will cause Metamor read file named "stuff.vhd". compiler searches file current directory, then Metamor directory. eight-character limit imposed library names some versions operating system.
Managing Large Designs
Alias association
library defined list files compile option. library alias compile option allows library defined containing list files order thay analyzed. Compile Options. Common uses files such Synopsys library library IEEE: IEEE <path>\ieee.vhd <path>\synopsys.vhd place package shared between separtely compiled design units library WORK: WORK my_pack.vhd There three special cases. Aliases library "std" ignored. Also file metamor.vhd must library named "metamor" file ieee.vhd must library named "ieee." good practice list unused libraries because large libraries significant amounts memory.
Managing Large Designs
Metamor VHDL Libraries
library files supplied with Metamor contain following packages STD.VHD IEEE.VHD NUM_BIT.MM0 NUM_STD.MM0 METAMOR.VHD VLBIT.VHD SYNOPSYS.VHD IEEE 1076 package 'standard' IEEE 1164 package 'std_logic_1164' IEEE 1076.3 package 'numeric_bit' IEEE 1076.3 package 'numeric_std' Metamor specific package 'attributes' Metamor specific package 'array_arith' Viewlogic package 'pack1076' Synopsys package 'std_logic_arith' Synopsys package 'std_logic_unsigned' Synopsys package 'std_logic_signed' package 'macros' package 'macros'
XBLOX.VHD LPM.VHD
Documentation these packages included within VHDL source files, short descriptions follow. XBLOX libraries only used association with XBLOX compilers.
std.standard
VHDL 1076 package, declares bit, bit_vector, boolean, etc.
ieee.std_logic_1164
IEEE standard 1164 package, declares std_logic, std_logic_vector, rising_edge(), etc.
Managing Large Designs
ieee.numeric_bit
This package part IEEE 1076.3 Draft Standard VHDL Synthesis Package. package supplied binary compiled form. source code available from IEEE part Standard. This package defines numeric types arithmetic functions with synthesis tools. numeric types defined: UNSIGNED: represents UNSIGNED number vector form SIGNED: represents SIGNED number vector form base element type type BIT. leftmost treated most significant bit. Signed vectors represented two's complement form. This package contains overloaded arithmetic operators SIGNED UNSIGNED types. package also contains useful type conversions functions, clock detection functions, other utility functions. This package binary file num_bit.mm0. this package library alias IEEE should num_bit.vhd. IEEE <path>\num_bit.vhd VHDL Design Libraries information alias association.
9-10
Managing Large Designs
ieee.numeric_std
This package part IEEE 1076.3 Draft Standard VHDL Synthesis Package. package supplied binary compiled form. source code available from IEEE part Standard. This package defines numeric types arithmetic functions with synthesis tools. numeric types defined: UNSIGNED: represents UNSIGNED number vector form SIGNED: represents SIGNED number vector form base element type type STD_LOGIC. leftmost treated most significant bit. Signed vectors represented two's complement form. This package contains overloaded arithmetic operators SIGNED UNSIGNED types. package also contains useful type conversions functions. This package binary file num_std.mm0, package depends upon IEEE.STD_LOGIC_1164. this package library alias IEEE should include ieee.vhd num_std.vhd. IEEE <path>\ieee.vhd <path>\num_std.vhd VHDL Design Libraries information alias association.
metamor.attributes
Declarations metamor specific synthesis attributes.
metamor.array_arith
This package contains subprograms that allow arithmetic operations arrays optimizing third party synthesis packages. These functions intended hidden from user within other functions contained third party package. There would implementations package body, optimized synthesis (uses these functions), other optimized simulation. documentation with file describes list assumptions example usage. More examples these functions found vlbit.vhd synopsys.vhd
Managing Large Designs
9-11
vlbit.pack1076
This package contains type subprogram declarations Viewlogic's built-in type conversion resolution functions. package been optimized with Metamor compiler. Vlbit based designs not) require some modification; this described below. Vlbit designs make register inference conventions that different from those used Metamor. case look preset/reset, which specified wait statement along with clock. Using Metamor, this will result gated clock, which probably what want. should replace wait statement with if-then style register inference. should validate using simulation also check that number registers used their type (flip-flop/latch, preset/reset, sync/async) what expected. When verbose mode, compiler reports register types, number instances.
ieee.std_logic_arith ieee.std_logic_unsigned
These packages versions Synopsys packages that have been optimized with Metamor compiler. When importing designs should validate using simulation also check number registers used their type (flip-flop/latch, preset/reset, sync/async) ensure they what expected. When verbose mode compiler reports register types, number instances. These packages file synopsys.vhd (although they ieee.std). these packages library alias IEEE should include ieee.vhd synopsys.vhd. VHDL Design Libraries information alias association.
9-12
Managing Large Designs
xblox.macros
This package contains component declarations Xblox macrocells, with Xblox compiler. These components instantiated your design usual way. example: compare port (d1,d2, a_ne_b package based ieee.std_logic_1164.std_logic. wish datatypes other than std_logic, then create your package copying from this one. There hidden magic words, except that port generic names must match Xblox specification. components that Xblox macrocells must have Metamor synthesis attribute 'macrocell' 'true'.
lpm.macros
This package contains component declarations macrocells, with compiler. These components instantiated your design usual way. example: lpm_compare generic (4,"unsigned") port (d1,d2, package based ieee.std_logic_1164.std_logic. wish datatypes other than std_logic, then create your package copying from this one. There hidden magic words, except that port generic names must match specification. components that macrocells must have Metamor synthesis attribute 'macrocell' 'true'. requires instance specific Properties. These specified using VHDL generics. component declarations include these generic declarations. Instance specific values specified with generic map. Some examples signal std_logic_vector(3 downto signal std_logic_vector(0 signal d3,d4 std_logic_vector(7 downto lpm_compare generic -default "signed" port (d1,d2, lpm_compare generic (2,"unsigned") port (d3,d4, y2); used lpm_compare generic (representation =>"unsigned", width port (d3,d4, used Managing Large Designs 9-13
Hierarchical Compilation
whole design need recompiled when only single architecture changes. Metamor supports this feature through hierarchical compilation. granularity hierarchical compilation component. This feature requires that user maintain link resulting elements hierarchy (components) external Metamor. user also responsible checking root leaf interfaces consistentcy. This feature only available with output formats that support hierarchy. component entity visible when design root compiled, entity bound that component. This results hierarchy instantiation output file with definition that leaf hierarchy. leaf entity that visible during first compilation generated second compilation using Metamor. Because binding between root leaf external VHDL compiler (the user links these together) certain VHDL features available hierarchical compilation boundary. user responsible ensure that component entity port definitions exactly match. Some things watch include: Leaf entity component names must same. Leaf entity component port names subtypes must same. Leaf instance have 'generic map'. Leaf have port that type that unconstrained. Ports that have array type must have matching directions entity component declaration. Leaf component declaration contain port (the component instantiation still contain port map) Root leaf must reference signal declared outside their scope (e.g. signal declared package). Configurations supported across hierarchical compilation boundary.
9-14
Managing Large Designs
Logic Metalogic
design description consists code serve three distinct functions. Logic expressions -logic hardware implementation. value logic expression changes over time. VHDL terms value depends upon signal. Metalogic expressions -logic about (not hardware implementation. value metalogic expression does change over time. VHDL terms value must depend upon signal. Metalogic values logic value extensions tools such simulators synthesis tools. Metalogic values describe state design model. Metalogic expressions important synthesis they imply hardware. This allows them compile faster, generally produces more efficient synthesis results. addition, some constraints VHDL synthesis depend upon certain expressions being metalogic expressions (i.e., they must vary over time). Metalogic values tool specific values (specific simulators synthesis tools) added design description. understanding required values important when porting VHDL code from simulator synthesis tool(in addition additional constraints design classic programming language, design description consists logic expressions, constant metalogic expressions, perhaps (mapped dont care) metalogic value. This section beginners
Logic Metalogic
10-1
Logic expressions
Logic expressions familiar hardware engineers, classic programming language consists logic expressions. VHDL examples logic expressions might a,b,c,d, signals
Metalogic expression
Anexample simple metalogic expression using constants. VHDL examples might ('0' '1') constants, generics, generates, loop iterators VHDL speak, static, then expression static expression (see LRM) also metalogical. Metalogic expressions also contain variables. More this later this section. more useful example metalogic expression might loop expression loop left(i) right(i+2); loop; expression implies logic. metalogic expression, used (and loop statement) specify information about design, which does appear implementation. result more concise, relationship between arrays left right more clear. course, five distinct assignments would produce same result. expression containing variable will metalogical variable's value depends only metalogic expression. Metalogical Variables very powerful, only possible tell they metalogical from context, shown following example. expression said metalogic expression static expression, metalogic expression addition contain variables whose values depend only upon metalogic expressions.
10-2
Logic Metalogic
larger example metalogic might following function, which converts vector integer. will that logic generated different each function call, depending upon argument passed each call. constant too_long_msg STRING "Array long integer."; constant too_short_msg STRING "Null array passed subprogram."; function to_integer BIT_VECTOR return INTEGER variable result INTEGER variable INTEGER begin Report null range assert arg'length report too_short_msg severity NOTE; Assert array size limit. assert arg'length report too_long_msg; Calculate bit_vector value. arg'reverse_range loop then result result test before multiplying avoid overflow arg'left then loop; return result; to_integer; Reviewing this function that variable depends only initial value integer current value that always metalogical variable assignments imply logic.
Logic Metalogic
10-3
variable 'result' depends initial value 'result' (metalogic), value (metalogic), 'arg', which depends argument function called with. function called with metalogic parameter, to_integer("010101"); then constant, hence metalogic. also follows that 'result' metalogic. function implies logic, just pull pull down. However, function were called with logical parameter, would metalogic, hardware implied. example: to_integer(some_signal); this case algorithm implemented such that hardware simply wires. (hint: binary representation always single many 0s). Variables declared subprograms allow metalogic expressions. same true variables declared process. However, variables process usually depend sensitivity list wait statement (statement list explicit implied). Therefore, they usually metalogical. simulation terms, variables process persist over time. Variables subprogram created when subprogram called destroyed when returns (like difference between static variables automatic variables
10-4
Logic Metalogic
Metalogic values
Metalogic values extensions design description. They provide additional information tools allow tools produce better results. examples unknowns simulation dont care logic optimization. these metalogic values alternatives logic values (0,1) within tools. These metalogic values have different meanings different tools. Unknowns allows detect design description errors during simulation. Errors such unconnected inputs connected outputs (try writing boolean equations these clearly describe logic. Unknowns uninitialized registers (but unknowns injected timing errors) also highlight boolean logic errors. long simulation propagates such metalogic know that design description does represent logic. Dont care works around limitations boolean representation, allowing logic minimizers technology mappers produce more compact description. high level language provides more elegant solution, which user never consider dont cares. This alternative describe design using multi-valued enumerated types place arrays booleans. Prep compare 'state_type' versions design. descriptions produce equally efficient results. understanding metalogic values significant because output synthesis tool boolean logic (0,1); therefore, metalogic values removed (and possibly used) during synthesis. This significant operation design depends upon metalogic values. design that depends some signal having value possible implementations: signal either (but never Within VHDL, only common metalogic values some elements enumerated type std_ulogic std_ulogic type IEEE standard 1076.3 specifies that four these values metalogic values, with specific semantics. However, simulator they just elements enumerated types. synthesis make attribute 'enum_encoding' describe which elements describe logic values which describe metalogic values (see Std_logic_ll64 Metamor follows standard considers '1', 'Z'. logic values remainder metalogic values. metalogic values used within Metamor's logic minimization.
Logic Metalogic
10-5
When using std_logic, metalogic values have meaning simulation tool another (dont care) synthesis tool. Within Metamor, metalogic values simply thrown away, treated expressions dont cares specified enum_encoding. Signals propagate metalogic values, only possibly 'Z'. metalogical values possible difference between simulation model hardware design. example, with metalogic argument equality opeartion will always return false synthesis, simulation result will depend upon current value other argument; therefore, unknown handling used simulation ignored synthesis: assert isome_signal report "unknown, news" severity error; function 'is_x' from 'ieee.std_logic_1164' used time synthesis simulation flag. This function will always return false within synthesis, result depends upon current value during simulation. is_x('W') then assert false report "simulation code" severity note; else assert false report "synthesis code" severity note; WARNING: such tricks impair your validation methodology
10-6
Logic Metalogic
XBLOX Macrocells
Macrocells components whose behavior defined outside VHDL some other (downstream) tool. Examples macrocells include Xilinx XBLOX macros, macros, target hardware specific macrocell such micro controller. Metamor compiler handles macrocells manner similar Hierarchical Compilation described Managing Large Designs. declare macrocell simply attribute Macrocell (value true) component declaration. component compare -component declaration port bit_vector(4 downto bit); component; attribute macrocell compare component true; attribute macrocell
Usage exactly like Hierarchical Compilation with exception; there requirement that component match entity because such entity exists (the behavior macrocell defined some other tool). instantiate this macrocell would other component. example: compare port
compiler will issue time message: component Macrocell "compare" This error, simply note that this component's behavior defined VHDL will defined macrocell compiler.
XBLOX
11-1
formal port declarations unconstrained, generics used, macrocell becomes parameterized macrocell. Parameterized macrocells only supported LPM, XBLOX Open Abel output formats. This described following section. compiler reports instantiated parameterized macrocells
addition macrocells automatically inferred compiler. Whether inferred instantiated, macrocells usually give better synthesis results terms both area delay; compilation usually faster too. verbose command line option will enable compiler print names inferred macrocells. Compile Options.
11-2
XBLOX
XBLOX
XBLOX specifications allow extended macrocell support. Macrocells parameterized. This means that each instance particular macrocell describe different amounts logic. Libraries component declarations provided (see section VHDL Design Libraries) Macrocell inferred. This means that compiler automatically recognizes some VHDL statements expressions equivalent macrocell.
also, Compile Options.
Macrocell Instantiation
example, Compare macrocell from Xblox library declared with unconstrained ports style parameter: component compare generic (style string ""); port std_logic_vector; a_eq_b, a_ne_b, a_lt_b, a_gt_b, a_le_b, a_ge_b std_logic); component; attribute macrocell compare component true; macrocell instantiated with input ports whose size varies with each instantiation. parameter style specified left XBLOX default. And, usual VHDL manner, named association pick from ports. example: port (a_byte, b_byte, a_eq_b port (a_byte, b_byte, a_eq_b a_ge_b bigger); compare generic ("RIPPLE") port (a_word, b_word, a_le_b =>lss); compare compare
XBLOX
11-3
Combinatorial Macrocell Inference
Inference occurs transparently user when output format supports parameterized macrocells. Inference maps VHDL relational arithmetic operators format specific macrocells. example, multiply operation below will results multiply macrocell format, adder macrocells XBLOX format. relational operations Compare macrocell. following concurrent statements equivalent a_nibble b_nibble; compare port (a_nibble, b_nibble, a_ne_b neq); Macrocell inference only occurs both operands VHDL signals more formally metalogic expressions). example, adding VHDL constants will produce adder macrocell.
11-4
XBLOX
Sequential Macrocell Inference
process contains both inferred flip flops (see Programming Sequential Logic) inferred combinational macrocell, compiler infer sequential macrocell. example counter with reset described using concurrent statement. count when reset else count when rising_edge(clock); Sequential macrocells often have synchronous load control, which specified using statement. Load inference lowest priority register control inference. example, accumulator with load: process(RST,CLK) begin then Reset else (CLK CLK'event) then load then else process; behavior;
XBLOX
11-5
characteristic load having lower priority than clock enable instance, characteristic target macrocell simply reflected VHDL macrocell inference engine. Sometimes your design specify different behavior still want take advantage macrocell inference. Suppose your design specified counter with enable load that higher priority than clock enable. could following process(RST,CLK) begin then Async Reset else CLK'event then then load dominates clock enable, clkena then sync load else process;
11-6
XBLOX
Synthesis Attributes Predefined attributes
feature VHDL that familiar programmers attributes. VHDL many predefined attributes which allow access information about types, arrays, signals. list supported attributes their definitions contained VHDL Quick Reference. Some examples are: integer'high integer'low value 2147483647 value -2147483647
declare subtype type integer subtype shorter integer range 100; shorter'high value shorter'low value shorter'base'high value 2147483647 when used with array 'high attribute value array index: type my_array array boolean; variable info my_array; info'high value There attributes which give access information about signal waveforms. Most signal attributes simulation, have meaning context synthesis. However one, 'event, useful. used signals specify edge sensitivity. usually used combination with value test specify rising falling edge. signal clock boolean; clock clock'event specifies falling edge.
Synthesis Attributes
12-1
User defined attributes
VHDL allows user define their attributes. Metamor uses this capability define attributes synthesis. declaration these attributes found system library 'metamor'. these attributes, either make them visible (use metamor.attributes.all), copy your VHDL source description. value these attributes must locally static. package attributes User defined place route information passed output file -attribute pinnum string; attribute part_name string; attribute property string; User defined encoding enumerated types -attribute enum_encoding string; User specified critical nodes -attribute critical boolean; User specified macrocells -attribute macrocell boolean; attributes;
12-2
Synthesis Attributes
Attribute 'critical'
This introduces nodes into design, does from VHDL source. attribute critical allows user specify signals VHDL description whose timing critical. assignment such specified signal imply node output logic description. Critical also used factoring under control user. attribute critical a,b,c signal true; -a,b,c nodes general, Metamor will create logic minimized design description which there mapping between objects VHDL source description combinational nodes output logic description. Sometimes this 'minimum logic' description (where logic nodes collapsed controlled optimizer) optimal propagation delay layout resulting logic. this event, user control logic minimization means attribute 'critical', which applied signal VHDL source description. This when delay resulting logic benefit from designers knowledge structure circuit (electrical/timing) characteristics implementation simply depend being logically minimal. Critical constrains both logic optimizer factoring function specified user. example application might carry chain. example, look level second implementation Prep4. Here critical used separate output encoder instance from input decoder next result faster design. compiling PLD, compile option product terms; single instance will with logic delay array path. Critical used this case because neither inputs outputs components registered. state machine inputs also encoded such that they (just) within product terms. multiple instance case, manual specification critical nodes combined output/input logic using critical produces better results than automatic factoring. relationship between name VHDL signal specified critical, equivalent node complex. example, signal result node redundant, many nodes hierarchy used. name VHDL signal will maintained unless this would lead conflict. prefixed with instance block labels, package names, suffixed with number represents more than wire.
Synthesis Attributes
12-3
Attribute 'enum_encoding'
need specify different machine encoding different hardware technologies. example, encoding preferred FPGA CPLD. further information User Defined Encoding Encoding Also Don't Cares more enum_encoding.
Attribute part_name
Metamor allows designers pass place route information fitters, netlists. This information meaning Metamor, simply passed from VHDL output file. part_name attribute used specify target device, applied level entity. attribute declared Metamor library attribute part_name string; value specified follows: library metamor; metamor.attributes.all entity special_attributes port(c bit_vector bit_vector downto 25); boolean) -usage part_name attribute part_name special_attributes entity "22v10"; special_attributes; device compile option will override value part_name attribute.
12-4
Synthesis Attributes
Attribute pinnum
Metamor allows designers pass place route information fitters, netlists. This information meaning Metamor, simply passed from VHDL output file. pinnum attribute used specify pinout target device, applied ports level entity. attribute declared Metamor library attribute pinnum string; value string containing comma (',') delimited list names numbers. These values assigned elements port left right order. example library metamor; metamor.attributes.all entity special_attributes port(a integer range bit_vector bit_vector downto 25); boolean) usage pinnum attribute pinnum signal "4,5,6,7"; extra ignored gets attribute pinnum signal "8,9"; missing number b(0) assigned attribute pinnum signal "a3,b4,a1"; ascending order c(0) "a3" attribute pinnum signal "w1,W2,w99"; descending order c(27) gets "w1" attribute pinnum signal "2"; single special_attributes;
Synthesis Attributes
12-5
Attribute property
Metamor allows designers pass place route information fitters, netlists. This information meaning Metamor, simply passed from VHDL output file. property attribute used pass arbitary string output file. applied entity value included head output file, applied port value included property port output file. attribute declared Metamor library attribute property string; value passed directly output file; therefore, will need know legal syntax that file. second example shows using VHDL functions make this task less error prone. library metamor; metamor.attributes.all entity special_attributes port(c bit_vector bit_vector downto 25); boolean) usage property entity attribute property special_attributes entity "lca some text" "lca more text" "lca more text" "amdmach Mach Specific STuff"; usage property port attribute property signal "Fast"; special_attributes; Strings passed output file exactly specified VHDL source, case maintained. characteristic VHDL that line character legal within string; therefore, create several lines concatenate strings line using "xxx" "yyy" shown example above. This little cluttered unless declare functions commonly used string values. example:
12-6
Synthesis Attributes
package xilinx function timespec(name,from, too,delay string) return string; end; package body xilinx returns timespec symbol function timespec(name,from,too,delay string) return string begin return "SYM, XXX" name TIMESPEC, LIBVER=2.0.0, name "=from:" from ":to:" delay "END" end; end; library ieee,metamor; ieee.std_logic_1164.all; metamor.attributes.all; work.xilinx.all; entity MORE_ATTRIBUTES port (d,c,ce,r,tri std_logic; std_logic; std_logic_vector(2 downto 0)); attribute property MORE_ATTRIBUTES entity attribute property signal "FAST"; pins "FAST" end;
Synthesis Attributes
12-7
Attribute Xilinx_BUFG
This attribute ignored compiler output format XNF. output format input output buffers being inserted, this attribute causes IBUFs replaced BUFGs. buffers being inserted, user simply instantiate BUFG. attribute must declared attribute Xilinx_BUFG boolean; example library IEEE; IEEE.STD_LOGIC_1164.all; entity prep7 generic (width natural 15); port (CLK, RST,LD,CE std_logic; std_logic_vector(width downto buffer std_logic_vector(width downto 0)); declare Xilinx layout attribute attribute Xilinx_BUFG boolean; mark ports using BUFG (CLK will BUFG default) attribute Xilinx_BUFG signal true; prep7;
12-8
Synthesis Attributes
Attribute Xilinx_GSR
This attribute ignored compiler output format XNF. output format XNF, this attribute used mark that uses global reset resource. same behavior STARTUP symbol. attribute must declared attribute Xilinx_GSR boolean; example: library IEEE; IEEE.STD_LOGIC_1164.all; entity prep7 generic (width natural 15); port (CLK, RST,LD,CE std_logic; std_logic_vector(width downto buffer std_logic_vector(width downto 0)); declare Xilinx layout attribute attribute Xilinx_GSR boolean; mark port using routing resource this startup symbol below attribute Xilinx_BUFG signal true; prep7;
Synthesis Attributes
12-9
architecture behavior prep7 Xilinx startup component STARTUP port (gsr,gts,clk std_logic '0'; q2,q3,q1q4,donein std_logic); component; begin Instantaiate startup Xilinx_GSR above STARTUP port (gsr rst); end; design units separately compiled linked with XNFMERGE unit contains startup symbol, units that contain startup symbol should Xilinx_GSR attribute.
12-10
Synthesis Attributes
Attribute foreign
VHDL external language interface allow users specify modules some non-VHDL form; implementation VHDL tool specific. foreign attribute supports external HDLs This mechanism only supported using those output formats that support hierarchy linking. This attribute applied architecture. value specifies name external module. example entity abel_code port (a,b bit_vector(0 bit_vector(0 abel_code; architecture simple abel_code attribute foreign simple architecture "adder"; begin simple These statements architecture ignored, call foreign language module 'adder' generated when entity abel_code instantiated VHDL design. inputs outputs adder must match port declarations VHDL. There constraints: VHDL ports must have locally static types, VHDL generics passed external module.
Synthesis Attributes
12-11
example, adder might described Abel MODULE adder a_0, a_1, a_2, a_3, a_4, a_5, a_6, pin; b_0, b_1, b_2, b_3, b_4, b_5, b_6, pin; sum_0, sum_1, sum_2, sum_3, sum_4, sum_5, sum_6, sum_7, sum_8 pin; [a_7.a_0]; [b_7.b_0]; [sum_8.sum_0]; EQUATIONS END; side effect foreign attribute that foreign module might defined VHDL. easier this provided hierarchical compilation feature described Managing Large Designs.
12-12
Synthesis Attributes
Attribute array_to_numeric
Some type conversion functions very slow compile during VHDL synthesis. This attribute accelerates compilation specific common case: converting arrays numbers. example converting bit_vector integer shown Logic Metalogic. This particular conversion specifies logic very slow compile. This aspect also discussed some detail Logic Metalogic. Metamor provides attribute, 'array_to_numeric', short circuit compilation such functions follows: function to_integer BIT_VECTOR return INTEGER variable result natural variable natural attribute array_to_numeric to_integer function true; begin Calculate bit_vector value. arg'reverse_range loop then result result test before multiplying avoid overflow arg'left then loop; return result; to_integer;
Synthesis Attributes
12-13
attribute only applied functions with array formal parameter returning numeric type when parameter return value have same synthesis encoding. Synthesis VHDL Types discussion encoding. array argument, 'left assumed most significant bit. array argument treated signed unsigned depending subtype function return value. subtype return value ('natural' subtype variable 'result' example above) signed (integer signed), array argument sign extended. subtype unsigned (natural unsigned), argument zero extended. When this attribute true, formal parameter returned function with subtype returned object. Since this function short circuits semantics VHDL should used with caution.
12-14
Synthesis Attributes
Attribute macrocell
Macrocells components whose behavior defined outside VHDL some other (downstream) tool. Examples macrocells include Xilinx XBLOX macros, macros, some target hardware specific macrocell such micro controller. Metamor compiler handles macrocells manner similar Hierarchical Compilation described Managing Large Designs. declare macrocell, simply attribute Macrocell (value true) component declaration. component compare -component declaration port bit_vector(4 downto bit); component; attribute macrocell compare component true; attribute macrocell Usage exactly like Hierarchical Compilation with exception; there requirement that component match entity because such entity exists (the behavior macrocell defined some other tool). instantiate this macrocell would other component: compare port compiler will issue time message: component Macrocell "compare" This error, simply note that this component's behavior defined VHDL; will defined macrocell compiler. formal port declarations unconstrained, generics used, macrocell becomes parameterized macrocell. Parameterized macrocells only supported LPM, XBLOX Open Abel output formats. macrocell component declaration parameterized: component compare -component declaration port bit_vector; bit); unconstrained component; attribute macrocell compare component true; attribute macrocell then compiler reports instantiated parameterized macrocells component Parameterized Macrocell "compare" Synthesis Attributes 12-15
12-16
Synthesis Attributes
Synthesis Coding Issues
common misconception that synthesis compiler 'synthesizes VHDL' this incorrect. tool synthesizes your design expressed VHDL. Understanding hardware that specifying simplest rule success. This particularly important critical timing. Conversely easiest fail write model your design then wonder synthesis tool didn't design' you. What does synthesize mean this context? means 'transform logic design specification into implementation' nothing couldn't yourself. synthesis tool simply handles details this transformation you. This section contains examples user coding problems. They real user issues, some obvious, others not. also: Happy
Synthesis Coding Issues
13-1
Test High Impedance
following example means floating' quite reasonable test perform simulation model. However, synthesis tool transform this into hardware element that matches this behavior. then std_logic something code specifies logic cell that looks drive fanin then outputs true driven, false driven true false. Such cell does exist most programmable silicon. IEEE 1076.3 specifies that this comparison should always false, statements inside executed, logic generated.
Long Signal Paths Nested
Multiple nested elsif clauses specify long signal paths. "000" then first branch elsif "001" then second branch elsif "010" then third branch elsif "011" then fourth branch elsif "100" then fifth branch else last branch
13-2
Synthesis Coding Issues
This code inefficient describe logic case statement would much better. good example test fourth branch, which depends three previous tests describes long signal path, with resulting logic delay. case when "000" when "001" when "010" when "011" when "100" when others case; first branch second branch third branch fourth branch fifth branch last branch
practice, branches contain very little logic, there branches, then there little difference. However, case statement generally results better implementation.
Synthesis Coding Issues
13-3
Long Signal Paths loops
Loops very powerful, each iteration loop replicates logic. variable that assigned iteration loop used next iteration results long signal path. This signal path obvious.An example where long signal path expected behavior might carry chain (the variable below): function (a,b:bit_vector) return bit_vector assumes descending variable bit_vector (a'length downto variable c:bit '0'; begin a'reverse_range loop sum(i) a(i) b(i) (a(i) (b(i) (a(i) b(i)); loop; sum(a'length) return sum; end; example where this expected behavior hidden your code Some predefined VHDL operations also imply long signal paths, Programming Combinational Logic.
13-4
Synthesis Coding Issues
Simulation Optimized Code
likely that code written optimal simulation speed will optimal description logic. following example assumed that only control input will active time. description efficient simulation, poor logic description because independence control signals described within VHDL code. out1 '0'; out2 '0'; out3 '0'; then out1 '1'; elsif then out2 '1'; elsif then out3 '1';
Synthesis Coding Issues
13-5
independence control signals need contained within design description. result slightly slower simulation, smaller logic implementation after synthesis. out1 '0'; out2 '0'; out3 '0'; then out1 '1'; then out2 '1'; then out3 '1'; Note that issue long signal path, unclear specification design. best optimizer world can't turn inefficient algorithm into efficient one. algorithm that efficient from viewpoint efficient from another.
13-6
Synthesis Coding Issues
Port Mode inout buffer
Simply issue overspecification. Inout speci
Other recent searches
TLP4227G - TLP4227G TLP4227G Datasheet
TLP4227G-2 - TLP4227G-2 TLP4227G-2 Datasheet
THS3001 - THS3001 THS3001 Datasheet
SN74AHC158 - SN74AHC158 SN74AHC158 Datasheet
SN54AHC158 - SN54AHC158 SN54AHC158 Datasheet
PCA9546A - PCA9546A PCA9546A Datasheet
P205PH08-12 - P205PH08-12 P205PH08-12 Datasheet
OST089S01GDXXXXT8E1A - OST089S01GDXXXXT8E1A OST089S01GDXXXXT8E1A Datasheet
DM74ALS1008A - DM74ALS1008A DM74ALS1008A Datasheet
2N3704 - 2N3704 2N3704 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
