Logic Simulator User's Guide Seventh Edition Real-Time Inter
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ACTIVE-CAD
Logic Simulator User's Guide
Seventh Edition
Real-Time Interactive Tools
Automated Logic Design Company, Inc. 3525 Conejo #111 Newbury Park, 91320 Phone (805) 499-6867 (805) 498-7945
Seventh Edition Revision January 1996 COPYRIGHT Copyright 1985-1996 ALDEC. rights reserved. part this publication reproduced, transmitted, transcribed, stored retrieval system, translated into language computer language, form means, electronic, mechanical, magnetic, optical, chemical, manual otherwise, without prior written permission ALDEC, Newbury Park, 91320. DISCLAIMER ALDEC makes representations warranties with respect contents hereof specifically disclaims implied warranties merchantability fitness particular purpose. Further, ALDEC reserves right revise this publication make changes from time time content hereof without obligation ALDEC notify person such revision changes. TRADEMARKS ACTIVE-CAD, Active Schematic, SUSIE SUSIE-CAD trademarks ALDEC, Inc. ACCESS, ACTEL, ALTERA, AMD, MACH, MAX, NEC, EPSON, LASER JET, FUTURENET, OMATION, RACAL-REDAC, TANGO, CAPFAST, CADNETIX, CASE TECHNOLOGY, APPLICATION BRAVO, XNF, LCA, XILINX, ORCAD, P-CAD, PC/XT/AT, PS/2, EDIF, P-DIF, VIEWLOGIC, VIEWSIM, WINTEK, MENTOR, POST SCRIPT, CORELDRAW trademarks registered trademarks their respective holders. This edition applies Release software higher. reference guide ACTIVE-CAD ACTIVE-FPGA products ALDEC Automated Logic Design Company, Inc. 3525 Conejo Rd., Suite Newbury Park, 91320 Phone (805) 499-6867 (805) 498-4086 (805) 498-7945 Email: support@aldec.com
Preface
ACTIVE-CAD simulator real-time interactive design analysis tool. work both with on-line schematic capture with number off-line schematic editors. Since design resides directly accessible data tables, interact with your design were real hardware breadboard. take full advantage ACTIVE-CAD power, must remember differs from other popular simulators:
start simulation moment load netlist draw single devices electrically active moment they connected replace parts while simulation progress instantly apply stimulus signal(s) test vector(s) design section feature selections instantly active, without compilations simulator directly control external hardware respond ACTIVE-CAD works like real hardware breadboard
signals generated external hardware device without compilation view improved design performance active signal lines gate; compilation design test vectors needed
Manual Organization
manual comprised five logical parts:
introduction real-time interactive simulation general description ACTIVE-CAD menus simulation process simulation supporting tools appendices
Preface
introduction real-time interactive simulation
Since real-time interactive simulators represent technology, Simulation Basics (Chapter will allow become familiar with real-time design analysis. Some your designs after reading this chapter. However, urge read additional chapters further explore breadth ACTIVE-CAD simulator.
General description ACTIVE-CAD menus
general description ACTIVE-CAD menus provided Using ACTIVE-CAD Simulator (Chapter Since this chapter gives overview available features, should become familiar with most software package. This also best product reference guide, right after Index.
outline simulation process
detailed description simulation process starts with section Loading Design ends with Printing Simulation Results Chapter
Simulation supporting tools
simulation support tools described chapters External Test Vector Editor, Mobic Model Builder Simulator Macro Operations. VHDL Shorthand software product manual. these chapters describe some advanced test vector development products modeling tools. Learning these tools optional.
Appendices
This collection ACTIVE-CAD-related specifications which lists libraries, some application notes specifications. ever need write your interfaces ACTIVE-CAD netlists test vectors, consult Appendices necessary information.
Application notes specific design issues
Some design issues have been covered several sections manual with different examples. Most design-specific customer inquiries have found their into section Quick Application Notes Chapter Additional application books also available technologies. Your comments invaluable invite share your experiences with will include them additional sections manuals. happy answer your questions make your time with ACTIVE-CAD most productive.
Chapter
Simulation Basics
Introduction
There many digital simulators. However, none them will give hardware breadboard feeling like real-time interactive ACTIVECAD simulator. Everything with ACTIVE-CAD will always directly related your hardware experience. There four basic steps design simulation:
creating electronic breadboard selecting test points monitoring creating applying design stimulus signals analyzing simulation results
ACTIVE-CAD creates electronic breadboard your design directly from netlist. However, unlike hardware breadboard, your electronic breadboard created within seconds perfect every respect: solder joints, miswirings, wrong polarities, chips, ground noise, signal line crosstalk, name possible problems. electronic breadboard tested with signals which called test vectors. Each test vector lists logical states stimulus signals selected time interval. testing 2-input gate, only need four test vectors (00, 11). However, testing 8-bit binary counter, then need test vectors (clocks) test operation. Hardware breadboards allow apply signal generator probes live board. Similarly, ACTIVE-CAD test vectors cre-
[<basic]
ated applied test point schematic while simulation progress. Because that, ACTIVE-CAD electronic breadboard operates like real hardware breadboard, manually toggle signal line real time. This analogy between ACTIVE-CAD real hardware strong that need only hours learn this simulation tool.
Schematic Design
Electronic Breadboard
Waveform Viewer (Logic Analyzer)
Test Vector Editor (Stimuli Signal Generator)
Figure 1-1. SUSIE Simulator Environment.
ACTIVE-CAD comes with test vector editor that allows create signals stimulating design circuits with desired action. apply these stimulus signals test vectors test point your design. test vector editor produce 1,000 independent signal waveforms (channels), each capable GigaHertz clock speed. ACTIVE-CAD signal generator thus superior hardware signal generator, fraction cost. Since ACTIVE-CAD display 1,000 signal channels, each operating GigaHertz clock speed, since automatically displays circuit timing errors, more powerful than logic analyzer. ACTIVE-CAD design environment shown Figure 1-1. Since ACTIVE-CAD simulator behaves like real hardware breadboard, ACTIVE-CAD-based designs operate closed loop with actual hardware located outside computer.
Introduction
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Creating Electronic Breadboard
Creating working hardware breadboard requires someone wire sockets insert components. same true electronic breadboard. Since ACTIVE-CAD incremental design environment, wires electronic breadboard inserts devices (simulation models) into sockets draw them. Loading external netlist automatically creates entire electronic breadboard, including loading appropriate device models.
Missing Models
using some components which ACTIVE-CAD does have model, such Pentium microprocessor, then socket will remain empty. Also, have purchased some libraries (not encoded into keylock), their component sockets will remain empty despite that they have been drawn ACTIVE-CAD schematic editor model libraries listed library manager. empty sockets electronic breadboards behave exactly like empty sockets hardware breadboards they don't load input signals they float output signal lines. Since ACTIVE-CAD real-time interactive simulator, assign outputs such devices your test vectors that emulate their behavior simulate entire design despite absence these device models. will find more information handling missing models Test Vectors Handling Missing Models included Loading Design (Section Chapter
Entering Design Test Points From Schematic
Since ACTIVE-CAD schematic imitates real hardware breadboard, select tests points on-line background simulator directly from schematic. select test point selection mode, click Simulation toolbox icon schematic editor then click desired test points. Each click will produce test points pins nodes signal names. selected test points will also into simulator once activated.
Loading External Design Netlists
create electronic breadboard design need load netlist. Because ACTIVE-CAD universal design verification tool, accepts netlists from other schematic editors. Over twenty most popular schematic netlist formats available, including some formats which hardly today. This means that should able simulate design matter
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Creating Electronic Breadboard
Simulator main menu
type logical state current cursor position Stimulator name
Signal name
Figure 1-2. SUSIE Simulator main window.
Upon loading netlist into ACTIVE-CAD simulator, will display screen shown Figure 1-2. Familiarize yourself with terminology this figure because will very useful following chapters. select test points design represented imported netlist, procedure described reference Figure 1-7. load design netlist, select Load Netlist option from File menu shown Figure 1-3. response, ACTIVE-CAD displays Load Netlist window Figure 1-4. Select desired netlist format from From Format field. Some available netlist formats shown Figure 1-5.
Figure 1-3. File Menu Options.
Introduction
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Figure 1-4. Load Netlist window.
ACTIVE-CAD automatically lists Input Netlist field (Figure 1-4) netlists selected netlist format. This simplifies your search because only desired netlist files listed.
Select desired netlist format
Figure 1-5. Simulator Netlist Formats.
Example
Select from From Format field shown Figure SUSIE Binary [*.ALB] format. Click TEST_A project Directories window then button. response ACTIVE-CAD should list TEST_A.alb netlist which supplied with software example flat netlist format. Click TEST_A.alb netlist then button. ACTIVE-CAD loads selected netlist displays messages about loading progress. Don't surprised after netlist been loaded there changes simulation screen; avoid
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Creating Electronic Breadboard
screen clutter only data have explicitly requested will displayed simulator screen. better understanding TEST_A netlist operation, refer Figure 1-6, which shows schematic design from which this netlist generated. ACTIVE-CAD provide connectivity information even recreate entire schematic from netlist. However, quick reference readily available schematic Figure 1-6. Directories window Load Netlist window (Figure 1-4) allows search netlist files drive throughout entire network ACTIVE-CAD been installed one. Since these typical Windows operations, details file search provided here.
Figure 1-6. TEST_A Schematic Design.
name currently loaded netlist appears title logic simulator. example, Figures show that netlist been loaded into simulator. additional verification that right netlist been loaded performed clicking Signal Selection button Waveform Viewer toolbar. response, Component Selection window shown Figure will list signal names components loaded design. quick review that list will confirm have loaded desired design.
Introduction
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Figure 1-7. Design Component Display.
NOTE: using schematic editor that integrated with ACTIVECAD through Windows interface protocol, then need load netlist because schematic changes automatically implemented simulator data base. most popular schematic editors that protocol communicate with SUSIE SUSIE-CAD, ACTIVE-CAD, DIGILAB Virtual Hardware Editor.
Selecting Design Test Points
stimulate hardware breadboard, need hardware signal generator apply signals selected test points breadboard. similar process employed with electronic breadboard. However, stimulus signals generated applied with much greater ease. select design test points which want apply external signals, select Signals option from Signals menu. have loaded TEST_A netlist that comes with ACTIVE-CAD simulator, then response ACTIVE-CAD will display window shown Figure 1-7. Signals Selection field displays design signals, such input output terminals, node names buses. select these signals display, double-click with left mouse button. This will instantly copy selected signal into Waveform Viewer window (Signal field Figure 1-2).
Example
With TEST_A netlist loaded, double-click input signal listed Signal Selection field Component Selection window (Figure 1-7). Note that signal been automatically copied Signal field Waveform Viewer window (Figure 1-2).
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Selecting Design Test Points
have large number adjacent signals transferred ACTIVE-CAD display, double-clicking tedious. Instead, first select desired signals then transfer them same time. select signals, hold down [Ctrl] click each desired signal name. When signals have been selected, click Move button Component Selection window (Figure 1-7). Note that selected signals have been transferred into ACTIVE-CAD logic simulator window order which they have been selected.
Example
Click OUT1 signal. Next, depress [Ctrl] click sequence signals Signal Selection field Component Selection window Figure 1-7. Following this, click Move button. Note that signals have been transferred Signal field ACTIVE-CAD display order which they have been selected. also select device test point apply stimulus signal select device pin, double-click selected device listed Component Selection window Figure 1-7. response, ACTIVECAD displays Pins for: window that lists pins selected device (Figure Double-click selected pins move them desired order. Marking signals then activating Move button copies signals order which they were listed window order which they were selected. Since ACTIVE-CAD real-time interactive simulator, delete test points while simulation progress. There limit what select display screen stimulate with signals developed simulator loaded test vector file.
Example
With TEST_A netlist loaded, double-click U1-7400 Figure 1-7. response, ACTIVE-CAD displays Figure which lists device pins Pins For: U1-7400 field. Double-click A1-1 moved ACTIVE-CAD screen.
Introduction
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Figure 1-8. Display pins.
Continue copy signals waveform viewer until waveform viewer shows signals listed Figure 1-9. Save this setup test points selecting Save Test Vectors option File menu. consistency with this Guide, save TEST_A file.
type signal signal name name number
Figure 1-9. Selected design test points.
Selecting Test Points Hierarchical Designs
your ACTIVE-CAD hierarchical simulation option, will able load hierarchical design netlists. ACTIVE-CAD software comes with TEST_H hierarchical netlist, which based hierarchical schematics shown Figures 1-10, 1-11 1-12. Loading hierarchical netlists identical loading flat netlist, described Example After loading TEST_H1 hierarchical design netlist, select Signals option from Signals menu. response, ACTIVE-CAD will display window shown Figure 1-13.
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[<basic] Selecting Test Points Hierarchical Designs
Figure 1-10. Schematic Macro
Figure 1-11. Schematic Macro
Introduction
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1-11
Figure 1-12. Level Schematic.
Signals Selection field displays design signals selected hierarchical level. Since starting point after loading hierarchical netlist level design, Figure 1-13 lists signals that level. select these signals display, double-click with left mouse button. This will instantly transfer selected signal into Signal field window shown Figure 1-2. also hold down CTRL key, click each desired signal, then transfer them ACTIVE-CAD screen activating Move button.
Figure 1-13. Hierarchical Design Structure Display.
select signals from selected hierarchical level, click selected hierarchical level Scan Hierarchy window shown Figure 1-13. Signals Selection window displays signals Component Selection window lists macros devices that hierarchical level.
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Creating Design stimulus Signals
select signals device pins screen display described reference flat design netlists.
Creating Design stimulus Signals
main advantages simulation over hardware breadboarding that don't have logic analyzer setups. data automatically captured analyzed simulator. This only improves design quality also saves time. However, development efficient test signals still remains major challenge. incremental simulation process very similar hardware debugging, where each input signal line signals from separate signal generator channel. However, once hardware pieces have been individually debugged integrated, they tested with signals that have strictly predefined time relationships. These signal sets called test vectors. Since design analysis needs change design evolves from simple circuit fully operational system, design testing methods must change well. thus important remember about changing needs optimum analysis methods each stage design development:
primarily signal waveforms incremental circuit development continuously optimize signal waveforms design grows save signal waveforms ASCII binary test vector files test vector files exclusively final system verification
Since many designers have strong hardware breadboarding background, ACTIVE-CAD comes with signal generator that mimics operation hardware signal generators. This simplifies transition from hardware circuit debugging incremental software design testing. Since final design testing different objectives from those incremental design analysis, Simulator Macro Operations (Chapter will address test vector generation batch mode design verification. Signals that stimulate circuit basis effective design testing. this reason, should become thoroughly familiar with effective signal waveform test vector generation. chapters this manual, test vectors most important even experienced designer, should still familiarize yourself with enclosed figures, warnings notes.
Introduction
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Signal Waveforms Test Vectors
issues design analysis signal waveforms test vectors different design stages. Figure 1-14 shows difference between these terms graphical form.
Signal waveforms horizontal waveforms that start time
continue time example, signal waveform string signal logical values times (0,1,0,1,0,1.)
Test vectors logical states signal lines given time
instance. They viewed vertical slices across signal lines. example test vector logical value because IN1=0, IN2=0 time (TV0=00H). Similarly, TV1=10H, TV2=01H, etc. NOTE: test vectors counted from top-most signal line Figure 1-14 (the left-most character TV0) signal bottom (right-most characters TV0). Also, input signals have High. Output signals have High. Since output signal, test vector assigns instead Similarly assigns instead signal waveform gives good view selected signal behavior over time. test vectors other hand give exact relationship between signals selected time instance. When deal with such signals clocks override signals, prefer signal waveforms. Also, when testing design real time, would usually generate apply signal waveforms rather than test vectors. Some designers prefer stimulate their designs with signal waveforms. Others prefer test vectors. truth that need both methods because design needs change move from incremental debugging mode final design verification. signal waveforms have been continuously upgraded optimized during incremental design analysis, then test vectors will readily available final design verification.
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Ready-Made Signal Waveforms
(t3) (t2) (t1) (t0)
Test Vectors
Signal Waveforms
Figure 1-14. Difference between waveform test vector.
ACTIVE-CAD comes with:
signal waveform editor off-line (external) test vector editor test vector macro editor
Ready-Made Signal Waveforms
Designing signal waveforms often very cumbersome time consuming, particularly complex designs. make your work easier, ACTIVE-CAD comes with over fifty (50) ready-made signal waveforms that fulfill over your interactive design testing needs. differentiate between signal waveforms test vectors, will call signal waveforms stimulators. allow broad range operations stimulators, special Stimulator sub-menu (Figure 115) provided within Logic Simulator main menu:
Figure 1-15. Stimulator menu.
Stimulators option displays window (Figure 1-16) with
ready-made stimulators. assign them signal names ACTIVE-CAD screen, they will directly control these signal lines.
Introduction
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1-15
Chip Controlled Mode gives direct control over selected signal line chip output without deleting stimulator which been previously controlling that signal line
Override Mode allows stimulators override assigned
output signals
Disconnect eliminates effect assigned stimulator Connect restores effect assigned stimulator Delete completely deletes selected stimulator from screen Delete deletes stimulators from screen
Ready-Made Stimulators
ACTIVE-CAD stimulators shown Figure 1-16. They have preassigned names which assign signal names displayed screen. assign stimulator selected signal line: Click Stimulators Stimulators menu. Click selected signal name, e.g. shown Figure 1-14. After selected signal name turns blue, click desired stimulator shown Figure 1-16. selected stimulator name appears Stimulator column, next signal line.
also assign stimulators follows: Click stimulator Figure 1-16 Holding left mouse button down drag cursor desired signal name, e.g. Figure 1-14. Release mouse button. selected stimulator instantly assigned. buttons Stimulator Selection window Figure 1-16 arranged into groups:
Keyboard keys (A-Z) which used direct interactive toggling signal lines while simulation progress.
Software-emulated counter with TRUE (B0-B15) INVERTED (NB0-NB15) outputs. These outputs provide clock signals with duty cycle. clock counter adjustable.
Formula stimulators. Formulas allow generate custom-made
signal waveforms from nested expressions that involve signal values
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[<basic]
Keyboard Keys
their duration. These formulas assigned selected Form buttons (F0-F15) which then assigned control signal lines.
Asynchronous clock stimulators defined with Clock Editor. Control buttons which allow control signal overriding capability.
Formula Clock Editor which allows define formula
stimulators asynchronous clocks.
Asynchronous clocks defined special clock signals Custom Signal; indicates manually drawn test vector Software-emulated binary counter Formula stimulators defined Formula Editor Control buttons
Keyboard keys allow toggle signal logical states directly from keyboard
TRUE outputs INVERTED outputs Formula Editor Clock Editor
Figure 1-16. Stimulator Window.
Keyboard Keys
When assigned stimulators, keyboard keys operate SPDT switches that switch signal line between GND. Figure 1-17 shows keyboard assigned gate input keyboard assigned reset input flip-flop U1A. Both keyboard keys directly control these inputs, irrespective other signals that provided connections other sections design. Note that cuts signal line connected other circuits. equivalent hardware cutting wire between flip-flops reset input other circuits board.
Introduction
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1-17
assigned input cuts other input signals
Keyboard stimulator represented switch that toggles between High logical states.
Figure 1-17. Keyboard stimulators.
Keyboard keys primarily used direct toggling selected signal lines while simulation progress. example, circuit Figure 1-18 under direct control keyboard keys
Overriding device input pins
device input pins overridden assigned keyboard keys times. example, referring Figure 1-18, keys control reset lines flip-flops, respectively. controls D-input first flip-flop. Even there circuit-generated signal into device input, keyboard will always override such signal. good example such case keyboard which overrides U1A-Q signal U2B-D input (Figure 1-18).
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Overriding device output pins
Figure 1-18. Direct Circuit Control with Keyboard Keys.
Overriding device output pins
keyboard keys override device outputs automatically forcing Override mode button Figure 1-16 Override Mode Figure 115). signals operating Override mode red. allow chip outputs take control outputs, select Chip Control mode button Figure 1-16). example, keyboard automatically overrides U1A-Q output signal until Chip control mode button) activated. assign same keyboard key, e.g. key, many signal lines needed. Using options Stimulator menu shown Figure 1-15, enable (Connect option) disable (Disconnect option) assigned keyboard keys.
Overriding signal names
keyboard assigned netlist name (e.g. Figure 1-18), controls signals node overriding mode. Otherwise, active output node will control that node.
Binary Counter
ACTIVE-CAD comes with in-software implemented 16-bit binary counter. shown Figure 1-19. counter automatically provides TRUE (B0-B15) INVERTED(NB0-NB15) stimulators that assigned signal line your design. These clocks have duty
Introduction
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1-19
cycle. binary counter driven signal, which selecting Clock Settings option from Options menu. Note that must enter one-half desired clock period. example, want clock speed nanosecond period), must enter nanoseconds, clock period. CTR4 CTR3 CTR2 CTR1
Figure 1-19. In-Software 16-bit Binary Counter.
rescale binary counter input clock from 1000 Hertz GigaHertz. Each counter stage divides clock half. example, have input clock MHz, output =100MHz, B1=50 MHz, B2=25 MHz, etc. Each stage 16-bit binary counter drives lamp shown Figure 1-19. B0-B15 signal lines TRUE binary counter outputs associated lamps green. inverted counter outputs (N0-N15) have lamps. assign same binary counter output signal, e.g. many signal lines needed. binary counter lamps shown simulator screen shown Figure 1-2. They allow view current state this signal generator.
Formula Stimulators
Formula Editor allows develop signal waveforms quickly efficiently. Because these waveforms, also called formula stimulators, shape duration, them non-repetitive functions bursts pulses duration. also formulas designing clocks with special duty cycles various logical states.
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Formula Stimulators
formula stimulators give freedom define redefine signal waveforms while simulation progress. This extremely simple very powerful method designing most complex design stimulus being widely used FPGA board-level designers.
double click desired formula name
Edit selected Formula stimulator this line When finished editing, press this button save formula. formula will added this list your viewing
Figure 1-20. Formula Editor Window.
process defining formula comprised writing:
parentheses (used nested expressions) logical signal state symbols (H,L,Z,X) duration signal states (e.g. 12.31 nanoseconds) number repetitions signals parentheses brackets defining buses
Example
(H2L3)3 There limit neither depth signal nesting signal duration. activate Formula Editor, click Formula button shown Figure 1-16. response, ACTIVE-CAD displays window shown Figure 1-20.
Introduction
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First, select formula name from Select Stimulator window double-clicking selected name, e.g. ACTIVE-CAD displays selected name Selected Stimulator field. Next, enter signal formula Formula: window, e.g. ((L20H15.01)5X32L24)52. Remember that must have same number left right parentheses. Otherwise ACTIVE-CAD will warn about error. After signal formula entry completed, press Assign Formula button shown Figure 1-20. Note that formula been transferred into Defined Assignments field. This formula instantly assigned signal line ACTIVE-CAD screen. Click Close exit window. assign formula selected signal waveform, click signal name shown Figure 1-14. selected signal name turns blue. Invoke Stimulator Selection window shown Figure 1-16 click Formula- associated lamp Formula field. also first click formula lamp Stimulator Selection window drag lamp over selected signal name Logic Simulator screen. There total formulas (F0.F15) provided with each ACTIVECAD simulator. However, request special option which provides signal formulas. When properly used, signal formulas generate test vectors faster than most powerful test vector editors.
Graphical Waveform Editor
Since ACTIVE-CAD real-time interactive simulator, perform on-line what-if analysis. Such analysis very useful because override input output with fifteen (15) logical states emulate desired signals these test points. example, emulate proposed FPGA changes forcing selected inputs outputs desired mentally computed logical states. monitoring their effects internal (chip) external (system) levels, know beforehand what proposed design changes will best ways force desired logical states graphical editor. allows tweak each signal with great precision force device pins fifteen (15) logical states. Resimulation comparison data with previous ones encourage discredit proposed design changes. either case, much
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Graphical Waveform Editor
closer problem solution, this reason dynamic what-if analysis most outstanding feature real-time simulators. invoke graphical test vector editor, select Edit option from Waveform menu shown Figure 1-21. response, ACTIVE-CAD displays buttons with different logical states (Figure 1-22). Note that mouse cursor also changes (Figure 1-23).
Figure 1-21. Waveform Menu.
Figure 1-23. Editing Cursor.
Figure 1-22. Logical States Waveform Editing.
List logical states
fifteen (15) buttons Figure 1-22 represent following signals:
strong logical level High strong High logical level Unkn_X strong Unknown logical level High_Z weak 3-state state that overridden weak signals Cnf_X indicates presence strong signals different logical values same node, e.g. High logical levels Res_L weak logical level Res_H weak High logical level Res_X weak Unknown logical level Ref_V special logic level signal, such used with devices High_V special high voltage level such used line drivers SV_L strong power supply signal which overrides other signal SV_H strong power supply signal which overrides other signals
Introduction
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SV_X indicates conflict between power signals same node Ua_L indicates signal undetermined strength Ua_H indicates High signal unknown strength
Follow these steps edit signal waveforms: Invoke waveform editor (Figure 1-22). Place cursor desired signal waveform location click mouse button. associated signal name turns green blue vertical cursor appears selected waveform location. Click desired logical state button shown Figure 1-22. Note that signal waveform changed state; this change taken place between last signal transition current blue cursor location. exit editor, click Cancel Edit Mode button Figure 1-22.
Note that edit signal waveforms, modified segments change green. Also, (Custom Signal) symbol been forced into Stimulator column indicate that displayed waveforms being forced device pins. symbol appears device output, need select Override mode clicking button shown Figure 1-16. Otherwise, device will control output signal, despite presence symbol. need more precise waveform editing than current time scale allows, place cursor over scale press mouse button. Note that blue stripe drawn drag cursor over area that want expand. When release mouse button, waveform expands over entire timing screen blue line disappears.
Applying Signal Waveforms
Read carefully following rules application external stimulus circuit designs. There only four rules that govern signal distribution node:
signal applied device input exists only that input
does spread through node other pin. example, apply signal U1A-2 (Figure 1-24), will only control that particular input will have effect U1B-4.
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Signal Waveforms Summary
apply signal device output pin, must asserted
with Overdrive Mode button Figure 1-16); Otherwise effect pins signal lines node. example, feeding signal into U1A-3 effect node unless this signal into Override Mode (see Keyboard KeysOverriding device output pins, this Chapter)
Figure 1-24. Applying Stimulators Circuits.
apply signal node node does have device output pins e.g. signal Figure 1-24), then will control pins entire node. However, apply signal node (e.g. VFRAME signal name Figure 1-24) which active device output, e.g. U3A-5, then will overridden that output. node names primarily connect wires between pages monitor what going node. However, apply stimulus signal node name only there output pins node.
apply signal input terminal, e.g. START, will control
entire node because there device output node. device output tri-stated, there conflict with signal applied terminal. However, device output totempole active 3-state, will conflict with terminal applied signal because terminal treated totem-pole signal source.
Signal Waveforms Summary
keyboard keys isolate design sections disconnect
feedbacks closely control problem areas. precision keyboard toggling limited length Short step, make small
binary counter outputs place clocks inputs multiplexers, decoders sections that operate symmetrical signal waveforms
Introduction
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formula signal waveforms semi-random asymmetrical signals, pulse bursts, etc.
Swap signal waveforms needed selecting appropriate buttons Stimulator window.
Start with keyboard keys progress more advanced
complex signal waveforms design becomes free basic problems.
signal waveforms saved test vectors. Save these test vectors, even sure their future need. Each test vector should have ample comments used what been tested with These comments written directly into each signal waveform.
Create extensive library test vectors design sections design functions; quality these libraries will help deal quickly with problems they will differentiate from your less experienced peers.
conserve disk space, save test vectors binary format.
ACTIVE-CAD always convert these files ASCII format when needed. Most important, before dive into more intricate simulation issues, practice four forms signal waveform editing least minutes. ACTIVE-CAD comes with some advanced test vector editors (External Test Vector Editor Test Vector Macro Editor) which should practice after have become experienced with signal waveform editors.
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Functional simulation mode
Analyzing Simulation Results
ACTIVE-CAD automatically checks every every device during each clock cycle timing violations conflicts. like having logic analyzer with thousands active signal channels. This logic analyzer also quite intelligent because knows what's right whet's wrong even have selected some signal lines display, ACTIVE-CAD will anyhow check them report problems. make design analysis most effective, should familiarize yourself with available options, ACTIVE-CAD comes with over forty (40) utilities that speed design analysis make your work easier. These utilities located within toolbox shown Figure 1-25 Patching, Options Utilities menus. Design analysis quick effective follow these simple rules:
your design analysis incrementally; never wait complete
design because size complexity overwhelm you.
First, verify functional design behavior. Next, using unit delay glitch simulator, check race conditions.
plan worst-case design analysis; write down
framework timing analysis.
Make sure that have accounted temperature, supply voltage loading effects.
Save design test vector files; ample comments your test
vectors.
Most important think your design schematic sheets;
Rather look through test vector files. should spend least much time design analysis creating schematics and/or VHDL design itself.
Functional simulation mode
Each design verification starts with functional behavior analysis. default, ACTIVE-CAD comes functional mode. However, some reason central button toolbox shown Figure Figure 1-25 does show (functional) mode, click till displays this symbol.
Analyzing Simulation Results
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Figure 1-25. Simulation toolbox.
power functional analysis mode lies accuracy simplicity visualization because directly shows cause effect relationship. example outputs gates lined with their inputs (Figure 1-26) flip-flop outputs lined with their rising falling clock edges (Figure 1-27). Such signal waveforms easy analyze, they allow quickly verify functional behavior your design.
NAND
Figure 1-26. Functional Gate Simulation.
Qn-1
Figure 1-27. Functional Flip-Flop Simulation.
Even circuit designing seems simple enough skip functional simulation mode, take risk. would surprised many details escape your attention even simplest designs. Once have confirmed functional design, will able proceed other design phases with greater confidence.
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Functional simulation mode
Figure 1-28 shows typical waveforms circuit shown Figure 1-6. Note OUT1 signal, which produced flip-flop, aligned with input clock CLK. similar alignment present between counter output input signal. Expanding scale: alignment between signals obscured display scale resolution, place cursor over scale, press mouse button, drag over area that want expand then release. drag mouse cursor, blue stripe appears marking area selected scale expansion. Upon release mouse button marked area will expanded cover entire screen.
Figure 1-28. Functional Circuit Simulation.
Another expand contract display scale click scale adjustment buttons shown Figure 1-29. Clicking Lower Scale Resolution button lowers scale resolution, e.g. from ns/DIV ns/DIV. Clicking Expanding Scale Resolution button will increase scale resolution, e.g. from ns/DIV ns/DIV.
Ruler display enable Zoom (LSR) waveforms button Zoom (ESR) waveforms button
Figure 1-29. Simulation scale adjustment buttons.
NOTE: functional simulation produces outputs with cause, switch GLITCH simulation mode viewing race conditions.
Analyzing Simulation Results
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Most functional simulators simulate combinatorial sequential devices with zero propagation delays result they cannot warn about race conditions. Other functional simulators like SUSIE SUSIE calculated functional circuit behavior based unit propagation delays displayed output data circuits zero propagation delays. This method several advantages because allowed capture race conditions functional mode. However, output test vector files were compatible with data from other simulators. generate test vector outputs that compatible with other simulators, current release ACTIVE-CAD assigns zero propagation delay combinatorial logic (gates, multiplexers, decoders, etc.) unit propagation delay sequential logical devices such flip-flops, registers counters. these sequential logical devices have feedbacks through combinatorial logic, they show output transitions that unexplainable pure functional analysis. This rare case, should happen, switch simulator GLITCH mode, which will display detail effects unit propagation delays.
Glitch Simulation Mode
When functional simulator produces output signal waveforms apparent reason, need painstakingly analyze circuit race conditions slower more complex timing simulator find reason unusual circuit behavior. Since glitch simulators display details that hidden functional mode, they excellent analysis tools unknown circuit behavior. assigning displaying unit propagation delays components signal paths, these simulators automatically display signal spikes that cause unusual circuit behavior. select GLITCH mode, click MODE button shown Figure 1-25 till displays letters. Simulate design with same test vectors that have used functional simulation. proper glitch mode follows:
Simulate your design functional mode find unexplained circuit behavior, switch simulator
GLITCH mode
Load test vectors that have used functional simulation Simulate again check race conditions
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Glitch Simulation Mode
don't need GLITCH mode outputs generated functional simulator look OKay. GLITCH mode should used only quick localized spike display. example, simulate functional circuit with 1,000 10,000 test vectors, would GLITCH mode only with test vectors, just enough gain good understanding some unexpected outputs generated spikes selected signal lines. best results, rescale signal waveforms achieve display similar functional mode. Next, compare sequential device outputs with corresponding waveforms generated functional simulation. outputs have states which have been seen functional mode, design race condition. However, logical states have been detected sequential device outputs, there circuit race condition. times some spikes signal lines that result propagation delays. However, they don't trigger sequential circuits they harmless ignored, unless cross-talk other effects must considered.
Example
Load TEST_C netlist file, which ALDEC format. schematic from which this netlist generated shown shown Figure Figure 1-30. Next, load signals stimulators shown Figure 1-31.
Figure 1-30. Assignment Stimulators Input Pins.
Toggle INIT input signal line toggling keyboard clicking STEP button. This resets flip-flop shown Figure 1-30. Next, INIT signal High, simulator functional mode click LONG step button times. Note that
Analyzing Simulation Results
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output signal U3A.Q1-5 being high without rising clock edge U3A.CLK1-3 input. investigate U3A.Q1-5 output changes without clock edge, lets switch GLITCH mode clicking MODE button shown Figure 1-25. Next, click LONG step button eight times watch what happens U3A.CLK1-3 signal line when U3A.Q1-5 changing logical High. shown shown Figure Figure 1-31, there small spike clock line. This signal spike result signal line propagating though different propagation channels (U1A-U1C U1B) input gate. putting additional probes these channels, view them greater detail.
Figure 1-31. Display Glitches Clock Pin.
Timing Simulation Mode
have confidence design, must simulated timing mode. select TIMING mode, click MODE button shown Figure 1-25 till displays letters. Generally, should first simulate design with same test vectors that have used functional simulation. This will give instant confirmation that previously simulated design will also pass timing criteria. make sure that design error goes undetected, ACTIVE-CAD checks every device model during each clock cycle. models tested both timing violations conflicts. ACTIVE-CAD checks following timing violations:
Setup hold times Clock High clock restrictions Pulse width reset, preset, etc. Clock edge reset pulse
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Timing Simulation Mode
Reset pulse preset pulse
ACTIVE-CAD libraries have been written VHDL Shorthand, which easy-to-use VHDL subset. models have timing information simulator functional, glitch unit delay modes, then models will analyzed timing performance.
Example
become more familiar with timing simulation process available options, load TEST_A netlist, which been generated from schematic shown Figure Figure 1-6. Select signal names listed shown Figure Figure 1-32 assign them stimulators listed same figure.
Figure 1-32. Timing Mode Circuit Analysis.
better understand timing simulation mode, follow these steps part Example Select functional (FN) simulation mode. keyboard-driven stimulators logical level perform single simulation step clicking STEP button. Toggle stimulators High logical state that flip-flop counter operate properly. Click LONG simulation step button within toolbox. Note that functional simulation proceeds without problems. Click MODE button toolbox switch simulator (timing) simulation mode. Click STEP button. Note that ACTIVE-CAD displays several timing violations warnings. Click several times button within error message window familiarize yourself with error messages. Click Cancel button error message display.
Analyzing Simulation Results
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from error messages, flip-flop some timing problems. Fortunately, ACTIVE-CAD real-time interactive simulator instantly replace parts with faster ones eliminate timing problem that exist: Click Patching menu select Change Technology. response, ACTIVE-CAD displays Figure 1-33.
Double-click U2-74LS74A Chip Selection field. Technology Selection window appears (Figure 1-34) lists replacement parts 74LS74A. Select faster part, e.g. 74F74. Click STEP button notice that timing violations related U2(74LS74A) device have disappeared.
Figure 1-33. Change Technology Window.
Figure 1-34. Device Replacement Window.
ACTIVE-CAD many additional features that will design analysis. Most these features located Options, Patching Utilities menus toolbox. learn about them reading appropriate chapters this Guide.
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Unit Delay Simulation Mode
Unit Delay Simulation Mode
Unit delay simulation mode simulation mode with propagation delays current simulation resolution. functionality similar Glitch mode, timings with more proportional time scale produced.
Quick Application Notes
Deleting empty rows between signals
delete empty rows, click turn
Signal menu Delete option Empty Rows
empty rows instantly deleted. Delete menu shown shown Figure Figure 1-35.
Figure 1-35. Signal Delete Menu.
work effectively with buses
most cases, ACTIVE-CAD does automatically create buses from netlist information. Unless netlist been generated ACTIVECAD schematic editor, need create these buses simulator editor. This editor gives freedom define redefine buses simulation progresses.
Creating
create bus, follow this procedure:
Quick Application Notes
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Arrange signal names ascending descending order, e.g.
DATA0, DATA1, DATA2, etc. other signal names present between these signal names.
Click top-most signal name. Press [Shift] click last member bus. Note
that signals between first last selected signal line turned blue.
Click option within Signal Menu. When window
shown Figure 1-35 appears, click Create.
response, simulator activates button. When this button activated, signals converted into single line.
Toggle button notice that first signal group
marked with asterisk (*), indicating name bus. other signals marked with plus sign.
Figure 1-36. Menu.
display control
show single line composition discrete signal lines. switch between these modes display, click button.
Selecting display format
Buses displayed binary, octal, decimal hexadecimal formats. define redefine display format time during simulation. select appropriate format follow this procedure:
Click selected Select from Figure 1-36 appropriate format
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Tracing design connectivity
Note that ACTIVE-CAD instantly converts existing buses desired format.
Naming renaming BUSES
name automatically assigned ACTIVE-CAD when create bus. derived from first signal name bus. However, change name using following procedure:
Click selected name Select Name option from window shown Figure 1-36 When Name window appears (Figure 1-37), enter
name click button
Figure 1-37. Name Window.
Tracing design connectivity
ACTIVE-CAD simulator allows trace signal connectivity throughout hierarchical levels. This particularly useful don't have latest schematics, designs that difficult work with schematic sheets. trace device signal name connectivity, follow these steps: Click selected device signal name, e.g. signal shown Figure Figure 1-32. When selected item turns blue, click Connections option Signal menu. Figure 1-38 displays connections selected item. Double-clicking pins listed shown Figure Figure (node listing) will display pins selected device. Double-clicking device pins will display signal node associated with selected pin.
Quick Application Notes
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This operation allows trace signal distribution verify schematic-netlist compatibility.
Figure 1-38. Signal Connectivity Table.
access window shown Figure 1-38 clicking signal selection button Waveform Viewer toolbar selecting signal from Figure then clicking RIGHT mouse button. ACTIVECAD will display window shown Figure 1-39. click View Connections option, ACTIVE-CAD will display window similar Figure 1-38. search signal line connections identical described above reference Figure 1-38.
Figure 1-39. Viewing Connectivity.
Searching signal names, components device pins
find signal names, devices device pins ACTIVE-CAD simulator listings clicking RIGHT mouse button fields shown Figure Figure 1-8. response, ACTIVE-CAD will display Figure 1-39. clicked Pins field, clicking Search for. option will display Figure 1-40. clicked Signal Selection field, clicking this option will display Figure 1-41. search signal name locations following:
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Searching signal names, components device pins
Enter signal name shown Figure 1-40 1-41 Click Select button
ACTIVE-CAD instantly highlights selected component signal name listing. using schematic editors that have direct coupling with ACTIVE-CAD through DDE, protocols, then selected test points will also marked schematic.
Figure 1-40. Search Window.
Figure 1-41. Search Signal Window.
Locating simulator data schematic sheets
trace location devices, pins, signal names macros schematic sheets directly from ACTIVE-CAD simulator. Also data selected schematic editor displayed ACTIVE-CAD simulator. This cross-probing requires that schematics have tight coupling with ACTIVE-CAD simulator. SUSIE-CAD, ACTIVE-CAD, DIGILAB, similar schematics have such interfaces. Cross-probing between simulator schematic designs greatly improves design comprehension speeds analysis. schematic editor vendors about their direct links with ACTIVE-CAD simulator.
Locating components schematics
locate component schematic sheet, click designation Chip Selection window Figure 1-8. Next, click RIGHT mouse button over Chip Selection window display local menu. Select from that local menu Find option. instantly switches display appropriate schematic sheet shows selected component location with around component
Quick Application Notes
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Locating device pins schematics
locate component schematic sheet, click designation Pins window Figure 1-8. Next, click RIGHT mouse button over Pins window display local menu (Figure 1-39). Select from that local menu Find option. instantly switches display appropriate schematic sheet shows selected component location with blob.
Locating signals schematics
locate signal schematic sheet, click designation Signals Selection window Figure 1-8. Next, click RIGHT mouse button over Signals Selection window display local menu, which similar Figure 1-39. Select from that local menu Find option. instantly switches display appropriate schematic sheet shows selected signal turning red.
Applying signal waveforms screen location
Most simulators require apply test vectors time beginning simulation. However, since ACTIVE-CAD real-time interactive simulator, apply your signals time screen location during simulation. process using formulabased signal waveforms comprised steps:
Creating editing formula-based signal waveforms Assigning signal waveforms selected screen locations
Creating formula-based signal waveforms
access formula editor, select sequence Waveform menu then Formula option. response, ACTIVE-CAD displays shown Figure 1-42 Formula options submenu. NOTE: Formula Editor described reference Figure 1-20 generates signals that start time waveform formula described here applies formulas signal waveforms desired time select Edit option, ACTIVE-CAD displays Figure 1-43 which allows enter signal waveform formula. This editor works similarly described Formula Stimulators, except:
does assign names generated signal waveforms
they cannot automatically assigned signal names. Instead, they have manually inserted into on-screen waveforms.
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Applying signal waveforms screen location
Since these waveforms screen location, they basic tool dynamic what-if analysis, which segments waveforms modified resimulated test design modification concepts.
Figure 1-42. Formula Menu.
Figure 1-43. Formula Signal Editor.
editor shown Figure 1-43 allows quick efficient development signal waveforms shape duration. They used non-repetitive functions bursts pulses duration with various logical states. formula stimulators give total freedom define redefine signal waveforms while simulation progress. process defining formula comprised
parentheses (used nested expressions) logical state symbols: H,L,Z,X hexadecimal values; e.g. [1FA5], [3C8], etc.
Quick Application Notes
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durations signal states (e.g. 12.31 nanoseconds) number repetitions signals listed parentheses
Example
Type into Enter Formula (Bus Signal) field shown Figure 1-43: (H2L3)4 High repeat times Next, click button. formula automatically added Available Formulas window will available editing signal waveforms. above formula will result following waveform: This segment added screen location many times needed. NOTE: There limit nesting signals their duration.
Example
Enter into Enter Formula (Bus Signal) field: ([3FC5]25.2[053A]33.4)25 This formula will generate 16-bit signal. first segment hexadecimal value 3FC5 lasts 25.2 nanoseconds. second segment hexadecimal value 053A lasts 33.4 nanoseconds. Both segments will repeated times. There limit nesting depth statements duration signal segments. must, however, always include brackets list duration each segment. segments formula must have same number hexadecimal characters (the same number lines). example, cannot 16-bit buses, e.g. formula ([3FC5]25.2[53A]33.4)2 incorrect because widths parenthesis different. create save tens formulas with ACTIVE-CAD. they overfill Available Formulas window shown Figure 1-43, window will change will able scroll contents with arrow buttons.
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Simulation precision
Applying formula-based signal waveforms
apply formula-based signal waveform: First, click screen location where want apply selected signal waveform. blue cursor will appear that location associated green cursor will highlight selected signal name. Next, select either Replace Insert option from window shown Figure 1-42. Replace option will allow override existing signal waveforms with ones. Insert option inserts applied signal waveform selected screen location shifts existing waveforms right. Click selected signal formula Available Formulas window shown Figures 1-42 then click button. selected signal waveform will instantly placed selected screen location. formulas created Figure 1-20 those created Figure 1-43 different. formula editor Figure 1-20 assigns concrete names each formula, forming independent signal waveform entities. These formulas assigned clicking directly signal names. Since formulas from Figure 1-20 always calculate logical states from time beginning simulation, independent when they used simulation process, they always produce same logical states some future time formulas Figure 1-43 have names, thus only concrete screen locations. Also, they cannot edited thereafter because they automatically integrated with existing signal waveforms, would say, they disappear crowd other waveforms.
Simulation precision
timing simulators operate with certain precision. This precision resolution fixed most simulators typically either picoseconds nanosecond. simulation time generally limited milliseconds picoseconds resolution second nanosecond resolution. hundred milliseconds life device long time. device process immense amount data. However, industrial controller complete that time only operations. working with devices that operate with microsecond speeds, much simulated with simulators that have such high resolution.
Quick Application Notes
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accommodate broad range electronic devices circuits with vastly different timing characteristics, ACTIVE-CAD variable simulation precision ranging from picoseconds millisecond. This means that simulate from milliseconds over hour device operation time. This broad time range allows simulate both high speed gallium arsenide circuits slow industrial controllers. simulation precision, select sequence: Options menu (Figure 1-45) Simulation Precision option desired simulation precision from Select Precision Simulation window shown Figure Figure 1-44.
Figure 1-44. Selecting Simulation Precision.
Upon rescaling simulation precision, ACTIVE-CAD moves cursor time cannot same simulation run) timing waveforms with different resolutions.
Simulation time estimate
Sometimes simulation take longer than expected. want warned beforehand about long simulations, select Options menu (Figure 1-45), then click Step Estimation option. Each time simulation step takes longer than seconds, ACTIVECAD will display window with time needed complete current simulation run. This window, shown shown Figure Figure
1-44
Automatic backup simulation results
1-46, counts down simulation time that know much longer simulation will take.
Figure 1-45. Options Menu.
Figure 1-46. Time Complete Simulation Window.
Automatic backup simulation results
protect yourself from loosing valuable simulation data, automatic data backup option selecting Timing Automatic Backup option from Options menu shown Figure Figure 1-45. response, ACTIVE-CAD displays screen shown Figure 1-47 which allows enter time intervals which automatic backup should take place. working interactive mode, that backup between minutes. working batch mode with long test vectors, backup half hour intervals.
Quick Application Notes
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Figure 1-47. Timing Backup Option.
Global design reset
Global Reset option Options menu allows reset devices their initial state without returning time This means that reset design time continue simulation, starting with test vectors that existed time
Design Error Handling
Error reporting
dynamically select which design errors should reported stored, eliminating errors that obscure your current analysis. error reporting procedure, select Error Reporting. option from Figure 1-45. response, ACTIVE-CAD displays table shown Figure 1-48. Toggle boxes indicate which errors want reported. must Work Mode Otherwise, error reports will disabled. However, error markings signal waveforms will continue appear irrespective these settings.
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Design Error Handling
Figure 1-48. Error Reporting Window.
Error Classes:
Timing Violation; reports timing violations related setup
hold times, clock widths, pulse widths, relationships between clock reset preset, etc. only select deselect errors. cannot select only some types timing violations.
conflict; reports violations involving conflicting logical
states signal nodes
Model Dependent; each model embedded error messages. certain conditions proper model operation met, e.g. setup time, appropriate model-embedded message will displayed.
File R/W; monitors reports hard disk Read/Write errors Design Netlist; lists errors detected during netlist import
Error handling
Display; displays detailed error message window. error
markings signal waveforms always present, independent whether have selected this feature.
Register; saves selected errors into Message future reference
Report; enters selected errors into simulation error report
which enabled from Error Viewer option Utilities menu
Correcting design timing errors
design have timing errors related device input signal violations (e.g. setup hold times) ones related layout delays. could some cases substitute faster part correct both device timing viola-
Quick Application Notes
1-47
tions layout delay problems. However, general rule high performance circuit designs, need analyze these errors separately then make decision problem should handled. have found timing violation that related devices, resolve problem analyzing:
Propagation paths failing device inputs Layout delays Device timing characteristics
Since ACTIVE-CAD timing violation reports indicate severe problem very outset determine problem curable device (technology) replacement, architectural design change layout modifications.
Checking worst-case test condition
There reason correct design that been tested over full range loading, temperature, voltage, device propagation other circuit constraints. need analyze data paths them worst case conditions. example, testing worst-case setup time condition (Figure 1-49), should devices their maximum propagation delays devices their minimum propagation delays. Similarly, testing worst-case hold time conditions, should minimum propagation delays maximum propagation delays. gates located same silicon device both channels, their minimum maximum timing parameters will identical. These gates will equally effect both signal channels their actual value will have effect setup hold times. Since 7400 type gates since 7400 four such gates single package, should gates both signal channels minimize effect device timing parameters.
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Design Error Handling
Figure 1-49. TEST_D Worst-Case Timing Analysis.
Example
This analysis worst-case setup time. have used same device package (e.g. U1B), need analyze propagation delay effects these gates. propagation delay value will produce same effect both input signal paths, thus compensating each other. (74LS10) maximum propagation delays, select Editing Timing Specification. from Patching menu. When Figure 1-50 appears, double-click device. response, ACTIVE-CAD displays gate timing parameters Figure 1-51. Click button note that delay values column, which used ACTIVECAD simulator, maximum propagation delays. Click button exit this window.
Figure 1-50. Selecting Device Editing.
Quick Application Notes
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Figure 1-51. Timing Parameters 74LS10.
Since worst-case setup time requires setting minimum propagation delay values, double-click device Figure 1-50, then click button shown Figure Figure 1-51. Return back ACTIVE-CAD simulator simulate design. design shown Figure Figure 1-49 does show hold time violations, hold time violations will appear either. Each setup propagation delays which caused design failure should saved future reference. need accumulate design problems before take action.
Analyzing ASICs setup hold times
analyzing ASIC design, have each cell minimum maximum value because cells behave just like gates shown Figure 1-49. They track each others propagation delays automatically their minimum maximum propagation values will have same overall effect circuit behavior. only test need perform entire design minimum maximum propagation delay values. entire design design macro specific propagation delays, follow below procedure global propagation delay setups.
Global design propagation delays setups
entire design sections selected propagation delay. This very useful when working with ASICs because with click mouse button, entire design rescaled desired propagation. change design delays global manner, double-click ROOT macro Scan Hierarchy field window shown Figure 150. response, ACTIVE-CAD displays Figure 1-52 which allows propagation delay selected design section
1-50
Design Error Handling
Minimum Maximum Average maximum value
Figure 1-52. Scan Hierarchy Global
value used rescale propagation delays temperature voltage. loading effects calculated ACTIVECAD they provided ASIC manufacturers through post-layout netlists devices. select Level option shown Figure 1-52, only cells devices that hierarchical level will affected. macros that level will affected they will retain their original settings. Selecting Branch option will effect components, including macros selected level.
Device related timing violations
want check faster part would cure problem, select Change Technology from Patching menu. response, ACTIVECAD displays Figure 1-53. Double-click selected device Chip Selection field. When window Figure 1-54 appears, select appropriate part click button. part instantly replaced simulator executable tables back schematic editor directly connected through DDE, protocols. continue simulation, will notice that device taken control timing display shows different timing performance.
Quick Application Notes
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Figure 1-53. Selecting part replacement.
Figure 1-54. Replacing part.
Analyzing line delays
Line delays have considerable effect high speed designs. analyze their effect, select Change Line Delays option from Patching menu. response, ACTIVE-CAD displays Scan Hierarchy window. Double-click selected hierarchy level line (layout) delays. there delays, ACTIVE-CAD will display table with delay values. edit these values emulate layouts. example, analyzing actual layout proposed changes, estimate propagation delay. verify possible side effects these changes, enter expected line delay values line delays table simulate changes. Only ACTIVE-CAD confirms proper design operation should implement proposed changes.
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Simulating Very Large Designs
Simulating Very Large Designs
ACTIVE-CAD does care your design load simulate practically design size your computer enough RAM. example, some users have reported that they have simulated designs excess 300,000 gates using just Mbytes RAM. However, efficient simulation, need least Mbytes basic software (Windows, ACTIVE-CAD simulator, libraries models symbols, etc.), plus Mbyte each 6,000 10,000 gates your design. exact amount required depends upon design topology. commercial simulators simulate entire netlist, which causes large designs simulate very slowly. design enough, slow simulation process point where becomes impractical effectively. simulation speed main constraint simulated design size. speed simulation process, hardware accelerators were touted late 80s. However, while they some application ASIC designs, they completely failed system level where some device models were missing were available format required hardware accelerators. method dealing with large designs selective simulation incremental design process (read Introduction Simulation Virtual Hardware, issued ALDEC, Inc.). selective simulation process allows simulate only desired design sections, down lowest hierarchical component level. select deselect design section while simulation progress decreasing size simulated section,you increase simulation speed. Since simulation speed proportional size simulated circuit, effectively simulate selected design sections independently large overall design patented selective simulation process available with SUSIE ACTIVE-CAD products only.
Selective design simulation option
Load netlist TEST_H (provided with your software), click Selective Simulation option Options menu. response, ACTIVECAD displays window shown Figure 1-55. Scan Hierarchy window shows hierarchical design structure, Chip Selection window lists devices macros selected hierarchical level.
Quick Application Notes
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Clicking hierarchical level Scan Hierarchy window displays Chip Selection window macros devices that hierarchical level. clicking these devices macros enable disable them from simulation. Disabling device sets output pins high-impedance logical state. override these pins with desired signal waveforms emulate operation disabled design sections. enabled chips macros dark. disabled ones white. selections instantly affecting simulation process.
Figure 1-55. Selective Simulation window.
Example
Load Test_H netlist copy simulators Signal field input output pins gate U1A, located hierarchical level. Assign these input pins stimulators shown Figure 1-56. Simulate LONG step. Next, select Selective Simulation from Options menu when window Figure 1-55 appears, click device Chip Selection field disable When device body shown Figure Figure 1-55 turns white, indicating disabled device, close window simulate another LONG step. Note that U1.Y13 output floating. After both LONG steps your display should look like shown Figure 1-57.
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Resetting Design
Figure 1-56. Simulation gate U1A.
deactivated device output
Figure 1-57. Activated Deactivated Gate Simulation
additional exercise, select gate from lowest hierarchical level TEST_H netlist (gate within macro which located within macro), then simulate this gate
enabling disabling gate directly enabling disabling macro that includes gate enabling disabling macro that includes above mentioned macro Note that when enable disable macros same effect when directly enable disable gate. selective simulation option allows select simulate combination macros devices from hierarchical level.
Resetting Design
Resetting presetting design desired logical state most complex operation simulation process because involves special features both simulator models.
Quick Application Notes
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Netlist Loaded
Power button
internal Power signal ACTIVE.
Execute Power models
7474.HDL Power Unkn_X;
7400.HDL Power High;
Simulate netlist
circuit stable?
outputs High Power settings specified
Execute Selective Preset specified Power settings
Figure 1-58. Power Process Flowchart.
design resetting process shown Figure 1-58. comprised
Executing Power-on instructions models simulating design
Asserting Power-on Settings device outputs Executing Preset operation, specified Power-on Settings
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Power-On model instructions
Power-On model instructions
Activating Power-on button simulation toolbox forces models execute their internal power-on instructions. Some models like combinatorial gates, decoders, etc., have Power Global Reset instructions. Typically, devices X-Unknown signal state, except Altera parts which logical zero. After models preset their power-on states, ACTIVE-CAD simulates design till stable state achieved. there more than 10,000 oscillations, ACTIVE-CAD declares unstable design condition displays error message.
Power-on Settings
After design achieved steady-state, ACTIVE-CAD executes Power-on Settings. These settings factory-provided default Power-on parameters. change them your requirements, however, parameters will affect only current simulation. Each time start ACTIVE-CAD, power-on parameters will automatically revert default factory settings. change view power setting Power_On Setting window (Figure 1-59) which displayed clicking Power Settings option within Options menu.
Figure 1-59. Power Settings Window.
default power-on settings follows:
models unknown state newly generated outputs override ones
Quick Application Notes
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comments measurements deleted Execute Preset activated
selecting appropriate options shown Figure Figure 1-59 change above settings. must, however, remember that logical levels applied power-on settings device pins remain these pins till they overridden first signal transitions generated these pins simulator. This times produce visually wrong logical levels gate outputs that have post-power-on signal transitions.
Preset
Execute Preset option Power_On Setting window (Figure 159) been selected, then will executed immediately after power-on settings have been completed. However, must select preset conditions (see Presetting design desired state section this Chapter) load preset file before clicking Power-on button. preset conditions have been ACTIVE-CAD, then preset conditions will executed during power-on procedure. NOTE: Since Power-on, Power-on Settings Preset output conflicting states, need carefully review each effect achieve desired power operation. simplify design analysis Power-on Settings Preset very sparingly.
Global Reset
ACTIVE-CAD allows have resets each model, power-on setting special logical level device output(s). example, Power-on Reset output pins unknown state Global Reset these outputs logical level. Global Reset executed selecting Global Reset option within Options menu. models which this reset instruction implemented within source code will respond this operation. Models without Global Reset instructions will ignore this command. NOTE: Most ACTIVE-CAD models, except some FPGA libraries (Actel, Xilinx) currently have Global Reset implemented.
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Setting simulation reference points (Milestones)
Setting simulation reference points (Milestones)
save memory, simulators save simulation data only those test points that displayed screen. logical states other test points which listed simulator Waveform Viewer stored memory only duration current simulation cycle overridden with next cycles data. compensate this complete loss data, ACTIVE-CAD milestones option which allows return selected simulation cycle entire design exact design conditions that existed that time. This option several major advantages over batch-mode simulators:
Rather than being forced start simulation from time
restart simulation from past simulation cycle
ACTIVE-CAD allows test points screen, starting from past simulation cycle
change design past simulation cycle, which
marked Milestone, view improvements
ACTIVE-CAD lets change test vectors past simulation cycle force system behavior
resimulate design from cycle just prior error
milestones option saves time because longer forced resimulate design from time Instead, marked simulation cycle (Milestone) starting point. There three mechanisms creating milestones:
automatic (periodical) manual breakpoint-driven
Automatic Milestones
some milestones along simulation highway, click Milestones option within Options menu. response, ACTIVE-CAD displays Milestones window shown Figure 1-60 which allows select number milestones placed screen time interval between them. Enter separation between milestones into Period window. specify time unit, will nanoseconds default. Since automatic milestones fill entire hard disk less than hour, ACTIVE-CAD built self protection mechanism which asks
Quick Application Notes
1-59
many milestones should saved. specify eight (8), then maximum eight milestones will saved milestone will overwrite first one. This provides shifting window milestones that tracks simulation process allows return selected milestone within that area.
Figure 1-60. Milestones Selection Window.
After have selected number milestones saved their time interval, need activate milestones setting option (Figure 1-60). Otherwise, milestones option will inactive.
Manual Milestones
greater convenience, ACTIVE-CAD allows manually simulation cycle (design condition) milestone. click Save button shown Figure 1-60, ACTIVE-CAD will save current simulation status reference point will always able return during simulation process. ACTIVE-CAD allows have unlimited number such manual milestones. return simulator past simulation cycles, represented milestones, select Milestones window shown Figure Figure 1-60, click desired milestone Active Milestones field then activate Load button. Confirm your selection clicking Close button. ACTIVE-CAD instantly sets entire design test vectors appropriate logical states then positions cursor desired (milestone) screen location.
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Runninglong simulations
Figure 1-61 shows waveform diagram device U1.A1-1 with additional simulation reruns (for same pin), both starting milestone. These reruns show different waveform patterns right milestone line, which caused applying test vectors performing design changes. This simulation flexibility from past cycle unique feature real-time simulators such ACTIVE-CAD, allows direct tweaking design behavior real time.
Breakpoint-driven Milestones
milestone breakpoint condition. Such milestones described Breakpoints chapter.
resimulating from milestone
Figure 1-61. Multiple Simulations from Selected Cycle
Milestones allow quickly verify various design concepts incremental fashion, without lengthy setups compilations. Effective milestones cornerstone real-time interactive simulation help your productivity, ALDEC included this feature even lowest cost software versions.
Runninglong simulations
need long design simulation, e.g. five hours, should click Simulation Stop option within Options menu. response, ACTIVE-CAD will display Start Long Simulation window (Figure 1-62). Enter into Simulation Running Time field long, hours, minutes seconds, will simulation. enter this data directly place cursor appropriate field up-down arrows desired simulation time values. activate long simulations timer, select Sim. Till option then click Start button. recommended that Stop But-
Quick Application Notes
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activated well, that interrupt simulation when needed. only time would probably want disable Stop Button when leaving office want anybody interfere with simulation process.
Figure 1-62. Long Simulation Setup Window.
Overcoming 4,000 test vectors limit
test vector vertical time slice waveform screen display with some signal transitions. Each test vector must have least signal transition. However, typical test vectors will have multiple simultaneous signal transitions, also called events. SUSIE-CAD products limited maximum 4,000 test vectors. can, however, simulate number test vectors follow this simple procedure:
have reached 2,000 test vector limit, save existing simulation results using Save Test Vectors option File menu
Click
Waveform Delete button delete waveforms from screen keys formulas test vector generation, need setups
Reload test vectors; using binary counter, keyboard Since deleting signal waveforms leaves design logical states
generated last simulation cycle, continue simulation activating Step Long (Step) buttons NOTE: When simulating design test vector segments, activate Power-on button, because will delete last simulation cycle data.
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simulate large memory devices
simulate large memory devices
fully simulate large memory chips, would need very expensive workstations, with memory. Fortunately, most designs verified simulating only first last Kbytes code. this done specify much memory should simulated, select Memory Range option from Options menu. When ACTIVE-CAD displays setup window shown Figure 1-63, enter into Lower Address Upper Address desired address space (number bytes). select value from pull down list type specific address range. default address space 1024 bytes, both lower upper limit. want simulate other memory ranges, need enter values before starting simulation process.
Figure 1-63. Selecting Memory Range Simulation.
NOTE: memory range that Memory Range option applied memory devices entire design, including internal microcontroller RAM.
search selected signal conditions
times need find certain signal conditions design. ACTIVE-CAD comes with option which facilitates such search both forwards backwards. time during simulation will instantly display conditions past test vectors (signal waveforms).
Quick Application Notes
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column
Figure 1-64. Column Location
select option, click View option Utilities menu. When View menu appears, click option. response, ACTIVE-CAD displays column, shown shown Figure 1-64. This column used entering signal conditions. ACTIVE-CAD searches logical listed signal conditions.
Creating conditions
enter signal conditions looking for, select Condition option from Options menu. response, ACTIVE-CAD displays table available signal logical states (Figure 1-65). Click signal name Signal field Figure 1-64 when turns blue, click desired logical state table Figure 1-65. Note that ACTIVE-CAD entered selected signal state column. Select some additional signal conditions want include search operation. least signals must transition(e.g. HIGH) ACTIVE-CAD will search condition signal states.
1-64
search selected signal conditions
Figure 1-65. Logical States Table
option allows search signal transitions. signal transition, select signal name Signal field. When turns blue, click first signal logical level table Figure 1-65. Next, click second signal logical state, that taking place after signal transition. response, field shown Figure Figure 1-63 will display signal transition selected signal line signal name will deselected (turned blue). bus, first select then enter desired state State window shown Figure Figure 1-65. Next, click blue button. delete signal condition within Tag, click associated signal name after turns blue, click button shown Figure Figure 1-65.
Searching tags
ACTIVE-CAD allows search conditions both left right directions. select search mode, click Search button shown Figure 1-25 till displays mode (Figure 1-66). Next, click left right pointing arrows left right button. Note that blue vertical cursor moves next condition selected direction.
Quick Application Notes
1-65
Figure 1-66. Simulator's Search buttons.
Stopping long simulations
Since ACTIVE-CAD releases mouse cursor when simulation progress, click STOP button simulators main toolbox terminate simulation. When simulation stops design retains last logical states that have been generated simulation process. STOP button terminates simulation process independently started, either with Step buttons Start Long Simulation option Options menu). NOTE: Stop button activated time unless disabled Start Long Simulation window, activated Simulation Stop option Options menu.
Manipulating switches
ACTIVE-CAD allows manipulate switches move jumpers while simulation progress. Since switch position takes instant effect, ACTIVE-CAD operates like real hardware breadboard. operate switch, draw schematic with switch select Switch Settings option from Patching menu. ACTIVE-CAD displays Switch Settings window which shows design hierarchy Scan Hierarchy window lists switches jumpers selected hierarchical level Chip Selection window. manipulate switch located selected hierarchical level, select that hierarchical level from Scan Hierarchy window then doubleclick desired switch Chip Selection window. ACTIVE-CAD instantly displays additional window with current switch position. Each click mouse cursor over switch outline will toggle, rotate move mechanical wiper position. switch position instant effect design behavior. After setting switch desired position, close setup window clicking Close button.
1-66
Simulating line (layout) delays
Simulating line (layout) delays
ACTIVE-CAD simulate line layout delays. Normally, these delays calculated layout tools into ACTIVE-CAD netlist.
Figure 1-67. Modifying Line Delays.
view line delays ACTIVE-CAD only when netlist includes such routing delays. line delays assigned device pins viewed edited real time selecting Change Line Delays option from Patching menu. ACTIVE-CAD responds with Figure 1-67 which lists design hierarchy. Double-clicking chip, cell macro hierarchical diagram Figure 1-67 displays layout propagation delays associated with selected item (Figure 168). Note that same have different layout delay values.
Quick Application Notes
1-67
Figure 1-68. Layout Propagation Delays Table.
Clicking Min, Avg. transfers values displayed these columns column which represents simulated values. directly edit delay values column. entering value into rescale propagation delay reference maximum parameters, listed column. NOTE: must click button shown Figure Figure 1-68 enforce line delay modifications.
Emulating layout changes
Before layout changes, should verify what effect they will have other cells devices. have general idea layout changes will effect layout delays, then enter expected delay values directly into column. design failing because timing problems, emulate proposed layout modifications they would cure problems. have good grasp physical limitations within your design, emulate various layouts entering them directly into column. Since editing timing table much quicker than modifying actual chip board layout, save time verifying proposed layout changes with real-time emulation process.
Presetting design desired state
ACTIVE-CAD allows design logical state, including forced signal transitions. must, however, remember that these set-
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Presetting design desired state
tings forced directly output signal lines they will overridden with devices actual output value after first (simulation) transition within device.
Manual design preset
preset signal lines desired signal logical states, click Selective Preset option within Utilities menu. ACTIVE-CAD responds with window shown Figure 1-69, which initially does display signal names. select signals preset operation, click button, select desired pins signal names from ACTIVE-CAD window.
Signal Field
Preset Column
Figure 1-69. Preset Conditions Table.
After device pins signal names have been selected, click Edit button. table with signal logical states (Figure 1-70) displayed. Click selected signal line shown Figure Figure 1-69 then desired logical state shown Figure Figure 1-70. Note that selected signal line been assigned logical state preset column Figure 1-69. also drag selected logical state from table Figure 1-70 drop over desired signal name Figure 1-69. assign same signal level multiple signals, hold down [Ctrl] while selecting additional signal lines. Next, click desired logical signal state table Figure 1-70. selected signal lines will assigned same selected logical state. force signal transition pin, e.g. from High-to-Low, first select pre-transition preset state (e.g. High) then select post-transi-
Quick Application Notes
1-69
tion state (e.g. Low). response, ACTIVE-CAD will display preset column Figure 1-69 selected signal transition, e.g. High-to-Low.
Figure 1-70. Selecting states selective preset.
Automatic preset from file
preset entire design selected signal conditions with click mouse (ACTIVE-CAD only). That preset performed time during simulation. file preset option, need prepare advance some preset files, described reference Figure 169, save these preset files clicking Save button shown Figure Figure 1-69. Next:
load selected preset file clicking Load button click Execute button activate presets click short Step Long step button simulate preset conditions
Passive components digital designs
Resistors always lower signal strength. example, test point Figure 1-71 strong signal. However, test point (other resistor), signal weak. Thus, several totem-pole outputs connected together resistors into single node. Also, totem-pole output connected through resistor supply voltage without creating conflict.
1-70
Using multiple clocks design
Figure 1-71. Passive Components Simulation.
passive components simulated follows:
resistor converts strong signal into weak capacitor first short circuit which opens after time inductor first open circuit which closes after time
time constants from Edit Timing Specification window which available from Patching menu. Setting these time constants identical changing propagation delay typical digital devices. NOTE: cannot connect series passive components. example, serial connection resistor capacitor needs replaced with capacitor alone. capacitors time constant should within Edit Timing Specification window.
Using multiple clocks design
Signal waveforms have limited duration, defined their formula. Clocks other hand repetitious signals that have time limitation, except simulator test vector limitations. binary counter outputs clock signals. However, need more complex clocks, define them using following procedure:
Simulating Netlist
1-71
Creating Clocks
Select Stimulator menu. Then select Stimulators option. When Stimulator Selection menu (keyboard) appears, select
Formula button
response, Stimulator window appears Select Clocks option from Mode field Double-click selected clocks (C1-C4) Select
Clock field
Enter clock formula into Formula field Click Assign Formula button Select another clock from Select Clock field repeat above
steps Note that enter clock formula, displayed Defined Assignments field Figure 1-20. When finish editing clock formulas, click Close button.
Applying Clocks
apply multiple clocks your design, follow this procedure: Click selected signal Signal field Waveform Viewer window mark signal blue. Select Stimulator menu. Then select Stimulators option. When Stimulator Selection window appears, click clock button (C1-C4), whose formula want apply. These buttons located right keyboard display, they black when defined. When gray, clock buttons have been assigned formula.
assign same clock formula number signals. four different signals, defined formulas, assigned design. addition, number clock signals based binary counter outputs(B0-BF N0-NF).
Simulating Netlist
ACTIVE-CAD work with schematic editors real-time interactive mode (DDE) mode off-line (netlist) mode. select operational
1-72
Incremental netlist mode
mode, select Project Manager from File menu. When Project Manger window appears (Figure 1-72), select Netlist option. response ACTIVE-CAD displays Project Netlist Configuration window shown Figure 1-73.
Figure 1-72. Project Manager window.
Figure 1-73. Netlist Configuration window.
Incremental netlist mode
click Schematic Netlist option shown Figure Figure 173, ACTIVE-CAD will communicate with associated schematic editor Windows protocols. Only initial design state loaded schematic netlist. additional schematic changes will through functions. This allows incremental netlist updating enables design modified while simulation progress. complete netlist selection, click button.
Simulating Netlist
1-73
Off-line netlist mode
click theExternal Netlist option shown Figure 1-73, ACTIVECAD highlights Select Netlist button External Netlist Format field. select desired netlist format, click External Netlist Format field, select desired netlist format then click Select Netlist button. simulator displays netlist selection window. Select desired external netlist complete netlist selection, click button Project Netlist Configuration window.
Flat netlist simulation
Flat netlists have their components connectivity explicitly listed. click Design Contents button, ACTIVE-CAD will explicitly list components Chip Selection field (Figure 174). that field lists hierarchical macros, designated Hxx, then loaded netlist hierarchical one. flat netlist displays only Root symbol Scan Hierarchy level. better understand difference between flat hierarchical netlist displays, compare Scan Hierarchy fields shown Figures 1-74 1-75. hierarchical design flattened before loaded into ACTIVE-CAD, will listed flat netlist, similar shown Figure 1-74 (there only Root Scan Hierarchy flied).
Figure 1-74. Listing Flat Netlist Components.
Hierarchical netlist simulation
Chip Selection field shown Figure Figure 1-75 lists hierarchical macros etc., mixed with some concrete devices that used design root level, then design netlist hierarchical format. Scan Hierarchy window displays hierarchical design struc-
1-74
Save Selected Signal Names
ture Signals Selection field lists signals that exist highlighted hierarchy level.
Figure 1-75. Listing Hierarchical Netlist Components
review ACTIVE-CAD internal netlist under text editor, will notice that only contains level components macros. hierarchical drawings listed library components their wiring components included within hierarchical library models. this reason, hierarchical netlist first look though missing components.
Save Selected Signal Names
Unlike batch-mode simulators, ACTIVE-CAD gives instant access design section. create sets signal files testing selected design sections, then test these design sections loading selected signal files screen. create file made selected signal names:
Load design netlist Select Signals option within Signals menu Select desired signals from window Save these signals file (using Save Test Vectors Save ASCII Test Vectors from File menu).
NOTE: important remember that save signal names alone, without associated waveforms.
Simulating Netlist
1-75
Moving test vectors from design another
move test vector files from design another even signal names match all. This very useful test certain design functions like counting, decoding, shifting, etc. transfer test vector files from design another, follow this simple procedure:
Save desired test vector file ASCII file
(use Save ASCII Test Vectors option File menu)
Using other editor, manually edit saved ASCII file
contain signal names
Save this file, preferably under name Load design netlist Load ASCII Test Vectors option File menu load
edited file
Switching between schematic external netlist
ACTIVE-CAD allows dynamically disconnect links online schematic simulate external netlist. switch from on-line schematic editor external netlist, select Netlist option from Project Manager window, which selectable from File menu. When Project Netlist window shown Figure 1-73 appears, click External Netlist option select appropriate netlist format file (see Loading Netlists). switch from external netlist on-line schematic editor, click Schematic Netlist option (Figure 1-73) button. ACTIVECAD will load currently active schematic design into simulator your subsequent design changes will incrementally.
Tracking Errors Through Design Netlist
ACTIVE-CAD allows track design errors directly from netlist signal state display. When error occurs, number test points around suspect devices along signal paths trace origin design problem. quicker track design problem tracing signal lines their states through netlist. Example shows typical signal tracing process though design netlist.
1-76
Tracking Errors Through Design Netlist
Example
Load TEST_A2 binary test vector file (Figure 1-76 which associated with TEST_A schematic. Simulate Long step; note that OUT1 signal line shows X_Unknown logical state. trace origin this X_Unknown state, click OUT1 signal name shown Figure Figure 1-76 then select Connections from Signal menu. ACTIVE-CAD responds with Figure 1-77, which shows that OUT1 driven U2(74LS74A).Q1 output pin.
Figure 1-76. TEST_A2 Test Vectors after long step.
Figure 1-77. OUT1 Signal Connections Listing.
analyze detail U2(74LS74A).Q1 output logical state status, click States button shown Figure 1-77, which forces ACTIVECAD display signal logical states. response, ACTIVE-CAD displays Figure 1-78 which lists:
Node resulting signal signal node Conv model will interpret input signal (inputs only) Model what model will output (outputs only)
Simulating Netlist
1-77
Stim shows manually applied pin/node override signal
Figure 1-78. OUT1 Logical States Table.
understand X_Unknown state been generated U2(74LS74A).Q1 pin, lets analyze inputs (you need know 74LS74A operates). First, double- click U2.Q1 output. When ACTIVE-CAD displays list device input pins, double-click U2(74LS74A).CLK1 signal line. response, ACTIVE-CAD displays window Figure 1-79 which confirms that U2.CLK1 signal line stimulus signal remains High_Z state. Clicking signal lines U2.PRE1 U2.CLR1, produces similar result.
Figure 1-79. Node Logical States Table.
Conclusion: device unknown state because input signals High_Z state been reset after power-on. Should there problem with U2(74LS74A).D1 input signal, could double-click this pin. This would list logical states signals U2.D1 node (Figure 1-80).
1-78
Simulate FPGA Designs System Level
Figure 1-80. Logical States Table U2.D1 Pin.
Typically, need only look output pins node because they control signals each node. Thus, double-clicking U1(7400).Y1 output would produce listing gate inputs. process signal tracing continue, described reference U2.D1 input. Connections option been expressly developed ALDEC technical support staff they quickly effectively trace design problem that they receive from around world. Once become familiar with this process, will able trace your design problems with insight that other simulation tool provide.
Simulate FPGA Designs System Level
accommodate various budgetary restrictions, ACTIVE-CAD products come basic configurations:
chip-level design tools, system-level design tools
Chip-level design tools
These low-cost tools allow simulate single device time. Each project separate FPGA ASCII design which enter troubleshoot pre-layout (functional) post-layout (timing) design cycles. ACTIVE-CAD products allow perform functional system-level analysis, based pre-layout design files. process functional system level simulation comprised following steps:
save each FPGA ASIC independent macro create top-level design with these macros included load this top-level design netlist into logic simulator
Simulating Netlist
1-79
chip-level ACTIVE-CAD allows only post-layout netlist loaded does care load several pre-layout netlists part same design file.
System-level design tools
system-level design tools allow simulate multiple FPGA ASIC chips board level. Since these ACTIVE-CAD products also simulate post-layout designs, they produce very reliable design data. board-level simulation capabilities most effectively, create schematic design with ASIC FPGA packaging information. Next, connect wire these packages together. Following this, assign these packages concrete FPGA ASIC netlists. using ACTIVECAD (DDE-related) schematic, select Assign Netlist option from Hierarchy menu. when netlist window appears, select desired netlist assign clicking selected package schematic.
Chapter
ACTIVE-CAD Logic Simulator
Using ACTIVE-CAD simulator
Simulator Window
ACTIVE-CAD simulator window contains title bar, menu control bar, located screen. Since ACTIVE-CAD handle multiple windows, items such signal waveforms, components, timing parameters1, etc. displayed separate windows. simulator main toolbox allows switch between functional, glitch timing simulation modes. also provisions running simulation steps, searching tags, breakpoints other options. elements simulator window shown Figure 2-1.
NOTE: timing simulation mode included SUSIE-CAD/HIER.
Simulator Window
Figure 2-1. Simulator Main Window.
Main toolbox provides quick access most important simulator operations. toolbox moved screen location displayed using View/Main Toolbox option Utilities menu. Step window used simulation steps. moved around screen. display this window select Simulation Step option Utilities menu. Title used display projects name. also used move simulator window around screen. move simulator window, click title drag window desired screen location. When simulator window been placed desired screen location, release mouse button. double click title bar, will toggle between regular full screen window size. System menu button invokes typical Windows menu, with options like Close, Maximize, Minimize, Move, etc. Minimize button allows reduce entire window (minimize) small icon that will placed bottom screen. restore window full size, need double-click minimized window icon.
Using ACTIVE-CAD simulator
Maximize button used display window over entire screen. restore window previous size, toggle upper right button maximized window. Menu includes eight menus which accessed clicking menu name pressing underlined character menu name. Schematic editor button switches screen ACTIVE-CAD schematic editor program. schematic editor already been started, ACTIVE-CAD will display window. Otherwise schematic editor will started. Short Long Step simulation buttons used perform short long simulation steps with single click mouse button. #10. Short Long Step Setup used Short Long Step duration. either click field enter value, click arrow access list predefined simulation steps. This setup window pops when select Simulation Step option from Utilities window. #11. Simulation time displays length current simulation cycle nanoseconds, counting from beginning simulation. maximum simulation time depends simulation resolution. 10ps resolution maximum time 42ms. other resolutions simulator simulate minutes hours hardware operational time. #12. Binary counter status binary counter displayed form yellow lights. means that logical high yellow means logical #13. Simulation mode setup allows select between timing mode with picoseconds resolution, glitch mode with Short step unit propagation delays, unit delay mode with propagation unit equal simulation precision functional mode with zero propagation delays. option available SUSIE-CAD/HIER. #14. Search button allows select item condition search timing diagram. choose from such items Breakpoints, Errors, Events, Milestones Tags. #15. Search Forward Backward buttons allow search timing areas items have selected with Search button (#14).
Waveforms Window
#16. Stop Simulation button stops simulation current simulation cycle. enabled disabled within window resulting from clicking Simulation Stop option within Options menu. #17. Power button initializes entire design. Power operation performed automatically beginning simulation after each interactive connectivity change.
Waveforms Window
typical waveform window shown Figure 2-2. Using Utilities menu, open multiple waveform windows, also called Waveform Viewers. signals displayed windows will same; However, view different parts waveform diagram different timing scales. minimize these windows, icons will placed bottom main window. NOTE: setups controls located within each Waveform Viewer window effect only that window. Waveform Viewer window following main areas: Signal entry comprised fields #14; field displays function listed signals pins, field displays signals names observed stimulated with test vector) Test vector entry includes field entering ready-made test vectors field direct test vector editing. current logical state signals under blue vertical cursor displayed field #18. Waveform window setups includes Scale display (#16) waveform window, waveform cursor position (#11) tool managing signals test vectors through #8). ACTIVE-CAD vertical cursors displayed signal waveform area. cursor simulation cursor. visible times indicates last simulation cycle. blue cursor editing cursor visible only click screen location editing viewing local simulation data. logical states under blue cursor explicitly listed column #18. Zoom Zoom these buttons (#15) used quickly expand contract waveform scale. Each mouse click these buttons changes scale next predefined value.
Using ACTIVE-CAD simulator
Figure 2-2. Timing Window.
waveform window tool following function buttons: Ruler On/Off enables disables waveform window ruler. don't need waveforms referenced time scale, disable ruler allow more room signals. Waveform Delete deletes waveforms without resetting simulation with Power Display Comments On/Off allows toggle comment display off. comments used document important situations waveform diagram both displayed specified screen locations printed with waveform diagram. Measurements On/Off enables display precise timing measurements between signal transitions, regardless scale. On/Off clicking this button meaningful only have defined some buses, either Signal entry (#14) schematic. Buses comprised several signals pins displayed hex, binary, decimal octal mode. When display mode, each signal line individually displayed.
Waveforms Window
Select Probes invokes Component Selection Waveform Viewer window which allows select signals pins display Waveform Viewer window. Stimulus invokes Stimulator Selection window that used define assign stimulators test vectors selected signals. This window includes such signal waveform generators binary counter, keyboard keys, asynchronous clocks waveform formulas. Logical States invokes Stimulator State Selection window that allows select assign logical state signal name device pin. logical states assigned input pins signals time during simulation. Time Scale Display Expansion (Ruler) dual purpose:
displays screen resolution. scale used general
reference simulation results (waveforms).
click scale drag mouse cursor, blue stripe follows mouse movement. release mouse button, area under blue stripe expands full screen display. used observing alignment signal transitions time measurements. #10. Signal Waveform Display displays test vectors that stimulate design real time responses from design. Blue cursor location displays current location blue cursor which used direct waveform editing, time measurements, comments insertion, etc. automatically hidden under cursor, immediately after first simulation event. #12. cursor location shows last simulation cycle. #13. Attribute field shows type signal (i=input, o=output, b=bi-directional). #14. Signal field displays names signals device pins which have been selected display. #15. Scale Adjustment field clicking left-hand field increments display scale signal waveforms, e.g. from division. Clicking right-hand field reduces display scale signal waveforms, e.g. from division. #16. Scale Display shows scale signal waveform display.
Using ACTIVE-CAD simulator
#17. Stimulator field allows enter names pre-defined stimulators. assigned stimulators will control associated signal lines. #18. Current Logical State displays logical states signal waveforms current blue cursor location.
ACTIVE-CAD Main Menus
ACTIVE-CAD operation controlled from menus, which load design, select test points, feed design stimulus design analysis environment. brief description each menu follows below. higher productivity, make yourself familiar with features available each menu. Since most Windows operations self-explanatory, attention will paid ACTIVE-CAD specific features, options operations. Some ACTIVE-CAD features invoked from several applications. minimize cross-referencing, these features will described detail several chapters.
FILE Menu
File menu allows load, save print selected design files:
Load Test Vectors Load ASCII Test Vectors Save Test Vectors Save ASCII Test Vectors Load Memory Chip Save Memory Chip Load Memory Block Save Memory Block Load Fuse Load Simulation Save Simulation Page Setup Print Setup Print Print Error Report
loads binary files with design stimulus loads ASCII files with design stimulus saves signal waveforms binary files saves signal waveforms ASCII files loads memory chip with data saves contents memory chip loads memory block data saves contents memory block loads fuse into selected device reloads previously simulated design saves simulation results future typical Page Setup operation typical Print Setup operation typical Print operation prints design error report
ACTIVE-CAD Main Menus
Project Manager Project Libraries Load Netlist Test
selects project resources selects device libraries simulation loads design (netlist) allows quick, single simulation
SIGNAL Menu
Signal menu allows select signals which will apply stimulus signals which will analyze detail:
Signals Hierarchy Connections Move Delete Select
extensive sub-menus selecting signals pins allows select signals/pins from hierarchical level allows track signal paths their logical values allows rearrange signals screen selects, creates enables buses display deletes signals buses from display selects deselects signals further processing location
Insert Empty Line inserts empty line current cursor Search Find. Signal
searches selected signal/pin name display screen locates selected signal/pin names DDE-connected schematic sheet allows define ASCII test vectors
STIMULATOR Menu
Stimulator menu allows select, create apply design stimulus signals, which also called test vectors:
Stimulators
Mode
allows create apply stimulus signals from special window giv
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