EZTAG USER TABL CONT INDEX BOOKS 1405 EZTag User G

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EZTAG
USER
TABL CONT INDEX BOOKS
1405
EZTag User Guide
Contents Introduction EZTag Download Cable Options In-System Tutorial EZTag with Workstations Error Messages
EZTag User Guide
Printed U.S.A.
EZTag User Guide
XACT, XC2064, XC3090, XC4005, XC-DS501 registered trademarks Xilinx. XC-prefix product designations, FastFLASH, FastCONNECT, EZTag, XACT-Floorplanner, XACT-Performance, XAPP, XAM, X-BLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, XPP, XSI, BITA, Configurable Logic Cell, CLC, Dual Block, FastCLK, HardWire, LCA, Logic Cell, LogicProfessor, MicroVia, PLUSASM, SMARTswitch, UIM, VectorMaze, VersaBlock, VersaRing, ZERO+ trademarks Xilinx. Programmable Logic Company Programmable Gate Array Company service marks Xilinx. registered trademark PC/AT, PC/XT, PS/2 Micro Channel trademarks International Business Machines Corporation. DASH, Data FutureNet registered trademarks ABEL, ABEL-HDL ABELPLA trademarks Data Corporation. SimuCad Silos registered trademarks P-Silos P/CSilos trademarks SimuCad Corporation. Microsoft registered trademark MS-DOS trademark Microsoft Corporation. Centronics registered trademark Centronics Data Computer Corporation. PALASM registered trademarks Advanced Micro Devices, Inc. UNIX trademark AT&T Technologies, Inc. CUPL, PROLINK, MAKEPRG trademarks Logical Devices, Inc. Apollo AEGIS registered trademarks Hewlett-Packard Corporation. Mentor IDEA registered trademarks NETED, Design Architect, QuickSim, QuickSim EXPAND trademarks Mentor Graphics, Inc. registered trademark Microsystems, Inc. SCHEMA SCHEMA trademarks Omation Corporation. OrCAD registered trademark OrCAD Systems Corporation. Viewlogic, Viewsim, Viewdraw registered trademarks Viewlogic Systems, Inc. CASE Technology trademark CASE Technology, division Teradyne Electronic Design Automation Group. DECstation trademark Digital Equipment Corporation. Synopsys registered trademark Synopsys, Inc. Verilog registered trademark Cadence Design Systems, Inc. Xilinx does assume liability arising application product described shown herein; does convey license under patents, copyrights, maskwork rights rights others. Xilinx reserves right make changes, time, order improve reliability, function design supply best product possible. Xilinx will assume responsibility circuitry described herein other than circuitry entirely embodied products. Xilinx devices products protected under more following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418; 4,853,626; 4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377; 34,363, 34,444, 34,808. Other U.S. foreign patents pending. Xilinx, Inc. does represent that devices shown products described herein free from patent infringement from other third party right. Xilinx assumes obligation correct errors contained herein advise user this text correction such made. Xilinx will assume liability accuracy correctness engineering software support assistance provided user. Xilinx products intended life support appliances, devices, systems. Xilinx product such applications without written consent appropriate Xilinx officer prohibited.
Xilinx Development System
Preface
About This Manual
This manual describes Xilinx's EZTag software, tool used Insystem progamming. Before using this manual, should familiar with operations that common Xilinx's software tools: bring system, select tool use, specify operations, manage design data. These topics covered Development System Reference Guide.
Manual Contents
This manual covers following topics. Chapter "Introduction," provides introduction Xilinx Boundary-scan JTAG capabilities. Chapter "EZTag Download Cable Options," provides information connecting using XChecker Serial Cable Parallel Download Cable download readback information in-system. Chapter "In-System Tutorial PCs," documents basics using interface download programming XC9500 family devices in-system. Chapter "EZTag with Workstations," documents basics using EZTag with from workstation environment. Appendix "Error Messages," provides list error messages that EZTag report. most error messages workaround suggested.
EZTag User Guide
Conventions
this manual following conventions used syntax clarification command line entries.
Courier font indicates messages, prompts, program files
that system displays, shown following example.
speed grade: -100
Courier bold indicates literal commands that must enter
syntax statement.
rpt_del_net=
Italic font indicates variables syntax statement. also, other conventions used following page.
xdelay design
Square brackets indicate optional entry parameter. However, specifications, such [7:0], they required.
xdelay [option] design
Braces enclose list items from which choose more.
xnfprep designname ignore_rlocs={true|false}
vertical separates items list choices.
symbol editor [bus|pins]
EZTag User Guide
Conventions Other conventions used this manual include following. Italic font indicates references manuals, shown following example. Development System Reference Guide more information. Italic font indicates emphasis body text. wire drawn that overlaps symbol, nets connected. vertical ellipsis indicates repetitive material that been omitted.
Name QOUT' Name CLKIN'
horizontal ellipsis indicates that preceding repeated more times.
allow block blockname loc1 loc2 locn
Xilinx Development System
Contents
About This Manual Manual Contents
Chapter
Introduction
Boundary Scan. What IEEE 1149.1. What used does work. Controller Instruction Register. Data Registers. JTAG Controller JTAG Controller States. JTAG Instructions Supported FastFLASH Parts Mandatory Boundary Scan Instructions. Optional Boundary Scan Instructions FastFLASH Reconfiguration Instructions. Device Operations. Data Security Feedback Disconnecting Modifying Programmed Design File BSDL Summary JEDEC Summary
Chapter
EZTag Download Cable Options
XChecker Hardware (Serial) Connecting XChecker Cable. Connecting XChecker Cable Your Workstation Connecting XChecker Cable Your Connection Your Target System.
EZTAG User Guide
EZTAG User Guide Header Connector Flying Lead Connectors. Cable Connections Connecting System Operation. Parallel Download Cable. Connecting Parallel Download Cable Connection Your Target System. Header Connector Flying Lead Connectors. Cable Connections Connecting System Operation. 2-10 2-10 2-11
Chapter
In-System Tutorial
Introduction Cable Setup Selecting Port Cable Device Chain. Configuring Device In-System. Modifying Chain Insert. Change Delete Saving Chain. Saving Modified Chain Data Security Selection.
Chapter
EZTag with Workstations
Using EZTag Software EZTag Files. design.jed eztag.pro. batch_file.cmd. device.bsd. Invoking EZTag. Downloading Verifying Command-Line Options -batch Batch Mode Operation Help Option. Specify Part Type. Specify Port Name
Xilinx Development System
Contents Verify Download Readback. Interactive Mode Commands Batch Execute Batch Mode Examples. Baud Specify Baud Rate Dump Erase Exit Terminate Session Functest Help Online Help Send Screen Display File. Part Specify Device Chain Partinfo Port Specify Download/Readback Port Program Quit Terminate Session. Reset Reset Target LCA/Cable. Save Save Option Settings Settings Display Settings -Temporarily Exit Operating System Verify Verify Target EPLD Bitstream. Troubleshooting Guide. Communication. Improper Connections Improper Unstable 4-10 4-10 4-11 4-11 4-11 4-12 4-12 4-12 4-13 4-13 4-14 4-14
Appendix Error Messages
Introduction Error Messages.
EZTAG User Guide
Chapter
Introduction
This chapter introduces basic concepts Xilinx JTAG capabilities XC9500 series products.
Boundary Scan
What IEEE 1149.1
Design complexity, difficulty loaded board testing, limited access surface mount technology industry leaders seek accord standard support solution these problems. Boundary Scan, formally known IEEE Standard 1149.1, primarily testing standard created alleviate growing cost designing producing digital systems. primary benefit standard ability transform extremely difficult printed circuit board testing problems (that could only attacked with ad-hoc testing methods) into well-structured problems that software handle easily swiftly. standard defines hardware architecture mechanisms solve aforementioned problems.
What used
Although primarily testing standard on-chip circuitry, proliferation standard opened door wide variety applications. standard itself defines instructions that used perform functional interconnect tests well built-in self test procedures. Vendor-specific extensions standard have been developed allow execution maintenance diagnostic applications well programming algorithms reconfigurable parts. latter
EZTag User Guide
Introduction that have been implemented addition mandatory operations standard some optional ones) FastFLASH family.
does work
level schematic test logic defined IEEE 1149.1 includes three blocks:
Controller
This responds control sequences supplied through test access port (TAP) generates clock control signals required correct operation other circuit blocks.
Instruction Register
This shift register-based circuit serially loaded with instruction that selects operation performed.
Data Registers
These bank shift register based circuits. stimuli required operation serially loaded into data registers selected current instruction. Following execution operation, results shifted examination. JTAG Test Access Port (TAP) contains four pins that drive circuit blocks control operations specified. facilitates serial loading unloading instructions data. four pins are: TMS, TCK, TDO. function each follows: this JTAG test clock. sequences controller well JTAG registers provided XC95108. this mode input signal Controller. controller 16-state that provides control logic JTAG. state rising edge determines sequence states controller. internal pull-up resistor provide logic system driven. -this serial data input JTAG instruction data registers. state controller well particular instruction held instruction register determines which register
Xilinx Development System
Introduction specific operation. internal pull-up resistor provide logic system driven. sampled into JTAG registers rising edge TCK. this serial data output JTAG instruction data registers. state controller well particular instruction held instruction register determines which register feeds specific operation. Only register (instruction data) allowed active connection between given operation. changes state falling edge only active during shifting data through device. This three-stated other times.
Figure
JTAG Architecture
JTAG Controller
JTAG Controller 16-state finite state machine, that controls scanning data into various registers JTAG architecture. state diagram controller shown Figure
EZTag User Guide
Introduction 1-1. state rising edge responsible determining sequence state transitions. There state transition paths scanning signal into device, shifting instruction instruction register shifting data into active data register determined current instruction.
JTAG Controller States
Test-Logic-Reset. This state entered power-up device whenever least five clocks occur with held high. Entry into this state resets JTAG logic state such that will interfere with normal component logic, causes IDCODE instruction forced into instruction register. Run-Test-Idle. This state allows certain operations occur depending current instruction. XC9500 family, this state causes generation program, verify erase pulses when associated in-system programming (ISP) instruction active. Select-DR-Scan. This temporary state entered prior performing scan operation data register passing Select-IR-Scan state. Select-IR-Scan. This temporary state entered prior performing scan operation instruction register returning TestLogic-Reset state. Capture-DR. This state allows data loaded from parallel inputs into data register selected current instruction rising edge TCK. selected data register does have parallel inputs, register retains state. Shift-DR. This state shifts data, currently selected register, towards stage each rising edge after entering this state. Exit1-DR. This temporary state that allows option passing Pause-DR state transitioning directly Update-DR state. Pause-DR. This wait state that allows shifting data temporarily halted.
Xilinx Development System
Introduction Exit2-DR. This temporary state that allows option passing Update-DR state returning Shift-DR state continue shifting data. Update-DR. This state causes data contained currently selected data register loaded into latched parallel output (for registers that have such latch) falling edge after entering this state. parallel latch prevents changes parallel output these registers from occurring during shifting process. Capture-IR. This state allows data loaded from parallel inputs into instruction register rising edge TCK. least significant bits parallel inputs must have value defined IEEE Std. 1149.1, remaining bits either hardcoded used monitoring security data protect bits. Shift-IR. This state shifts values instruction register towards stage each rising edge after entering this state. Exit1-IR. This temporary state that allows option passing Pause-IR state transitioning directly Update-IR state. Pause-IR. This wait state that allows shifting instruction temporarily halted. Exit2-IR. This temporary state that allows option passing Update-IR state returning Shift-IR state continue shifting data. Update-IR. This state causes values contained instruction register loaded into latched parallel output falling edge after entering this state. parallel latch prevents changes parallel output instruction register from occurring during shifting process.
JTAG Instructions Supported FastFLASH Parts
Mandatory Boundary Scan Instructions
BYPASS. BYPASS instruction allows rapid movement data from other components board that required perform test operations.
EZTag User Guide
Introduction SAMPLE/PRELOAD. SAMPLE/PRELOAD instruction allows snapshot normal operation components taken examined. also allows data values loaded onto latched parallel outputs boundary scan shift register prior selection other boundary-scan test instructions. EXTEST. EXTEST instruction allows testing off-chip circuitry board level interconnections.
Optional Boundary Scan Instructions
INTEST. INTEST instruction allows testing on-chip system logic while components already board. HIGHZ. HIGHZ instruction forces drivers into high impedance states. IDCODE. IDCODE instruction allows blind interrogation components assembled onto printed circuit board determine what components exist product. USERCODE. USERCODE instruction allows user-programmable identification code shifted examination. This allows programmed function component determined.
FastFLASH Reconfiguration Instructions
ISPEN. ISPEN instruction activates FastFLASH part insystem programming. FPGM. FPGM instruction used program fuse locations specified address. FERASE. FERASE instruction used perform erase block fuse locations. FVFY. FVFY instruction used read programming fuse locations specified address. ISPLD. ISPLD instruction loads programmed values into device memory. then activates device operate according programmed values.
Xilinx Development System
Introduction
Device Operations
Programming information extracted from JEDEC file generated fitter software. JEDEC file name defaults <design>.jed. full pathname provided file this name searched along XACT path. Device operation options available users are: Program. Download contents JEDEC file device programming registers. Program Verify. Download contents JEDEC file device programming registers. Configure device read back contents device programming registers compare them with JEDEC file. Report differences user. Program, Verify Test. Same Program Verify (above) with addition Functional Test (see below). Verify. Read back contents device programming registers compare them with JEDEC file. Erase. Clear device configuration information. Functional Test. Apply user-specified functional vectors from JEDEC file device, comparing results obtained against expected values. Report differences user. Read Manufacturer's Read contents JTAG IDCODE register. Display contents user. Read User Signature. This value will have been user programming time. valid only after programming. This function reads contents JTAG USERCODE register displays result user. Bypass. Ignore this device when addressing devices JTAG boundary scan chain. Readback. Reads back contents device programming registers creates JEDEC file with results. Checksum. Reads back contents device programming registers calculates checksum comparison against expected value.
EZTag User Guide
Introduction
Data Security
programming operations optionally select enable "Data Protection" Data Security" both. When enabled, Data Security disables reading programmed contents device (the device's signature remain readable). Data Protection allows only reading programmed data. device contents cannot altered. When both Data Security Data Protection enabled, device neither read re-programmed.
Feedback
When using PC-based graphical user interface, alert boxes operation execution provide immediate feedback success failure specified operation. Detailed information regarding failure located system file, provided both workstation based tool.
Disconnecting
Turn target system power before disconnecting FastFLASH BSCAN Download cable XChecker cable.
Modifying Programmed Design File
flow does change modified programmed design file. There shortcuts even with minor change.
BSDL Summary
Boundary Scan Description Language (BSDL) uses subset VHDL describe boundary scan features component. BSDL file required each kind boundary-scan device system. BSDL files FastFLASH devices provided part product release. user responsible providing BSDL files non-FastFLASH parts used boundary-scan chain.
Xilinx Development System
Introduction system looks BSDL files along XACT path current working directory. name BSDL file assumed <device name>.bsd.
JEDEC Summary
This fuse functional verification vector file. This ASCII file containing configuration information and, optionally, vectors that used verify functional behavior configured part. JEDEC file generated each FastFLASH device system. system looks JEDEC files along XACT path current working directory. name JEDEC file assumed <design name>.jed, specified exactly user.
EZTag User Guide
Chapter
EZTag Download Cable Options
This chapter gives specific information about using EZTag with XChecker Cable Parallel Download Cable. EZTag download, read back, verify design configuration data device, probe internal logic states EPLD design. cables available from Xilinx. first serial RS-232 known XChecker that connect serial port. second Parallel Download Cable that connect printer port. This chapter documents both cables. Note: have Parallel Download Cable proceed page 2-8.
XChecker Hardware (Serial)
XChecker hardware consists cable assembly with internal logic, test fixture, headers connect cable your target system. have serial system need DB-9/DB25 adapter connect host computer. Using XChecker hardware requires either standard DB-9 DB25 RS-232 serial port, parallel port. have different serial port connection, need provide appropriate adapter. Figure
EZTag User Guide
EZTag User Guide shows XChecker cable hardware accessories.
Keyed Connection Target System
Connection Host Computer
DB-25 Connector DB-9 Connector Connect FPGA Demo Board
required connect host computer
Test Fixture Enlarged show mating plugged slots
XChecker Cable Assembly
Flying Lead Connector
X1724a
Flying Lead Connector
Connection Target System
Figure XChecker Hardware Accessories
Xilinx Development System
EZTag Download Cable Options Figure show bottom views XChecker cable.
View
XChecker Cable
Header Header
Model: DLC4 Power: 100mA Typ. Serial: 12345
CAUTION
TRIG
CCLK PROG INIT
SENSITIVE ELECTRONIC CLKI Made U.S.A. DEVICE CLKO
Bottom View
X2580
Figure XChecker Cable cable assembly houses internal circuitry consisting Xilinx FPGA static RAM. internal Xilinx FPGA functions interface between XChecker software target system. static stores data readback. XChecker cable with single EPLD several connected boundary-scan chain download readback configuration data. XChecker cable transmits configuration data target EPLDs kHz. Communication between host system XChecker cable dependent host system capability. Table lists valid baud rates serial cables using supported platforms. Parallel cables will support transfer rate your system uses. When XChecker cable used drive JTAG TAP, special configuration file "xckjtag.sys" downloaded automatically FPGA cable assembly. This configuration file converts FPGA into special-purpose JTAG processing unit. Special instructions sent FPGA serial port sequence exercise target system JTAG circuitry. data captured XChecker's static RAM. This then uploaded host
EZTag User Guide
EZTag User Guide serial port further processing. Table Valid Baud Rates
Baud Rate Platform
indicates supported baud rate
9600
19200
38400
115.2K
Connecting XChecker Cable
There simple steps connecting cable: Connect cable your host system serial port. Connect cable your target system.
Connecting XChecker Cable Your Workstation
workstations XChecker cable connects your system RS-232 serial port. need DB-9/DB-25 adapter, which accommodates most serial ports, that connect XChecker cable your host system.
Connecting XChecker Cable Your
connect serial XChecker cable connects your system RS232 serial port (you need DB9/DB25 adapter). EZTag software will automatically identify XChecker cable when correctly connected your choose also select this connection manually. serial port manually:
Cable Serial Port [Comn]
Xilinx Development System
EZTag Download Cable Options
Connection Your Target System
need appropriate pins target system connecting target system board header connection cable. These connectors must standard 0.025-inch square male pins that have dedicated traces target system control pins. connect these pins with header connector flying lead connector. Note: XChecker cable draws power from target system through GND. Therefore, power XChecker, well target system, must stable. connect signals before connecting ground.
Header Connector
When layout printed circuit board with JTAG insystem programming testing, adjustments will make process connecting downloading easier. Provide header pins your printed circuit board VCC, GND, TCK, TDI, TDO.
header connector standard 9-pin signals, key) header connectors that 0.025 square male pins. order listed Table 2-2. These header connectors keyed assure proper orientation cable assembly.
Flying Lead Connectors
flying lead connector flying lead header connectors with eight standard individual female connectors that onto 0.025 square male pins. Each lead labeled identify proper connection.
Cable Connections
Connections between cable assembly target system leads. connection JTAG boundary-scan systems need only ensure that VCC, GND, TDI, TCK, (TDO) pins connected. Once installed properly, connectors provide power cable, allow download readback configuration data, provide logic probe device pins.
EZTag User Guide
EZTag User Guide Each 100- series resistor. must provide external pull-up resistor (approximately 10-50-k) where indicated. Table describes connections target circuit board. Table XChecker Cable Connections Definitions
Name
Function
Connections
Power Supplies target system typically) cable. Ground Supplies ground target system reference cable. ground Read Data Read back data from target system read this pin. Test Data this signal used transmit serial test instructions data. Test Clock this clock drives test logic devices boundary-scan chain. Test Mode Select this signal decoded controller control test operations. used. used. used. used. used. used. used. Connect system pin. Connect system pin. Connect system pin.
(TDO)
Connect system pin.
CLKI CLKO CCLK PROG INIT
Unconnected. Unconnected. Unconnected Unconnected Unconnected Unconnected. Unconnected.
Xilinx Development System
EZTag Download Cable Options
Name TRIG
Function used. used. used.
Connections Unconnected. Unconnected. Unconnected.
Connecting System Operation
Connect XChecker cable host system your target system shown Figure 2-3.
NOTES: XC4000\XC5200 PROG XC4000\XC5200 only INIT XC3000\XC4000\XC5200 only
Flying Leads Header Connector
CCLK
Note Note
Note
PROG
Host RS232 Port
INIT
Target Device
X6357
XChecker
Target System
Figure XChecker Connections JTAG Boundary-scan
EZTag User Guide
EZTag User Guide
Parallel Download Cable
Parallel Download Cable consists cable assembly containing logic protect your PC`s parallel port headers connect your target system. Using Parallel Download Cable requires equipped with compatible parallel port interface with DB25 standard printer connector. Figure shows Parallel Download Cable.
Keyed Connection Target System
Connection Host Computer
DB-25 Connector
DB25 Standard DB-9 Connector Parallel Connector
Connect FPGA Demo Board
required connect host computer
Test Fixture Enlarged show mating plugged slots
Parallel XChecker Cable Assembly
Flying Lead Connector
X1724a
JTAG Flying Lead Connector
Connection Target System
Figure
Parallel Download Cable Accessories
cable assembly contains logic designed electrically isolate target system from parallel port your host system.
Xilinx Development System
EZTag Download Cable Options parallel download cable used with single EPLD several connected boundary-scan chain download readback configuration data. transmission speed Parallel Download Cable determined solely speed which host transmit data through parallel port interface.
Connecting Parallel Download Cable
connect parallel cable your system's parallel printer port. EZTag software will automatically identify cable when correctly connected your choose also select this connection manually. parallel port manually:
Cable Parallel Port [LPTn]
Connection Your Target System
need appropriate pins target system connecting target system board header connection cable. These connectors must standard 0.025-inch square male pins that have dedicated traces target system control pins. connect these pins with header connector flying lead connector. Note: parallel cable draws power from target system through GND. Therefore, power cable, well target system, must stable. connect signals before connecting ground.
Header Connector
When layout printed circuit board with JTAG insystem programming testing, adjustments will make process connecting downloading easier. Provide header pins your printed circuit board VCC, GND, TCK, TDI, TDO.
header connector standard 9-pin signals, keys) header connector that fits 0.025 square male pins. order listed Table 2-3. These header connectors keyed assure proper orientation cable assembly.
EZTag User Guide
EZTag User Guide
Flying Lead Connectors
flying lead connector flying lead header connectors with eight standard individual female connectors that onto 0.025 square male pins. Each lead labeled identify proper connection.
Cable Connections
Connections between cable assembly target system leads. connection JTAG boundary-scan systems need ensure that VCC, GND, TDI, TCK, pins connected. Once installed properly, connectors provide power cable, allow download readback configuration data, provide logic probe device pins. Table describes connections target circuit board. Table XChecker Cable Connections Definitions
Name
Function
Connections
Power Supplies target system typically) cable. Ground Supplies ground target system reference cable. ground Read Data Read back data from target system read this pin. Test Data this signal used transmit serial test instructions data. Test Clock this clock drives test logic devices boundary-scan chain. Connect system pin. Connect system pin. Connect system pin.
2-10
Xilinx Development System
EZTag Download Cable Options
Name
Function Test Mode Select this signal decoded controller control test operations.
Connections Connect system pin.
Connecting System Operation
Connect parallel cable host system your target system shown Figure 2-5.
NOTES: XC4000\XC5200 PROG XC4000\XC5200 only INIT XC3000\XC4000\XC5200 only
Flying Leads Header Connector
CCLK
Note Note
Note
PROG
Host RS232 Port
INIT
Target Device
X6357
XChecker
Target System
Figure Parallel Download Cable Connection JTAG Boundary-scan
EZTag User Guide
2-11
Chapter
In-System Tutorial
Introduction
This chapter will take through basic steps involved programming XC9500 family device in-system from EZTag supports XC9500 family devices, including: XC9536 XC95108 XC95216
Cable Setup
setup your system download configurations in-system must first connect EZTAG parallel download cable follows: Connect EZTAG Download Cable parallel printer port your This cable contains drivers buffer signals they driven into system. Attach flying leads EZTAG Download Cable (see Figure 3.1). Leads attach inside row. connector designed only correct way. power drivers derived from target system. Connect cable's wires corresponding signals target board. Next connect JTAG inputs. Connect TCK, TDI, target board. TRST supported XC9500 EZTAG Download Cable. your JTAG parts have TRST pin, should connected VCC.
EZTag User Guide
EZTag User Guide Warning: Cable protection ensures that parallel port cannot damaged through normal cable operation. increased safety, please power before target system powered
Attach lead's connector first pins
Figure
EZTAG Cable Leads
Selecting Port Cable
select serial parallel port your cable from EZTag Interface. parallel port:
Cable Parallel Port [LPTn]
serial port:
Cable Serial Port [Comn]
Device Chain
device chain serial chain where first device enters last device. must deliver signal back cable. signals enter devices parallel. When EZTAG device chain must list devices chain order even they BYPASS mode. List every device chain whether they Xilinx devices some other third party device.
Xilinx Development System
In-System Tutorial
Figure
Device Chain
Configuring Device In-System
have created programming files (<filename>.jed) ready download them XC9500 devices in-system through JTAG chain, proceed follows: Make sure cable attached properly target board turned
Memory
CPLD
FPGA
EZTAG Cable
System Logic
Target Figure JTAG Connections
Make sure that BSDL files non-XC9500 devices stored along XACT search path.
EZTag User Guide
EZTag User Guide Invoke EZTAG-JTAG Download Software menu doubleclicking EZTAG-JTAG Download Software icon.
Figure EZTAG Menu with Programming Bypass Mode. Select operations desired each XC95108 part. Under Device Programming Files find disk directory containing files want use. Double-click file name. Device Type File name should appear Chain Description. Click once Operation down arrow select type operation want select. Select Program (this default).
Select Bypass each non-XC-9500 part. These parts will appear under Device BSDL Files. Double-click file each part that appears Chain Description. Note that Bypass selected default Operation each foreign
Xilinx Development System
In-System Tutorial part. Bypass only supported mode Operation nonFastFLASH parts. Note: Chain Description scroll right that will allow scroll around chain. your chain more than three entries, this necessary view them all.
Figure
EZTAG Menu showing Operation Options
Select Execute button. Download will begin. When Execute works properly window appears delivers processing messages. When processing completed, message appears lets know status results execution. errors occur, they will listed message log.
Note: will take between thirty sixty seconds download part using Silicon Evaluation Release software.
Modifying Chain
Chain Editing Operations located EZTAG menu. They softkeys listed Insert, Change, Delete.
EZTag User Guide
EZTag User Guide addition, want start over, File Clear Chain. This will clear entries Chain Description.
Insert
insert softkey allows insert device into chain. When insert, device number selected subsequent devices moved down chain. insert device, follow these instructions: With mouse, click once number Chain Description. number column found left Device Type. Device Type File Name that should highlighted, indicating that this selected element this operation. Click Insert softkey once. Select file enter into chain double-click. file should enter highlighted line push files below highlighted line down chain one. highlighting disappears element number longer selected.
Change
change softkey changes entry Chain Description line, deleting entry line replacing with selected file. change device: With mouse, click once number Chain Description. number column found left Device Type. Device Type File Name that should highlighted. Click Change softkey once. Select file enter into chain double-click. device should enter highlighted line replace file that line. highlighting disappears element number longer selected.
Delete
delete softkey deletes entry Chain Description. items below that line move entry chain.
Xilinx Development System
In-System Tutorial With mouse, click once number Chain Description. number column found left Device Type. Device Type File Name that should highlighted. Click Delete softkey once. highlighted line will deleted items chain below that line will move place chain.
Note: When chain editing operation active, selected files double-clicking) added chain.
Saving Chain
save EZTAG chain description later use, create Chain Description File (.cdf) using:
File Save
screen titled File Operation will appear. This screen will allow select directory path place file also name file, should retain .cdf file extension. name your file, mouse highlight asterisk File Name line, then type name want click once
Figure
Saving File
EZTag User Guide
EZTag User Guide
Saving Modified Chain
previously saved chain description template creating another chain description, want modify description save under another name, Save command.
File Save
This will bring File Operation menu. name your file, mouse highlight asterisk File Name line, then type name want click once
Data Security Selection
Xilinx device selected programming secured with Data Security (DS) Data Protection (DP) both. When enabled, Data Security disables reading programmed contents device (the man.id signature remain readable). Data Protection allows only reading programmed data. device contents cannot altered. When both Data Security Data Protection enabled, device neither read re-programmed. enable Data Security Data Protection both: Find checkboxes Chain Description. They should only appear rows which programming involved (Program, Verify, Test). Enter check either both boxes clicking once box. change your mind about security, click once again. check will disappear.
Xilinx Development System
EZTag with Workstations
Chapter
EZTag with Workstations
This chapter gives specific information about using EZTag workstation environment perform JTAG operations. EZTag download, read back, verify design configuration data device, probe internal logic states EPLD design. EZTag software supports XC9500 family Xilinx EPLD devices, including:
XC9536 XC95108 XC95216
EZTag software support following capabilities.
EZTag allows download design EPLD target system. EZTag verify EPLD configuration comparing original JEDEC programming file after configuring EPLD. program multiple EPLDs connected boundary-scan chain. apply test vectors from JEDEC file through boundary-scan EPLDs using INTEST instruction.
Using EZTag Software
This section describes EZTag files commands.
EZTag Files
must become familiar with following files, which used EZTag software.
EZTag User Guide
EZTag with Workstations
design.jed
design.jed file contains configuration information target design JEDEC standard formats. file generated fitter software. This file optionally contain functional test vectors functional verification XC9500 devices.
eztag.pro
eztag.pro file contains default values EZTag options: part, design, baud, port. These option values updated every EZTag session. EZTag recognize xchecker.pro file, must located same directory which started EZTag software.
batch_file.cmd
batch files text files used execute commands batch mode, extension ".cmd" required.
device.bsd
files contain Boundary Scan Description Language (BSDL) specifications operation boundary-scan logic given device. non-XC9500 device your boundary-scan chain, required supply this file.
Invoking EZTag
start EZTag using following methods:
Command line entry from system shell. Only download verify supported. cannot interactively probe internal logic. Command line entry only used when there exactly device boundary-scan chain. Interactive commands from system shell. This mode offers additional commands download readback also allows probe internal logic states target system device.
Downloading
download design after connecting XChecker cable host system target system. download design, enter
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EZTag with Workstations following command operating system prompt. eztag design_name When specify options, EZTag software selects port where cable connected sets baud rate maximum allowed platform. modify communication port baud rate changing appropriate settings xchecker.pro file. download interactive mode, enter following command system prompt. eztag following message screen: Xilinx EZTAG XC9500-Pre-Release-V2.0.a-JTAG Boundary-Scan Download Copyright Xilinx, Inc. 1991-1995. rights reserved. Cable type 'XCHECKER' Cable connected '/dev/ttya' Baud rate 38400 specify number, type, names order devices boundary-scan chain:
part part_type:design_name
program design, enter this command string: program design_name
Verifying
After have properly configured device, verify configuration compare your original design. most applications, verification needed, this feature helpful with designs that experience extremely unstable noisy conditions. download verify design, enter following command string operating system prompt. eztag design_name Specifying option causes XChecker cable download
EZTag User Guide
EZTag with Workstations file design.jed target system initiate readback immediately after configuration data been downloaded. execute readback after device been operation, interactive commands, follows: eztag This command invokes interactive mode, EZTAG prompt appears. part part_type:design_name part commands identifies number number, type, name order devices boundary-scan chain. this case there device only. Then program device, enter: eztag program design_name program command downloads design.jed target device. want readback after target device operation, execute Verify command. eztag verify design_name This command initiates readback, compares data design.jed file. also execute program verify operations step typing: eztag program design_name
Command-Line Options
This section describes EZTag command-line options. data files configuration bitstream files JEDEC format. When specify options data files, XChecker system defaults interactive mode. specify options specify data file, default options specified xchecker.pro file sets port. command-line syntax follows: eztag options datafile Note: abbreviate options minimum number distinctive characters option name.
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EZTag with Workstations Commands options case-sensitive.
-batch Batch Mode Operation
Syntax Abbreviation -batch bat_file.cmd
Batch option executes commands batch mode. bat_file must have ".cmd" extension contain valid EZTag commands, including interactive commands. comments files using symbol, either command line line.
Help Option
Syntax Abbreviation -help
Help option displays command line usage information.
Specify Part Type
Syntax Abbreviation -part parttype:design_name
Specify Part Type option defines part used such XC95108 XC95216. This option always required specifies number, type, name order devices boundary-scan chain. parts specified order from closest closest TDO.
Specify Port Name
Syntax Abbreviation -port portname
Specify Port Name option identifies port connection XChecker cable. specify this option, default option AUTO, searches cable connected port, parallel serial. Valid ports supported platforms listed Table 4-1.
EZTag User Guide
EZTag with Workstations Table Valid Ports XChecker Cable
Platform HP700 com1 com1 /dev/ttya** /dev/tty00
Communication Ports com2 /dev/ttyb** /dev/tty01 lpt1* lpt2*
*Use with parallel download cable only. **ttya ttyb must readable writable ensure proper connection.
Verify Download Readback
Syntax Abbreviation
Verify Download Readback option executes download readback current EPLD design verification. EZTag reads configuration from EPLD compares original bitstream. specify this option, readback executed after configuration.
Interactive Mode Commands
This section describes EZTag interactive mode commands. interactive mode commands, enter eztag system prompt. Note: abbreviate commands using least number distinctive characters, with command line options, must least characters. repeat previous command using either equal sign, "=," exclamation point, "!."
Batch Execute Batch Mode
Syntax Abbreviation batch bat_file.cmd
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EZTag with Workstations Batch command executes commands batch mode. bat_file must have ".cmd" extension contain valid EZTag commands. pound sign, precede comment lines batch file.
Examples
following examples show methods using Batch command from EZTag prompt: batch bat_file.cmd bat_file.cmd
Baud Specify Baud Rate
Syntax Abbreviation baud baud_rate
Baud command specifies communication baud rate. initialization, fastest baud rate your host system automatically selected. Table lists valid baud rates. Table Valid Baud Rates
Platform 9600
indicates valid baud rate
Baud Rate 19200 38400 115200
Dump
Syntax Abbreviation dump command will read contents part create dump part_name file_name
EZTag User Guide
EZTag with Workstations JEDEC file with results. file created will default part_name.jed. Optionally, specify your name using flag. part_name must have been specified with part command.
Erase
Syntax Abbreviation This command erases programmed contents specified part. part_name must have been specified with part command. erase part_name
Exit Terminate Session
Syntax Abbreviation exit
Exit command terminates current EZTag session, asks whether save current program options xchecker.pro file, returns system shell.
Functest
Syntax Abbreviation functest command will functional vectors associated JEDEC file (file_name) specified device (part_name) using intest command. part_name same JEDEC file_name, then file_name does need specified. part_name must have been specified with part command. functest part_name file_name]
Help Online Help
Syntax Abbreviation help topic
Help command displays online help topic requested 24line segments. Enter scroll forward next lines. Enter exit Help.
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EZTag with Workstations
Send Screen Display File
Syntax Abbreviation -out file_name string
command sends screen output file_name file. this command capture output Readback Show command. There option command.
-out
-out option closes previous file, opens one, places string beginning file. There variable command:
string
variable string insert your comments into file, which normally only captures screen display.
Part Specify Device Chain
Syntax Abbreviation part device_type:part_name device_type:part_name
This command must executed first. describes devices chain software. device_type used find BSDL file associated with each part. BSDL files must named device_type.bsd. part_name arbitrary name associate with device instance chain. will usually proper name (the file name without extension) JEDEC file associated with device that location boundary-scan chain, although could anything. boundary scan chain order must start with closest device TDI, proceed order through chain until reaches last device, which closest TDO. When multiple "part" commands issued, information associated with very last maintained.
Partinfo
Syntax partinfo -signature -checksum part_name
EZTag User Guide
EZTag with Workstations Abbreviation partinfo command returns manufacturer's identification (id), user signature (-signature) device checksum (-checksum) particular part_name. three switches specified single command. part_name must have been specified part command.
Port Specify Download/Readback Port
Syntax Abbreviation port portname
port command specifies download/readback port. Table lists valid entries; ports listed bold face defaults. port defined Auto, ports scanned search cable. Table Valid Ports XChecker Cable Communication Ports com1 com1 /dev/ttya** /dev/tty00 /dev/ttyb** /dev/tty01 com2 lpt1* lpt2*
Platform HP700
*Use with parallel download cable only readback). **ttya ttyb must readable writable ensure proper connection.
Program
Syntax Abbreviation This command programs specified part. part_name same JEDEC file_name, then file_name does need specified. part_name must have been part command. There four options that specified (individually together): after programming device reads back contents verifies that they agree with associated JEDEC file. executes functional test after programming using vectors program [-v] [-t] [-s] [-p] part_name file_name]
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EZTag with Workstations contained associated JEDEC file. sets data security device. This disables readback device' programmed contents. device must erased reprogram sets data protect device. This disables over-write device`s programmed contents. device cannot erased reprogrammed.
Quit Terminate Session
Syntax Abbreviation quit
Quit command terminates current EZTag session asks whether save current program options xchecker.pro file.
Reset Reset Target LCA/Cable
Syntax Abbreviation reset [-cable]
Reset command resets boundary-scan state machines XChecker cable. default reset boundary-scan state machines. There option Reset command.
-cable
-cable option reprograms XChecker cable's internal FPGA. re-initializes cable, including setting correct baud rate. This option useful event power glitches that could affect proper cable operation. With this option, could remove power from target system, then restore power, while running EZTag; Reset command re-initializes cable proper settings.
Save Save Option Settings
Syntax save
EZTag User Guide
4-11
EZTag with Workstations Abbreviation
Save command saves settings four interactive command results xchecker.pro file; baud rate (Baud command), design name (Load command), device type (Parttype command) port name (Port command). initialization, EZTag reads xchecker.pro file defaults current session. This file must current directory XACT environment search path. EZTag updates profile information every session. xchecker.pro file created when exit from your first EZTag session.
Settings Display Settings
Syntax Abbreviation settings
Settings command provides listing following information; port name, baud rate, type cable, design name, part type package type, clock source, hardware trigger status. also lists number clocks first subsequent snapshots, number signals defined probe list, number signals defined display list.
-Temporarily Exit Operating System
Syntax Abbreviation none
command allows temporarily exit from EZTag operating system prompt. Enter exit return EZTag.
Verify Verify Target EPLD Bitstream
Syntax Abbreviation verify part_name file_name]
This command reads back configuration registers specified part compares contents against JEDEC file. part_name same JEDEC file_name, file_name does need specified.
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Xilinx Development System
EZTag with Workstations
Troubleshooting Guide
This section simple guide understanding more common issues might encounter when configuring EPLDs with EZTag. These issues likely fall into three groups; communication, improper connections, improper unstable VCC.
Communication This section describes several issues that involve integrity bitstream that EZTag transmits target EPLDs, correct connection boundary-scan chain.
Improper Connections This section involves assigning configuration pins invalid signals voltage levels.
Improper Unstable This section describes several causes incorrect configuration sequences incorrect responses from target system.
Communication
Observing following guidelines should minimize communication difficulties that occur between XChecker hardware target system. attach extension cables target system side XChecker cable; this compromise configuration data integrity cause checksum errors. Attach XChecker cable configuration leads firmly target system. After connecting target system, specify chain configuration using "part" command. Then "partinfo part_name" command read IDCODE from each part system. This will verify integrity boundary-scan chain. verify feature assure integrity configuration data. this from command line with option interactive mode specifying verify command.
EZTag User Guide
4-13
EZTag with Workstations
Improper Connections
Always make sure that XChecker leads connected properly. Note: Connecting XChecker leads wrong signal will cause permanent damage XChecker internal hardware. must connect ground. workstations, must have read write permissions port which connect XChecker cable. EZTag might issue message stating that cable connected port ttyx. When this message, follow check list below:
board must have power since XChecker Cable uses power from board. Check device driver using following command string: /dev/ttya /dev/ttyb
result should following: crw-rw-rwcrw-rw-rwq
root12,0 month date time /dev/ttya root12,1 month date time /dev/ttyb
Reconnect XChecker cable another valid port. Read /etc/ttyab file. There should lines, follows: ttya ``/usr/etc/getty std.9600'' local secure ttyb ``/usr/etc/getty std.9600'' local secure unknown unknown
port connect modem remote login, cannot that port. port must Consult your System Administrator information /etc/ttyab file different than what listed aforementioned list.
Improper Unstable
Never connect control signals XChecker before ground. Xilinx recommends following sequence: Turn power target system. Connect VCC, ground, then signal leads,
4-14
Xilinx Development System
EZTag with Workstations Turn power target system. Warning: with CMOS device, input/output pins internal FPGA should always lower equal potential than rail voltage avoid internal damage. Make sure rises stable level within 10ms. Stable should between 4.75 5.25 event power glitches, interactive Reset command with option (Cable option) reconfigure XChecker internal FPGA interactive program command reconfigure target EPLD.
EZTag User Guide
4-15
Appendix
Error Messages
Introduction
This section describes error messages that EZTag generate. Following each error message, there suggested workaround.
Error Messages
Error 001: Command file file.cmd found.
Make sure that command file specified current directory environment search path. Make sure that command file ".cmd" extension
Error 002: Internal Error Command table syntax error Cmd=valid_command.
This internal program error that normally should occur. entering command sequence again. error persists, reinstalling your EZTag software. error reappears, call Xilinx Technical Support. prepared duplicate error reference specific files examples.
Error 003: Diagnostic supported this cable.
Diagnostics command, well other readback verification commands only supported XChecker cable.
Error 010: Cannot open output file file_name.
Check available disk space. Current directory file must have write permission.
Error 011: Cannot create output file file_name.
Check available disk space. Current directory file must have write permission.
EZTag User Guide
Error Messages
Error 012: Cannot open input file file_name.
Make sure file_name file exists your working directory environment search path. Current directory file must have write permission.
Error 013: File file_name found.
file_name file does exist current directory search path. Make sure that file_name file exists your working directory environment search path.
Error 021: Help file eztag.hlp accessible
Make sure that XACT environment variable points XACT directory (the XACT directory equivalent "Installation Directory" workstations). Also make sure that eztag.hlp directory XACT\MSG. cannot find eztag.hlp XACT\MSG directory, must reinstall XChecker software.
Error 022: help command command entered.
Help available specified command. Refer Interactive Mode Commands section Chapter help.
Error 023: Cannot save configuration file_name.pro.
Check available disk space. Current directory file must have write permission.
Error 024: Invalid command line line number.
Check file xchecker.pro your current directory illegal commands. Delete xchecker.pro file. EZTag creates profile when exit from session.
Error 030: Ambiguous command.
Enter minimum unique characters that identify command enter complete commands with abbreviations.
Error 031: Invalid command.
command entered illegal. Refer Interactive Mode Commands section Chapter help.
Error 032: Invalid number arguments.
Refer Interactive Mode Commands section Chapter help.
Xilinx Development System
Error Messages
Error 033: Invalid option selected option.
Refer Command-Line Options Interactive Mode Commands sections Chapter help.
Error 034: Invalid value given parameter.
Refer Command-Line Options Interactive Mode Commands sections Chapter help.
Error 035: Value required command entered.
Refer Interactive Mode Commands section Chapter help.
Error 050: System Error Messages
System error codes usually string messages generated your operating system.
Error 051: System file error code.
System error codes usually string messages generated your operating system.
Error 101: Cable initialized.
Reissue Reset command with option, cycle power XChecker cable then issue Reset command with option. Improper Unstable section Chapter
Error 102: Cable located.
cable been recognized port. Make sure there power your board XChecker cable. using test fixture, must connect ground XChecker cable draws power from your target system, from your host computer. Also make sure RS-232 connector firmly attached.
Error 103: Invalid port name.
Refer XChecker Hardware section Chapter help.
Error 104: Invalid baud specified.
Refer XChecker Hardware section Chapter help.
Error 105: Cable reset.
Cycle power cable. Reset command with option.
EZTag User Guide
Error Messages
Error 107: Communication line broken.
Reset command with option. Also make sure there power your board XChecker cable. Check power port connections.
Error 108: Communication checksum error.
Check induced noise your target system from your target system into XChecker connections. cable extensions. XChecker cable length tested produce minimal noise levels. Remember that logic High must 80-100% Logic must 0-25% VCC.
Error 109: Cable power.
Make sure there power from your target system XChecker cable. cable draws power from external source, from host computer.
Error 110: Communication time-out.
EZTag received expected signal; example, system trigger initiate readback data coming from readback. Make sure that selected options trigger readback what intended. Check connections.
Error 120: Cannot communicate cable.
Reset command with option. Also, ensure that there power your board XChecker cable. Check connections. Make sure RS-232 connector firmly attached.
Error 121: Cable datafile file_name empty.
Reset command with option. Make sure that XACT environment variable points XACT directory workstations, XACT directory equivalent "Xilinx_Directory" referenced installation notes).
Error 122: Cable datafile file_name invalid format.
workstations, XACT directory equivalent "Xilinx_Directory" referenced installation notes.
Error 122: Can't open cable datafile file_name.
workstations XACT directory equivalent "Xilinx_Directory" referenced installation notes.
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Error Messages
Error 123: XChecker cable connected port portname.
Ensure that there power your board XChecker cable. must connect ground test fixture, using cable draws power from your target system, from host computer. Ensure that RS-232 connector firmly attached.
Error 124: XChecker cable connected system.
Ensure that there power your board cable. must connect ground test fixture, using XChecker draws power from your target system, from host computer. Ensure that RS-232 connector firmly attached.
Error 125: Fail reading cable status.
using Reset command with cable option. Ensure that there power your board cable. Check connections.
Error 126: Unsupported command this cable.
Interactive Mode Commands section valid with XChecker cable. using previous parallel serial download cables, only Load command download.
Error 128: Read only number bits received.
Check connections. Check noise that induced into your target system from your target system into XChecker connections. cable extensions. XChecker cable length tested produce minimal noise levels. Remember that logic High must 80-100% Logic must 0-25% VCC.
Error 130: Invalid baud rate. Current baud rate baud rate.
Table valid baud rates your computer.
Error 131: Missing baud rate. Current baud rate baud rate.
Interactive Mode Commands section Chapter correct command usage.
Error 134: Cannot communicate with port port name.
Check this manual supported ports. Port command.
EZTag User Guide
Error Messages
Error 135: Invalid port name port name.
Refer Table supported ports. Port command.
Error 141: Datafile file_name empty.
specified datafile either empty contains invalid data. EZTag supports only JEDEC format.
Error 142: Datafile file_name found.
file_name file does exits current directory search path. Check your environment search path make sure that contains directory where file_name
Error 143: Can't open datafile file_name.
file file_name does exits current directory search path. Check your environment search path make sure that contains directory where file_name located.
Error 220: part type defined.
part type specified your design (using Part command) invalid. Check Programmable Logic Data Book valid part types packages.
Error 1001: Unable execute erase command address string instance string.
specified device instance could erased. Check data protect enabled this disables erase functionality. Also check integrity cable connections.
error 1003: Unable program addresses instance string.
specified device instance could programmed. Check data protect data security enabled this disables programming functionality. data security enabled, first issue "erase" command then execute program command. Also check integrity cable connections.
error 1004: Verification instance string against program file string failed.
specified device instance could verified. Check data security enabled this disables readback functionality. this case, check integrity cable connections. error persists have part Xilinx customer service
Xilinx Development System
Error Messages should contacted.
Error 1005: Unable program address string instance string with data string.
specified device instance could programmed. Check data protect data security enabled this disables programming functionality. data security enabled, first issue "erase" command then execute program command. Also check integrity cable connections.
error 1006: Unable verify address string instance string against data string.
specified device instance could verified. Check data security enabled this disables readback functionality. this case, check integrity cable connections. error persists have part Xilinx customer service should contacted.
error 1011: Verification failed address value instance string. Expected: value. Read: value.
specified device instance could verified. Check data security enabled this disables readback functionality. this case, check integrity cable connections. error persists have part Xilinx customer service should contacted.
Error 1014: description device named string been supplied. Please make sure that BSDLdescription loaded this device. Error 1015: description instance named string device been supplied. Please make sure that JTAG connection description supplied this device.
Check that specified part exists boundary-scan chain that declared your "part" command. "part" command will override previously specified one. current "part" database displayed typing "part" followed carriage return.
Error 1017: boundary scan chain instruction register sequence incorrect value. This corresponds scan chain break near part string.
Verification integrity boundary-scan chain failed. Check
EZTag User Guide
Error Messages cable connections "part" command specification current "part" database displayed typing "part" followed carriage return.
Error 1018: multi-part boundary scan chain, name particular boundary scan part instance which operate must specified. Please retry this command with instance name specified.
must specify particular instance upon which operated. Respecify command with that information. That specify "erase instanceName" "erase".
Error 1021: Unable execute erase command instance string
specified device instance could erased. Check data protect enabled this disables erase functionality. Also check integrity cable connections.
Error 1022: Unable execute functional test command using vectors JEDEC file string. Error 1023: Functional test vectors failed instance string. Error 1024: Functional test vector value failed instance string number value. Expected output value: value Actual output value: value
When running functional test using INTEST instruction, applied functional vectors mismatched predicted values. This either functional error design error vectors specified. This will also occur when vectors targetted different design applied. Re-check integrity your design database information.
error 1025: Mismatched address values during verification instance string. Check JEDEC file cable connections. Expected addressvalue: value. Read: value.
specified device instance could verified. Check data security enabled this disables readback functionality. this case, check integrity cable connections. error persists have part Xilinx customer service should contacted.
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Error Messages
Error 1026: Illegal IDCODE read from device identification register instance string. IDCODE value: string
IDCODE read from specified part does conform 1149.1 standard. This often result cable connection. Check integrity cable connection.
Error 1028: Error reading data value from address string device string while calculating checksum. Error 1029: Data integrity errors while reading data values from device string will result incorrect checksum.
While reading back data calculate checksum, errors occured. Check data security enabled this disables readback functionality. this case, check integrity cable connections. error persists have part Xilinx customer service should contacted.
Error 1030: Unable program data protect address string device string. Error 1031: Programming failures when programming data protect bits device string. Error 1032: Unable program data security address string device string. Error 1033: Programming failures when programming data security bits device string.
specified device instance could programmed. Check data protect data security already enabled this disables programming functionality. data security enabled, first issue "erase" command then execute program command. Also check integrity cable connections.
Error 1034: Error reading data value from address string device string while generating JEDEC file. Error 1035: Data integrity errors while reading data values from device string will result incorrect incomplete JEDEC file.
While reading back data generate JEDEC file, errors occured. Check data security enabled this disables readback functionality. this case, check integrity cable connections. error persists have part
EZTag User Guide
Error Messages Xilinx customer service should contacted.
Error 1036: Xchecker configuration file boundaryscan driver found. Check XACT path setting locate file named `xckjtag.sys'.
When Xchecker reconfiguration file xckjtag.sys found loaded correctly above messages displayed. Check that your XACT path includes release "data" directory that file "xckjtag.sys" exists Also, check integrity connections xchecker cable both serial port target system.
Warning 1037: Data protection enabled instance string (NOTE: device programming contents cannot altered).
This warning message issued when data protect enabled. displayed with each operation addressing this device.
Warning 1038: Data security enabled instance string (NOTE: device programming contents cannot read).
This warning message issued when data security enabled. displayed with each operation addressing this device.
Error 1039: device string Xilinx part (IDCODE: string) Error 1040: device string XC9500 part (IDCODE: string) Please verify specification order parts boundary-scan chain. Error 1041: device string XC95108 part (IDCODE: string). Please verify specification order parts boundary-scan chain. Error 1042: device string currently supported XC9500 part (IDCODE: string) Please verify specification order parts boundary-scan chain.
These messages displayed when software identifies that specified operation targetting improper device. Check that specified part exists boundary-scan chain that declared your "part" command. "part" command will override previously specified one. current "part" database displayed typing "part" followed carriage return.
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Error Messages
Error 1043: JEDEC file string device type string. specified part string actually string device. Please re-generate your JEDEC file. Error 1044: specified part string type string which JEDEC files cannot generated.
These messages displayed when software identifies that specified JEDEC file associated with instance supported device does match specified device. Check that specified part exists boundary-scan chain that declared your "part" command. "part" command will override previously specified one. current "part" database displayed typing "part" followed carriage return.
Error 1046: checksum calculated reading programmed device values differs from expected result.
While reading back data calculate checksum, errors occured. Check data security enabled this disables readback functionality. this case, check integrity cable connections. error persists have part Xilinx customer service should contacted.
Error 1047: Xchecker re-configuration file boundary-scan driver completed. Check XACT path setting, cable connections version file named `xckjtag.sys'.
When Xchecker reconfiguration file xckjtag.sys found loaded correctly above message displayed. Check that your XACT path includes release "data" directory that file "xckjtag.sys" exists Also, check integrity connections xchecker cable both serial port target system.
Error 1048: device string XC95216 part (IDCODE: string) Please verify specification order parts boundary-scan chain.
This message displayed when software identifies that specified operation targetting improper device. Check that specified part exists boundary-scan chain that declared your "part" command. "part" command will override previously specified one. current "part" database displayed typing "part" followed carriage return.
EZTag User Guide
A-11
Index
Symbols
+3-V adapter,
header connectors, 2-5, HIGHZ,
boundary scan, 1-1, 1-5, BSDL, BYPASS, bypass,
IDCODE, IEEE 1149.1, instruction register, INTEST, ISPEN,
checksum,
JEDEC, 1-7,
data protection, data registers, data security, data transfer, 1-4,
manufacturer's modifications,
erase, EXTEST,
programming,
FastFLASH, 1-5, feedback, FERASE, flying lead connectors, 2-5, 2-10 FPGM, functional test, FVFY, readback,
SAMPLE/PRELOAD, security, signature,
EZTag User Guide
index
controller, 1-2, controller states, TCK, TDI, TDO, test access port, testing, TMS,
USERCODE,
verify,
XChecker baud rates, cable connections, 2-5, 2-6, 2-10 communications guidelines, 4-13 connecting cable, connecting download, 2-7, 2-11 connecting host system, connecting target system, 2-5, connecting control signals ground, 4-14 downloading, files used, hardware, improper connections, 4-14 invoking, options command line, displaying help, executing batch file, specifying part type, specifying port names,
verifying download readback, interactive mode displaying help, displaying option settings, executing batch file, exiting XChecker, 4-7, 4-8, naming screen output file, resetting internal logic, saving option settings, 4-11 saving screen output file, specifying baud rate, specifying download/readback port, 4-10 specifying part type, 4-9, 4-10 suspending XChecker, 4-12 verifying target bitstream, 4-12 verifying configuration,
Xilinx Development System

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