XC6200 Development System January 1998 (Version 1.2) Table C
|
|
|
Top Searches for this datasheet
XC6200 Development System
January 1998 (Version 1.2)
Table Contents
FEATURES DESCRIPTION. ARCHITECTURE MODES OPERATION MODE 6200, 6200 RAM. MODE RAM. MODE 6200 RAM. MODE 6200 MODES: SRAM INTERFACE. 6200 INTERFACE 6200 INTERFACE. READ 6200 IOBS CLOCKING PROGRAMMABLE CLOCK GENERATOR PROGRAMMABLE REFERENCE CLOCK CONVERTER INTERRUPT LOGIC. EXPANDABILITY. SERIAL DOWNLOAD. 6200 SERIAL DOWNLOAD SUPPORT SOFTWARE REFERENCES. APPENDIX MEMORY APPENDIX SPACE REGISTER SUMMARY APPENDIX XC6200 DESCRIPTIONS XC6200 PINOUTS WEST SIDE. XC6200 PINOUTS SOUTH SIDE. XC6200 PINOUTS EAST SIDE XC6200 PINOUTS NORTH SIDE APPENDIX MEZZANINE CONNECTOR PINOUT
January 1998 (Version 1.2)
MEZZANINE PINOUT MEZZANINE PINOUT MEZZANINE PINOUT MEZZANINE PINOUT MEZZANINE PINOUT
January 1998 (Version 1.2)
XC6200 Development System
Features
Based Development System Upto User Programmable Gates fast SRAM Monitoring Xilinx 6200 Flexible clock generation Xilinx 6200
Expansion Mezzanine connectors standard prototyping board
Plug Play Compliant Hardware implements XC6200 Compute Element Reference Design Device Driver interface board implements standard Application Binary Interface First affordable FPGA Coprocessor platform medium volume applications Debugger software supports validation XC6200 based designs reduces time market
Xchecker Serial Download SRAM Conv Switches PROM 4013 PROM 6200 SRAM
Xilinx 6216
Multiplexers Mezzanine Pins SRAM Clocking
Xilinx 4013E
SRAM
Switches
Connector
Figure Board layout
January 1998 (Version 1.2)
Description
XC6200 development system (XC6200DS) high performance based input/output coprocessor Win95 WinNT based PC's. XC6200DS supports time-to-volume advantages XC6200 FPGA family four ways. XC6200DS cuts verification time complex designs implementing test harness into which real data (e.g. graphics images) loaded results displayed analyzed using host Conventional logic simulators orders magnitude slow support this application generation test vectors unwieldy time consuming. XC6200DS allows development software proceed parallel with FPGA logic design design printed circuit board. Xilinx supplies drivers plug play software which simplifies development based applications. XC6200DS boards supplied product final customers used volume demonstration platform until market demand justifies custom board design application. XC6200DS schematics, layout, 6200 FPGA design files support software source made available developer support package used basis customer products.
XC6200DS realises hardware software standard XC6200 based algorithm accelerators. supporting minimum feature specified hardware standard implementing driver software specified software standard, hardware vendors guaranteed that their systems compliant applications. standard allows third party developers create `shrink wrapped' applications consisting FPGA configurations host code within single Microsoft Windows executable file.
Memory
Reconfig. FPGA
Local Memory
Display
Network
Disk
Figure FPGA Coprocessor
January 1998 (Version 1.2)
XC6200 Development System
Architecture
Xilinx 6200 development system consists Xilinx 4013E compute element. compute element consists Xilinx 6200 FPGA four 8-bit wide SRAM's controller chips control data flow. Figure shows primary components architecture. Xilinx 4013E FPGA used interface. Approximately chip used this function remaining area used card control logic. XC4013E electrically functionally 100% compliant. details interface logicore product description which available separately from Xilinx primary component compute element Xilinx 6216. board architecture allows XC6200 reconfigured through interface during run-time. interface provides direct access from host logic cells within user's circuit. output cell's function unit read flip-flop within cell written through interface. compute element memory organised into banks. Each bank consists maximum 512K SRAM's. bank accessed from either Interface XC6200. banks memory have separate address busses four read/write signals control RAMs individually. development system provides flexible architecture order implement wide variety algorithms. Multiple modes operation set-up selecting muxes switch desired manner. These modes described detail following section (Modes Operation). 44-bit external data path available XC6200 Input Output Blocks (IOB's). This data path used attach daughter boards video I/O, network connections, sensor I/O.
WA[19:0] EA[19:0] SRAM ED[31:0] SRAM
Xilinx 6200
WD[31:0]
SRAM
Data
SRAM
Address Xilinx 4013E
Figure Board Architecture
Interface
January 1998 (Version 1.2)
Modes Operation
development system configured operate with regards memory reads writes many different configurations. Some possible configurations outlined below.
Mode 6200, 6200
Data Data Interface Address Xilinx 6216 Address
Local Memory Bank
Bank
Figure Mode Configuration
Single 32-bit read write local memory from 6216 address both banks memory Concurrent local memory accesses reconfigure logic 6216 while still processing data from local memories store data into 6216 registers access data from local memories
Mode
Address Local Memory Bank Interface Xilinx 6216 Bank Data
Figure Mode Configuration Single 32-bit read write local memory from address both banks memory 6216 address data disabled
January 1998 (Version 1.2)
XC6200 Development System
Mode 6200
Data Interface Xilinx 6216 Address
Local Memory Bank
Bank
Figure Mode Configuration Single 32-bit read write local memory from 6216 address both banks memory store data into 6216 registers access data from local memories
Mode 6200
Data Interface Xilinx 6216
Local Memory Bank
Address Bank
Data Address
Data Address Local Memory Bank Interface Xilinx 6216 Data Address Bank
Figure Mode Configuration bank memory filled interface other bank read from 6216 that real-time image processing performed address generated from 4013E from 6216
January 1998 (Version 1.2)
Modes: Separate read/write control signals each memory chip.
SRAM Interface
SRAM [Ref. PCI/6200 Evaluation Board mapped transparently into region memory address space. address mapped East Address EA[19:0] (see Figure follows: EA[19:0] PCI_ADDRESS[21:2] mapping bytes within data AD[31:0] West Data WD[31:0] follows: AD[7:0] corresponds WD[7:0] AD[15:8] corresponds WD[15:8] AD[23:16] corresponds WD[23:16] AD[31:24] corresponds WD[31:24] SRAM access interface Xilinx 6200 controlled switches which enabled Bank Control register. Bank Control Register, used effectively split on-board SRAM into independent 16-bit banks. Each bank then owned (i.e. controlled) either Interface (4013) 6200. Control particular bank defined ownership address, data control signals SRAM chips bank question. During SRAM access interface, switches enabled then West Data WD[31:0] connected East Data ED[31:0].
Bank Control Register (2Ch) 6200 owns bank 6200 owns bank
When bank controlled interface, data from interface that bank held high impedance, allowing 6200 drive Conversely, user PCI/6200 board must ensure that when 6200 does particular bank, must attempt drive data that bank. When 6200 owns both banks, writes SRAM from will return undefined data. arrangement data host's memory, when performing transfer from SRAM, depends current value Bank Control Register. Bank1 controls data bits[15:0] Bank2 controls data bits [31:16]:-
January 1998 (Version 1.2)
XC6200 Development System
Bank owned 6200 6200
Bank owned 6200 6200
Data arrangement host memory Bank data Bank data undefined Bank data Bank data undefined undefined undefined
6200 Interface
6200 Interface 6200 register read/write mechanism supported interface, mapped into region memory address space. address mapped East Address EA[19:0] (and therefore address 6200 register read/write interface) follows: EA[19:0] PCI_ADDRESS[21:2] mapping bytes within data AD[31:0] West Data WD[31:0] follows: AD[7:0] corresponds WD[7:0] AD[15:8] corresponds WD[15:8] AD[23:16] corresponds WD[23:16] AD[31:24] corresponds WD[31:24] Bank Control Register effect 6200 accesses. 6200 reset, RESET# pin, cleared, GCLR pin, writing Reset Register. write this register cause either, both, none these signals asserted single clock cycle (therefore, >30ns): CLEAR RESET
Reset Register (10h) Assert RESET# clock Assert GCLR clock
Read 6200 IOBs thirty-two IOBs 6200 connected directly pins Interface, read asynchronously with respect design running 6200. They useful monitoring 6200 without disturbing state, example. thirty-two IOBs read simultaneously performing read Register.
DA15
CON8
CON1
Register (20h) CON[8:1] DA[15:0] DB[7:0]
January 1998 (Version 1.2)
Clocking
Clock signals XC6200 timing board memory accesses generated from board based clock chip controlled from XC4013E. There various optional methods which board clock signal generated. these methods pass clock signal board programmable clock generator chip which then generates appropriate clocking frequency 6200 rest board. Three main sources clock signals available: board crystal oscillator external clock signal from mezzanine connectors clock 6200 also single stepping mode where each clock transition initiated host software access. Programmable Clock Generator PCI/6200 Evaluation Board allows 6200 what termed `continuous clock mode' `single clock mode'. continuous clock mode, global clock driving 6200 simply continuously. single clock mode, global clock stopped, individual clock pulses individual trains clock pulses sent 6200, under control user's software. PCI/6200 board into continuous clock mode reset, performing write (with dummy data) specific location space. board into single clock mode, write made another location space. Once board single clock mode, user send trains clock pulses 6200 writing values Step Register. value written Step Register unsigned 16-bit integer, representing number clock pulses send 6200.
Step Register (28h)
Number clocks
sequence clock pulses, E_STEP Event Status Register high, remaining high until acknowledged, optionally, interrupt caused host. When 6200 read performed while board single clock mode, three 6200 clock pulses required. required data read third switching data bus. 6200 write requires minimum clock pulses. These accesses never cause interrupt, alter Event Status Register.
January 1998 (Version 1.2)
XC6200 Development System
Programmable Reference clock well stopping starting 6200 clock, PCI/6200 Evaluation Board permits clock frequency range 1MHz 33MHz sent XC6200 global clock. singlebit register allows configuration clock generator chip bit-serial mode. Refer data sheet ICD2053B details bitstream format SDATA
Clockgen Register (14h) Serial Data
programmable clock chip used derive 6200 clock requires reference clock. registers shown below used determine which reference clock frequency used.
Ref. Registers (3Ch) On-board oscillator Clock External clock
Converter
purpose converter monitor power supply current (IDD) XC6200. power consumption exceeds preset value XC4013E will reset enabled) XC6200, clearing faulty user configuration. Users also monitor power consumption software help track down less dramatic intermittent faults their designs evaluate power consumption different 6200 designs. Circuitry PCI/6200 board measures supply current drawn 6200. Read Register eight register space which returns last reading made analogue-to-digital converter. equation converting readings supply current values follows: (ADC reading) ~5.0 (mA) times, last reading from analogue-to-digital converter available Read Register unsigned eight value:
Read Register (24h)
Reading
January 1998 (Version 1.2)
host interrupted when 6200 supply current exceeds user-programmable threshold. addition, 6200 automatically reset when this event occurs. Threshold Register written with value consisting
unsigned eight threshold value, single flag, which true, causes 6200 reset when threshold exceeded.
RSTEN
Threshold Register (24h)
Threshold Reset Enable
threshold exceeded when reading exceeds threshold value written into Threshold Register. When exceeded, E_ADC Event Status Register high, remains high until acknowledged, even current falls below threshold.
Interrupt Logic
There three possible sources interrupts from PCI/6200 Evaluation Board:
last clock pulse sequence been sent 6200. 6200 requests interrupt. 6200 supply current threshold exceeded.
Each above events masked using Event Mask Register. event cause interrupt host when corresponding Event Mask When event cause interrupt host. disable interrupts entirely, Event Mask Register should written with
6200
STEP
Event Mask Register (34h) enable clock enable 6200 enable current threshold
Whether masked not, event status available Event Status Register. Even masked Event Mask Register, when 6200 requests interrupt, example, corresponding will Event Status Register. addition, masked event status available Event Status Register, which consists bitwise product detected events Event Mask. 6200 requests interrupt host pulsing signal CON8 low. interface senses falling edge this signal, sets E_6200 Event Status Register. Provided that masked Event Mask Register, I_6200 will also set.
January 1998 (Version 1.2)
XC6200 Development System
C_OK I_ADC I_6200 I_STEP
E_ADC E_6200 E_STEP
Event Status Register (30h) clock 6200 Current threshold clock event 6200 event Current threshold event Level CONFIG_OK
C_OK simply level signal CONFIG_OK from 6200, discussion below does apply this flag. Those bits prefixed with denote event) appear Event Status Register regardless Event Mask Register. Those bits prefixed with denote interrupt) appear Event Status Register only corresponding event (E_) corresponding Event Mask Register following diagram illustrates relationship between event bits interrupt bits:
Event Mask Register
M_ADC M_6200 M_STEP
I_STEP Clock step event
I_6200 6200 event
I_ADC threshold event
E_STEP
E_6200
E_ADC
CONFIG_OK
C_OK
January 1998 (Version 1.2)
Once event occurred, order clear event condition Event Status Register, necessary acknowledge performing write Event Acknowledge Register. Writing particular clears event condition associated with that bit. written particular effect.
A_ADC A_6200 A_STEP
Event Acknowledge Register (38h) acknowledge clock event acknowledge 6200 event acknowledge current threshold event
Expandability
Access complete range board signals busses provided through five mezzanine connectors. Details mezzanine pinouts found Appendix User defined designs connected mezzanine connectors allowing complete configurability testing design through bus. mezzanine connectors also used connect several XC62000DS boards together create high performance system. Xilinx chips daughter boards have their configuration loaded slaves from XC62000DS. XCHECKER connector supports Xilinx XCHECKER XC4000 JTAG circuitry.
Serial Download
PROM chips allow complete configuration XC4013 XC6200 chips. XC4013 prom configures XC4013E-2 power-up, whereas XC6200 prom initiated interface. Given suitable configuration XC4013E Flash device power source development system operate outside host computer. 6200 Serial Download PCI/6200 Evaluation Board initiates 6200 Serial download asserting XC6200 Serial line then negating signal after SECE line negated i.e. completion serial download sequence. single-bit register used store value Serial line. register defaults (negated) power-up. Note. Con7/Seclk, Con4/Sereset Con3/SECE dual purpose pins (Serial download control signals general purpose output pins). Therefore, users design must reframe from configuring pins general purpose outputs when using 6200 Serial Download feature.
Serial-
Dwnload Register (38h) Serial
January 1998 (Version 1.2)
XC6200 Development System
Support Software
XC6200DS supplied with; win95 winNT device driver, level class function software level graphical user interfaces. device driver supports standard interface XC6200 board provides easy access XC6200 device XC4013. This interface allows easy reconfiguration registers, board memory, processing interrupts etc. device driver uses FASTmap interface transfer user logic XC6200 device. Additional non-standard support provided with monitoring on-board power consumption availability single stepping clock mode allowing easy debugging XC6200 device. graphical user interface WebScope provides complete real-time debugging interface XC6200DS. graphical display allows complete access XC6200 device giving both graphic display logic values cell outputs symbolic display logic groups cells. Through WebScope interface complete real-time simulation design undertaken matter seconds compared with hours involved real-time standard simulation. user interface PCITEST provides complete debugging interface XC6200DS. PCITEST provides; command line interface board, graphical register display XC6200DS features command file capability. typical design flow shown figure
Figure XC6200 Logic Design Flow
January 1998 (Version 1.2)
References
Cypress Programmable Clock Generator ICD2053B August 1994 Revised 1995. Xilinx XC6200 Field Programmable Gate Arrays DataSheet April 1997 -Version 1.10 Xilinx Programmable Logic Data Book 1996. Xilinx LogiCore Master Slave Interface User's Guide July 1996 Version National Semiconductor ADC0804 8-bit compatible converters May, 1989. Memory Static 1995 Data Book.
January 1998 (Version 1.2)
XC6200 Development System
Appendix Memory
Space Assignments Offset Type Function Unused Reset Register Clockgen Register Enter continuous clock mode Enter single clock mode Read 6200 IOBs Read Register Threshold Register Step Register Bank Control Register Event Status Register Event Acknowledge Register Event Mask Register XC6200 Serial Download Clock Reference select
Memory Space Assignments Address Type Function Read SRAM Write SRAM 6200 register read 6200 register write
January 1998 (Version 1.2)
Appendix Space Register Summary
CLEAR RESET Reset Register (10h) Assert RESET# clock Assert GCLR clock
SDATA
Clockgen Register (14h) Serial Data
DA15
CON8
CON1
Register (20h) CON[8:1] DA[15:0] DB[7:0]
Read Register (24h)
Reading
RSTEN
Threshold Register (24h)
Threshold Reset Enable
Step Register (28h)
Number clocks
January 1998 (Version 1.2)
XC6200 Development System
Bank Control Register (2Ch) 6200 owns bank 6200 owns bank
A_ADC A_6200 A_STEP
Event Acknowledge Register (30h) acknowledge clock event acknowledge 6200 event acknowledge current threshold event
C_OK
Event Status Register (30h) clock 6200 Current threshold clock event 6200 event Current threshold event Level CONFIG_OK
E_ADC E_6200 E_STEP
I_ADC I_6200 I_STEP
6200
STEP
Event Mask Register (34h) enable clock enable 6200 enable current threshold
Serial-
Dwnload Register (38h) Serial
January 1998 (Version 1.2)
Ref. Registers (3Ch) On-board oscillator Clock External clock
January 1998 (Version 1.2)
XC6200 Development System
Appendix XC6200 Descriptions
XC6200 Pinouts West Side
PinOut
HQ240
XC6200DS
PinOut
HQ240
XC6200DS
D0/W1 D1/W3 D2/W5 D3/W7 D4/W9 D5/W11 D6/W13 D16/W33 D7/W15 D17/W35 D18/W37 D8/W17
WD_0 WA_7 WD_1 WA_8 WD_2 WA_9 WD_3 WA_10 WD_4 WA_11 WA_12 WA_13 WD_5 WA_14 WA_15 WA_16 WD_6 WD_16 WA_17 WD_7 WD_17 WA_18 WD_18 WD_8 WA_19
D19/W39 D9/W19 D20/W41 D21/W43 D10/W21 D22/W45 D24/W49 D11/W23 D23/W47 D25/W51 D12/W25 D26/W53 D27/W55 D13/W27 D28/W57 D14/W29 D29/W59 D15/W31 D30/W61 D31/W63
WD_19 WD_9 WD_20 WD_21 WD_10 WD_22 WD_24 WD_11 WD_23 WD_25 WD_12 WD_26 WD_27 WD_13 WD_28 WD_14 WD_29 WD_15 WD_30 WD_31
January 1998 (Version 1.2)
XC6200 Pinouts South Side
PinOut
HQ240
XC6200DS
PinOut
HQ240
XC6200DS
RdWr/S1 CS/S3 W12/S0 OE/S5 W10/S2 Reset/S7 W8/S4 W6/S6 W4/S8 W2/S10 W0/S12 Serial/S9 Wait/S11 GClk/S13 GClr/S15
RDWR# WA_6 WA_5 RESET# WA_4 WA_3 WA_2 WA_1 WA_0 6K_WE1# 6K_WE2# 6K_WE3# 6K_WE4# SERIAL# WAIT 6K-OE1# 6K-OE2# GCLK 6K-OE3# GCLR LED1 6K-OE4# LED2
G1/S17 G2/S19 E0/S50 E2/S52 E4/S54 ShiftDOut/S21 SEData/S23 E6/S56 E8/S58 E10/S60 E12/S62 SECE/S25 SEReset/S27 SEClk/S29 ConfigOK/S31
P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120
ED_0 ED_1 ED_2 SEDATA ED_3 ED_4 CON1 CON2 ED_5 ED_6 CON3 CON4 CON5 CON6 CON7 C_OK CON8
January 1998 (Version 1.2)
XC6200 Development System
XC6200 Pinouts East Side
PinOut
HQ240
XC6200DS
PinOut
HQ240
XC6200DS
A0/E1 A1/E3 A2/E5 A3/E7 A4/E9 A5/E11 A16/E33 A17/E35 A6/E13 A7/E15
P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150
ED_7 EA_0 ED_8 EA_1 ED_9 EA_2 ED_10 EA_3 ED11 ED12 ED13 EA_4 ED_14 ED_15 ED_16 EA_5 EA_16 ED_17 EA_17 EA_6 ED_18 EA_18 ED_19 EA_7 EA_19
A8/E17 A9/E19 A10/E21 A11/E23 A12/E25 A13/E27 A14/E29 A15/E31
P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180
EA_8 ED_20 EA_9 ED_21 ED_22 EA_10 ED_26 ED_23 ED_28 EA_11 ED_24 ED_25 EA_12 ED_27 ED_29 ED_30 EA_13 ED_31 EA_14 EA_15
January 1998 (Version 1.2)
XC6200 Pinouts North Side
PinOut
HQ240
XC6200DS
PinOut
HQ240
XC6200DS
P240 P239 P238 P237 P236 P235 P234 P233 P232 P231 P230 P229 P228 P227 P226 P225 P224 P223 P222 P221 P220 P219 P218 P217 P216 P215 P214 P213 P212 P211
P210 P209 P208 P207 P206 P205 P204 P203 P202 P201 P200 P199 P198 P197 P196 P195 P194 P193 P192 P191 P190 P189 P188 P187 P186 P185 P184 P183 P182 P181
DA10 DA11 DB10 DB11 DB12 DB13 DA12 DA13 DB14 DB15 DA14 DA15
January 1998 (Version 1.2)
XC6200 Development System
Appendix Mezzanine Connector Pinout
Mezzanine Pinout Pin# SignalName C25/TCK C22/INTB# C14/BUSMODE1# C24/INTD# G2/CLK C28/REQ# 5V/V(I/O) DB12/AD[28] DB9/AD[25] DB6/AD[22] DB3/AD[19] 5V/V(I/O) C4/FRAME# C10/DEVSEL# C30/SDONE# C8/PAR 5V/V(I/O) DA12/AD[12] DA9/AD[09] DA6/AD[06] DA4/AD[04] 5V/V(I/O) DA2/AD[02] DA0/AD[00] SignalName -12V C21/INTA# C23/INTC# PCI-RSVD* PCI-RSVD* C12/GNT# DB15/AD[31] DB11/AD[27] C3/C-BE[3]# DB5/AD[21] DB1/AD[17] C6/IRDY# C11/LOCK# C29/SBO# DA15/AD[15] DA11/AD[11] C0/C-BE[0]# DA5/AD[05] DA3/AD[03] DA1/AD[01] C31/REQ64# Pin#
January 1998 (Version 1.2)
Mezzanine Pinout
Pin#
Signal Name C26/TMS C18/TDI PCI-RSVD* C15/BUSMODE2# C20/RST# 3.3V PCI-RSVD* DB14/AD[30] DB8/AD[24] C13/IDSEL 3.3V DB2/AD[18] DB0/AD[16] C5/TRDY# C9/PERR# 3.3V C1/C-BE[1]# DA14/AD[14] DA8/AD[08] DA7/AD[07] 3.3V PCI-RSVD PCI-RSVD C32/ACK64#
Signal Name C27/TRST# C19/TDO PCI-RSVD* PCI-RSVD* 3.3V C16/BUSMODE3# C17/BUSMODE4# DB13/AD[29] DB10/AD[26] 3.3V DB7/AD[23] DB4/AD[20] C2/C-BE[2]# PCI-RSVD 3.3V C7/STOP# C_OK/C_OK DA13/AD[13] DA10/AD[10] 3.3V PCI-RSVD PCI-RSVD PCI-RSVD PCI-RSVD 3.3V PCI-RSVD
January 1998 (Version 1.2)
XC6200 Development System
Mezzanine Pinout Pin# Signal Name PCI-RSVD* BANK1_SEL/C-BE[6]# LED1/C-BE[4]# 5V/V(I/O) WD_31/AD[63] WD_29/AD[61] WD_27/AD[59] WD_25/AD[57] 5V/V(I/O) WD_23/AD[55] WD_21/AD[53] WD_19/AD[51] WD_17/AD[49] WD_15/AD[47] WD_13/AD[45] 5V/V(I/O) WD_11/AD[43] WD_9/AD[41] WD_7/AD[39] WD_5/AD[37] WD_3/AD[35] WD_1/AD[33] 5V/V(I/O) PCI-RSVD* PCI-RSVD* Signal Name ED_16/C-BE[7]# BANK2_SEL/C-BE[5]# LED2/PAR64 WD_30/AD[62] WD_28/AD[60] WD_26/AD[58] WD_24/AD[56] WD_22/AD[54] WD_20/AD[52] WD_18/AD[50] WD_16/AD[48] WD_14/AD[46] WD_12/AD[44] WD_10/AD[42] WD_8/AD[40] WD_6/AD[38] WD_4/AD[36] WD_2/AD[34] WD_0/AD[32] PCI-RSVD* PCI-RSVD* Pin#
January 1998 (Version 1.2)
Mezzanine Pinout Pin# Signal Name ED_7 ED_5 ED_3 ED_1 WA_19 WA_17 WA_15 WA_13 WA_11 WA_9 WA_7 WA_5 WA_3 WA_1 EA_19 EA_17 EA_15 EA_13 EA_11 EA_9 EA_7 EA_5 EA_3 EA_1 ED_31 ED_29 ED_27 ED_25 ED_23 ED_21 ED_19 ED_17 Signal Name ED_6 ED_4 ED_2 ED_0 WA_18 WA_16 WA_14 WA_12 WA_10 WA_8 WA_6 WA_4 WA_2 WA_0 EA_18 EA_16 EA_14 EA_12 EA_10 EA_8 EA_6 EA_4 EA_2 EA_0 ED_30 ED_28 ED_26 ED_24 ED_22 ED_20 ED_18 Pin#
January 1998 (Version 1.2)
XC6200 Development System
Mezzanine Pinout Signal Name 6K_WE3# 6K_WE1# 6K_OE3# 6K_OE1# CLKIN WAE0# OE3# OE1# CS3# CS1# WE3# WE1# BE3# BE1# WAIT CON8 CON6 CON4 CON2 ED_15 ED_14 GCLK ED_11 ED_9 RESET# Signal Name 6K_WE4# 6K_WE2# 6K_OE4# 6K_OE2# DONE WAE1# OE4# OE2# CS4# CS2# WE4# WE2# BE4# BE2# SEDATA GCLR SERIAL# CON7 CON5 CON3 CON1 ED_13 ED_12 ED_10 ED_8 RDWR# 5V-CLC
January 1998 (Version 1.2)
Other recent searches
WE128K32-XG2TXE - WE128K32-XG2TXE WE128K32-XG2TXE Datasheet
uPD78F0114 - uPD78F0114 uPD78F0114 Datasheet
TES-5WI - TES-5WI TES-5WI Datasheet
DF7A6 - DF7A6 DF7A6 Datasheet
BTD2150AM3 - BTD2150AM3 BTD2150AM3 Datasheet
BD317 - BD317 BD317 Datasheet
BAW56N3 - BAW56N3 BAW56N3 Datasheet
2SC5550 - 2SC5550 2SC5550 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
