X2845 Fitting Your Design Xilinx Synopsys Interface EPLD Use
|
|
|
Top Searches for this datasheet
Getting Started with Xilinx EPLDs Designing with EPLDs Compiling Your Design
X2845
Fitting Your Design
Xilinx Synopsys Interface EPLD User Guide
Simulating Your Design EPLD Architecture Library Component Specifications Attributes
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Xilinx Synopsys Interface EPLD User Guide
XACT, XC2064, XC3090, XC4005, XC-DS501 registered trademarks Xilinx. XC-prefix product designations, XACT-Performance, XAPP, X-BLOX, XChecker, XDM, XDS, XEPLD, XFT, XPP, XSI, BITA, Configurable Logic Cell, CLC, Dual Block, FastCLK, HardWire, LCA, Logic Cell, LogicProfessor, MicroVia, PLUSASM, UIM, VectorMaze, ZERO+ trademarks Xilinx. Programmable Logic Company Programmable Gate Array Company service marks Xilinx. registered trademark PC/AT, PC/XT, PS/2 Micro Channel trademarks International Business Machines Corporation. DASH, Data FutureNet registered trademarks ABEL, ABEL-HDL ABELPLA trademarks Data Corporation. SimuCad Silos registered trademarks P-Silos P/CSilos trademarks SimuCad Corporation. Microsoft registered trademark MS-DOS trademark Microsoft Corporation. Centronics registered trademark Centronics Data Computer Corporation. PALASM registered trademarks Advanced Micro Devices, Inc. UNIX trademark AT&T Technologies, Inc. CUPL trademark Logical Devices, Inc. Apollo AEGIS registered trademarks Hewlett-Packard Corporation. Mentor IDEA registered trademarks NETED, Design Architect, QuickSim, QuickSim EXPAND trademarks Mentor Graphics, Inc. registered trademark Microsystems, Inc. SCHEMA SCHEMA trademarks Omation Corporation. OrCAD registered trademark OrCAD Systems Corporation. Viewlogic, Viewsim, Viewdraw registered trademarks Viewlogic Systems, Inc. CASE Technology trademark CASE Technology, division Teradyne Electronic Design Automation Group. DECstation trademark Digital Equipment Corporation. Synopsys registered trademark Synopsys, Inc. Verilog registered trademark Cadence Design Systems, Inc. Xilinx does assume liability arising application product described herein; does convey license under patents, copyrights, maskwork rights rights others. Xilinx, Inc. reserves right make changes, time, order improve reliability, function design supply best product possible. Xilinx, Inc. cannot assume responsibility circuitry described herein other than circuitry entirely embodied products. Xilinx products protected under least following U.S. patent: 5,224,056. Xilinx, Inc. does represent that Xilinx products free from patent infringement from other third-party right. Xilinx assumes obligation correct errors contained herein advise user this text correction such made. Xilinx will liable accuracy correctness engineering software assistance provided user. Xilinx products intended life support appliances, devices, systems. Xilinx product such applications without written consent appropriate Xilinx officer prohibited.
XACT Development System
XEPLD Files Design Example Fitter Reports
X2845
Glossary
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
XACT Development System
Preface
About This Manual
Xilinx Synopsys Interface (XSI) allows implement Xilinx EPLD designs created with Synopsys Design Compiler software. Synopsys synthesis software creates circuit designs from hardware description languages such VHDL Verilog HDL, using component libraries supplied Xilinx XC7000 EPLD family. This manual shows software, along with Synopsys Design Compiler Simulator, create efficient designs Xilinx EPLDs. assumed that familiar with Synopsys software. Please refer Synopsys manuals detailed information Synopsys software.
Manual Contents
following brief overview contents each chapter.
Chapter "Getting Started with Xilinx EPLDs," presents basic EPLD design flow along with brief example. This "road map" showing each step process. Each step explained more detail subsequent chapters. Chapter "Designing with EPLDs," shows architecture specific features Xilinx EPLDs achieve highest performance logic density. should read this chapter before creating your design. Chapter "Compiling Your Design," shows Design Compiler with Xilinx EPLD Synopsys Interface software.
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Xilinx Synopsys Interface EPLD User Guide
Chapter "Fitting Your Design," provides description fitter operation shows select target device, your design into device, create device programming file, save your pinouts design iteration. Chapter "Simulating Your Design," shows perform functional timing simulation your design using Synopsys simulator. Appendix "EPLD Architecture," provides overview XC7000 family along with device selection information Appendix "Library Component Specifications," provides specifications Xilinx components including instantiated, inferable, scalable cells. Appendix "Attributes," provides specifications Xilinx attributes which used control fitting your design. Appendix "XEPLD Files Programs," provides description each file program used Xilinx software. Appendix "Design Example," provides thorough example demonstrating capabilities software. Appendix "Fitter Reports," provides example reports showing type information available design analysis. Appendix "Glossary," provides definitions terms phrases that unfamiliar you.
Xilinx Software Features
Xilinx Synopsis Interface (XSI) following features EPLD design development:
Supports EPLD devices including XC7272 XC7336 XC7318. Design synthesis using Synopsis VHDL Verilog HDL. Design compilation using either Synopsys Design Compiler FPGA Compiler. High-level inferencing operators using EPLD high-speed arithmetic carry chain operands width.
XACT Development System
Preface
VHDL functional simulation original source designs (including XC7000-specific library components). VHDL full-timing simulation (post-fitting) using device port declarations from original source design. Static Timing Report produced XEPLD Fitter (post-fitting). Attributes controlling register initial states. Attributes assigning locations. Attributes allocating logic EPLD Fast Function Blocks Fast Inputs. Attributes controlling XEPLD optimization clocks, input registers, output enable signals, register initial states, UIM-AND functions.
Unsupported Features
currently following limitations EPLD design development:
technology-specific optimization (for speed density) performed Synopsys synthesizer; such optimization performed Xilinx EPLD Translator Core Tool (XEPLD). timing area information contained XC7000 library. Therefore, timing area estimation available from Synopsys Design Compiler. Timing resource utilization results available from XEPLD after completion fitting (fitnet). XEPLD fitter (v5.0) currently does support timingconstraint-driven optimization; Synopsys timing constraints have effect EPLD design processing. Instead, attribute designate EPLD Fast Function Block Fast Input resources. Verilog simulation supported this package.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
XACT Development System
Conventions
following conventions used this manual's syntactical statements: Courier font regular Courier font bold italic font System messages program files appear regular Courier font. Literal commands that must enter syntax statements bold Courier font. Variables that replace syntax statements italic font. Square brackets denote optional items parameters. However, specifications, such [7:0], they required. Braces enclose list items from which must choose more. vertical ellipsis indicates material that been omitted. horizontal ellipsis indicates that preceding repeated more times. vertical separates items list choices. This symbol denotes carriage return.
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Contents
Chapter Getting Started with Xilinx EPLDs
Creating Synopsys Setup Files. Design Compiler Setup File Simulator Setup File (.synopsys_vss.setup) Verifying Your Installation Verifying Synopsys Software Access Verifying Xilinx Software Access Verifying Your File Structure Xilinx EPLD Design Flow Design Example. Design Entry Step1 Create Design Directory Functional Simulation Step Analyze Your Design Step Analyze Your Test Bench Step Invoke Simulator Step Debugger Step Trace Signals. Step Simulation Step Return UNIX Synthesizing Your Design (Compiling) Step Enter Shell Environment. Step Analyze Your Source Design. Step Elaborate Your Design Step Synthesize Your Design Step Place Buffer Cells Step Specify Target Device Step Specify Initial Register States Step Output Netlist Step Exit Shell 1-10 1-10 1-14 1-14 1-15 1-16 1-16 1-16 1-16 1-17 1-17 1-18 1-18 1-18 1-18 1-19 1-19
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Xilinx Synopsys Interface EPLD User Guide
Preparing Netlist Step Create Flattened Netlist Fitting Your Design Step Your Design Timing Backannotation Step Create Static Timing Report Timing Simulation Step Analyze Your Original Design. Step Analyze Your Back-Annotated Design. Step Analyze Your Test Bench Step Invoke Simulator. Step Open Waveform Viewer. Step Simulation Step Return UNIX Programming EPLD Step Program EPLD.
1-19 1-19 1-20 1-20 1-21 1-21 1-21 1-21 1-21 1-22 1-22 1-23 1-24 1-24 1-24 1-25
Chapter
Designing with EPLDs
VHDL Design File Requirements Using Registers Latches Preventing Register/Latch Optimization. Using Input Registers Using Macrocell Registers Using Input Latches. Using Macrocell Latches. Specifying Register/Latch Initial States. Specifying Predefined Initial States Specifying Initial States Individual Registers/Latches Using Ports. Selecting 3-State Control Sources. Assigning Specific Fast Output Enable Signals. Preventing Optimization Using Special Logic Functions Binary Counters. Binary Down Counters Binary Up/Down Counters State Machines Registered Arithmetic Functions Comparators Targeting Specific Device Specifying Device 2-10
viii
XACT Development System
Contents
Using Synopsys Part Attribute Using Xilinx Syn2EPLD Command. Specifying Locations. Controlling Design Performance Using High-Speed Clocks Assigning Specific High-Speed Clocks. Preventing FastCLK Optimization Selecting EPLD Function Block Types Specifying High-Speed Paths Specifying High-Density Paths Using EPLD FastInputs Selecting Low-Power Operation Design Rule Checker. General Design Rule Violations Component Design Rule Violations. FastCLK, Clock Enable, Fast Output Enable Violations
2-11 2-11 2-11 2-12 2-12 2-12 2-13 2-13 2-13 2-13 2-14 2-14 2-14 2-14 2-15 2-15
Chapter
Compiling Your Design
Using Synopsys Shell Step Entering Shell Environment Step Analyzing Design Step Elaborating Design Step Compiling Your Design Step Defining EPLD Signals. Step Specifying Attributes Step Writing Netlist.
Chapter
Fitting Your Design
Fitter Overview. Fitter Operation Step Create Flattened Netlist File Specifying Target Device. Using Target Device Specified Part Attribute Step Your Design Options Step Verify Your Design Timing Step Create Device Programming File. Step Save Your Pinouts
Chapter
Simulating Your Design
Recommended EPLD Simulation Strategy
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Controlling Initial States Registers Simulating Master Reset. Preparing Timing Simulation Preparing Functional Simulation. Creating Test Bench File. Initializing Registers Configuration Declaration Functional Simulation. Design Implementation Preparing Timing Model Timing Simulation.
5-10 5-11
Appendix EPLD Architecture
Device Selection Universal Interconnect Matrix High-Density Function Blocks Shared Private Product Terms. Arithmetic Logic Unit Carry Lookahead (7300 Family Only) Macrocell Flip-Flop. Fast Function Blocks. Product Term Expansion XC7336 XC7318 Fast Function Blocks. Input/Output Blocks. A-10 A-10
Appendix Library Component Specifications
ACC. Inferencing Component Instantiation Truth Table Logic Symbol ADD. Inferencing Component Instantiation Truth Table Logic Symbol ADSU Inferencing Component Instantiation Truth Table Logic Symbol ADSUR. Inferencing Component Instantiation
XACT Development System
Contents
Truth Table Logic Symbol AND2 AND8 Inferencing Component Instantiation Truth Table Logic Symbol BUF. Inferencing Component Instantiation Truth Table Logic Symbol BUFCE. Inferencing Component Instantiation Truth Table Logic Symbol BUFE Inferencing Component Instantiation Truth Table Logic Symbol BUFFOE Inferencing Component Instantiation Truth Table Logic Symbol BUFG Inferencing Component Instantiation Truth Table Logic Symbol CBX1. Inferencing Component Instantiation Truth Table Logic Symbol CBX2. Inferencing Component Instantiation Truth Table Logic Symbol COMPEQ Inferencing Component Instantiation Truth Table Logic Symbol COMPLE_TC COMPLE_US. Inferencing Component Instantiation
B-10 B-10 B-10 B-10 B-11 B-11 B-11 B-11 B-12 B-12 B-12 B-12 B-13 B-13 B-13 B-13 B-14 B-14 B-14 B-14 B-15 B-15 B-15 B-15 B-16 B-16 B-16
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Truth Table Logic Symbol COMPLT_TC COMPLT_US Inferencing Component Instantiation Truth Table Logic Symbol COMPNE Inferencing Component Instantiation Truth Table Logic Symbol DEC. Inferencing Component Instantiation Truth Table Logic Symbol FDCP Inferencing Component Instantiation Truth Table Logic Symbol FDCPE Inferencing Component Instantiation Truth Table Logic Symbol FDPC Inferencing Component Instantiation Truth Table Logic Symbol IBUF Inferencing Component Instantiation Truth Table Logic Symbol Inferencing Component Instantiation Truth Table Logic Symbol IFDX1 Inferencing Component Instantiation Truth Table Logic Symbol ILD. Inferencing Component Instantiation
B-16 B-17 B-17 B-17 B-17 B-18 B-18 B-18 B-18 B-19 B-19 B-19 B-19 B-20 B-20 B-20 B-20 B-21 B-21 B-21 B-21 B-22 B-22 B-22 B-22 B-23 B-23 B-23 B-23 B-24 B-24 B-24 B-24 B-25 B-25 B-25 B-25 B-26 B-26 B-26
XACT Development System
Contents
Truth Table Logic Symbol INC. Inferencing Component Instantiation Truth Table Logic Symbol Inferencing Component Instantiation Truth Table Logic Symbol IOBUFE. Inferencing Component Instantiation Truth Table Logic Symbol IOBUFEX1 Inferencing Component Instantiation Truth Table Logic Symbol Inferencing Component Instantiation Truth Table Logic Symbol OBUF Inferencing Component Instantiation Truth Table Logic Symbol OBUFE. Inferencing Component Instantiation Truth Table Logic Symbol OBUFEX1 Inferencing Component Instantiation Truth Table Logic Symbol OR8. Inferencing Component Instantiation Truth Table Logic Symbol SUBT Inferencing Component Instantiation Truth Table Logic Symbol
B-26 B-27 B-27 B-27 B-27 B-28 B-28 B-28 B-28 B-29 B-29 B-29 B-29 B-30 B-30 B-30 B-30 B-31 B-31 B-31 B-31 B-32 B-32 B-32 B-32 B-33 B-33 B-33 B-33 B-34 B-34 B-34 B-34 B-35 B-35 B-35 B-35 B-36 B-36 B-36 B-36
Xilinx Synopsys Interface EPLD User Guide
xiii
Xilinx Synopsys Interface EPLD User Guide
XOR2 XOR8 Inferencing Component Instantiation Truth Table Logic Symbol
B-37 B-37 B-37 B-37
Appendix Attributes
Global Attributes. LOWPWR MRINPUT. NO_FOE NO_FCLK NO_IFD. PRELOAD. Signal Attributes OPT_OFF OPT_UIM SLEWRATE Synopsys Attributes Part Type Assignment Register Initial State.
Appendix XEPLD Files Appendix Design Example
Interface Design Description.
Appendix Fitter Reports
Resource Report Static Timing Report Combinational Pad-to-Pad Delays. Setup-to-Clock Time Clock-to-Output Delays. Cycle Time Example Timing Report Pin-List Report F-13
Appendix Glossary
XACT Development System
Getting Started with Xilinx EPLDs
X2845
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Chapter
Getting Started with Xilinx EPLDs
This chapter shows prepare your setup files verify your installation. also provides design walk-through overview basic steps implementing Xilinx EPLD designs using Synopsys. remaining chapters this manual provide additional detailed information each step. design walk-through assumes that have installed configured Xilinx software libraries. installation instructions, Xilinx Synopsys Interface Release Notes that accompany this manual.
Creating Synopsys Setup Files
After have installed Xilinx software must configure Synopsys Design Compiler simulator setup files access XC7000 libraries. This section shows configure setup files verify that your setup working properly. setup files must located each design directory where XC7000 designs processed. Note: will find sample setup files $DS401/tutorial/ synopsys/epld.vhd/scan directory. However, before using them, must edit .synopsys_dc.setup file contained tutorial directory typing actual $DS401 path into search_path variable.
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Xilinx Synopsys Interface EPLD User Guide
Design Compiler Setup File
Your Design Compiler setup file (.synopsys_dc.setup) must contain following lines: search path $DS401_path/synopsys/libraries/ syn} link_library {xc7000.db xc7000.sldb} target_library {xc7000.db} symbol_library {xc7000.sdb} synthetic_library {xc7000.sldb} bus_naming_style "%s<%d>" bus_dimension_seperator_style "><" bus_interface_style "%s<%d>" edifout_netlist_only true cell edifout_ground_name edifout_ground_pin_name edifout_power_name edifout_power_pin_name xnfout_library_version "2.0.0" Where $DS401_path actual interface directory path specified $DS401 variable. Note: cannot environment variables synopsys_dc.setup file.
Simulator Setup File (.synopsys_vss.setup)
Your Simulator setup file, .synopsys_vss.setup, must contain following lines: xc7000: TIMEBASE TIME_RES_FACTOR Note: either $DS401 environment variable actual path specification .synopsys_vss.setup file. final verification that your XEPLD Synopsys Interface ready use, have provided complete design example run, which described later this chapter. quickly verify VHDL
XACT Development System
Getting Started with Xilinx EPLDs
design entry, begin design example step scan.script scan.dc described.
Verifying Your Installation
Before attempting compile design, good idea verify that have access installed software. simple verification process described below.
Verifying Synopsys Software Access
verify that your system correctly configured access Synopsys software, enter following UNIX commands: which dc_shell which vhdlan using simulator) negative response either command, (such vhdlan this means that either software installed properly that your system path properly include Synopsys software directories. Refer Synopsys documentation installation instructions.
Verifying Xilinx Software Access
verify that your system correctly configured access Xilinxsupplied software, enter following UNIX commands: which fitnet fitnet cannot found, XEPLD Translator Core Tool (DS550) installed your path. which syn2epld syn2epld cannot found, installed your path. echo $DS401 This variable should point directory found Step echo $XACT This variable should point XACT directory found Step (unless XACT data files were installed different location
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
than XACT executables). $XACT variable should also print your (DS-401) directory installed different location.
Verifying Your File Structure
verify that have necessary files EPLD development, file structure diagram Figure 1-1.
$DS401 sedif2xnf lib_compile syn2epld vmh2vss xnf2vss data synopsys xprim_7000 *.xnf tutorial synopsys epld scan scan.dc scan.script scan.vhd scan_tb.vhd .synopsys_dc.setup .synopsys_vss.setup synopsys libraries xc7000.db xc7000.sdb xc7000.sldb epld install_dw.dc .synopsys_vss.setup *.vhd.e *.vhd.e.update epld *.syn (Generated running lib_compile) *.sim (Generated running lib_compile) *.mra (Generated running lib_compile)
Figure File Structure EPLD Development
XACT Development System
Getting Started with Xilinx EPLDs
Xilinx EPLD Design Flow
Figure shows basic design flow creating EPLD designs. Each step described following design example.
Design Entry
design_name.vhd
Functional Simulation (optional) analyze compile Synthesis
design_name.sxnf design_name.sedif
Prepare Netlist
syn2epld
design_name.xff
fitnet
Fitting
design_name.vmh
vmh2vss Timing Backannotation Saving Pinouts (optional) Device Programming vhdldbx Timing Simulation
design_name.tim
Static Timing Verification
pinsave makeprg
design_name_vss.vhd design_name_vss.sdf
design_name.prg
Figure Basic EPLD Design Flow
Design Example
following design example used demonstrate basic EPLD design flow. This design implements counter with variable start stop values which loaded into registers from data input bus. When START input asserted, start value loaded into counter counter outputs enabled. counter outputs
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
increment each clock cycle until counter value matches stop value. counter outputs disabled next clock cycle. design implemented Xilinx XC7354-10PC44 device. help understand design, equivalent schematic shown Figure 1-3.
INIT=R
AND2B1 IPAD START IBUF
OE_REG
INIT=R
IPAD8DATA_IN_[7:0] IBUF8
I[7:0] IPAD WRITE_START IBUF
FD8CE
DATA[7:0] D[7:0] Q[7:0] START[7:0]
CB8CLE
Q[7:0] D[7:0] Q[7:0]
OBUFE8
C_OUT_[7:0]
OPAD8
O[7:0]
START_REG
COUNT
COMP8
A[7:0]
OBUF DONE OPAD
FD8CE
END[7:0] WRITE_END IBUF D[7:0] Q[7:0] IPAD
B[7:0]
DONE_REG
END_REG CLOCK IBUF IPAD CLEAR IBUF
IPAD
Title: Comments: Date: Copyright Xilinx rights reserved Corporation, 1994 PART=7354-10PC44 Rev: SCAN EPLD Tutorial Design Ver:
6-21-1994_11:41
Figure Schematic Representation SCAN Design VHDL source file (scan.vhd) scan example design shown Figure 1-4.
XACT Development System
Getting Started with Xilinx EPLDs
-Xilinx EPLD Synopsys VHDL Tutorial Design -File: scan.vhd -Target Device: XC7354-10PC44 -Author: Xilinx Corporation -Copyright Xilinx Corporation 1994 -All rights reserved -Requirements: Xilinx Synopsys Interface v3.2 -Xilinx XEPLD (DS550) v5.0 -Synopsys Design Compiler v3.1 Standard library configuration -Library IEEE; Library xc7000; IEEE.STD_LOGIC_1164.all; IEEE.STD_LOGIC_UNSIGNED.all; xc7000.components.all; entity scan port (CLOCK, CLEAR, START, WRITE_START, WRITE_END: std_logic; DATA_IN: std_logic_vector downto C_OUT: std_logic_vector downto DONE: std_logic; MRESET: std_logic); MRESET used timing simulation only -end scan; architecture behavior scan signal START_REG: std_logic_vector downto signal END_REG: std_logic_vector downto "11111111"; signal COUNT: std_logic_vector downto "00000000"; signal OE_REG, DONE_REG: std_logic '0'; Initial states used fn'l sim. only -begin Registers without asynchronous clear -process (CLOCK) begin (CLOCK'event CLOCK='1') then (WRITE_START '0') then START_REG DATA_IN;
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
(WRITE_END '0') then END_REG DATA_IN; Registered comparator (COUNT END_REG) then DONE_REG '1'; else DONE_REG '0'; process; -OE_REG register with asynchronous clear -process (CLEAR, CLOCK) begin (CLEAR '1') then OE_REG '0'; elsif (CLOCK'event CLOCK='1') then (START '1') then OE_REG '1'; elsif (DONE_REG '1') then OE_REG '0'; process; Counter with asynchronous clear parallel load -process (CLEAR, CLOCK) begin (CLEAR '1') then COUNT "00000000"; elsif (CLOCK'event CLOCK='1') then (START '1') then COUNT START_REG; Counter parallel load -elsif (OE_REG '1') then COUNT COUNT Counter increment -end process;
Three-state counter outputs -C_OUT COUNT when (OE_REG '1') else "ZZZZZZZZ"; DONE DONE_REG; behavior;
Figure Example Design Source File (scan.vhd)
XACT Development System
Getting Started with Xilinx EPLDs
Design Entry
Typically will enter your design Synopsys VHDL/HDL form using text editor. However, required source, setup, test bench files this design example have already been entered contained $DS401/tutorial/synopsys/epld/ vhd/scan directory (see Figure 1-1).
Step1 Create Design Directory
Create local copy scan tutorial directory follows:
Change your current working directory local, writable location which will place scan working directory. Copy entire scan directory tree from XEPLD Synopsys Interface tutorial area into your current directory follows:
Change your current directory scan tutorial directory follows: scan
Verify that search_path variable your .synopsys_dc.setup file, your current working directory, points directory path where your Xilinx EPLD Synopsys Interface library installed, which should value your $DS401 variable.
Note: search_path variable must explicitly defined; environment variables allowed .synopsys_dc.setup file. need more information design entry Synopsys Design Compiler manuals.
Functional Simulation
Functional simulation verifies logic your design. This will save time catching logic errors early development cycle. using VHDL System Simulator (VSS), skip this section continue with step
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
must analyze your source design file before simulation. created test bench VHDL/HDL simulation, must also analyze after analyzing your design.
Step Analyze Your Design
Analyze scan design entering following Synopsys command UNIX command line: vhdlan scan.vhd will analyzer version number copyright notice. analysis works properly will returned UNIX prompt with error messages displayed.
Step Analyze Your Test Bench
this example test bench provided (scan_tb.vhd). this file, configuration named CFG_SCAN_TB declared. test bench file shown Figure 1-5. Analyze test bench scan entering following Synopsys command UNIX command line: vhdlan scan_tb.vhd Again, will analyzer version number copyright notice. analysis works properly will returned UNIX prompt with error messages displayed.
1-10
XACT Development System
Getting Started with Xilinx EPLDs
library IEEE; library xc7000; IEEE.std_logic_1164.all; IEEE.std_logic_misc.all; IEEE.std_logic_arith.all; IEEE.std_logic_components.all; STD.Textio.all; xc7000.components.all; entity scan_tb scan_tb; architecture test scan_tb component scan port (CLOCK, CLEAR, START, WRITE_START, WRITE_END: std_logic; DATA_IN: std_logic_vector downto C_OUT: std_logic_vector downto DONE: std_logic; MRESET: std_logic); component; signal signal signal signal signal begin UUT: scan port (CLOCK, CLEAR, START, WRITE_START, WRITE_END, DATA_IN, C_OUT, DONE, MRESET); CLOCK, CLEAR, START, WRITE_START, WRITE_END: DATA_IN: std_logic_vector downto C_OUT: std_logic_vector downto DONE: std_logic; MRESET: std_logic; std_logic;
Xilinx Synopsys Interface EPLD User Guide
1-11
Xilinx Synopsys Interface EPLD User Guide
DRIVER: process begin MRESET '0'; CLEAR '0'; START '0'; WRITE_START '1'; WRITE_END '1'; DATA_IN "00000000"; CLOCK '0'; wait MRESET '1'; wait CLOCK '1'; wait CLOCK '0'; DATA_IN "01111101"; WRITE_START '0'; wait CLOCK '1'; wait CLOCK '0'; DATA_IN "10000001"; WRITE_START '1'; WRITE_END '0'; wait CLOCK '1'; wait CLOCK '0'; WRITE_END '1'; START '1'; wait CLOCK '1'; wait CLOCK START wait CLOCK loop; loop '0'; '0'; '1';
1-12
XACT Development System
Getting Started with Xilinx EPLDs
wait CLOCK START wait CLOCK wait CLOCK START wait CLOCK wait CLOCK CLEAR wait CLOCK wait CLOCK CLEAR wait wait; process; test;
'0'; '1'; '1'; '0'; '0'; '1'; '0'; '1'; '1'; '0'; '0';
configuration CFG_SCAN_TB scan_tb test for; CFG_SCAN_TB;
Figure Test Bench File (scan_tb.vhd)
Xilinx Synopsys Interface EPLD User Guide
1-13
Xilinx Synopsys Interface EPLD User Guide
Step Invoke Simulator
Invoke simulator entering following Synopsys command UNIX command line: vhdldbx will following window selecting analyzed configurations:
Figure VHDLDBX Window
Step Debugger
Select CFG_SCAN_TB from menu. This brings Synopsys VHDL Debugger window shown Figure 1-7.
1-14
XACT Development System
Getting Started with Xilinx EPLDs
Figure Synopsys VHDL Debugger
Step Trace Signals
Click lower section Synopsys VHDL Debugger window enter following command: trace *'signal This command selects signals test bench level display brings Dynamic Waveform Viewer (Waves).
Xilinx Synopsys Interface EPLD User Guide
1-15
Xilinx Synopsys Interface EPLD User Guide
Step Simulation
Click button Debugger window simulation waveform specified test bench. resulting trace display shown Figure 1-8.
Figure Synopsys Dynamic Waveform Viewer (Waves)
Step Return UNIX
Return UNIX environment selecting EXECUTE-QUIT from VHDL Debugger menu. need more information functional simulation "Simulating Your Design" chapter.
Synthesizing Your Design (Compiling)
Synthesizing your design converts VHDL source text into netlist that composed logic primitives. netlist form that read Xilinx fitter.
Step Enter Shell Environment
Enter Synopsys Shell environment entering following Synopsys command UNIX command line: dc_shell
1-16
XACT Development System
Getting Started with Xilinx EPLDs
will Shell license information command-line prompt. Verify that software version v3.1 newer. Note: commands required compile scan design example shown following steps through These commands contained compiler script files. have FPGA compiler, appropriate commands contained scan.script, which entering following Synopsys command: include scan.script have only Design Compiler, appropriate commands contained scan.dc which entering following Synopsys command: include scan.dc choose these compiler scripts, step when compilation complete. Unless otherwise specified, commands steps 10-16 same both FPGA Compiler Design Compiler.
Step Analyze Your Source Design
Read analyze your VHDL source design file entering following Synopsys command: analyze -format vhdl scan.vhd warning messages during this step normal. source file contains initial signal values that used only functional simulation these values ignored during synthesis. Actual register initial states using attributes shown step
Step Elaborate Your Design
build design based your analyzed VHDL file, entering following Synopsys command: elaborate scan This command displays each register 3-state buffer encountered your design.
Xilinx Synopsys Interface EPLD User Guide
1-17
Xilinx Synopsys Interface EPLD User Guide
Step Synthesize Your Design
synthesize implementation your design based cells XC7000 technology library enter following Synopsys command: compile -map_effort mapping effort save compilation time because synthesizer does perform speed area optimization EPLD designs; optimization performed XEPLD fitter. Note: this design example, compiler produces warning about port connected nets; this warning safely ignored. This warning also occurs step
Step Place Buffer Cells
place buffer cells top-level ports design, enter following Synopsys commands: set_port_is_pad insert_pads
Step Specify Target Device
using FPGA Compiler, enter following Synopsys command specify target EPLD: set_attribute scan part -type string 7354-10pc44
Step Specify Initial Register States
this design want counter OE_REG flip-flop initialized zero. states remaining flip-flops determined fitter achieve best logic optimization. have FPGA Compiler, enter following Synopsys commands specify initial states: set_attribute find(cell COUNT*) fpga_xilinx_init_state -type string set_attribute find(cell OE_REG*) fpga_xilinx_init_state -type string
1-18
XACT Development System
Getting Started with Xilinx EPLDs
Step Output Netlist
design database complete ready output netlist form. have FPGA Compiler, write XNF-formatted netlist entering following Synopsys command: write -format -hierarchy -output scan.sxnf have Design Compiler, write EDIF-formatted netlist entering following Synopsys command: write -format edif -output scan.sedif
Step Exit Shell
Exit Shell entering following Synopsys command: exit returned UNIX prompt. need more information compiling your design, "Compiling Your Design" chapter. synthesizer creates gate-level design with physical device information; physical layout device done next step. speed area estimates provided XC7000 library. Therefore attempt create timing report perform estimated timing simulation this time.
Preparing Netlist
Synopsys compiler produces file named design_name.sxnf design_name.sedif which contain references macros. This file must translated into flattened netlist file (design_name.xff) Xilinx fitter.
Step Create Flattened Netlist
using FPGA Compiler (and created design_name.sxnf file), create design_name.xff file fitter entering following UNIX command line: syn2epld scan
Xilinx Synopsys Interface EPLD User Guide
1-19
Xilinx Synopsys Interface EPLD User Guide
using Design Compiler (and created design_name.sedif file), create design_name.xff file fitter entering following UNIX command line: syn2epld scan.sedif 7354-10pc44 When file translation finished, will message "Netlist written file scan.xff." need more information preparing netlist, "Fitting Your Design" chapter.
Fitting Your Design
XEPLD fitter translates your logical design file (design_name.xff) into physical device layout.
Step Your Design
your design into target device, enter following UNIX command line: fitnet scan fitter displays series progress messages resource summary that shows well your design fits into target device. During execution, fitnet produces warning message about AND-gate that "does drive anything removed"; this safely ignored. When fitter finished will message "Design successfully mapped. Examine following report files:.". Assuming there errors, need only examine resource summary already displayed. Resource report also saved file design_name.res. need more information fitting, "Fitting Your Design" chapter. need more information interpreting reports, "Fitter Reports" appendix.
1-20
XACT Development System
Getting Started with Xilinx EPLDs
Timing Backannotation
After fitting, XEPLD fitter produce static timing report that shows calculated worst case timing logic paths your design. also creates timing simulation file VHDL with Synopsys simulator.
Step Create Static Timing Report
create Static Timing Report create backannotated VHDL file simulator, enter following Xilinx command UNIX command line: vmh2vss scan When file translation finished will that following files have been written: scan.tim, scan_vss.vhd, scan_vss.sdf. Static Timing Report (scan.tim) this example provided "Fitter Reports" appendix. This report shows that critical path this design (clock output delay enable C_OUT pins) 20ns. worst case cycle time 13ns.
Timing Simulation
Timing simulation uses actual device delays based physical layout your design after fitting. using simulator, skip this section step
Step Analyze Your Original Design
Analyze original scan design reuse port declarations contained entity entering following Synopsys command UNIX command line: vhdlan scan.vhd
Step Analyze Your Back-Annotated Design
Analyze back-annotated design architecture, produced Xilinx vmh2vss command, entering following Synopsys command UNIX command line: vhdlan scan_vss.vhd
Xilinx Synopsys Interface EPLD User Guide
1-21
Xilinx Synopsys Interface EPLD User Guide
will analyzer version number copyright notice. analysis works properly will returned UNIX prompt with error messages displayed.
Step Analyze Your Test Bench
Analyze simulation test bench entering following Synopsys command UNIX command line: vhdlan scan_tb.vhd Again, will analyzer version number copyright notice. analysis works properly will returned UNIX prompt with error messages displayed.
Step Invoke Simulator
Invoke Synopsys simulator entering following Synopsys command UNIX command line: vhdldbx -sdf scan_vss.sdf -sdf_top /SCAN_TB/UUT CFG_SCAN_TB your convenience, this command line contained script file, which execute typing following UNIX command line: dbx_scan This will open simulator window shown Figure 1-9. -sdf parameter specifies timing back-annotation file produced vmh2vss. -sdf_top parameter specifies level test bench hierarchy which back annotation information will applied.
1-22
XACT Development System
Getting Started with Xilinx EPLDs
Figure Synopsys VHDL Debugger
Step Open Waveform Viewer
TRACE command specify same signals used during functional simulation step Enter following command VHDL Debugger command line: trace *'signal This opens Dynamic Waveform Viewer window.
Xilinx Synopsys Interface EPLD User Guide
1-23
Xilinx Synopsys Interface EPLD User Guide
Step Simulation
simulation clicking button lower section Synopsys VHDL Debugger window. This will timing simulation test bench display simulation trace your design shown below Figure 1-10.
Figure 1-10 Synopsys Dynamic Waveform Viewer (Waves)
Step Return UNIX
Return UNIX environment selecting EXECUTE-QUIT from simulator menu. need more information timing simulation, Simulating Your Design" chapter.
Programming EPLD
After have verified your design ready program EPLD.
1-24
XACT Development System
Getting Started with Xilinx EPLDs
Step Program EPLD
Create EPLD programming file entering following UNIX command line: makeprg scan scan01 This creates file that downloaded device programmer. parameter specifies user signature string "scan01" that programmed into special EPROM cells device that read identification. need more information device programming, documentation that accompanies your device programmer.
Xilinx Synopsys Interface EPLD User Guide
1-25
Xilinx Synopsys Interface EPLD User Guide
1-26
XACT Development System
Designing with EPLDs
X2845
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Chapter
Designing with EPLDs
This chapter discusses design techniques, library components, attributes best performance from Xilinx EPLDs. more information library components, "Library Component Specifications" appendix. more information attributes, "Attributes" appendix.
VHDL Design File Requirements
plan instantiate components from XC7000 library perform simulation will need declare Xilinx XC7000.components package your design source file. generally good idea always declare this package EPLD designs. declare XC7000.components package, insert following lines your VHDL source file: library xc7000; xc7000.components.all;
Using Registers Latches
Xilinx EPLD architecture allows implement both registers latches within function block macrocells within input pads. This section shows assign logic specific registers latches, control their initial states after power applied. Xilinx fitter uses input registers latches implement functions whenever possible reduce device macrocell resource requirements. Register functions using control inputs, such clear, preset, clock enable, will only implemented macrocell registers; only simple D-type flip-flops optimized into input pads.
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Xilinx Synopsys Interface EPLD User Guide
eligible optimization into input pad, register's inputs must come directly from input ports ports. (clock) input signal must used anything other than register clocking, (data) input signal must used other input.
Preventing Register/Latch Optimization
prevent fitter from automatically assigning registered latched functions input pads, instantiate NO_IFD global attribute cell your source design follows: NO_IFD; where instance name. Note: NO_IFD attribute does prevent from instantiating specific input register latch components.
Using Input Registers
want assign specific register your design input pad, instantiate IFDX1 component. Clock input must driven BUFG component (global FastClk), Clock Enable input used) must driven BUFCE component (Global Clock Enable). Except signals declared FastInputs, input signal must used other input.
Using Macrocell Registers
Inferred registered functions will placed either into macrocells input pads discretion fitter unless register optimization turned off. register optimization turned (using NO_IFD attribute) then inferred registers will placed into macrocells. techniques used infer registers EPLD designs different than other Synopsys design. example, following behavioral VHDL process implements D-type flip-flop with asynchronous clear clock-enable:
XACT Development System
Designing with EPLDs
process (CLEAR, CLOCK) begin (CLEAR '1') then '0'; elsif (CLOCK'event CLOCK='1') then '1') then 'D'; process; also instantiate FDCP, FDPC, FDCPE register components. none control inputs used, software will attempt optimize these registers into input pads, provided optimization enabled.
Using Input Latches
want assign specific latch your design input pad, instantiate component. input must driven BUFG component (global FastClk). Except signals declared FastInputs, input signal must used other input.
Using Macrocell Latches
Inferred latched functions will placed into macrocells only. also instantiate (latch) component. Note: EPLD architecture does support transparent latches with asynchronous clear preset using single macrocell.
Specifying Register/Latch Initial States
When EPLD powered when Master Reset activated, registers latches forced into initial state. control initial state register latch, allow fitter choose initial state based most efficient usage resources. initial states registers your design, after fitting, performing timing simulation. fitter will determine initial states registers device, default, based optimal design performance, unless specify initial states described below.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Specifying Predefined Initial States
Each registered latched component library defined initial state. want these predefined states, must prevent fitter from optimizing registers/latches that would change their initial states. predefined initial states, specified "Library Component Specifications" appendix, instantiate preload attribute cell your source design follows: preload; where instance name. Note: When specify preload inhibit fitter from using certain resources EPLD implement registers your design. This require more device resources decrease performance.
Specifying Initial States Individual Registers/ Latches
want define initial state selected registers/latches, initial state attribute using following Shell commands. using FPGA Compiler, enter following: set_attribute "inst_name" fpga_xilinx_init_state -type string state where:
inst_name name cell instance evaluated means Shell "find" function. state either (reset (set
example, specify initial state register named QOUT_reg<2> using FPGA Compiler, enter following: set_attribute "QOUT_reg<2>" fpga_xilinx_init_state -type string QOUT registers: set_attribute find (cell QOUT_reg*) fpga_xilinx_init_state -type string
XACT Development System
Designing with EPLDs
Note: This attribute overrides other methods specifying initial states. Note: cannot change initial state input registers latches (IFDX1 components); their initial states always implemented indicated "Library Component Specifications" appendix. more information using attributes, "Attributes" appendix.
Using Ports
Unless otherwise specified, compiler will automatically infer IBUF, OBUF, IOBUFE cells top-level input, output, ports. However, Xilinx component library also includes specialpurpose buffer cells that allow explicitly instantiate specific functions. will want explicitly assign buffer cells following reasons:
There more clocks signals your design than there FastClock pins available device. Xilinx fitter automatically assigns most frequently used clock signals FastClock pins most frequently used 3-state control inputs pins. force specific clocks onto global FastClock pins instantiating BUFG cell. force specific output enable signals onto global pins instantiating BUFFOE cell. want some clocks, output enable signals, registers optimized automatically. globally inhibit optimization these resources instantiating NO_FCLK, NO_FOE, NO_IFD attribute cells. this case manually assign selected clock inputs global FastClock inputs instantiating BUFG BUFFOE component. Instantiate IFDX1 components explicitly implement registers latches input pads. generating global clock signals from within your design. want drive global FastClock inputs from signals within your design, must first drive those signals onto corresponding device through output buffer
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
then back into chip through either BUFG component (for FastClocks) through BUFFOE component (for inputs).
Selecting 3-State Control Sources
Xilinx EPLDs have dedicated high-speed routing that used fast output enable signals (FOE). unused routing automatically assigned fitter most used output enable signals your design unless turn optimization using NO_FOE attribute. eligible optimization, output enable signal must come directly from input port used other logic function.
Assigning Specific Fast Output Enable Signals
want assign specific output enable signal your design net, instantiate BUFFOE input buffer drive Enable input OBUFEX1 IOBUFEX1 component. signal produced BUFFOE component cannot used other logic, including input ordinary OBUFE IOBUFE components.
Preventing Optimization
prevent fitter from automatically assigning output enable signals unused nets, instantiate NO_FOE cell your source design follows: NO_FOE; where instance name.
Using Special Logic Functions
Binary Counters
infer binary counters using "+1" operation achieve optimal performance EPLD. also instantiate either CBX1 CBX2 components only count mode.
XACT Development System
Designing with EPLDs
Binary Down Counters
infer binary down counters using "-1" operation achieve optimal performance. also instantiate either CBX1 CBX2 components only down count mode.
Binary Up/Down Counters
best results, when creating up/down counters, instantiate CBX1 component (up/down counter with asynchronous clear) CBX2 component (up/down counter with synchronous reset). These counters scalable width they optimized Xilinx EPLD architecture. infer up/down counters, your design will require more device resources implement will slower. Note: Inferred counters will automatically wrap from 0's. need write conditional expressions detect terminal count; this would create unnecessary additional logic cause your counter slower. example, write following: (count "11111111") then count "00000000"; else count count
State Machines
When initially compile state machine, binary encoding option (the default). logic complexity binary encoded state machine results poor device resource utilization, less fully encoded state assignments explicitly your VHDL design. general more registers represent state vectors reduce amount combinational logic required each state flipflop. One-hot-encoding rarely most efficient create state machines EPLDs (unlike Xilinx FPGA designs). Other schemes such Gray coding help EPLD designs because EPLD architecture primarily composed D-type flip-flops.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Registered Arithmetic Functions
When creating simple pipelined arithmetic functions (where register control logic required), operators ordinary clocked process achieve good results. example: process (clock) begin (clock'event clock '1') then When creating registered arithmetic functions with register control logic, instantiate component (Adder/Subtracter/ Accumulator) ADSUR component (Adder/Subtracter with registered output) best results. These components scalable width they optimized Xilinx EPLD architecture. infer these functions, your design will require more device resources implement will slower. Note: Register control logic includes functions such synchronous asynchronous reset, clock enable, parallel load.
Comparators
Magnitude comparators expressed either behaviorally, using operators, instantiating COMPLT COMPLE components. They implemented essentially same subtracter, with carry-out serving comparator output. 3-bit look-ahead logic low-order comparator saves about macrocells EPLD over straight subtracter solution. EPLD high-speed arithmetic carry chain used magnitude comparators larger than bits. Equality comparators implemented combinatorially using gates each operand bit. EPLD HDFB accommodate 8-bit equality compare single macrocell. Equality comparators bits expressed either behaviorally, using operator, instantiating COMPEQ COMPNE components. comparators larger than bits, which require more than macrocell, should COMPEQ COMPNE components
XACT Development System
Designing with EPLDs
that gate logic combining macrocells' intermediate results implemented possible (without extra delay). Comparator outputs high-speed applications often pipelined before driving other logic passing off-chip. breaking larger comparators into 8-bit slices pipelining each slice, gate logic combining slices still implemented (for on-chip logic). following example, pipelined 16-bit comparator (with Boolean-type output cannot maximum frequency EPLD because logic preceding register cannot single macrocell: process (clock) begin (clock'event clock '1') then 15); process; following example, 16-bit comparator broken into 8bit registered comparators, joined UIM-based AND-gate. This solution clocked maximum frequency EPLD drives on-chip logic: process (clock) begin (clock'event clock '1') then 15); process;
Targeting Specific Device
Before fitting your design must select target device. have three questions consider when selecting EPLD:
many signal pins required? much Logic resources required? much performance (speed) required?
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
answers these questions determine which device will choose contain your design. Device selection iterative process, shown following steps: Xilinx EPLD data book make preliminary choice. This choice usually based number required signal pins because this often easiest question answer. easiest begin with largest device (XC73108); this gives best chance successful fit. Otherwise, very rough estimate number required macrocells follows: [(the number output ports) (the number internal registers driving output ports)] [20%] fitter your design using selected device. After fitting, Resource Report indicates much device resources were required. This will help determine best device size. your design does will need choose larger device partition your design among multiple devices. have unused logic resources, want smaller device. Once optimal device size been determined, create Static Timing Report that will indicate calculated timing your design based device layout. also simulate timing your design using Synopsys simulator. This timing information will help select optimal target device speed. "EPLD Architecture" appendix shows device selection chart. "Library Component Specifications" appendix shows which library components used with specific target devices. device data sheets more information.
Specifying Device
There ways specify target EPLD which implement your design:
setting part attribute Shell (using FPGA Compiler). specifying part parameter Xilinx syn2epld command.
2-10
XACT Development System
Designing with EPLDs
Using Synopsys Part Attribute
using FPGA Compiler, following Synopsys attribute Shell prompt specify target device: set_attribute design_name part -type string part_number example: set_attribute scan part -type string 7354-10PC44 This attribute optional specify part number Xilinx syn2epld command, shown below. using Design Compiler, should always specify part number parameter syn2epld command.
Using Xilinx Syn2EPLD Command
When flattening netlist file fitter after compiling, also specify target device entering following Xilinx command UNIX command line: syn2epld part_number design_name [.sedif] example, UNIX prompt enter: syn2epld 7354-10PC44 scan Note: valid part number specified syn2epld command will override part number specified Shell attribute. "Attributes" appendix more information attributes. "Fitting Your Design" chapter more information fitter commands.
Specifying Locations
Specify device pins which place signals using following Synopsys attributes Shell. using FPGA Compiler, enter following: set_attribute port_name pad_location -type string pin_number
Xilinx Synopsys Interface EPLD User Guide
2-11
Xilinx Synopsys Interface EPLD User Guide
example, place "start" signal using FPGA Compiler: set_attribute start pad_location -type string location attribute explicitly override saved pinout made with fitter pinsave command. "Fitting Your Design" chapter more information pinsave command. Note: method specifying numbers depends target device package type. "Attributes" appendix more information.
Controlling Design Performance
Devices Xilinx EPLD family include Fast Function Blocks (FFBs) and/or High Density Function Blocks (HDFBs). Fast Function Blocks provide shortest delay paths while High Density Function Blocks provide most logic resources. EPLDs also contain special high speed routing clocks, output enable signals, clock enable signals, logic inputs FFBs. control your design performance using attributes assign specific signals your design appropriate physical EPLD resources.
Using High-Speed Clocks
Xilinx EPLDs have dedicated high-speed (FastCLK) routing that used global clock signals. unused FastCLK routing automatically assigned fitter most used clock signals your design eligible) unless turn optimization. eligible FastCLK optimization, input port signal must used only register clocking using positive clock edge. Note: EPLD Fast Function Blocks, input registers, input latches must FastCLK routing; they cannot normal signal routing clocks.
Assigning Specific High-Speed Clocks
want assign specific clock your design FastCLK instantiate BUFG buffer cell your design.
2-12
XACT Development System
Designing with EPLDs
Note: Signals driven BUFG buffer always FastCLK routing independent NO_FCLK attribute.
Preventing FastCLK Optimization
prevent fitter from automatically assigning your clock signals unused high-speed FastCLK nets, instantiate NO_FCLK cell your source design follows: NO_FCLK; where instance name.
Selecting EPLD Function Block Types
assigning logic signals specific EPLD Function Block resources, control performance logic paths your design.
Specifying High-Speed Paths
assign logical signal Fast Function Block (shortest delay paths), instantiate attribute cell your source design connect intended output signal follows: instance_name: port (signal_name); example: port (OE_REG);
Specifying High-Density Paths
assign logic signal High Density Function Block (normal delay paths), instantiate attribute cell your source design attach intended HDFB output signal follows: instance_name: port (signal_name); example: port (DONE_REG); "Attributes" appendix more information.
Xilinx Synopsys Interface EPLD User Guide
2-13
Xilinx Synopsys Interface EPLD User Guide
Using EPLD FastInputs
Some inputs FFBs taken directly from input pins using high-speed FastInput path which bypasses Universal Interconnection Matrix. assign input port signals EPLD FastInputs, instantiate attribute cell your source design connect intended FastInput signal follows: instance_name: port (signal_name); example, assign fast_in1 signal EPLD Fast Input: port (fast_in1); Note: input signal declared FastInput also used input input register latch (IFDX1 ILD).
Selecting Low-Power Operation
Macrocells most EPLD devices configured operate either high-speed (default) low-power mode. specify that macrocells device operate low-power mode, instantiate global LOWPWR attribute cell your source design follows: LOWPWR; where instance name.
Design Rule Checker
Design Rule Checker (DRC) reads design from database checks design rules have been violated. following partial list rules that checked.
General Design Rule Violations
displays error warning
Open (hanging) inputs found. Unless otherwise specified, inputs library component must connected tied GND. Some library components only used particular target EPLD. will generate error attempt these
2-14
XACT Development System
Designing with EPLDs
components other EPLDs. Restrictions components found library data sheets.
Component Design Rule Violations
component correct usage applications illustrated Library data sheets. displays error
component outputs connected same pad. component output connected pads. input connected directly output pad. pins driven GND. clocks driven GND. Multiple input buffers connected same (the exception when IBUF used with IFD, IFDX1, receive FastInput signal). connected component other than buffer, another pad. IPAD connected OBUF-type component. OPAD connected input control-input buffer (such IBUF, BUFG, IFD).
FastCLK, Clock Enable, Fast Output Enable Violations
displays error
There more FastCLK, pins design than target EPLD support. FastCLK, signal drives component that clock, input. combination fast clocks logic components pads cannot supported target EPLD. clocking requirement component met. Some component clock inputs only driven fast clock others only logic clock. Component clocking requirements listed library data sheets.
Xilinx Synopsys Interface EPLD User Guide
2-15
Xilinx Synopsys Interface EPLD User Guide
2-16
XACT Development System
Compiling Your Design
X2845
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Chapter
Compiling Your Design
supports both VHDL Verilog design synthesis. Either Synopsys FPGA Compiler Design Compiler used compile EPLD designs; there differences between compilers either features supported mapping efficiency. following discussion, term "compiler" refers either FPGA Compiler Design Compiler. This chapter describes compile your design using Synopsys Design Compiler shell Shell). also Synopsys graphical user interface, Design Analyzer, process your designs. Before compiling will need develop your VHDL Verilog source file (design_name.vhd design_name.v). Usually good idea perform functional simulation your VHDL source design before trying synthesize "Simulating Your Design" chapter information functional simulation.
Using Synopsys Shell
Synopsys compiler synthesizes your source design creates netlist file composed logic primitives that used Xilinx fitter (XEPLD) implement your design EPLD. compiler commands executed from within Synopsys Shell environment
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Xilinx Synopsys Interface EPLD User Guide
Step Entering Shell Environment
Enter Synopsys Shell environment entering following Synopsys command UNIX command line: dc_shell will Shell prompt.
Step Analyzing Design
interpret your design verify that free errors, enter following Synopsys command VHDL designs: analyze -format vhdl design_name.vhd Verilog designs: analyze -format verilog design_name.v example, command used scan example "Getting Started with Xilinx EPLDs" chapter: analyze -format vhdl scan.vhd your source file contains initial signal values (which used only functional simulation) they will cause warnings that safely ignored; these initial signal values used during synthesis. Actual register initial states using attributes shown "Attributes" appendix. analyze command finds errors, will need make necessary corrections your source file before continuing with synthesis. analyze command successful, continue next step which builds your logic design.
Step Elaborating Design
derive logical design, based your VHDL/HDL description, enter following Synopsys command: elaborate design_name
XACT Development System
Compiling Your Design
example, command used scan example "Getting Started with Xilinx EPLDs" chapter: elaborate scan During this step, compiler displays information about registers 3-state buffers encountered your design. ready compile your design using XC7000 target library.
Step Compiling Your Design
When compile your design, Synopsys synthesizer uses components Xilinx XC7000 technology library create actual implementation your design. synthesize your design based XC7000 technology library enter following Synopsys command: compile [-map_effort low] mapping effort parameter optional. However, recommended that save compilation time. synthesizer does perform speed area optimization EPLD designs; this optimization performed after compilation XEPLD fitter.
Step Defining EPLD Signals
must define which signals connected physical pins EPLD. following command identify ports your design which synthesizer needs infer buffer: set_port_is_pad port_name this command ports that already instantiated using buffer cells from library. automatically place buffer cells top-level ports design, enter following Synopsys commands: set_port_is_pad
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
ports that were specified set_port_is_pad, following command adds appropriate buffer cells your design: insert_pads
Step Specifying Attributes
Attributes used control physical implementation your design; attributes optional. using FPGA Compiler, attributes that want this time are:
Part type (you also part type from fitter command line). Register initial states. assignments.
example, attributes used scan example "Getting Started with Xilinx EPLDs" chapter: set_attribute scan part -type string 7354-10pc44 set_attribute find(cell COUNT*) fpga_xilinx_init_state -type string set_attribute find(cell OE_REG*) fpga_xilinx_init_state -type string "Attributes" appendix complete details supported attributes. design database complete ready output netlist file Xilinx fitter.
Step Writing Netlist
using FPGA Compiler, write your synthesized design file netlist format entering following Synopsys command: write -format -hierarchy -output design_name.sxnf where:
-format specifies file format. -hierarchy specifies that levels design hierarchy written.
XACT Development System
Compiling Your Design
-output design_name.sxnf specifies your output file name, which should same your source file name, with extension: .sxnf.
example, command used scan example "Getting Started with Xilinx EPLDs" chapter: write -format -hierarchy -output scan.sxnf using Design Compiler, must write your synthesized design file EDIF netlist format entering following Synopsys command: write -format edif -output design_name.sedif where:
-format edif specifies EDIF file format. -output design_name.sedif specifies your output file name, which should same your source file name, with extension: .sedif.
example, have only Design Compiler, would write scan design from "Getting Started with Xilinx EPLDs" chapter using following command: write -format edif -output scan.sedif This process Shell. usually exit Shell before fitting. Before exiting wish save design database Synopsys format executing write command. exit Shell entering following Synopsys command: exit None Synopsys timing area analysis reports useful this time because XC7000 technology library does contain timing area estimation data. Xilinx fitter provides Static Timing Report which shows calculated worst case timing each logic path your design. ready begin fitting process described next chapter.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
XACT Development System
X2845
Fitting Your Design
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Chapter
Fitting Your Design
After have compiled your logic design using Synopsys compiler ready implement your design EPLD. This chapter shows your design, create device programming file, save your pinouts design iteration.
Fitter Overview
XEPLD Xilinx EPLD fitter software. XEPLD uses logical design produced Synopsys compiler create physical layout target EPLD. XEPLD performs following functions:
Reads netlist file (design_name.sxnf design_name.sedif) produced Synopsys compiler reports rule violations error file (design_name.err). Minimizes combinational logic your design that requires least number product term resources. Optimizes, partitions, maps your design within architecture target device. Creates pin-save file (optional) that used lock signal names device pins, allowing keep device pinouts during design iterations. Creates Static Timing Report that shows calculated worstcase timing signal paths your design. Creates timing simulation files that used Synopsys simulator. Creates device programming file (design_name.prg).
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Xilinx Synopsys Interface EPLD User Guide
Creates detailed reports that show information such type quantity device resources used device pinouts.
Fitter Operation
following steps show your logical design into target device using XEPLD fitter.
Step Create Flattened Netlist File
Synopsys FPGA Compiler produces top-level XNF-formatted file named design_name.sxnf. Synopsys Design Compiler produces top-level EDIF-formatted file named design_name.sedif. Either these files contain macros must translated into flattened netlist file Xilinx fitter using syn2epld command. specify target device part number Synopsys Shell using part attribute) must specify target device type this time.
Specifying Target Device
create flattened netlist, specify target device, enter following Xilinx command UNIX command line: syn2epld part_number design_name [.sedif] omit .sedif extension, syn2epld looks design_name.sxnf file (produced FPGA Compiler). specify .sedif extension, syn2epld reads EDIF netlist produced Design Compiler. example, UNIX prompt enter: syn2epld 7354-10PC44 scan This command creates flattened netlist which saved design_name.xff. Note: valid part number specified syn2epld command will override part number specified Shell attribute. complete list device types shown "EPLD Architecture" appendix.
XACT Development System
Fitting Your Design
Using Target Device Specified Part Attribute
using FPGA Compiler specified part attribute Shell, enter syn2epld command without parameter UNIX command line follows: syn2epld design_name
Step Your Design
invoke fitter, enter following Xilinx command UNIX command line: fitnet design_name [options]
Options
Ignore assignments specified pad_location attributes. Drive unused pads GND. previously saved (frozen) pinout. example, invoke fitter scan design, driving unused EPLD signals GND, enter following command: fitnet scan fitnet command produces various reports:
Resource Report (design_name.res) indicates well your design fits target device. This report shows utilization macrocells, Function Blocks each type device pin, indicates amount remaining logic resources device. Resource summary also displayed near fitnet process. Pinlist Report (design_name.pin) shows signals assigned each target device.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Partitioner Report (design_name.par) Mapping Report (design_name.map) show detailed physical layout your design within EPLD. Equation File (design_name.eqn) contains boolean equations representing final implementation your design after minimization optimization, expressed Xilinx PLUSASM syntax.
Step Verify Your Design Timing
Generate Static Timing Report timing simulation files entering following Xilinx command UNIX command line: vmh2vss design_name
Options
Allows same test bench file timing simulation functional simulation. generates design_name_vss.vhd file architecture only, using original indexes matching port declarations your original source design file (design_name.vhd). option default specify option. Generates test bench file timing simulation (tb_design_name_vss.vhd). also generates design_name_vss.vhd file with both entity architecture. Static Timing Report saved design_name.tim. This report shows calculated worst case timing logic paths your design. "Fitter Reports" chapter complete description Static Timing report. timing simulation model produced vmh2vss composed files:
design_name_vss.vhd structural VHDL design file (for simulation only). design_name_vss.sdf Verilog-style timing back-annotation file.
XACT Development System
Fitting Your Design
select option will also following file:
tb_design_name_vss.vhd VHDL test bench timing simulation.
Step Create Device Programming File
After satisfied that your design functioning properly create device programming file. This file used EPLD programmer implement your design. create device programming file, enter following Xilinx command UNIX command line: makeprg design_name signature] Where signature optional user-defined signature string that programmed into device identification. This command creates file named design_name.prg. EPLD programmers available from Xilinx from third-party developers. your device programmer documentation instructions download programming file.
Step Save Your Pinouts
Modifying EPLD designs after board layout requires ability save re-use device location information. save your pinouts future design iterations, enter following Xilinx command UNIX command line: pinsave design_name This command creates pin-save file named design_name.vmf. During subsequent invocation fitnet command, specify option restore pinouts saved .vmh file. Note: Making major changes your design prevent fitter from achieving successful mapping fitnet option. fitter fails, running without option still possible. modified design into selected device, need delete some assignments .vmh file, allowing those pins move locations.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Note: cannot previously saved pinout change size package type target device. EPLD Data Book determine which devices EPLD family have compatible pinouts across similar packages. After successful your design ready perform timing simulation described next chapter.
XACT Development System
X2845
Xilinx Synopsys Interface EPLD User Guide
Simulating Your Design
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Chapter
Simulating Your Design
Xilinx EPLD Synopsys Interface supports both functional timing simulation designs using simulator. This chapter shows prepare designs simulation test bench.
Recommended EPLD Simulation Strategy
Because flexibility simulation environment, there many ways which verify your design. following steps, which explained subsequent sections, show recommended flow EPLD simulation. Specify initial states your registers. attributes control initial states registers your actual design implementation, must also re-specify those initial states your source design file functional simulation. Create test bench file. following guidelines described this chapter, same test bench used both functional timing simulation. Perform functional simulation. This allows debug logic your source design before implementing EPLD. Implement design EPLD. This provides necessary physical resource information necessary timing simulation. Prepare timing model. vmh2vss software prepares timing model your design simulation provides static timing report.
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Xilinx Synopsys Interface EPLD User Guide
Perform timing simulation. re-using functional simulation test bench file, easily compare results prevent errors that caused accidental differences between separate test bench files. these preparation simulation steps demonstrated design example shown "Getting Started with Xilinx EPLDs" chapter.
Controlling Initial States Registers
This section shows declare initial states registers your design simulation. your design does depend initial states registers, then skip this section next section, "Creating Test Bench File". actual initial states your registers determined initial state attributes specified Shell during compilation default initial states which specified each registered cell Xilinx component library. Note: preload optimization turned OFF, default initial states defined library, will changed Xilinx software. preload optimization turned then initial states changed fitter during optimization. "Attributes" appendix more information preload optimization control. timing simulation model produced Xilinx software reflects actual register initial states that implemented device, regardless whether they explicitly specified automatically assigned fitter.
Simulating Master Reset
Xilinx EPLDs have Master Reset function that initializes device registers either when power applied when input pulsed. reset signal physically available your logic. However, must pulse reset signal beginning timing simulation proper register initialization. following sections show simulate Master Reset function both functional timing simulation.
XACT Development System
Simulating Your Design
Preparing Timing Simulation
When generate your timing simulation model, vmh2vss automatically creates input port named MRESET. When simulating, must first pulse MRESET low, prior exercising logic, registers into their initial states. test bench stimulate your design, must include MRESET signal input ports EPLD test bench described next section "Creating Test Bench File". MRESET signal used timing simulation only; used functional simulation cannot used your design. However, include your functional simulation test bench, that test bench also used later timing simulation without modification. using same test bench file both functional timing simulation, must also include MRESET port declaration your source design file follows: port MRESET std_logic MRESET used anywhere else your design. During synthesis will warnings about unconnected MRESET port (during Compile Insert Pads operations). Xilinx fitter software will also ignore unconnected MRESET port during implementation. scan tutorial source file listing example MRESET input port declared VHDL design.
Preparing Functional Simulation
Simulate register initialization (Master Reset) defining, your source design file, initial values registered signals. signal declarations such following: port signal_name: port_direction signal_type initial_value; signal signal_name: signal_type initial_value; variable signal_name: signal_type initial_value; example: port Nreg5 std_logic '0'; signal Qreg6: std_logic '0'; variable Qreg: std_logic_vector "00000001";
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
These initial values used only functional simulation; they used during synthesis synthesizer will give warning that these values being ignored. Also, these initial values used Xilinx software device implementation. Note: fitter change initial states registers during optimization (assuming that preload optimization remains enabled). Therefore, functional simulation, should declare only initial states that will actually implemented Xilinx fitter, based your specifications. These states specified your source design file using initial state attributes Shell. ready create test bench file.
Creating Test Bench File
This section shows create test bench file that used both functional timing simulation. example test bench presented here consists VHDL file containing instance EPLD design being tested procedure that applies simulation input waveforms EPLD.
Initializing Registers
functional simulation, registers initialized before first simulation cycle time zero) initial values declared your source design file. timing simulation, test bench, include MRESET input port EPLD component declaration instance port shown Figure 5-1. beginning simulation sequence, applying active-low pulse MRESET initializes registers. This pulse ignored during functional simulation because MRESET signal used anywhere source design. During vmh2vss (after fitnet) MRESET port automatically generated timing simulation model. Then, during timing simulation when test bench applies MRESET pulse, timing simulation model will initialize registers they actually implemented EPLD.
XACT Development System
Simulating Your Design
Note: designs targeted XC7318, XC7336, XC7354, specify MRINPUT attribute, device will have Master Reset pin. However, timing model will still respond reset pulse port order simulate power-on reset function, which always performed EPLD when power applied.
Configuration Declaration
design test bench wish simulate, must declare configuration which identifies specific architecture applying design. When invoke simulator, must select name configuration that been previously analyzed. Figure shows typical configuration declaration test bench file. test bench always used simulate design source file, does need configuration declaration.
library xc7000 xc7000.components.all;. entity scan_tb scan_tb; architecture test scan_tb component scan port (CLOCK, CLEAR, MRESET std_logic); component; signal CLOCK, CLEAR, .MRESET; begin UUT: scan port (CLOCK, CLEAR, MRESET); driver: process begin MRESET '0';CLEAR <='0';. wait 25ns; MRESET '1';. wait; process; test; configuration CFG_SCAN_TB scan_tb test for; CFG_SCAN_TB; -and other packages-
-test bench ports-
-same scan.vhd-
-same ports scan.vhd-connect local signals ports-assert initial values ports -wait, repeat-release MRESET before applying other input transitions-after inputs, suspend process-
Figure Simulation Test Bench SCAN Design After have created test bench file, ready begin using simulator (such vhdldbx) functional simulation.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Functional Simulation
Functional simulation used debug your logic before fitting your design into EPLD. Xilinx EPLD Synopsys Interface fully supports functional simulation cells XC7000 library (including DesignWare operators). prepare test bench configuration simulation, must analyze each design test bench source files proper bottom-up sequence. following procedure uses stand-alone VHDL Analyzer (vhdlan) VHDL Debugger Simulator (vhdldbx). Analyze your source EPLD design file. Enter following UNIX command: vhdlan design_name.vhd example: vhdlan scan.vhd Analyze test bench file. Enter following UNIX command: vhdlan test_bench_name.vhd example: vhdlan scan_tb.vhd Invoke Synopsys Simulator. Enter following UNIX command invoke VHDL debugger: vhdldbx then prompted configuration name. Select name configuration declared test_bench_name.vhd file. example, scan design, select following: CFG_SCAN_TB vhdldbx selector window appears shown Figure 5-2.
XACT Development System
Simulating Your Design
Figure Selector Window (vhdldbx) After click vhdldbx user interface window appears shown Figure 5-3.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Figure User Interface Window (vhdldbx) your simulation, typically first declare signals want display trace window. example, display signals appearing EPLD pins, enter following vhdldbx command: trace *'signal.
XACT Development System
Simulating Your Design
simulation vectors your test bench, select command. resulting trace window will look similar Figure
Figure Functional Simulation Waveforms SCAN Design After functional simulation successful, ready implement your design create physical layout information required timing simulation.
Design Implementation
After have debugged your design using functional simulation, compile using synthesis implement EPLD using Xilinx fitter. Design implementation prerequisite performing timing simulation. Shell Synopsys graphic interface (Design Analyzer) create EDIF netlist file required Xilinx fitter. This gate-level netlist file consists cells from XC7000 library does contain timing information. Xilinx fitter processes netlist file places logical design into physical architecture target EPLD. After design implemented Xilinx fitter, actual target device timing information available timing simulation. following steps show overview EPLD implementation procedure.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Analyze source design file. This must repeated synthesis environment Shell); results vhdlan cannot used synthesis. Compile design, targeting XC7000 library, create netlist. Xilinx fitter, using fitnet command process netlist. Usually, simulation repeated until after fitting when actual timing results have been applied. verify that fitting process completed, review error file (design_name.err) which shows errors warnings that occurred during implementation. These errors also displayed screen process running. also examine Resource Report (design_name.res) which also displayed screen process running. Resource Report tells well your design fits into target device. wish target smaller device more functions your design there remaining unused resources. After design implementation, ready prepare timing model timing simulation.
Preparing Timing Model
When synthesize your design, create EDIF netlist file Xilinx fitter, busses (such those declared std_logic_vector) decomposed into individual nets. original definition your ports design entity retained through fitting process. vmh2vss software cannot regenerate timing model complete with your original port declarations, does provide options preparing timing model:
Using vmh2vss with option (the default) generates timing model architecture only, without entity. external signals appearing design, that were originally defined ports, will then represented within model architecture using subscript notation compatible with port declarations. re-using entity from your source design with architecture timing model (produced vmh2vss -b),
5-10
XACT Development System
Simulating Your Design
perform timing simulation using same test bench chip interface used functional simulation. example: vmh2vss scan
Using vmh2vss with option generates timing model complete VHDL design. entity that design will list individual signals that comprise busses original design. However, original structure preserved. This normally forces modify chip interface your functional simulation test bench before using timing simulation. This because your original test bench interfaces EPLD using ports cannot interface timing model. example: vmh2vss scan
vmh2vss software also creates static timing report which shows calculated timing logic paths your design. should review this report (design_name.tim) satisfactory timing, before simulation. this point need rerun fitter, specifying different EPLD speed grade. Also, achieve required timing, need modify your design apply attributes control mapping speed-critical paths. When satisfied with your static timing results, proceed timing simulation.
Timing Simulation
Timing simulation performed after implementing your design (using Xilinx fitnet command), creating timing model (using vmh2vss), reviewing static timing report. prepared your test bench properly, used option (default) vmh2vss, same test bench timing simulation used functional simulation. using same test bench easily verify that functionality device after mapping matches functionality your source design. also eliminate risk errors from accidental differences between test bench files.
Xilinx Synopsys Interface EPLD User Guide
5-11
Xilinx Synopsys Interface EPLD User Guide
Analyze your source design file re-use port declarations entity. Enter following UNIX command: vhdlan design_name.vhd example: vhdlan scan.vhd Replace architecture your source design with timing architecture produced vmh2vss vhdlan design_name_vss.vhd example: vhdlan scan_vss.vhd architecture replaced Synopsys data base analyzing timing model file; need modify your design source file. Analyze test bench file name used functional simulation. Enter following UNIX command: vhdlan test_bench_name.vhd example: vhdlan scan_tb.vhd simulation data base contains test bench design which interfaces chip through your source design entity read step contains timing model architecture read step Invoke Synopsys Simulator. Enter following UNIX command: vhdldbx then prompted configuration named test_bench_name.vhd file. example, scan design, select following: CFG_SCAN_TB Before clicking "OK" must specify timing backannotation file information Arguments box.
5-12
XACT Development System
Simulating Your Design
backannotated timing .sdf file applied various instances within design_name_vss.vhd file. However, simulating with test bench, must specify simulator) EPLD design instance which want apply backannotated timing. then find referenced instances. using vhdldbx need specify parameters:
file name .sdf backannotation timing file: -sdf design_name_vss.sdf example: -sdf scan_vss.sdf
sdf_top instance test bench configuration which backannotated timing applied: -sdf_top chip_instance_name example: -sdf_top /scan_tb/UUT backannotated timing parameters .sdf file applied relative chip instance.
specify these parameters either dialog which appears after invoking vhdldbx shown Figure 5-5), UNIX command line invoke vhdldbx.
Xilinx Synopsys Interface EPLD User Guide
5-13
Xilinx Synopsys Interface EPLD User Guide
Figure Selector Window with Timing Backannotation Parameters Entered (vhdldbx) convenience, parameters into command script file. command line scan design provided dbx_scan script file tutorial directory. command line invocation format vhdldbx -sdf design_name_vss.sdf -sdf_top chip_instance_name configuration_name scan design example, should enter following: vhdldbx -sdf scan_vss.sdf -sdf_top /scan_tb/UUT CFG_SCAN_TB
5-14
XACT Development System
Simulating Your Design
same simulation vectors timing simulation functional simulation. However, timing simulation, registers their initial states response active-low pulse MRESET input.
Figure Timing Simulation Waveforms SCAN Design After successful timing simulation ready create device programming file.
Xilinx Synopsys Interface EPLD User Guide
5-15
X2845
Xilinx Synopsys Interface EPLD User Guide
EPLD Architecture
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Appendix
EPLD Architecture
Xilinx EPLD family uses simple PAL-like architecture provide both high speed high density variety packages configurations. Through unique Dual-Block architecture, High Density Function Blocks (FBs) provide high speed maximum logic density implementing complex functions while Fast Function Blocks (FFBs) provide even higher speed critical decoding ultra-fast state machine applications. more information Programmable Logic Data Book. EPLD architecture consists multiple Function Blocks blocks interconnected shown Figure A-1.
Input
Output
Output
Block
Block
X3204
Figure EPLD Architecture Block Diagram
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Xilinx Synopsys Interface EPLD User Guide
Device Selection
following table shows Xilinx EPLD family, grouped user application. this table select best target device your design. Package options speed grades always being updated. Check latest device data sheets most date information. Table Device Selection Chart Fast Functions 7318
22VI0 Equivalent Macrocells FFBs Flip-Flops Fast Inputs Supported Fast Clock Inputs Fast Output Enab. Fast Clock Enab.
Features
Dual Block Arch. Fast High Density 7354
High Density Functions 7236A
7336
7372
73108
7272A
Pin-to-Pin delay (ns.) Clock Frequency (Mhz) Signal Pins (max) Speed Grades
PLCC CLCC PQFP PLCC CLCC PLCC CLCC PQFP PQFP
XACT Development System
EPLD Architecture
Universal Interconnect Matrix
Universal Interconnect Matrix(UIM) functions unrestricted crossbar switch. guarantees complete interconnection internal functions provides constant, short interconnect delays. receives inputs from Macrocells, bidirectional pins, dedicated input pins provides outputs each High-Density Function Block outputs each Fast Function Block. input drive more outputs with interconnect delay remaining constant. When multiple inputs connected same output, this output produces logical input signals. choosing appropriate signal inversions, this logic also implement wide NAND, functions. This provides additional level logic with additional delay. Macrocell feedback signal that disabled output enable product term represents High input UIM. Programming several such Macrocell outputs onto same output thus emulates 3-state line. When Macrocell outputs enabled, output assumes level.
High-Density Function Blocks
Each High Density Function Block contains nine Macrocells which configured either registered combinatorial logic. detailed Function Block diagram shown Figure A-2. Each receives signals their complements from additional three inputs from FastInput (FI) pins. Note: XC7272A architecture, including ALU, slightly different. data sheet details.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Array Inputs from from Fast Input Pins (FI) Sharable P-Terms Function Block Private P-Terms Macrocell Arithmetic Carry-In from Previous Macrocell Feedback Enable Override Macrocells
CLOCK RESET
Fast Clocks
Global Fast
(see fig.3)
Control
Input-Pad Register/Latch (optional) Register Trasparent Control Feedback Polarity
More Macrocells
Clock Select
Shift-In from Previous Local Feedback
Shift-Out Next
forced high when P-term used Feedback Input
Arithmetic Carry-Out Next Macrocell
X1829
Figure Function Block Schematic
Shared Private Product Terms
Each Macrocell contains five private product terms that used primary inputs combinatorial functions implemented Arithmetic Logic Unit (ALU), individual Reset, Set, OutputEnable, Clock logic functions flip-flop. Each Function Block also provides additional shared product terms, which uncommitted product terms available nine Macrocells within Four private product terms ORed together with four shared product terms drive input ALU. input driven fifth private product term eight remaining shared product terms. shared product terms
XACT Development System
EPLD Architecture
logic delay each shared product term connected nine Macrocells Function Block.
Arithmetic Logic Unit
versatility each Macrocell enhanced through additional gating control functions available ALU. detailed block diagram XC7300 XC7236A shown Figure A-3. logic mode arithmetic mode. logic mode, functions 2-input function generator using 4-bit lookup table that programmed generate Boolean function from inputs. function generator inputs, widening function maximum inputs. them, which means that sum-of-products used mask other. also them, toggling flip-flop comparing sums products. Either both sum-of-product inputs inverted, either both ignored. Therefore, implement additional layer logic with speed penalty. arithmetic mode, generate arithmetic difference inputs. Combined with carry input from next lower Macrocell, operates 1-bit full adder generating carry output next higher Macrocell. dedicated carry chain propagates between adjacent Macrocells crosses boundaries between Function Blocks providing very fast arithmetic operation with additional resource requirements.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
Arithmetic Logic Unit (ALU)
Carry Output
Sum-ofProducts Sum-ofProducts
Function Generator Macrocell Flip-Flop
Arithmetic Carry Control Carry Input
X3206
Figure Schematic
Carry Lookahead (7300 Family Only)
Each Function Block provides carry lookahead generator capable anticipating carry across nine Macrocells. This reduces ripple-carry delay wide arithmetic functions such add, subtract, magnitude compare that first nine bits, plus carry lookahead delay higher-order Function Blocks.
Macrocell Flip-Flop
output drives input programmable D-type flip-flop. flip-flop triggered rising edge clock input, configured transparent, making output identical input, independent clock. Macrocell clock source programmable private product terms global FastCLK signals. FastCLK signals distributed every Macrocell flip-flop with short delay minimal skew. asynchronous Reset product terms override clocked operation. both asynchronous inputs active simultaneously, Reset overrides Set. addition driving chip output buffer, Macrocell output routed back UIM. private product term configured control Output Enable output buffer feedback
XACT Development System
EPLD Architecture
UIM. configured control feedback, Output Enable product term forces feedback control input High when Macrocell output disabled.
Fast Function Blocks
Each Fast Function Block receives signals their complements from UIM. inputs individually selected from UIM, FastInput pins, nine Macrocell feedbacks from FFB. programmable array each generates product terms drive nine Macrocells, which configured registered combinatorial logic. logic shown Figure A-4. Five product terms from programmable array allocated each Macrocell. Four these product terms ORed together drive input programmable D-type flip-flop. fifth product term drives asynchronous active-high Input Macrocell flip-flop. flip-flop configured transparent produce combinatorial output.
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
from Fast Input Pins
Array
Inputs from
Sum-of-Products from Previous Macrocell from Macrocell Feedback Private P-Terms Macrocell
Fast Clocks
Macrocells
Global Fast Control
P-Term Assignment Control Feedback Sum-of-Products Succeeding Macrocell
Register Transparent Control
X3307
Figure Fast Function Block Schematic 7354, 7372, 73108, 73144 programmable clock source global FastCLK signals (FCLK0 FCLK1) that distributed with short delay minimal skew over entire chip. Macrocells drive chip outputs directly through 3-state buffers. Each output buffer permanently enabled, permanently disabled, controlled dedicated Fast Output Enable inputs. Macrocell output also routed back UIM.The XC7300 family provides product term expansion feature that increases product-term flexibility without disabling Macrocell outputs. Product term expansion transfers product terms increments four product terms from Macrocell next.
XACT Development System
EPLD Architecture
Product Term Expansion
Complex logic functions requiring product terms implemented using this method. When product terms assigned adjacent Macrocells, product term normally dedicated function becomes D-input Macrocell register. Thus, Macrocell still usable while product terms transferred adjacent Macrocells.
From Previous Macrocell Single-Product Term Assignment
Eight-Product Term Assignment
X3205
Figure Product Term Expansion
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
XC7336 XC7318 Fast Function Blocks
Fast Function Blocks within XC7318 XC7336 slightly different from those rest Xilinx EPLD family shown Figure A-6.
Global Fast from Fast Input Pins Array
Inputs from
Sum-of-Products from Previous Macrocell from Macrocell Feedback Private P-Terms Macrocell
Fast Clocks
Block Macrocells Control
Output Polarity
P-Term Assignment Control Feedback Sum-of-Products Succeeding Macrocell Feedback
Register Transparent Control
X5218
Figure Fast Function Block Schematic 7318 7336
Input/Output Blocks
blocks provide 3-state outputs registered, latched, direct inputs. block registers also implement logic equations therefore decrease macrocell resource requirements. Macrocells drive chip outputs directly through 3-state output buffers, each individually controlled Output Enable product term. additional configuration option allows output disabled permanently. dedicated Fast Output Enable inputs also
A-10
XACT Development System
EPLD Architecture
configured control chip outputs instead conjunction with, individual Output Enable product term. Figure block schematic diagram. Each signal input chip connected programmable input structure that configured direct, latched, registered. latch flip-flop FastCLK signals latch enable clock. Latches transparent when FastCLK High, flip-flops clock rising edge FastCLK. flip-flop includes active-low clock enable, which when High, holds present state flip-flop inhibits response input signal. clock enable source global Clock Enable signals (CKEN0 CKEN1). additional configuration option polarity inversion each input signal.
Xilinx Synopsys Interface EPLD User Guide
A-11
Xilinx Synopsys Interface EPLD User Guide
Fast Fast Macrocell P-Term
I/O. FCLK/O, CKEN/O FOE/O Pins Only Driver
From Macrocell Register
Output Polarity
Feedback CKEN0 CKEN1
Input Polarity
FastCLK0 FastCLK1
Function Block AND-Array Fast Input Pins Only) Input Pins Only
FastCLK2 Global Select
X2832
Figure Input/Output Block Schematic CKEN0 CKEN1 inputs only available XC7300 family devices. Also, programmable input polarity feature available XC7272A.
A-12
XACT Development System
X2845
Xilinx Synopsys Interface EPLD User Guide
Library Component Specifications
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Appendix
Library Component Specifications
This appendix describes each Xilinx library components which summarized following table.
Used with These Devices Component Name ADSU ADSUR AND2-AND8 BUFCE BUFE BUFFOE BUFG CBX1 CBX2 COMPEQ COMPLE_TC COMPLE_US COMPLT_TC COMPLT_US COMPNE FDCP FDCPE FDPC IBUF Component Description Adder/Subtracter/Accumulator Adder Adder/Subtracter Adder/Subtracter with Registered Outputs Gates Buffer Clock Enable Inp. Buff. Input Reg. 3-State Buffer Fast Output Enable Input Buffer FastCLK Input Buffer Up/Down Counter with Asynchronous Clear Up/Down Counter with Asynchronous Reset Equal-To Comparator Less-Than-Or-Equal Comparator, Comp. Less-Than-Or-Equal Comparator, Unsigned Less-Than Comparator, Complement Less-Than Comparator, Unsigned Not-Equal Comparator Decrementor Edge-Triggered D-Type Flip-Flop with Asynchronous Clear Preset Edge-Triggered D-Type Flip-Flop with Clock Enable, Async. Clear Preset Edge-Triggered D-Type Flip-Flop with Asynchronous Clear Preset Input Buffer Input Register Scalable Inferable 7272 7236 7318 7336 7354 7372 73108
Xilinx Synopsys Interface EPLD User Guide December, 1994 (0401289
Xilinx Synopsys Interface EPLD User Guide
Used with These Devices Component Name IFDX1 IOBUFE IOBUFEX1 OBUF OBUFE OBUFEX1 OR2-OR8 SUBT XOR2-XOR8 Component Description Input Register with Clock Enable Input Latch Incrementer Inverter Bi-Directional Buffer Bi-Directional Buffer D-Type Latch Output Buffer 3-State Output Buffer 3-State Output Buffer with Enable Gates Subtracter Gates Scalable Inferable 7272 7236 7318 7336 7354 7372 73108
XACT Development System
Library Component Specifications
adder/subtracter/accumulator.
Inferencing
synthesizer does this component inference.
Component Instantiation
generic (WIDTH wordlength) port (Q=>output, B=>in_operand, C=>clock, CE=>clock_en, R=>sync_reset, L=>load_en, SUB=>add_sub_ctl);
Truth Table Logic Symbol
initial state "0".
B(width-1:0)
Q(width-1:0)
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
adder bound operator.
Inferencing
sum_signed in1_signed in2_signed;
Component Instantiation
generic (WIDTH wordlength) port (S=>sum, A=>in1, B=>in2);
Truth Table Logic Symbol
A(width-1:0) S(width-1:0) B(width-1:0)
XACT Development System
Library Component Specifications
ADSU
ADSU adder/subtracter. ADSU bound operators.
Inferencing
(sub_ctl '0') then sum_signed in1_signed in2_signed; else sum_signed in1_signed in2_signed;
Component Instantiation
ADSU generic (WIDTH wordlength) port (S=>output, A=>in1, B=>in2, SUB=>sub_ctl);
Truth Table Logic Symbol
A(width-1:0) S(width-1:0) B(width-1:0)
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
ADSUR
ADSUR registered adder/subtracter.
Inferencing
synthesizer does this component inference.
Component Instantiation
ADSUR generic (WIDTH wordlength) port (Q=>output, A=>in1, B=>in2, C=>clock, CE=>clock_en, R=>sync_reset, SUB=>add_sub_ctl);
Truth Table Logic Symbol
initial state "0".
A(width-1:0) B(width-1:0) Q(width-1:0)
XACT Development System
Library Component Specifications
AND2 AND8
AND2 through AND8 gates with inputs.
Inferencing
synthesizer uses these components when creating functions that require gates.
Component Instantiation
AND2 port (O=>out,I1=>in2,I0=>in1);
Truth Table Logic Symbol
AND6 AND7 AND8
AND5
AND4 AND3 AND2
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
buffer.
Inferencing
synthesizer does this component inference.
Component Instantiation
port (O=>out_port, I=>in_port);
Truth Table Logic Symbol
XACT Development System
Library Component Specifications
BUFCE
BUFCE input buffer used drive global signal (Chip Enable) EPLD input registers. BUFCE only used drive input IFDX1 components.
Inferencing
synthesizer does this component inference.
Component Instantiation
BUFCE port (O=>global_ce, I=>in_port);
Truth Table Logic Symbol
Xilinx Synopsys Interface EPLD User Guide
Xilinx Synopsys Interface EPLD User Guide
BUFE
BUFE non-inverting 3-state buffer.
Inferencing
synthesizer uses these components when creating functions that require 3-state buffers that drive internal signals.
Component Instantiation
BUFE port (O=>ts_out, I=>inp, E=>enable);
Truth Table Logic Symbol
B-10
XACT Development System
Library Component Specifications
BUFFOE
BUFFOE input buffer used drive global signal (Fast Output Enable). BUFFOE only used drive input OBUFEX1 IOBUFEX1 components
Inferencing
synthesizer does this component inference.
Component Instantiation
BUFFOE port (O=>global_foe, I=>in_port);
Truth Table Logic Symbol
Xilinx Synopsys Interface EPLD User Guide
B-11
Xilinx Synopsys Interface EPLD User Guide
BUFG
BUFG input buffer used drive Global FastCLK signal. Note: BUFG only drive register clock inputs (including IFDX1) input components. cannot drive component.
Inferencing
synthesizer does this component inference.
Component Instantiation
BUFG port (O=>global_clk, I=>in_port);
Truth Table Logic Symbol
B-12
XACT Development System
Library Component Specifications
CBX1
CBX1 loadable up/down counter with asynchronous clear.
Inferencing
synthesizer does this component inference.
Component Instantiation
CBX1 generic (WIDTH wordlength) port (Q=>output, all_ones, all_zeros, D=>load_data, C=>clock, CLR=>async_clr, L=>load_ctl, CEU=>count_up_ctl, CED=>count_down_ctl);
Truth Table Logic Symbol
D=111. Q=111. Q=111. Q=111. D=000. Q=000. Q=000. Q=000.
ILLEGAL CONDITION
initial state "0".
D(width-1:0)
Q(width-1:0)
Xilinx Synopsys Interface EPLD User Guide
B-13
Xilinx Synopsys Interface EPLD User Guide
CBX2
CBX2 loadable up/down counter with synchronous reset.
Inferencing
synthesizer does this component inference.
Component Instantiation
CBX2 generic (WIDTH wordlength) port (Q=>output, all_ones, all_zeros, D=>load_data, C=>clock, R=>sync_reset, L=>load_ctl, CEU=>count_up_ctl, CED=>count_down_ctl);
Truth Table Logic Symbol
D=11. Q=11. Q=11. Q=11. D=00. Q=00. Q=00. Q=00.
ILLEGAL CONDITION
initial state "0".
D(width-1:0)
Q(width-1:0)
B-14
XACT Development System
Library Component Specifications
COMPEQ
COMPEQ equal-to comparator.
Inferencing
synthesizer does this component inference.
Component Instantiation
COMPEQ generic (WIDTH wordlength) port (EQ=>comparison, A=>in1, B=>in2);
Truth Table Logic Symbol
Condition
A(width-1:0) B(width-1:0)
Xilinx Synopsys Interface EPLD User Guide
B-15
Xilinx Synopsys Interface EPLD User Guide
COMPLE_TC COMPLE_US
COMPLE_US unsigned binary less-than-or-equal-to comparator. COMPLE_TC two's complement less-than-or-equal-to comparator. These components bound "<=" ">=" operators.
Inferencing
comparison (in1_signed in2_signed);
Component Instantiation
COMPLE_US generic (WIDTH wordlength) port (LE=>comparison, A=>in1, B=>in2); COMPLE_TC generic (WIDTH wordlength) port (LE=>comparison, A=>in1, B=>in2);
Truth Table Logic Symbol
Condition
A(width-1:0) B(width-1:0)
B-16
XACT Development System
Library Component Specifications
COMPLT_TC COMPLT_US
COMPLT_US unsigned binary less-than comparator. COMPLT_TC two's complement less-than comparator. These components bound operators.
Inferencing
comparison (in1_unsigned in2_unsigned);
Component Instantiation
COMPLT_US generic (WIDTH wordlength) port (LT=>comparison, A=>in1, B=>in2); COMPLT_TC generic (WIDTH wordlength) port (LT=>comparison, A=>in1, B=>in2);
Truth Table Logic Symbol
Condition
A(width-1:0)
B(width-1:0)
Xilinx Synopsys Interface EPLD User Guide
B-17
Xilinx Synopsys Interface EPLD User Guide
COMPNE
COMPNE not-equal-to comparator.
Inferencing
synthesizer does this component inference.
Component Instantiation
COMPNE generic (WIDTH wordlength) port (NE=>comparison, A=>in1, B=>in2);
Truth Table Logic Symbol
Condition
A(width-1:0) B(width-1:0)
B-18
XACT Development System
Library Component Specifications
decrementor. bound "-1" operation.
Inferencing
sum_signed in_signed
Component Instantiation
generic (WIDTH wordlength) port (S=>sum, A=>in);
Truth Table Logic Symbol
A(width-1:0)
S(width-1:0)
Xilinx Synopsys Interface EPLD User Guide
B-19
Xilinx Synopsys Interface EPLD User Guide
FDCP
FDPC edge-triggered D-type flip-flop with preset clear.
Inferencing
synthesizer uses this component functions that require Dtype registers latches.
Component Instantiation
FDCP port (Q=>out, QN=>out_inv, D=>data, C=>clock, CLR=>async_clr, PRE=>async_set);
Truth Table Logic Symbol
initial state "0".
B-20
XACT Development System
Library Component Specifications
FDCPE
FDCPE edge-triggered D-type flip-
Other recent searches
VDD12 - VDD12 VDD12 Datasheet
VDD78 - VDD78 VDD78 Datasheet
RF2352 - RF2352 RF2352 Datasheet
LY61256 - LY61256 LY61256 Datasheet
IR12-21C - IR12-21C IR12-21C Datasheet
HVL355C - HVL355C HVL355C Datasheet
BSN304 - BSN304 BSN304 Datasheet
BSN304A - BSN304A BSN304A Datasheet
2SA985 - 2SA985 2SA985 Datasheet
2SA985A - 2SA985A 2SA985A Datasheet
1729225 - 1729225 1729225 Datasheet
14A-30-36 - 14A-30-36 14A-30-36 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
