Xilinx Synopsys Interface Version Software, Interface, Libraries June

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Release Document
Xilinx Synopsys Interface Version Software, Interface, Libraries June 1995
Read This Before Installation
Software Versions
Program APRLOOP HM2RPM LCA2XNF MakeBits MakePROM MAP2LCA MemGen XChecker Version XDelay XEMake XMake XNFBA XNFCvt XNFMAP XNFMerge XNFPrep XSimMake Program Version
Contents
Introduction Contents Hardware Software Documentation Maintenance Support Features This Release Lookup Table Optimization XC5200 Support XC3000 Optimization Support XC3000 XC5200 FPGA Compiler Design Flow Targeting XC5200 with Synopsys Version Targeting XC4025 with Version FPGA Compiler Does Write Block Names Default Synlibs Output Enhanced Support Default Slew Rates Support Inferred Pull-up/Pull-down Control Support Reading Netlists with XC4000 Carry Logic Primitives Improved X-BLOX Inference Optimization Enhancements/Modifications/Bug Fixes Programs XC5200 Primitives Flip-Flops Latches Clocks Primitives Special Functions System Requirements Disk Space Requirements SPARC HP-PA Installation Starting Installation Program Installation Requirements Remote Tape Operation Selecting Installation Directory XACT Installed Same Platform XACT Installed Installed Different Platform Program Versions Authorization Codes License Manager
June 1995
Synopsys
Installation Screen Messages Licensing Optional Components Tape Drive Specification Xilinx Window System Installing From CD-ROM UNIX System Installing From Tape UNIX System Installing From Tape HP-PA System Configuring Your Workstation Directory Tree Structure Synopsys Startup File Library Setup Setting .synopsys_dc.setup File Editing .synopsys_vss.setup File Analyzing DesignWare Simulation Libraries Device Package Support Known Issues X-BLOX DesignWare Library Must Analyzed Turn Density Optimization Better EPLD Timing XC4000A Slew Rate Selection Incorrect Synopsys V3.3a Unbonded I/Os Must Instantiated I/Os Default Correct Slew Rate FPGA Compiler Issues Errors Your Design Contains Timing Loops Compiler Issues Warning Asynchronous Preset Clear Flip-Flops Prevent Multiple OBUFs Driven Same EPLD Designs Design Analyzer Requires Replace FPGA Command EPLDs Issues Error X-BLOX Merges Flip-Flops into Issues Error Indicating That Many Instances Have Same BLKNM XNFPrep Error When Design Exceeds Maximum Number Clock Buffers Removed Compiler Compiler Replaces BUFGP_F with BUFGS_F Xilinx-supplied Hard Macros Automatically Incorporated into Your Designs Promdata.xnf File must Copied Promdata.sxnf File Path Reference Simulation Models Incorrect Xilinx Customer Support Information Registration, Authorization, Customer Service Technical Support Training
June 1995
Synopsys
Introduction
Welcome Synopsys Interface Package from Xilinx! This release note supports following products. Xilinx Synopsys Interface (DS-401) Xilinx Synopsys Interface Standard Development System Package (DS-SY-STD)
Contents
Development System (DS) product received contains software, documentation, and/or hardware. Base, Standard, Extended packages contain hardware, software, documentation. Interface Update products have software documentation only.
Hardware1
XChecker Download Readback Cable
Software
Xilinx software platforms provided CD-ROM. also place order 1/2" floppies. Xilinx software Sun4 series workstations HP700 workstations provided CD-ROM. Software other supported workstations provided appropriate cartridge tape media.
Documentation1
Getting Started Packet Additional Products Services Packet XACT Installation Guide XACT Libraries Guide Design Migration Guide Xilinx Synopsys Interface FPGA User Guide Xilinx Synopsys Interface EPLD User Guide XACT User Guide XACT Reference Guide, Volumes included maintenance upgrade packages
June 1995
Synopsys
XACT Hardware Peripherals Guide XEPLD Design Guide XEPLD Reference Guide XEPLD Software Quick Reference Card XEPLD Hardware Quick Reference Card Programmable Logic Data Book XACT Design Implementation Core Tools Known Issues
Maintenance Support
This product comes with free technical product information telephone support (toll-free U.S. Canada). also e-mail your questions. last page this release note offices phone numbers. This product comes with year maintenance; will receive software documentation updates automatically during that time. will receive notice year giving instructions renew your maintenance contract.
Features This Release
Lookup Table Optimization
3.3a version Synopsys tools, FPGA Compiler libraries lookup table (LUT) optimization. XC3000, XC3100, XC3000A, XC3100A, XC52000 families, these libraries allow FPGA Compiler synthesize your design collection lookup tables (function generators), registers, pads. Using these libraries, compiler works directly with building blocks architecture your design implemented targeted device exactly synthesized.
XC5200 Support
Synopsys Design Compiler FPGA Compiler synthesis libraries VHDL System Simulator (VSS) simulation libraries included XC5200 family, including support mapping using FPGA compiler. complete listing cells XC5200 synthesis simulation libraries included these notes. various translation programs utilities have been updated XC5200 family. default output from Synlibs specifies gate-level Design Compiler libraries. access FPGA Compiler cell libraries, option Synlibs. example, when using FPGA Compiler target XC5210-5, type:
June 1995
Synopsys
synlibs 5210-5 Synlibs utility responds follows: Note: continuation character added readability.
link_library {xprim_5210-5.db xprim_5200-5.db xgen_5200.db xfpga_5200-5.db xio_5200-5.db} target_library {xprim_5210-5.db xprim_5200-5.db xgen_5200.db xfpga_5200-5.db xio_5200-5.db} symbol_library {xc5200.sdb} synthetic_library {standard.sldb}
XC3000 Optimization Support
FPGA Compiler libraries have been created XC3000, XC3100, XC3000A, XC3100A families with 4-input cell (xc3000_lut4) 5-input cell (xc3000_lut5). 3.3a version FPGA Compiler uses single optimization cell time. more than cell present target library, compiler uses cell with largest number inputs. FPGA Compiler uses 4-input cell unless enable 5-input cell with following commands: Note: Substitute appropriate library name your target architecture. remove_attribute xfpga_3100a-3/xc3000_lut5 dont_use remove_attribute xfpga_3100a-3/xc3000_lut5 dont_touch set_dont_use xfpga_3100a-3/xc3000_lut4 set_dont_touch xfpga_3100a-3/xc3000_lut4 Preliminary testing indicates that default 4-input cell gives best results, however, 5-input cell improve critical path block level delays expense using more function generators. default output from Synlibs specifies gate-level Design Compiler libraries. access FPGA Compiler cell libraries, option Synlibs. example, when using FPGA Compiler target XC3142A-3, type: synlibs 3142a-3
June 1995
Synopsys
Synlibs utility responds follows: Note: continuation character added readability.
link_library {xprim_3142a-3.db xprim_3100a-3.db xgen_3000.db xfpga_3100a-3.db} target_library {xprim_3142a-3.db xprim_3100a-3.db xgen_3000.db xfpga_3100a-3.db} symbol_library {xc3000.sdb} synthetic_library {standard.sldb}
XC3000 XC5200 FPGA Compiler Design Flow
FPGA Compiler design flow XC3000 XC5200 device families similar XC4000 flow. However, although FPGA Compiler libraries used these families, Replace_fpga command should used. this command with XC3000 XC5200 design, compiler issues warning message indicating that Replace_fpga command used these families. want convert cells gates schematic viewing simulation, Replace_fpga command with "-force" option. Refer Synopsys online command help more information. default .synopsys_dc.setup files default compile scripts XC3000 XC5200 FPGA Compiler designs included $DS401/examples/ synopsys directory. suggested default compile script XC3000 XC5200 FPGA Compiler designs shown here:
Script Synopsys Xilinx FPGA Compiler v3.3*/ Optimization Design Flow XC3000/5200*/ Xilinx June 1995 <design_name> PART <part_type> analyze -format vhdl ".vhd" elaborate current_design remove_constraint -all create_clock "CLOCK" -period set_port_is_pad insert_pads
June 1995
Synopsys
compile report_fpga report_timing report_cell write -format set_attribute write -format exit
".fpga" -nets ".timing" ".cell" -hierarchy -output ".db" "part" -type string PART -hierarchy -output ".sxnf"
Targeting XC5200 with Synopsys Version
using Synopsys Version tools want target XC5200 devices, cannot libraries this release because database files were compiled using Synopsys Version 3.3. Database files gate-level Design Compiler libraries available upon request from Xilinx technical hotline calling 1-800-255-7778. Since mapping FPGA Compiler only available Version 3.3, these libraries available Version 3.2.
Targeting XC4025 with Version
This release does contain device-specific libraries XC4025. XC4025 designs, Xilinx recommends that compile with XC4013 libraries with speed grade want XC4025 then change part type XMake command line. Alternatively, "part" attribute your dc_shell script appropriate XC4025 device (with package speed grade).
FPGA Compiler Does Write Block Names Default
FPGA Compiler does write block names elements default this release. This modification greatly improves place route results. previous releases, following line added compile scripts just before SXNF files were written: set_attribute design "xnfout_use_blknames" -type boolean FALSE longer need this command, however, there adverse effects used (the attribute FALSE default).
Synlibs Output Enhanced
Synlibs outputs symbol library synthetic library strings addition link target libraries. default appropriate X-BLOX DesignWare library included synthetic library string. want this default, delete X-BLOX DesignWare information from synthetic library string.
June 1995
Synopsys
Support Default Slew Rates
default slow slew rate (high slew control) specified libraries outputs unless otherwise specified. Refer FPGA User Guide more information setting slew rates.
Support Inferred Pull-up/Pull-down Control
cells have attributes that allow infer pull-up pull-down resistors using set_pad_type command Synopsys tools. example, attach pull-up resistor input port named INPUT1, type: set_pad_type -pullup INPUT1 XC3000 families, only infer pull-ups. infer pull-up connections following cells: IBUF, IFD, ILD, IOBUF, IOBUF_N_F, IOBUF_N_S, OBUFT, OBUFT_F, OFDT, OFDT_F. BUFG_F, ACLK_F, GCLK_F XC4000 families, infer both pull-ups pull-downs. infer pull-up pull-down connections following cells: IBUF, IFDI_F, IFDI, IFD_F, IFD, ILD_1, ILD_1F, ILDI_1, ILDI_1F, IOBUF, IOBUF_N_F, IOBUF_N_S, OBUFT, OBUFT_F, OBUFT_S, OFDT, OFDT_F, OFDT_S, OFDTI, OFDTI_F, OFDTI_S, BUFG_F, BUFGP_F, BUFGS_F.
Support Reading Netlists with XC4000 Carry Logic Primitives
cell CY4_ mode cells have been added xgen_4000.db generic library improved post-implementation analysis. This library addition allows Read command's -xnf option allow FPGA Compiler read postroute files. After design read, perform timing analysis synthesize design again. Post-route files (generated with LCA2XNF) must processed XNF2VSS before they read FPGA Compiler avoid unresolved reference illegal record error messages.
Improved X-BLOX Inference Optimization
Don't Touch Don't attributes have been removed from X-BLOX cells common primitive libraries. This allows inferred X-BLOX components with unconnected outputs removed during optimization.
June 1995
Synopsys
Enhancements/Modifications/Bug Fixes Programs
Syn2XNF, XSIFix, Synlibs, Speedcheck, XNF2VSS programs have been enhanced support XC5200 family. Syn2XNF been enhanced support XC7000 devices. XNF2VSS supports LCANET version numbers that caused XNF2VSS misinterpret device tristate been fixed. that caused cell misinterpreted cell been fixed. Synlibs been enhanced provide link, target, synthetic, symbol library information XC5200 XC7000 families. Also, default library information Design Compiler XC3000 XC5200 families, FPGA Compiler XC4000 families. option specify FPGA Compiler library information XC3000 XC5200 families.
XC5200 Primitives
Table AND/OR Gates Name AND2 AND3 AND4 AND5 AND12 AND16 Outputs Inputs I11, I10, I15, I14, I13, I12, I11, I10, I11, I10,
NAND2 NAND3 NAND4 NAND5 NAND12
June 1995
Synopsys
Name NAND16
Outputs
Inputs I15, I14, I13, I12, I11, I10, I11, I10, I15, I14, I13, I12, I11, I10, I11, I10, I15, I14, I13, I12, I11, I10,
OR12 OR16
NOR2 NOR3 NOR4 NOR5 NOR12 NOR16
XOR2 XOR3 XOR4 XOR5 XNOR2 XNOR3 XNOR4 XNOR5 Table Inverter Name
Outputs
Inputs
Notes delay
June 1995
Synopsys
Table
Buffer Name Outputs 3-State Buffer Name Outputs Inputs Notes Synopsys tools synthesize internal 3-state condition using BUFTs. highimpedance state floating unless pullup resistor instantiated. Inputs Notes delay
Table
BUFT
Table
Decoders Name Outputs A<3:0> A<7:0> A<15:0> A<31:0> A<63:0> Inputs
DECODE4* DECODE8* DECODE16* DECODE32* DECODE64*
Indicates that must instantiate this primitive.
Table
Decoders Implementing Carry Logic Name Outputs Inputs C_IN, A<3:0> C_IN, A<7:0> C_IN, A<15:0>
DEC_CC4 DEC_CC8 DEC_CC16 Table
Resistor Inputs, Open-Drain 3-State Outputs Name Outputs Inputs Notes delay; used IOBs BUFTs
PULLUP
June 1995
Synopsys
Table
Resistor Ground Inputs Name Outputs Inputs Notes delay; used BUFTs
PULLDOWN
Flip-Flops Latches
This section lists flip-flops latches, which include flip-flops 1-bit transparent-High latches. Table Flip-Flops Name Outputs Inputs Notes With Clear Direct; initial startup value Clock Enable with Clear Direct; initial startup value With Preset Direct; initial startup value Clock Enable with Preset Direct; initial startup value
FDCE
FDPI FDPEI
Table
1-bit Transparent-High Latches Outputs Inputs Notes Active Enable Active Enable
Name LD_1 LDC_1 LDCE LDCE_1
Active Enable
June 1995
Synopsys
Clocks
This section lists clock buffer primitives. Table Clock Buffers Outputs Inputs Notes delay included Fast implementation clock; using dedicated
Names BUFG* BUFG_F
Indicates that must instantiate this primitive.
Primitives
This section lists primitives, which include input buffers, input buffers with flip-flop, input buffers with inverted latch, output buffers, 3-state output buffers, 3-state output buffers with flip-flop, output buffers with flip-flop, bidirectional buffers. buffers with flip-flops latches available XC4000H libraries. Table Input Buffers Outputs Inputs Notes Unbonded
Name IBUF IBUF_U*
Indicates that must instantiate this primitive.
Table
Output Buffers Name Outputs Inputs Notes Fast slew rate Slow slew rate Unbonded
OBUF OBUF_F OBUF_S OBUF_U*
Indicates that must instantiate this primitive.
June 1995
Synopsys
Table
3-State Output Buffers Name Outputs Inputs Notes Fast slew rate Slow slew rate Unbonded
OBUFT OBUFT_F OBUFT_S OBUFT_U*
Indicates that must instantiate this primitive.
Table
Bidirectional Buffers Outputs Inputs/ Outputs Inputs Notes Slow slew rate Fast output slew rate Slow output slew rate
Name IOBUF IOBUF_N_F IOBUF_N_S
Special Functions
This section lists special functions, which include boundary scan, readback, startup, mapping, flag cells, power, ground primitives. Table Boundary-Scan Logic Controller Outputs TDO, DRCK, IDLE, SEL1, SEL2, RESET, UPDATE, SHIFT Inputs TDI, TMS, TCK, TDO1, TDO2, Notes delay
Name BSCAN
Output BSCAN Output BSCAN Input BSCAN
June 1995
Synopsys
Name
Outputs
Inputs
Notes Input BSCAN Input BSCAN Input BSCAN Input BSCAN
connect IBUF TCK, TDI, input pads. Similarly, connect OBUF output. must connect IBUF symbol. Similarly, must connect OBUF symbol. Table Bitstream Readback Boundary-Scan Logic Controller (for Readback Function) Name RDBK Table Outputs DATA, Inputs TRIG Notes delay
Readback Controller (for Readback Function) Outputs Readback Function Outputs DATA, Inputs CLK, TRIG Notes delay Inputs Notes delay
Name RDCLK Table
Name READBACK Table
Startup Configuration Controller Outputs Q1Q4, DONEIN Inputs GTS,
Name STARTUP Table
Internal 5-Frequency Clock Signal Generator Outputs OSC1, OSC2 Inputs Notes delay
Name OSC5
June 1995
Synopsys
Name OSC52 CK_DIV Table
Outputs OSC1, OSC2 OSC1, OSC2
Inputs
Notes delay
Mapping Primitives Outputs Inputs Notes Pins unlocked from signals; function generator closed additional logic. Pins unlocked from signals; function generator closed additional logic. Pins locked external signals; function generator closed additional logic. Pins unlocked from signals; function generator open additional logic. Pins locked external signals; function generator open additional logic. Pins unlocked from signals; function generator closed additional logic. Used connect FMAPs form 5-input function.
Name FMAP_PUC
F5MAP_PUC
FMAP_PLC
FMAP_PUO
FMAP_PLO
HMAP_PUC
F5_MUX
June 1995
Synopsys
Table
Flag Cells Cell Inputs Power/Ground Name Outputs GROUND Carry Logic Cell Outputs COUT Inputs INIT Description Carry chain multiplexer. Initialization element carry chain. Description Signal critical path. Signal timing critical. Save signal; treat external connection. Signal explicit net.
C_FLAG N_FLAG S_FLAG X_FLAG Table
Table
CY_MUX CY_INIT
June 1995
Synopsys
System Requirements
Before installing DS-401 software, verify that your system meets requirements listed below.
Disk Space Requirements
following amount disk space required each option. numbers listed below approximation exactly match numbers that appear your screen during installation process. XC3000 (XC3000/A/L XC3100/A): XC4000 with X-BLOX (XC4000/A/D/H): XC5200: XC3000, XC4000, XC5200: XC7000:
SPARC
Sun-4 (SPARC) workstation running 4.1.x Swap Space
Note: swap space requirement Xilinx tools; Synopsys tool swap space requirement information, refer Synopsys System Installation Configuration Guide. RAM: Network: TCP/IP Display Interface: X-Windows (Xapollo, HPVue, OpenWindows) Disk space full install: Tape drive CD-ROM drive
HP-PA
HP-PA workstation running HP-UX Version 9.01 higher Swap Space
Note: swap space requirement Xilinx tools; Synopsys tool swap space requirement information, refer Synopsys System Installation Configuration Guide. Disk Space
June 1995
Synopsys
cartridge tape drive, local network-connected Disk space full install: Tape drive CD-ROM drive
Installation
This section explains install DS-401 software. Your software must installed same platform Synopsys software. However, Xilinx Development System, XACT V5.1 software, installed same network different network (platform); example, your XACT software might reside while your Synopsys tools reside UNIX-based workstation. Important: Synopsys Standard package (DS-SY-STD) available selectable package, however install this package selecting components. install DS-SY-STD package, first install XACT core tools from XACT CD-ROM selecting DS-3PA-STD package. Next, install DS401 software from CD-ROM into different directory than XACT tools. Note: installing DS-401 standalone package, ignore licensing messages that appear your screen during installation process. "Authorization Codes License Manager" section this release note more information.
Starting Installation Program
Installation Requirements
DS-401 installation requires cartridge tape CD-ROM drive. drive local machine remote-login accessible (via network). installation does require that logged root unless installing software directory that requires root privilege. should logged owner installation directory.
Remote Tape Operation
access remote tape drive, establish remote session machine with tape drive using rlogin command. important that remote tape drive same type your workstation. example, installing DS-401 workstation, tape drive must tape drive. cannot mount your file system remote machine, perform following.
June 1995
Synopsys
your system administrator mount your file system target machine repeat rlogin command. remote shell connect host execute specified commands. access host means remote shell, must able execute commands from remote shell target machine receive messages. following commands should result messages displayed your screen. workstation installation, enter following. remote echo HP-PA workstation installation, enter following. remsh remote echo
Selecting Installation Directory
best results, install DS-401 software subdirectory your system. existing DS-401 customer, important that create completely directory DS-401 software instead overwriting existing DS-401 XACT directory. Installing current release DS-401 directory allows validate your installation before removing software. recommended that select directory where user programs installed, such /usr, /usr/dev, /usr/local, then create separate subdirectory DS-401 programs. default install option install DS-401 software ./ds401_3.3 directory.
XACT Installed Same Platform
XACT Development System V5.1 installed, should install DS-401 Version software different directory than existing XACT directory (such /usr/local/ds401_3.3).
XACT Installed Installed Different Platform
XACT Development System installed installed different platform, must create directory installation DS-401. DS-401 installed different platform than XACT, refer Xilinx Synopsys Interface FPGA User Guide instructions translate transfer files between different platforms.
June 1995
Synopsys
Program Versions
will install following versions programs. Program Name Syn2XNF SEDIF2XNF Speedcheck Synlibs XNFMerge XSIFix XNF2VSS VMH2VSS Syn2EPLD 3.6.0 3.3.0 3.3.0 3.3.0 3.3.0 3.2.0 3.2.0 Version
Authorization Codes License Manager
current version DS-401 software does require licensing, need obtain authorization codes DS-401. necessary restart your Synopsys license manager DS-401 V3.3 tools.
Installation Screen Messages
Licensing
DS-401 does require license. ignore licensing messages that appear your screen during installation process. installing DS-SY-STD system, refer XACT Installation Guide licensing information.
Optional Components
There five installation components: required data files, required binary files, optional XC3000 files, optional XC4000 files, optional XC7000 files. XC3000 files contain libraries XC3000/A/L XC3100/A devices. XC4000 files contain libraries XC4000/A/D/H devices. XC5200 files contain libraries XC5200 devices. XC7000 files contain libraries XC7000 EPLDs.
June 1995
Synopsys
Tape Drive Specification
When prompted specify tape drive local remote, enter performed remote login used remote shell.
Xilinx Window System
ignore following message during installation. Before using Xilinx Window System programs, user must issue command `xhost allow Xilinx programs such xdm, xact xdelay connect display. most secure xhost `xhost <hostname>', where <hostname> name computer you're running
Installing From CD-ROM UNIX System
Check system requirements defined "System Requirements" section this release note. Insert CD-ROM into drive. Start window manager (OpenWindows X-Windows). Execute platform-specific commands. Sun4, enter following. mkdir /cdrom mount hsfs /dev/sr0 /cdrom /cdrom/install
Note: period must typed part install command. HP700, enter following. mkdir /cdrom mount /dev/dsk/3s0 /cdrom /cdrom/INSTALL\;1 Note: Workstation users must have root privileges mount commands root prompt, user prompt). Directories device names vary; therefore, check these names with your system administrator. Follow instructions your screen. have enough space, Xilinx recommends that install directory. This procedure enables validate installation before removing software.
June 1995
Synopsys
Refer "Setting Xilinx Environment" appendix XACT Installation Guide information update your configuration file with proper environment variables. Before running software, must install start network license manager. license manager running, protected applications start automatically. Authorize your software using information "License Management Workstations" section XACT Installation Guide.
Installing From Tape UNIX System
target system. node without tape drive, machine with tape drive shown following command example. /usr/ucb/rlogin machine_with_tape_drive following command create installation directory. /bin/mkdir directory_name Move installation directory. full_path/directory_name Insert tape into drive. Load installation script with following commands. /bin/mt /dev/rst0 rewind /bin/tar /dev/rst0
Note: common name UNIX systems tape drive /dev/rst0. Verify this name with your system administrator. cannot mount your file system machine with tape drive, rlogin. Instead, load installation script from your system shown following command. Remote remote node with tape drive used installation. remote /bin/mt /dev/rst0 rewind remote /bin/dd if=/dev/rst0 bs=20b /bin/tar
June 1995
Synopsys
installation script with following command follow instructions that appear your screen. period slash must typed part command. ./install Read text that concludes installation. messages displayed installation program stored "reminder" file. Your existing reminder file saved reminder.1.
Installing From Tape HP-PA System
target system. node without tape drive, machine with tape drive shown following command example. /usr/ucb/rlogin machine_with_tape_drive following command create installation directory. /bin/mkdir directory_name Move installation directory. full_path/directory_name
Note: software must installed disk that configured long file names. attempt install software disk that does support long file names, installation program stops directs move different disk. Insert tape into drive. Load installation script with following commands. /bin/mt /dev/rmt/0m rewind /bin/tar Oxvf /dev/rmt/0m options include (capital ensure that installer owns files, rather than just Xilinx user identification. common tape device name HP-PA systems /dev/rmt/0m 4-mm tape drive zero /dev/rmt/0m). Verify this name with your system administrator. installation program expects read from device configured density, rewind, Berkeley-style close. Such devices often have names such "/dev/rmt/c201d3lnb." last three characters lower case LNB.
June 1995
Synopsys
cannot mount your file system machine with tape drive, rlogin. Instead, load installation script from your system shown following command. Remote remote node with tape drive used installation. remsh remote /bin/mt /dev/rmt/0m rewind remsh remote /bin/dd if=/dev/rmt/0m bs=20b /bin/tar Oxvf installation script with following command follow instructions that appear your screen. period slash must typed part command. ./install Read text that concludes installation. messages displayed installation program stored "reminder" file. Your existing reminder file saved reminder.1.
Configuring Your Workstation
software, need make changes your environment described this section. Modify your .cshrc .login file include full path executables follows. $path) Substitute platform following: sparc, hppa, rs6000. full path installation directory XACT environment variable setting.
June 1995
Synopsys
following table list environment variables need depending your system configuration/setup. System Configuration Environment Variable
DS-401 XACT setenv XACT installed same platform different directories DS-401 XACT installed different platforms DS-401 platform, enter following. setenv XACT {DS-401_v3.3_Dir} XACT platform, enter following. setenv XACT {XACT_5.1_Dir}
environment variable, DS401, full path installation directory, follows. setenv DS401 {DS-401_v3.3_Dir}
Directory Tree Structure
After have completed installation, should have directory tree structure files shown follows. installed only XC3000 files, XC4000 files, XC5200 files, XC7000 files, will have files listed following figure.
June 1995
Synopsys
DS401_dir/ bin/platform/ synlibs syn2xnf sedif2xnf speedcheck xnfmerge syn2epld xnf2vss vmh2vss lib_compile data/synopsys/ parttype.spd <~44 .spd files> partlist.xct text.spd xmap_3000/ <~250 .xnf files> xmap_4000/ <~250 .xnf files> xmap_5200/ <~250 .xnf files> xprim_3000/ <~60 .xnf files> xprim_4000/ <~160 .xnf files> xprim_5200/ <~100 .xnf files> xprim_7000/ <~30 .xnf files> xunmap_3000/ <~250 .xnf files> xunmap_4000/ <~250 .xnf files> xunmap_5200/ <~250 .xnf files> synopsys/ libraries/dw/lib/fpga <xblox_dw_modules>.o <xblox_dw_modules>.syn <xblox_dw_modules>.sim <xblox_dw_modules>.mra libraries/dw/lib/epld <dw_modules>.syn <dw_modules>.sim <dw_modules>.mra libraries/dw/src/fpga README install_dw.dc <xblox_dw_modules>.vhd.e <xblox_dw_modules>.vhd.e.update libraries/dw/src/epld README install_dw.dc install_xc7000.dc <dw_modules>.vhd.e <dw_modules>.vhd.e.update libraries/syn/ xgen_family.db
June 1995
Synopsys
xfpga_family-speedgrade.db xprim_parttype-speedgrade.db xprim_family-speedgrade.db xio_parttype-speedgrade.db xdc_family-speedgrade.db xc3000.sdb xc4000.sdb xblox_4000.sldb xc7000.db xc7000.sdb xc7000.sldb xc5200.sdb libraries/sim/src/ xc4000 README install_xc4000.dc xc4000_FTGS.vhd.e xc4000_FTGS.vhd xc3000 README install_xc3000.dc xc3000_FTGS.vhd.e xc3000_FTGS.vhd xc5200 README install_xc5200.dc xc5200_FTGS.vhd.e xc5200_FTGS.vhd libraries/sim/lib/ xc4000 <vss4k_FTGS>.syn <vss4k_FTGS>.sim <vss4k_FTGS>.mra xc3000 <vss3k_FTGS>.syn <vss3k_FTGS>.sim <vss3k_FTGS>.mra xc5200 <vss5k_FTGS>.syn <vss5k_FTGS>.sim <vss5k_FTGS>.mra tutorial/synopsys/ fpga/x4000/ verilog dc/x3000a/ verilog
June 1995
Synopsys
epld verilog vss/xc4000 examples/synopsys/ fc4k.synopsys_dc.setup dc4k.synopsys_dc.setup dc3k.synopsys_dc.setup 7k.synopsys_dc.setup fpga.script dc.script fpga/ xc4000/ vhd/<design-directory> verilog/<design-directory> xc4000a/ vhd/<design-directory> verilog/<design-directory> xc4000h/ vhd/<design-directory> verilog/<design-directory> xc3000/ vhd/<design-directory> verilog/<design-directory> xc4000/ vhd/<design-directory> verilog/<design-directory> xc4000a/ vhd/<design-directory> verilog/<design-directory> xc4000h/ vhd/<design-directory> verilog/<design-directory>
June 1995
Synopsys
Synopsys Startup File Library Setup
Setting .synopsys_dc.setup File
Refer "Getting Started" chapter Xilinx Synopsys Interface FPGA User Guide instructions Synopsys start-up file FPGA designs. XC5200 designs, XC4000 .synopsys_dc.setup file, however, must modify link, target, symbol, synthetic library statements. Xilinx recommends that move four library statements your .synopsys_dc.setup file. Since Synlibs outputs complete library definition statements, append Synlibs output your .synopsys_dc.setup file. EPLD designs, your .synopsys_dc.setup file must contain lines listed below. (This supercedes "Creating Synopsys Setup Files" section Xilinx Synopsys Interface EPLD User Guide.)
search_path define_design_lib xc7000 -path\ link_library {xc7000.db xc7000.sldb} target_library {xc7000.db} symbol_library {xc7000.sdb} synthetic_library {xc7000.sldb} bus_naming_style "%s<%d>" bus_dimension_separator_style "><" bus_inference_style "%s<%d>" edifout_netlist_only true cell edifout_write_properties_list {LOC} compile_fix_multiple_port_nets true xnfout_library_version "2.0.0"
Editing .synopsys_vss.setup File
access simulation models XC5200 family, following line your .synopsys_vss.setup file: XC5200
June 1995
Synopsys
Analyzing DesignWare Simulation Libraries
DS-401 provides DesignWare libraries that support X-BLOX functions XC4000 designs high-level macro functions XC7000 designs. DS-401 also provides simulation libraries supporting VSS. need analyze DS-401 DesignWare VHDL files after install DS-401 before synthesize your first Xilinx design. VSS, also need analyze VHDL simulation models after install DS-401 before simulate your first Xilinx design. must repeat these steps each time install update your Synopsys software. analyze DesignWare files, change your current directory each DesignWare library source directories FPGA and/or EPLD (whichever applicable) install_dw.dc script, follows. dc_shell install_dw.dc dc_shell install_dw.dc previous commands analyze encrypted DesignWare VHDL files place output files into $DS401/synopsys /libraries/dw/lib/epld directories. should analyze DesignWare library files either VHDL Verilog languages synthesis. Make sure $SYNOPSYS environment variable where Synopsys software installed have write privileges $DS401/synopsys/libraries/ dw/lib/* directories. analyze model files, change your current directory simulation library source directory each Xilinx family using install_family.dc script. Substitute family with xc3000, xc4000, xc7000 follows. dc_shell install_xc3000.dc dc_shell install_xc4000.dc dc_shell install_xc5200.dc dc_shell install_xc7000.dc Note: simulation files XC7000 family located $DS401 /synopsys/libraries/dw/src/epld directory.
June 1995
Synopsys
previous commands analyze encrypted models place output files into /xc4000, $DS401/synopsys/libraries/ dw/lib/epld directories.
June 1995
Synopsys
Device Package Support
This master table Xilinx devices. X-BLOX supports XC3000A/L, XC3100A/L, XC4000 device families. Device
XC2018 XC2064 XC2018L XC2064L XC3020 XC3030 XC3042 XC3064* XC3090* XC3020A XC3030A XC3042A XC3064A* XC3090A* XC3020L XC3030L XC3042L XC3064L* XC3090L* XC3120 XC3130 XC3142 XC3164* XC3190* XC3195* XC3120A PC44 PC44 PC84 PC68 CB100 PC44 CB100 PQ100 PC84 CB164 PQ208 CB100 PC44 VQ100 CB100 TQ144 PC84 CB164 TQ176 PC84 PC84 PC84 PC84 PC84 CB100 PC44 CB100 TQ100 PC84 CB164 PQ208 PC84 CB100 PC68 PC68 VQ64 VQ64 CQ100 PC68 CQ100 TQ100 PG132 CQ164 PC68 PC68 PC84 VQ100 PG132 PC84
Packages
PC84 PD48 VQ100 PC68 PC84 PC84 PP132 PC84 PC84 PC84 PG84 PP132 PG175 PG84 PG68 TQ100 VQ64
Speed Grades
-100 -100 -130 -130
PC84 PG84 PG84 PQ160 PG175 PG84 PG84 PG132 PQ160 PP175
PG84 PQ100 PG132
PQ100 TQ100 PP132
-100 -100 -100 -100 -100
-125 -125 -125 -125 -125
PP175 PQ100 PQ100 PP132 TQ144 PQ160
PQ160
VQ64 PQ100
PQ208
VQ64 TQ144 TQ144 TQ176 PC68 PC68 PC84 TQ144 PG132 CQ164 PG175 PC68
VQ100 VQ100
PC84 PC84 PG84 PP132 PC84 PG223 PC84
PG84 PG84 PG132 PQ160 PG175 PP175 PG84
PQ100 PQ100 PP132
TQ100 PQ100
PP175 PQ160 PQ100
PQ160 PQ208
June 1995
Synopsys
Device
XC3130A XC3142A XC3164A* XC3190A* XC3195A* XC4003 XC4005* XC4006* XC4008* XC4010* XC4013* XC4002A XC4003A XC4004A* XC4005A* XC4010D* XC4013D XC4003H XC4005H* XC7236 XC7272 XC7318 XC7336 XC7354 XC7372 XC73108 XC73144 XC7236A XC7272A PC44 VQ100 CB100 TQ144 PC84 CB164 TQ176 PC84 PC84 CB164 PC84 MQ208 BG225 PQ208 BG225 PQ240 PC84 CB100 PC84 PC84 PC84 PQ160 PG191 MQ240 PC44 PC68 PC44 PC44 PC44 PC68 BG225 BG225 PC44 PC68 PC68 PC84 VQ100 PG132 PC84 PG175 PG120 PC84 PG156 PC84 CB196
Packages
PC84 PG84 PP132 PG175 PG223 PQ100 PG156 PQ160 PG191 MQ208 PG84 PG132 PQ160 PP175 PP175 PQ160 PQ208 PQ160 PC84 PQ100 PP132 TQ144 PQ160 PQ160 PQ208 PQ208 PG191 PQ160 VQ64 PQ100
Speed Grades
PQ208 PQ208
PQ160 PQ208
MQ208 MQ240 PG223 PG120 PC84 PG120 PG156 PQ160 PQ208 PG223 PC84 PQ44 PQ44 PC68 PC84 PC84 PG184 PC84 PQ100 PG120 PQ160 PQ160 VQ100 PQ100 TQ144 PQ208
VQ100 TQ144
PQ240 PG84
PG84 PG144 PQ160 PG84
PQ100 PQ100
PQ160
*Not supported Base Packages.
June 1995
Synopsys
Known Issues
X-BLOX DesignWare Library Must Analyzed Platform: Workstations Architecture: XC4000/A/D/H Design Step: Installation Reference Number: Available using Synopsys compiler Version 3.3a, must analyze X-BLOX DesignWare files simulation libraries. need analyze X-BLOX DesignWare VHDL files before target X-BLOX DesignWare library. analyze DesignWare files, refer README files located directories. need analyze simulation libraries before target them. analyze simulation libraries, refer "Analyzing DesignWare Simulation Libraries" section this release note more information. Turn Density Optimization Better EPLD Timing Platform: Workstations Architecture: XC7000 Design Step: Design Coding Reference Number: Available default, fitnet density optimization property (DENSITY_OPT) enabled, which causes some logic paths retain longer propagation delays than possible attempt pack more logic into device. many synthesis designs, density optimization produces little density benefits. Therefore, achieve maximum performance, should disable density optimization specifying NO_DENS attribute cell your design. design fails into desired device because requires more function blocks than available, removing NO_DENS density optimization help your design.
June 1995
Synopsys
XC4000A Slew Rate Selection Incorrect Synopsys V3.3a Platform: Workstations Architecture: XC4000A Design Step: Design Optimization Reference Number: 19166 Synopsys V3.3a, slew rate selection XC4000A devices incorrect. medium slew rate maps output that slow. Refer FPGA User Guide detailed information slew rates. Unbonded I/Os Must Instantiated Platform: Workstations Architecture: XC3000/A/L, XC3100/A, XC4000/A/D/H Design Step: Insertion Reference Number: Available must instantiate anything connected unbonded I/O, example, OFD_U, Synopsys tools will replace with another component, bonded counterpart. Therefore, must instantiate both unbonded primitive which connected. I/Os Default Correct Slew Rate Platform: Workstations Architecture: XC4000/A/D/H Design Step: Insertion Design Optimization Reference Number: Available Xilinx strongly recommends that your types device defaults. your pads default values, type following command before execute Port Insert Pads commands. XC4000/A/D devices, enter following. set_pad_type -slewrate HIGH all_outputs() XC4000H devices, enter following. set_pad_type -slewrate HIGH all_outputs() set_pad_type -voh 4.75 -vol all_outputs()
June 1995
Synopsys
FPGA Compiler Issues Errors Your Design Contains Timing Loops Platform: Workstations Architecture: XC4000/A/D/H Design Step: Compile Reference Number: 14433 following error occurs have timing loops timing constraints specified your design. FPGA Compiler breaks timing loops places Don't Touch attributes cells timing loop, which causes Replace FPGA command replace CLBs. Design contains CLBs, perform replace_fpga first. Remove Don't Touch attributes cells timing loop before running Replace FPGA command follows. remove_attribute find(cell, "*") dont_touch replace_fpga Compiler Issues Warning Asynchronous Preset Clear Flip-Flops Platform: Workstations Architecture: XC3000/A/L, XC3100/A, XC4000/A/D/H, XC5200 Design Step: Compile Reference Number: Available Synopsys issues following warning message described asynchronous preset clear flip-flop XC4000 design, preset flip-flop XC3000 XC5200 design. Warning: Target library contains replacement register `register' (**FFGEN**). (TRANS-4) This warning occurs because there primitives available match these descriptions library, device architecture does support these flip-flops.
June 1995
Synopsys
Prevent Multiple OBUFs Driven Same EPLD Designs Platform: Workstations Architecture: XC7000 Design Step: Compile Reference Number: Available synthesizer produces netlist containing more output ports (OBUFs) driven same net, fitnet produces following fatal error. ppi2051:[Error] 'node_name' driving multiple output buffers. intend same signal driven onto multiple output pins EPLD, should check design errors remove extraneous output ports. want implement redundant output pins, prevent error setting following attribute shell re-compiling design. Synopsys automatically inserts extra buffers before OBUFs produce desired signal each output. Design Analyzer Requires Replace FPGA Command EPLDs Platform: Workstations Architecture: XC7000 Design Step: Write File Reference Number: Available FPGA Compiler process EPLD design using Design Analyzer interface, must execute Replace FPGA command before write file, even though command effect EPLD designs. Issues Error X-BLOX Merges Flip-Flops into Platform: Workstations Architecture: XC3000A/L, XC3100A, XC4000/A/D/H Design Step: Implementation Reference Number: 17444 issues this error message your design contains timing specifications. ERROR 7019: Qualifier "pad_name" spec doesn't match input pad.
June 1995
Synopsys
flip-flop synthesized into flip-flop (DFF) Synopsys, subsequent X-BLOX design merge flip-flop into thus cause issue error follows. ***PPR: ERROR 7019: Qualifier "pad_name" spec doesn't match input pad. perform following. Remove timing specifications from your design include them constraints file. Remove "xlnx_hier_blknm=1" from .synopsys_dc.setup file, Uniquify command. prevent X-BLOX from merging flip-flop into IOB, X-BLOX with "mergeio=false" option shown following example. xblox design mergeio=false Issues Error Indicating That Many Instances Have Same BLKNM Platform: Workstations Architecture: XC3000A/L, XC3100A, XC4000/A/D/H, XC5200 Design Step: Implementation Reference Number: Available This error occurs have more than occurrence same subdesign your design, synthesis tool attached same block name (BLKNM) parameter instances same subdesign. issues this message because logic that being mapped this BLKNM attribute exceeds amount allowed CLB. correct this problem, perform following. Execute following command before writing file. xlnx_hier_blknm=1 Issue Uniquify command before compiling level design. Perform compile -ungroup_all.
June 1995
Synopsys
XNFPrep Error When Design Exceeds Maximum Number Clock Buffers Platform: Workstations Architecture: XC3000/A/L, XC3100/A, XC4000/A/D/H, XC5200 Design Step: Implementation Reference Number: Available This XNFPrep error occurs when insert_pads command Synopsys automatically infer I/Os. Error 3673: design uses `number' BUFGS symbols. maximum allowed There only four primary global clock buffers (BUFGP) four secondary global clock buffers (BUFGS) XC4000 architecture. There global clock buffer (GCLK) alternate clock buffer (ACLK) XC3000 family. There four global clock buffers (BUFG_F) XC5200 architecture. However, Synopsys place more than four BUFGPs BUFGs XC4000 design; more than GCLK ACLK XC3000 design; more than four BUFG_Fs XC5200 design. Consequently, XNFPrep issues error. correct problem, include following lines your script file before compile design, type them command line. set_pad_type -no_clock set_pad_type -clock "clock_port" Refer Xilinx Synopsys Interface FPGA User Guide more information. Removed Compiler Platform: Workstations Architecture: XC4000/A/D/H Design Step: Implementation Reference Number: 19735 incorporate XC4000 boundary scan capability configured FPGA using Synopsys tools, must manually instantiate boundary scan library primitives source code level. These primitives include TDI, TMS, TCK, TDO, BSCAN. must assign Synopsys Don't Touch attribute connected from port boundary scan symbol before execute Insert_pads Compile commands.
June 1995
Synopsys
Compiler Replaces BUFGP_F with BUFGS_F Platform: Workstations Architecture: XC4000 Design Step: Compile Reference Number: 21544 Synopsys compiler replaces BUFGP_F primitives with BUFGS_F primitives. instantiate BUFGP_F primitive, must attach Don't Touch attribute Xilinx-supplied Hard Macros Automatically Incorporated into Your Designs Platform: Workstations Architecture: Available Design Step: Available Reference Number: 22906 "Appendix current version User Guide, following stated: have Xilinx-supplied hard macros existing design, must copy appropriate file from $XACT/data/hmlib directory your design directory." current release, this longer applicable. hard macros automatically incorporated into your designs. Promdata.xnf File must Copied Promdata.sxnf File Platform: Workstations Architecture: Available Design Step: Available Reference Number: 22905 "Using FPGA Compiler" "Using Design Compiler" chapters User Guide, "Using MemGen" section missing following step: After have created promdata.xnf file with MemGen program, must copy this file promdata.sxnf file.
June 1995
Synopsys
Path Reference Simulation Models Incorrect Platform: Workstations Architecture: Available Design Step: Available Reference Number: 23670 "Simulating Your FPGA Design" chapter User Guide, library path definitions FTGS models incorrect. current release book, path XC4000 XC3000 Replace "vss" with "sim" create following correct path definitions: XC4000 XC3000
June 1995
Synopsys
Xilinx Customer Support Information
registration, authorization codes, update information, warranty status, shipping, product issues, technical support call Monday through Friday, a.m. p.m. Pacific time.
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Technical Support
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Training
United States Canada Xilinx Training Administrator .1-408-879-5090 International customers contact your local sales representative.
June 1995
Synopsys
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Xilinx Synopsys Interface Version Software, Interface, Libraries June

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