Xilinx Synopsys Interface FPGA User Guide Using FPGA Compiler Usi
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Introduction Getting Started FPGA Compiler Tutorial Design Compiler Tutorial
Xilinx Synopsys Interface FPGA User Guide
Using FPGA Compiler Using Design Compiler Simulating Your FPGA Design Files, Programs, Libraries
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291 Printed U.S.A.
Conventions
following conventions used this manual's syntactical statements. Courier font regular Courier font bold italic font System messages program files appear regular Courier font. Literal commands that must enter syntax statements bold Courier font. Variables that replace syntax statements italic font. Square brackets denote optional items parameters. Braces enclose list items from which must choose more. vertical ellipsis indicates material that been omitted. horizontal ellipsis indicates that preceding repeated more times. vertical separates items list choices. This symbol denotes carriage return.
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291
Xilinx Synopsys Interface FPGA User Guide
XACT Development System
Contents
Chapter
Introduction Xilinx Synopsys Interface
What XSI? Design Compiler Versus FPGA Compiler Xilinx Documentation Set. Documentation. XACT Documentation
Chapter
Getting Started
Software Configuration Verifying Software Installation. Modifying Default Synopsys Startup File Using FPGA Compiler Generic FPGA Compiler Startup File Contents Modifying Search Paths. Modifying DesignWare Library Search Path. Using Synlibs with FPGA Compiler Using Design Compiler XC4000 Designs. Generic Design Compiler Startup File Contents. Modifying Search Path Modifying DesignWare Library Search Path. Using Synlibs with Design Compiler Using Design Compiler XC3000 Designs. Generic Design Compiler Startup File Contents. Modifying Search Path Using Synlibs XC3000 Devices 2-11 2-11 2-11 2-12 2-13 2-14 2-15
Chapter
FPGA Compiler Tutorial XC4000 Designs
Before Begin. Required Files. Exiting Tutorial Design Flow Count8 Design Description Invoking Design Analyzer Reading Design File.
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291
Xilinx Synopsys Interface FPGA User Guide
Analyzing Design File Creating Design File Inserting Buffers Defining Input Ports Pads Defining Output Port Using Insert Pads Command Estimating Pre-Layout Timing Selecting Operating Condition Setting Wire-Load Models. Optimizing Speed. Compiling Design Evaluating Results Viewing Estimated Area Results. Viewing Estimated Timing Results. Saving Area Timing Results File. Saving Design Writing File Replacing CLBs IOBs with Gates Setting Design Part Type Removing BLKNM Attributes Saving Design File SXNF File. Exiting Design Analyzer Executing Commands from Script File. Placing Routing Your Design Using XMake. Same Network XACT Software Different Network Than XACT Software. Running Syn2XNF Running XMake Examining XMake Output Files. Reviewing XMake File. Checking Warnings Errors File. Checking File. Comparing Actual Versus Estimated Area Results Using XDelay Invoking XDelay Comparing Actual Versus Estimated Timing Results Verifying Your Design Using XChecker
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Chapter
Design Compiler Tutorial XC3000A Designs
Before Begin Required Files.
XACT Development System
Contents
Exiting Tutorial Design Flow Count8 Design Description Invoking Design Analyzer Reading Design File. Analyzing Design File Creating Design File Inserting Buffers Defining Input Ports Pads Defining Output Port Using Insert Pads Command. Estimating Pre-Layout Timing. Selecting Operating Condition Setting Wire-Load Models Optimizing Speed Compiling Design. Evaluating Results Viewing Estimated Area Results. Viewing Estimated Timing Results Saving Report Results File Saving Design. Writing File. Setting Design Part Type. Saving Design File SEDIF File. Exiting Design Analyzer Executing Commands from Script File. Placing Routing Your Design Using XMake. Same Network XACT Software Different Network Than XACT Software Running Syn2XNF. Running XMake Examining XMake Output Files Reviewing XMake File Checking Warnings Errors File Checking File. Comparing Actual Versus Estimated Area Results Using XDelay Invoking XDelay. Comparing Actual Versus Estimated Timing Results Verifying Your Design Using XChecker
4-12 4-13 4-15 4-16 4-16 4-17 4-17 4-17 4-19 4-20 4-22 4-25 4-25 4-28 4-28 4-28 4-28 4-29 4-30 4-33 4-34 4-34 4-34 4-35 4-35 4-36 4-36 4-37 4-42 4-43 4-44 4-45 4-45
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Chapter
Using FPGA Compiler
Before Begin FPGA Compiler Design Flow Same Platform XACT Software. Different Platform than XACT Software Setting Wire-Load Model. Wire-Load Models Xilinx FPGAs Changing Wire-Load Model Wire-Load Models Determined Operating Conditions Configuring IOBs. XC4000/A/D IOBs Inputs Outputs XC4000/D Slew Rate. XC4000A Slew Rate XC4000H IOBs Inputs Outputs XC4000H Slew Rate. Assigning Prohibiting Locations. Implementing 3-State Registered Output. Directly Driving 3-State Signal Directly Driving 3-State Signal Inserting Bidirectional I/Os Instantiating Registered Bidirectional I/O. Compiling Bidirectional Using Unbonded IOBs (XC4000/A Only) Adding Pull-Up Pull-Down Resistors. Removing Default Input Delay Initializing Flip-Flop Preset. Inserting Clock Buffers Controlling Clock Buffer Insertion Determining Number Clock Buffers Preventing Insertion Clock Buffers. Using Memory XC4000 RAMs XC4000 ROMs. Using MemGen Performing Boundary Scan 5-10 5-11 5-12 5-13 5-14 5-15 5-15 5-15 5-17 5-19 5-20 5-21 5-25 5-25 5-26 5-26 5-26 5-27 5-30 5-30 5-31 5-31 5-32 5-34 5-37
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XACT Development System
Contents
Using Global Set/Reset Startup State. Preset Versus Direct Clear Changing States Increasing Performance with Net. Using X-BLOX DesignWare Library. Operators Using X-BLOX Modules. Improving Timing X-BLOX Modules Creating Timing Specifications Setting Timing Constraints. Create Specifications Input Ports Clock Create Specifications Input Output Ports Create Tighter Constraints Output Ports Create Tighter Constraints Input Ports Prevent Specifications Indicated Paths Create Clocks Input Ports. Controlling Timing Specifications Written Control Number Constraints Written. Create Default Timing Constraints Compiling Design. Optimizing Logic Across Hierarchical Boundaries Flattening Design. Compiling Design with Hierarchy. Compiling Design Without Hierarchy Creating Unique Names Multiple Instances Compiling Design That Contains Feedthroughs Compiling Design with Instantiated Cells. Compiling XC4000 Designs. Compiling XC4000H Designs Creating Area Report Evaluating Timing Delays Generating Reports Debugging Generating Configuration Report. Generating Hierarchical Schematic Creating Level Each IOB. Creating Level Each Function Generator Writing Saving Design. Saving File Replacing CLBs IOBs with Gates Invoking Replace FPGA Command. Your Design Contains Hierarchy
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Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Removing Synopsys Mapping Removing FMAP HMAP Symbols Removing BLKNM Attributes Setting Design Part Type Saving SXNF File. Translating SXNF Files Files Using Syn2XNF. Syntax Input Files Output Files. Options. -dir. -force. -help -out. -parttype. Using XACT Development System Same Platform XACT Software Different Platform Than XACT Software
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Chapter
Using Design Compiler
Before Begin Design Compiler Design Flow. Same Platform XACT Software Different Platform Than XACT Software Setting Wire-Load Model. Wire-Load Models Xilinx FPGAs Changing Wire-Load Model Wire-Load Models Determined Operating Conditions Configuring IOBs. XC4000/A/D IOBs Inputs Outputs XC4000/D Slew Rate. XC4000A Slew Rate XC4000H IOBs Inputs Outputs XC4000H Slew Rate. XC3000/A/L XC3100/A IOBs 6-10 6-10 6-11 6-12 6-13
XACT Development System
Contents
Inputs. Outputs XC3000/A/L XC3100/A Slew Rate Assigning Prohibiting Locations Implementing 3-State Output. Directly Driving 3-State Signal Directly Driving 3-State Signal Inserting Bidirectional I/Os. Instantiating Registered Bidirectional Compiling Bidirectional Using Unbonded IOBs Adding Pull-Up Pull-Down Resistors Removing Default Input Delay (XC4000 Only) Initializing Flip-Flop Preset (XC4000 Only). Inserting Clock Buffers. XC4000/A/D/H Clock Buffers. XC3000/A/L XC3100/A Clock Buffers. Controlling Clock Buffer Insertion Determining Number Clock Buffers Preventing Insertion Clock Buffers Using Memory. XC4000 RAMs ROMs. Using MemGen. Performing Boundary Scan XC4000 Devices. Using Global Set/Reset XC4000 Devices Startup State. Preset Versus Direct Clear Changing States Increasing Performance with Net. XC3000 XC3100 Devices Using X-BLOX DesignWare Library. Operators Using X-BLOX Modules. Improving Timing X-BLOX Modules Compiling Design. Compiling Design That Contains Feedthroughs Compiling XC3000 XC4000 Designs. Compiling XC4000H Design Creating Area Report Evaluating Timing Delays
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Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Writing Saving Design. Saving File Setting Design Part Type Saving SEDIF File. Translating SEDIF Files Files Using Syn2XNF. Syntax Input Files Output Files. Options. -dir. -force. -help -map. -out. -parttype. -sub Using XACT Development System Same Platform XACT Software Different Platform Than XACT Software
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Chapter
Simulating Your FPGA Design
Recommended FPGA Simulation Strategy. Editing Setup File. Check Your Source File Controlling Initial States Registers Simulating Global Set/Reset Preparing Timing Simulation Preparing Functional Simulation. Creating Test Bench File. Initializing Registers Configuration Declaration Functional Simulation. Design Implementation Preparing Timing Model Timing Simulation. 7-12 7-14 7-14
Chapter
Files, Programs, Libraries
Directory Structure File Descriptions. Program Descriptions.
XACT Development System
Contents
Library Descriptions Supported Part Types Speed Grades. xprim_family-s.db xprim_parttype-s.db xio_4kparttype-s.db xfpga_family-s.db. xdc_family-s.db. Unsupported Part Types Speed Grades.
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Appendix XC3000/A/L XC3100/A Primitives
XC3000 Primitives Basic Gates Flip-Flops Latches Clocks Oscillators Primitives Special Functions
Appendix XC4000/A/D/H Primitives Hard Macros
XC4000 Primitives Basic Gates Flip-Flops Latches Clocks Primitives Special Functions X-BLOX Modules XC4000 Hard Macros B-16 B-19 B-20
Appendix Selection Guide
XC3000/A/L XC3100/A Primitives. XC4000/A/D/H Primitives.
Xilinx Synopsys Interface FPGA User Guide
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Xilinx Synopsys Interface FPGA User Guide
XACT Development System
Introduction
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Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291 Printed U.S.A.
Xilinx Synopsys Interface FPGA User Guide
XACT Development System
Chapter
Introduction Xilinx Synopsys Interface
This chapter introduces XSI, discusses compiler options, FPGA Compiler Design Compiler, describes documentation set.
What XSI?
design tool allows implement Xilinx Field Programmable Gate Array (FPGA) designs using either Synopsys FPGA Compiler Design Compiler synthesis tool. These Synopsys High-Level Design Automation (HLDA) tools create optimize circuit designs from hardware descriptions written VHSIC Hardware Description Language (VHDL) Verilog HDL. Library support XC4000 family also includes DesignWarelibrary that maps adder/subtracter, comparator, incrementer/ decrementer functions appropriate X-BLOXTMmodules. X-BLOX implements these functions using features XC4000 family such fast carry logic. X-BLOX included standard software packages. Before starting Xilinx design with Synopsys, read next chapter, "Getting Started."
Design Compiler Versus FPGA Compiler
contains libraries XC3000/A/L, XC3100/A, XC4000/ A/D/H families. either FPGA Compiler Design Compiler synthesize design Xilinx devices. Design Compiler (V3.1x later) provides following features.
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291
Xilinx Synopsys Interface FPGA User Guide
Optimizes flip-flops latches input/output block (IOB) Optimizes 3-state buffers Encodes one-hot state machines Uses configurable logic block (CLB) Clock Enable automatically
addition features provided Design Compiler, FPGA Compiler delivers more efficient results more accurate timing area reporting follows.
Optimizes logic XC4000 family architectures Reports area timing device architecture, example, CLB, IOB, 3-state buffer Passes timing constraints XACT-Performanceutility Reads (Xilinx Netlist Format) reader files design reuse back-annotation post-route results
Note: This manual assumes that using FPGA Compiler synthesis tools XC4000 devices. have FPGA Compiler, provides XC4000 libraries that with Design Compiler. FPGA Compiler XC3000 XC3100 devices; however, libraries these devices Design Compiler synthesis features.
Xilinx Documentation
Xilinx documentation consists series books that help XACT® Development System with your Synopsys tools.
Documentation
documentation includes following manuals.
Release Notes provide detailed instructions installing software additional platform-specific information, well known issues workarounds. Xilinx Synopsys Interface FPGA User Guide, this guide, contains information your Synopsys tools with XACT Development System create FPGA designs. "Preface" describes contents each chapter.
XACT Development System
Introduction Xilinx Synopsys Interface
Xilinx Synopsys Interface EPLD User Guide contains information your Synopsys tools with XACT Development System create EPLD designs.
XACT Documentation
XACT documentation includes following manuals.
XACT User Guide contains overview XACT Development software, including general design implementation flows configuration hints. XACT Reference Guide provides detailed information programs that XMake invokes during design implementation design verification stages. X-BLOX User Guide describes X-BLOX synthesis tool, which consists library modules describe high-level functions. XACT Libraries Guide presents information about various Xilinx-provided primitives macros.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
XACT Development System
Getting Started
X2845
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291 Printed U.S.A.
Xilinx Synopsys Interface FPGA User Guide
XACT Development System
Chapter
Getting Started
This chapter enables verify that Xilinx software installed. This chapter also describes following.
Modify your Synopsys startup file, .synopsys_dc.setup Synlibs program determine correct libraries FPGA Compiler Design Compiler
Note: Read this chapter before begin FPGA Compiler tutorial Design Compiler tutorial.
Software Configuration
Your software (DS-401) must installed same platform Synopsys software. However, XACT software (DS-502) installed same network different network (platform); example, your XACT software might reside while your Synopsys tools reside UNIX-based workstation. more information, consult installation section release notes your system administrator.
Verifying Software Installation
This section enables verify that XACT, X-BLOX, installed your system that your .cshrc .login files include required environmental variables search paths. platform where XACT software installed. verify that your system XACT Development System software (DS-502), type which system prompt.
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291
Xilinx Synopsys Interface FPGA User Guide
full path appears onscreen. system cannot find PPR, refer installation instructions release notes your system administrator. verify that X-BLOX (DS-380) been installed, type which xblox system prompt. full path X-BLOX appears onscreen. system cannot find X-BLOX, refer installation instructions release notes. verify that (DS-401) been installed, type which syn2xnf system prompt. Note: installed different platform, that platform before executing Syn2XNF command. full path appears onscreen. system cannot find Syn2XNF, refer installation instructions release notes your system administrator. Change following directory. DS401-Directory directory where installed. List contents this directory verify that source X-BLOX DesignWare files were placed this directory during installation. This directory should contain object file X-BLOX DesignWare symbol modules (xblox_dw_module.syn) simulation modules (xblox_dw_module.sim). Note: variable xblox_dw_module refers X-BLOX DesignWare primitive name. find files this directory, refer release notes your system administrator. README file contains installation instructions located directory. Refer installation notes instructions analyze X-BLOX DesignWare modules.
XACT Development System
Getting Started
Modifying Default Synopsys Startup File
.synopsys_dc.setup file startup file Synopsys synthesis tools. This file contains search path libraries, Synopsys libraries, user libraries. provides default Synopsys startup file. This section describes modify this default setup file include path Xilinx link target libraries FPGA Compiler Design Compiler well other required libraries. provides default Synopsys startup file following directory. DS401-directory/synopsys DS401-Directory directory where installed. know location this directory, type following system prompt. echo $XACT system displays paths XACT environment variable lists path first. already have .synopsys_dc.setup file, must modify your file include commands found Xilinx-supplied default startup file. already have Synopsys startup file, copy appropriate Xilinx-supplied startup file your home working directory rename follows. .synopsys_dc.setup Substitute tech with following options.
fc4k using FPGA Compiler dc4k using Design Compiler with XC4000 devices dc3k using Design Compiler with XC3000/A/L XC3100/A devices
following sections describe modify your setup file selected compiler.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Using FPGA Compiler
FPGA Compiler requires five libraries synthesis Xilinx devices. libraries separated reduce disk space. This section describes modify search path, modify DesignWare library search path, Synlibs display appropriate target link libraries. Figure example default startup file provided with software fc4k.synopsys_dc.setup. Refer your Synopsys documentation more information about Synopsys startup file.
Figure Synopsys Startup File
Generic FPGA Compiler Startup File Contents
This section describes sample .synopsys_dc.setup file illustrated Figure 2-1.
XACT Development System
Getting Started
search_path
This line sets search path Xilinx Synopsys-supplied library files.
link_library {xprim_4005-5.db xprim_4000-5.db xgen_4000.db xio_4000-5.db xfpga_4000-5.db} target_library {xprim_4005-5.db xprim_4000-5.db xgen_4000.db xio_4000-5.db xfpga_4000-5.db}
These lines specify default target link libraries that indicate which compiler used. sample libraries XC4005-5 device. these libraries FPGA Compiler tutorial. Synlibs program determines correct libraries different device types speed grades. Refer "Using Synlibs with FPGA Compiler" section that follows more information Synlibs change link target libraries different part type speed grade. target link libraries device-specific. Therefore, might want specify target link libraries generic startup file.
symbol_library xc4000.sdb
This line specifies symbol libraries.
define_design_lib WORK -path ./WORK
This line creates directory store intermediate files created Analyze command users.
define_design_lib xblox_4000 -path
This line specifies directory where X-BLOX DesignWare components reside.
synthetic_library {xblox_4000.sldb standard.sldb}
This line specifies synthetic library.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
compile_fix_multiple_port_nets true
This line allows Synopsys optimization algorithm insert extra logic into design ensure that there feedthroughs that output ports connected same net.
xlnx_hier_blknm
This line creates unique names each instance submodule hierarchical design that have more than instance same module.
xnfout_library_version "2.0.0"
This line allows Synopsys write version file. default, Synopsys writes version file. must specify this command using V3.1 later libraries XACT V5.0 later software.
bus_naming_style "%s<%d>" bus_dimension_separator_style "><" bus_inference_style "%s<%d>"
These lines READ parameters Xilinx netlist formats. indexing form ``bus<index>.''
Modifying Search Paths
Modify search path line default .synopsys_dc.setup file include path Synopsys installation directories follows. determine Synopsys installation path, enter following command line. echo $SYNOPSYS Open setup file text editor replace DS401-Directory with full path directory where software installed (the $XACT environment variable contains this path). Replace SYNOPSYS-Directory with path where your Synopsys software installed (usually stored environment variable $SYNOPSYS).
XACT Development System
Getting Started
Modifying DesignWare Library Search Path
X-BLOX DesignWare library contains descriptions adders, subtracters, comparators, incrementers, decrementers that X-BLOX modules. X-BLOX also generates Xilinx-optimized implementations common functions. have X-BLOX package, follow this procedure. Modify following line your .synopsys_dc.setup file X-BLOX DesignWare library. define_design_lib xblox_4000 -path /lib/fpga DS401-XACT-Directory full path directory where software installed (the $XACT environment variable contains this path). X-BLOX, comment remove following lines Synopsys startup file. Enclose your comments with (slash, asterisk) (asterisk, slash), illustrated following example. define_design_lib xblox_4000 -path /lib/fpga synthetic_library {xblox_4000.sldb standard.sldb}
Using Synlibs with FPGA Compiler
Synlibs displays link target libraries specified part type speed grade. Synlibs from directory follows. synlibs parttype-speedgrade example, list link target libraries XC4005-5 device, would enter following. synlibs 4005-5 system displays output onscreen, illustrated Figure 2-2.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
link_library {xprim_4005-5.db xprim_4000-5.db xgen_4000.db xio_4000-5.db xfpga_4000-5.db} target_library {xprim_4005-5.db xprim_4000-5.db xgen_4000.db xio_4000-5.db xfpga_4000-5.db}
Figure Synlibs Output with FPGA Compiler Note: target link libraries default startup file plan perform FPGA Compiler tutorial. must copy output from Synlibs into your Synopsys startup file. UNIX Append (>>) command redirect output Synlibs your .synopsys_dc.setup file follows. synlibs parttype-speedgrade .synopsys_dc.setup After redirect output, text editor delete default target link libraries. Warning: must list libraries your setup file order that they appear Synlibs output.
Using Design Compiler XC4000 Designs
Design Compiler requires five libraries synthesis Xilinx XC4000 devices. libraries separated reduce disk space. This section describes modify search path, modify DesignWare Library search path, Synlibs display appropriate target link libraries. Figure example generic startup file XC4000 design, dc4k.synopsys_dc.setup, using Design Compiler.
XACT Development System
Getting Started
Figure Generic XC4000 Design Compiler Startup File
Generic Design Compiler Startup File Contents
This section describes sample .synopsys_dc.setup file illustrated Figure 2-3.
search_path
This line sets search path Xilinx Synopsys-supplied library files.
link_library {xprim_4005-5.db xprim_4000-5.db xgen_4000.db xdc_4000-5.db xio_4000-5.db} target_library {xprim_4005-5.db xprim_4000-5.db xgen_4000.db xdc_4000-5.db xio_4000-5.db}
These lines specify default target link libraries, which XC4005-5 device.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Synlibs program determines correct libraries different device types speed grades. Refer "Using Synlibs with Design Compiler" section that follows more information Synlibs change link target libraries different part type speed grade. target link libraries device-specific. Therefore, might want specify target link libraries your generic startup file.
symbol_library xc4000.sdb
This line specifies symbol libraries.
define_design_lib WORK -path ./WORK
This line creates directory store intermediate files created Analyze command users.
define_design_lib xblox_4000 -path
This line specifies directory where X-BLOX DesignWare components reside.
synthetic_library {xblox_4000.sldb standard.sldb}
This line specifies synthetic library.
compile_fix_multiple_port_nets true
This line allows Synopsys optimization algorithm insert extra logic into design ensure that there feedthroughs that output ports connected same net.
bus_naming_style "%s<%d>" bus_dimension_separator_style "><" bus_inference_style "%s<%d>"
These lines READ parameters Xilinx netlist formats. indexing form ``bus<index>.''
edifout_netlist_only true cell edifout_write_properties_list "instance_number port_location part"
These lines EDIF parameters Xilinx devices.
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XACT Development System
Getting Started
Modifying Search Path
Modify search path line default .synopsys_dc.setup file include path Synopsys installation directories follows. determine Synopsys installation path, enter following command line. echo $SYNOPSYS Open setup file text editor replace DS401-Directory with full path directory where software installed (the $XACT environment variable contains this path). Replace SYNOPSYS-Directory with path where your Synopsys software installed (usually stored environment variable $SYNOPSYS).
Modifying DesignWare Library Search Path
X-BLOX DesignWare library contains descriptions adders, subtracters, comparators, incrementers, decrementers that X-BLOX modules. X-BLOX also generates Xilinx-optimized implementations common functions. have X-BLOX package, following line your .synopsys file X-BLOX DesignWare library. define_design_lib xblox_4000 -path /lib/fpga Verify that your .synopsys_dc.setup file contains following statement. synthetic_library {xblox_4000.sldb standard.sldb}
Using Synlibs with Design Compiler
Synlibs displays link target libraries specified part type speed grade. Synlibs from directory follows. synlibs parttype-speedgrade
Xilinx Synopsys Interface FPGA User Guide
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Xilinx Synopsys Interface FPGA User Guide
must specify option list link target libraries with Design Compiler. example, list link target libraries XC4005-5 device with Design Compiler, would enter following. synlibs 4005-5 system displays output onscreen illustrated Figure 2-4.
link_library {xprim_4005-5.db xprim_4000-5.db xgen_4000.db xdc_4000-5.db xio_4000-5.db} target_library {xprim_4005-5.db xprim_4000-5.db xgen_4000.db xdc_4000-5.db xio_4000-5.db}
Figure Synlibs Output with Design Compiler (XC4000) must copy output from Synlibs into your Synopsys startup file. UNIX Append (>>) command redirect output Synlibs your .synopsys_dc.setup file follows. synlibs parttype-speedgrade .synopsys_dc.setup After redirect output, text editor delete default target link libraries. Warning: must list libraries your setup file order that they appear Synlibs output.
Using Design Compiler XC3000 Designs
Design Compiler requires four libraries synthesis Xilinx XC3000/A/L XC3100/A devices. libraries separated reduce disk space. This section describes modify search path Synlibs display appropriate target link libraries. Figure example generic startup file, dc3k.synopsys_dc.setup, XC3000A design using Design Compiler.
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XACT Development System
Getting Started
Figure Generic XC3000A Design Compiler Startup File
Generic Design Compiler Startup File Contents
This section describes sample .synopsys_dc.setup file illustrated Figure 2-5.
search_path
This line sets search path Xilinx Synopsys-supplied library files.
link_library {xprim_3020a-6.db xprim_3000a-6.db xgen_3000.db xdc_3000a-6.db} target_library {xprim_3020a-6.db xprim_3000a-6.db xgen_3000.db xdc_3000a-6.db}
These lines specify default target link libraries that indicate which compiler Synopsys uses. link target libraries XC3020A-6 device. these libraries Design Compiler tutorial XC3000A devices.
Xilinx Synopsys Interface FPGA User Guide
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Xilinx Synopsys Interface FPGA User Guide
Synlibs program determines correct libraries different device types speed grades. Refer "Using Synlibs XC3000 Devices" section that follows more information Synlibs change link target libraries different part type speed grade. target link libraries device-specific. Therefore, might want specify target link libraries your generic startup file.
symbol_library xc3000.sdb
This line specifies symbol libraries.
define_design_lib WORK -path ./WORK
This line creates directory store intermediate files created Analyze command users.
compile_fix_multiple_port_nets true
This line allows Synopsys optimization algorithm insert extra logic into design ensure that there feedthroughs that output ports connected same net.
bus_naming_style "%s<%d>" bus_dimension_separator_style "><" bus_inference_style "%s<%d>"
These lines READ parameters Xilinx netlist formats. indexing form ``bus<index>.''
edifout_netlist_only true cell edifout_write_properties_list "instance_number port_location part"
These lines EDIF parameters Xilinx devices.
Modifying Search Path
Modify search path line default .synopsys_dc.setup file include path Synopsys installation directories follows. determine Synopsys installation path, enter following command line. echo $SYNOPSYS
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XACT Development System
Getting Started
Open setup file text editor replace DS401-Directory with full path directory where software installed (the $XACT environment variable contains this path). Replace SYNOPSYS-Directory with path where your Synopsys software installed (usually stored environment variable $SYNOPSYS).
Using Synlibs XC3000 Devices
Synlibs displays link target libraries specified part type speed grade. Synlibs from directory follows. synlibs parttype-speedgrade example, list target link libraries XC3020A-6 device, enter following. synlibs 3020a-6 system displays output onscreen illustrated Figure 2-6.
link_library {xprim_3020a-6.db xprim_3000a-6 xgen_3000.db xdc_3000a-6.db} target_library {xprim_3020a-6.db xprim_3000a-6 xgen_3000.db xdc_3000a-6.db}
Figure Synlibs Output with Design Compiler (XC3000) Note: target link libraries default setup file plan perform Design Compiler tutorial XC3000A devices. must copy output from Synlibs into your Synopsys startup file. UNIX Append (>>) command redirect output Synlibs your .synopsys_dc.setup file follows. synlibs parttype-speedgrade .synopsys_dc.setup After redirect output, text editor delete default target link libraries. Warning: must list libraries your setup file order that they appear Synlibs output.
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Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291 Printed U.S.A.
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XACT Development System
Chapter
FPGA Compiler Tutorial XC4000 Designs
provides interface between Synopsys synthesis tools Xilinx XACT Development System. This interface enables description create your design XACT tools map, place, route design. This tutorial provides step-by-step information FPGA Compiler XC4000 designs takes approximately hour complete. FPGA Compiler understands XC4000 architecture maps XC4000 CLBs. Note: XC3000/A/L XC3100/A designs, FPGA Compiler Design Compiler results same. Refer "Design Compiler Tutorial XC3000A Designs" chapter.
Before Begin
Before starting this tutorial, make sure that Xilinx Synopsys Interface (DS-401), XACT Development System (DS-502), X-BLOX (DS-380), Synopsys FPGA Compiler installed. Note: X-BLOX must installed plan DesignWare library. verify correct installation these tools, refer "Getting Started" section beginning this user guide, which describes modify default Synopsys startup file include appropriate libraries search path.
Required Files
access files need perform this tutorial, follow these steps. Replace DS401-Directory with directory where software installed.
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291
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files need following directories. VHDL users Verilog users /x4000/vhd /x4000/verilog
this tutorial, design called count8, which modulo (8-bit) counter. directory contains VHDL version, count8.vhd, verilog directory contains Verilog version, count8.v. Change your working directory. Create directory called count8 change that directory. mkdir count8 count8 Copy files from either VHDL Verilog tutorial directory into count8 directory. VHDL count8 design, enter following command line. /vhd Verilog count8 design, enter following command line. /verilog Note: backslash continuation character; enter command line. know location DS401-Directory, type following, which displays paths XACT environment variable. path appears first. echo $XACT
Exiting Tutorial
exit stop tutorial time. best results, complete steps section before quitting. must exit Design
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FPGA Compiler Tutorial XC4000 Designs
Analyzer before completing tutorial, must re-run tutorial from beginning.
Design Flow
This section illustrates Xilinx implementation flow count8 tutorial design. Generally, design process starts with description desired circuit functions ends with file, binary file that contains configuration data your design, file, which back-annotation simulation. Figure illustrates Xilinx XC4000 implementation flow synthesis. checklist proceed with your XC4000 design.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
XMake count8 count8.sxnf syn2xnf.log Syn2XNF count8.xff xnfprep.log XNFPrep count8.xtg xblox.log X-BLOX count8.xg xnfprep.log XNFPrep count8.xtf ppr.log count8.lca XDelay count8.lca MakeBits
X4825
count8.xnf Functional Simulation X-BLOX Modules
Functional Simulation With X-BLOX Modules
Timing Simulation
count8.bit
count8.lca
Figure Xilinx XC4000 Implementation Flow Synthesis Note: design flow, which precedes running XMake, beginning "Using FPGA Compiler" chapter.
Count8 Design Description
This section contains description count8 design used this tutorial. Figure shows VHDL code Figure shows Verilog code.
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count8 design counts 255, then starts again zero. count only when Enable High Clear Low. Clear High, counter resets synchronously. Enable Low, counter disabled. output signal COUT.
Figure VHDL Code Count8
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Xilinx Synopsys Interface FPGA User Guide
Figure Verilog Code Count8
Invoking Design Analyzer
this section learn invoke Design Analyzer verify that Synopsys startup file (.synopsys_dc.setup) been properly installed modified described release notes "Getting Started" chapter this user guide. Perform following steps. From count8 directory, Synopsys Design Analyzer background entering following command. design_analyzer .synopsys_dc.setup file generates errors warnings, system displays them onscreen. receive error warning messages, refer "Getting Started" chapter. Note: command.log file your working directory lists variable settings Design Analyzer. verify that Synopsys
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FPGA Compiler Tutorial XC4000 Designs
read correct .synopsys_dc.setup file, view command.log file. Verify that your Synopsys options were correctly. Setup Defaults. system displays following dialog box.
Figure Defaults Dialog Verify that your settings match following. search_path /syn SYNOPSYS-Directory/libraries /syn xprim_4005-5.db xprim_4000-5.db xgen_4000.db xio_4000-5.db xfpga_4000-5.db xprim_4005-5.db xprim_4000-5.db xgen_4000.db xio_4000-5.db xfpga_4000-5.db xc4000.sdb
link_library
target_library
symbol_library
fields dialog long enough show default information. view hidden information, position your
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
cursor specific field left arrow enlarge width Defaults window. Note: DS401-Directory directory where Xilinx Synopsys Interface software installed, SYNOPSYS-Directory where Synopsys FPGA Compiler installed. Select Cancel close window.
Reading Design File
this section learn Design Analyzer analyze create design file.
Analyzing Design File
Analyze command checks syntax logic, converts file intermediate format during simulation. analyze design file, perform following steps. Select File Analyze. from Design Analyzer menu. system displays Analyze File dialog shown Figure 3-5.
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Figure Analyze File Dialog left mouse button click once count8.vhd VHDL users, count8.v Verilog users. system displays count8.vhd count8.v File Name(s) field. Click Analyze window displays informational, error, warning messages. system also displays processing messages Command Window. display Command window, select Setup Command Window from Design Analyzer menu.) Figure illustrates Analyze window output.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Figure Analyze Window Click Cancel close Analyze window.
Creating Design File
create design file, perform following steps. Elaborate command. File Elaborate. Elaborate Design dialog appears follows.
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Figure Elaborate Design Dialog Scroll library list click WORK. Click once count8(BEHAVIORAL). system displays count8(BEHAVIORAL) Design field. Click system displays informational messages Elaborate window illustrated Figure 3-8.
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Figure Elaborate Window Click Cancel close Elaborate window. symbol that represents count8 design appears Design Analyzer main screen follows.
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Figure Top-Level Symbol Count8 Design
Inserting Buffers
this section define ports top-level design inputs, outputs, clock ports, bidirectional ports. Also, Insert Pads commands necessary buffers top-level design. Defining port causes Insert Pads command attach buffer that port, which Xilinx tools then recognize. Note: Count8 one-level design. FPGA Compiler optimize registers 3-state functions into IOBs. Refer "Using FPGA Compiler" chapter this user guide more information. following procedures describe define input ports, CLEAR ENABLE; input clock, CLOCK; output bus, COUT <7:0>. actual buffers added design until pads inserted.
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Note: procedures this section only apply inserting IBUFs, ILDs, IFDs, OBUFs, IOBUFs, OFDS, OFDTs. other configurations, must instantiate buffers into design. "XC3000/A/L XC3100/A Primitives" "XC4000/A/D/H Primitives Hard Macros" appendixes information other available buffers.
Defining Input Ports Pads
define input ports pads, perform following steps. Click left mouse button count8 icon illustrated Figure 3-9. system changes solid line dotted line indicate that icon selected. Click down arrow icon display design Symbol View. system displays count8 design Symbol View illustrated Figure 3-10.
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Figure 3-10 Symbol View Select CLEAR, CLOCK, ENABLE input ports clicking with left mouse button, other with middle mouse button. middle mouse button extends selection. dotted rectangle indicates that ports selected. Note: deselect input port, click again with middle mouse button. Select Attributes Optimization Directives Input Port. from Design Analyzer menu. Input Port Attributes dialog appears shown Figure 3-11.
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Figure 3-11 Input Port Attributes Dialog Click next Port Pad. Select Apply. system sets attributes CLEAR, CLOCK, ENABLE ports. Click Cancel close dialog box.
Defining Output Port
define output port pad, perform following steps. Select COUT [7:0] clicking with left mouse button. dotted rectangle indicates that output port selected. Select Attributes Optimization Directives Output Port. from Design Analyzer menu. Output Port Attributes window appears first, then Selector dialog appears over illustrated Figure 3-12.
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Figure 3-12 Selector Output Port Attributes Dialog Boxes Selector window, select Cancel. Selector dialog disappears. Output Port Attributes dialog box, click labeled Port Pad. Select Apply. Select Cancel close dialog box. Note: also define inputs, outputs, clock buffers using Port command Synopsys DC-shell prompt Design Analyzer command window follows. This command sets ports pads simple step. set_port_is_pad
Using Insert Pads Command
After ports defined pads, insert buffers using following procedure. Command window open, select Setup Command Window. from Design Analyzer menu. Command window appears. Design analyzer prompt Command window, type insert_pads.
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Command window displays informational messages. want move Command window place your desktop where does obscure Design Analyzer main window. Figure 3-13 illustrates Command window output after running Insert Pads command.
Figure 3-13 Command Window Output Insert Pads Command
Estimating Pre-Layout Timing
libraries contain operating conditions wire-load models that used provide pre-layout timing estimate your design.
Selecting Operating Condition
offers operating condition parameters called worst-case commercial (WCCOM). operating conditions selected automatically used Synlibs generate link target libraries. more information Synlibs command, refer "Getting Started" chapter beginning this user guide.
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Setting Wire-Load Models
libraries offer worst-case average wire-load models. Wire loads estimated delays design that been partitioned into CLBs IOBs. Refer "Using FPGA Compiler" chapter this user guide more information. Synopsys uses these estimates guidelines optimize your design FPGA. actual wire loads cannot determined until after design been placed routed. models device speed-grade dependent, with average wire-load model (parttype-speedgrade_avg) worst-case wireload model (parttype-speedgrade_wc) each. average wire-load model mean test suite worst-case average plus standard deviation. Therefore, worst-case model more conservative. average wire-load model selected automatically used Synlibs generate link target libraries.
Optimizing Speed
Before compiling design, area speed constraints improve results. this section timing constraint. most effective results from FPGA Compiler, constraints must accurate achievable. example, timing goal ports, FPGA Compiler adds buffers critical paths duplicates logic heavily loaded nets, attempting achieve this goal. unrealistic goal might cause significant unwarranted area increases. Refer Synopsys Design Compiler Reference Manual details optimization techniques. Path timing includes both logic delays. gate, CLB, timing delays worst-case commercial estimates specified nanoseconds. wire-load delays either average estimates worst-case estimates. Actual delays determined only after PPR. Additional timing information about primitives included "XC4000/A/D/H Primitives Hard Macros" appendix this user guide Programmable Logic Data Book.
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clock constraint, follow these steps. Select CLOCK placing cursor CLOCK port pressing left mouse button. Select following menu options from Attributes menu. Attributes Clocks Specify. system displays Specify Clock dialog follows. default clock period
Figure 3-14 Specify Clock Dialog Select Apply Cancel. waveform appears above CLOCK indicate setting timing constraint.
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Compiling Design
this section learn compile design with recommended options. optimization process part Compile command. Optimization complex series transformations guided constraints that specify. optimization steps technology mapping, which transforms Boolean logic network representation your design into interconnected gates that selected from target technology library. mapping Low, Medium, High. Refer Synopsys Design Compiler Reference Manual more details about mapping other optimization techniques. compile count8 design, following. Select Tools FPGA Compiler. from Design Analyzer menu. FPGA Compiler dialog appears follows.
Figure 3-15 FPGA Compiler Dialog Click Optimization. Design Optimization dialog appears follows.
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Figure 3-16 Design Optimization Dialog Make sure Design shaded Effort Medium. Click system displays informational messages compilation errors Compile window Command window. Once design compiled, click Cancel close Compile window. Select Cancel close FPGA Compiler window.
Evaluating Results
design optimized XC4000 architecture mapped into CLBs IOBs. libraries contain both area timing information. this section view area report estimated utilization timing report estimated delays. also learn redirect report output from screen file. View schematic design selecting gate picture icon left side Synopsys Design Analyzer window.
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system displays schematic view count8 design.
Figure 3-17 Schematic View When finish viewing schematic, click arrow icon switch Designs View illustrated Figure 3-18.
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Figure 3-18 Designs View
Viewing Estimated Area Results
evaluate estimated area results, perform following steps. Click count8 icon. Select Tools FPGA Compiler. from Design Analyzer menu. FPGA Compiler window appears. Select Report. Report dialog appears follows.
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Figure 3-19 Report Dialog Analysis Reports section, select boxes next FPGA Resources Timing. Select Apply. Report Output window appears. scroll Report Output window view design statistics. Select Cancel close Report Output window. Note: close Report dialog box. Figure 3-20 illustrates example report file. This report shows area utilization (CLBs used) count8 design.
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Figure 3-20 Area Utilization Report Note: Clock pads IOBs, they listed separately this report.
Viewing Estimated Timing Results
evaluate timing results, perform following steps. Analysis Reports section Report dialog box, click left Timing with left mouse button. Deselect FPGA Resources box. Select Apply. Report Output window opens. results reported worstcase timing delay estimates. final results cannot determined until after PPR.
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When finished reviewing Report Output window, select Cancel. Note: close Report dialog box.
Saving Area Timing Results File
save estimated area timing results report file, perform following steps. Locate Send Output field bottom Report dialog box. Select File. Place your cursor File field. Double-click highlight default report file name. Type count8.timing Select Apply Cancel. Note: close FPGA Compiler window. Xilinx libraries worst-case delays. Synopsys timing delay estimates include wire-load delays addition gate delays. most cases, actual results better than pre-placement routing Synopsys estimates. Figure 3-21 complete timing report count8 design, which called count8.timing.
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Figure 3-21 Timing Report (count8.timing)
Saving Design
this section learn save your design (Synopsys Database file) file, replace CLBs IOBs with gates, design part type speed grade, save design into SXNF file.
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Writing File
save design file, following. Select count8 icon with left mouse button. Select File Save from Design Analyzer menu. system saves file count8.db.
Replacing CLBs IOBs with Gates
After design compiled, contains elements. create SXNF file, FPGA Compiler must convert these CLBs IOBs gates. Perform following steps. FPGA Compiler window, select FPGA Cells Gates. system displays FPGA window. Note: mapping logic into CLBs written SXNF file retained PPR. Refer "Using FPGA Compiler" chapter this user guide information about remove mapping information. Select Cancel close FPGA window. Select Cancel close FPGA Compiler window.
Setting Design Part Type
select particular part count8 design, type following command Design Analyzer prompt Command window. Note: (backslash) line continuation marker. type command line. set_attribute count8 "part" -type string "4005pc84-5"
Removing BLKNM Attributes
allow XACT software more freedom during placement routing, Xilinx recommends writing block names SXNF
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file. prohibit writing block names, enter following command Design Analyzer prompt Command window. set_attribute find(design,"*") "xnfout_use_blknames" -type boolean false
Saving Design File SXNF File
next step save design file SXNF file follows. Select following menu options. File Save Save File dialog appears illustrated Figure 3-22.
Figure 3-22 Save File Dialog Click field next File Name. Change extension .sxnf. Place your cursor right count8.db, backspace delete then replace with sxnf. Click next File Format. system displays list formats.
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Select XNF. Make sure Save Designs Hierarchy shaded. Select
Exiting Design Analyzer
done with Synopsys FPGA Compiler ready XACT Development System. exit Design Analyzer, following. Select File Quit from Design Analyzer main menu. Quit Design Analyzer? window appears. Click exit. following section reference section that describes running script that invokes Synopsys tools. continue with tutorial, skip "Placing Routing Your Design Using XMake" section.
Executing Commands from Script File
Warning: execute commands this section. this section reference execute script file. have already executed these commands through Design Analyzer menus. script file compile your design instead using pulldown menus. commands illustrated this tutorial listed script file, count8.script. execute this script either from Design Analyzer DCShell. Each command annotated script file. Comments start with Each command corresponds command already executed this tutorial. procedures execute count8.script file from Design Analyzer following. Invoke Synopsys Design Analyzer background. design_analyzer
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Open Command window view script executes. Setup Command Window. Execute count8.script file. Setup Execute Script. Execute File dialog appears shown Figure 3-23.
Figure 3-23 Execute File Dialog Select count8.script. system displays count8.script File Name field. Select Exit Design Analyzer. Figure 3-24 Figure 3-25 illustrate actual text count8.script file VHDL Verilog HDL, respectively.
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Figure 3-24 VHDL Script File Count8
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Figure 3-25 Verilog Script File Count8
Placing Routing Your Design Using XMake
XMake automates translation portion Xilinx design flow, which makes processing complex design simple running program. Given name top-level SXNF file, XMake finds processes lower-level drawings. produces file that placed routed, well file ready downloading FPGA. invoke XMake from within XACT Design Manager (XDM) from shell tool window.
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this section translate count8 design using XMake from shell tool window. Refer XACT Reference Guide details about each program that XMake runs about running XMake from XDM. procedure translating count8 design slightly different installed different platform network than that XACT Development System. Follow procedures that apply your specific configuration.
Same Network XACT Software
Follow procedures this section software installed same network platform XACT Development System software. find command-line options that XMake used XMake output file, count8.out. XMake from shell tool window, type following. xmake count8.sxnf Refer Figure flow diagram that illustrates Xilinx implementation flow synthesis.
Different Network Than XACT Software
Follow procedures this section software installed different network platform than XACT Development System software. installed machine that does have access both XACT Development System executable files, must Syn2XNF first then copy output files platform where XACT executable files reside. Refer Figure flow diagram that illustrates Xilinx implementation flow synthesis. following sections describe Syn2XNF XMake programs.
Running Syn2XNF
Because software installed different platform than XACT software, must first Syn2XNF translate your design into file, follows.
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Change directory where count8.sxnf file located execute following command. syn2xnf count8.sxnf SYN2XNF software might display following message, which prompts overwrite existing file that same design name. WARNING: file count8.xff already exists. want overwrite (yes system displays previous message, enter Syn2XNF creates following output files: count8.xff, count8.xnf syn2xnf.log. Copy count8.xff count8.xnf files platform network where XACT software installed. Note: option with Copy command preserve files' time stamp.
Running XMake
Perform following steps translate count8 design using XMake. platform where XACT Software installed. Open shell tool window. Enter following command line. xmake count8 option causes XMake start with file skip translation process. XMake program processes necessary design files, displaying progress screen. translation successful, XMake issues this message. `count8.bit' been made, check output `count8.out' sure examine count8.out, count8.prp, count8.rpt files warnings errors, described "Examining XMake Output Files" section this manual.
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Examining XMake Output Files
addition routed file bitstream file, XMake generates three very useful output files. this section open each file familiarize yourself with contents.
file, count8.out, contains output from programs that XMake invokes. This information also displayed onscreen during processing. file, count8.prp, (Design Rules Checker) report file generated XNFPrep. file, count8.rpt, contains placement routing results. This report also contains listing unrouted pins nets.
Reviewing XMake File
When XMake, output XMake program appears screen. file shows every program XMake, command options selected, output each individual program. warnings errors produced programs XMake appear file. should always review file after running XMake, even warnings error messages during design processing. warnings errors occur, save yourself some time catching problem instead later design process. Examine count8.out file count8 design follows. Open shell tool window. Change project directory. text editor view count8.out.
Checking Warnings Errors File
XNFPrep finds errors warnings, file directs examine file. file also contains detailed list logic trimmed XNFPrep unnecessary. This file useful debugging tool.
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should expect some warning messages count8.prp files errors. Examine count8.prp file count8 design. following headers correspond table contents found count8.prp.
XNFPrep Errors lists errors found design. Errors problems with design that cause XMake terminate. must reported errors. XNFPrep Warnings lists warnings found design. Warnings notify unusual aspects your design. should correct warnings; however, mandatory. Clock Signals Report contains summary clock signals and/or global buffers assist determining best global buffers. This section also contains list guidelines consider when assigning signals global buffer. Timing Specification Summary contains list XACTPerformance timing specifications used design. Logic Trimming shows logic removed from your design sourceless loadless signals ground connection. should review this section verify that logic required your design been removed design error.
Checking File
After XMake runs PPR, generates report file with .rpt extension, which contains important information following categories.
Partition, Place, Route Summary includes number occupied CLBs that approximately corresponds total area provided Synopsys Report. Chip Pinout Description contains list pins used design locations specified constraints file. Critical Nets indicates nets that were assigned constraint. Feedthrough Split Nets indicates nets with names that were modified could re-powered. Re-powering
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signal regeneration accomplished using special function CLB.
Deletion Traceback enables check nets cells that were removed that should remain. Synopsys Check Design tool detects unconnected pins unused cells.
Examine count8.rpt file make sure there unrouted pins nets. text editor view this file. Figure 3-26 illustrates each page file.
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Figure 3-26 File
Comparing Actual Versus Estimated Area Results
file contains partition, place, route summary that includes number occupied CLBs that approximately corresponds total area number provided Synopsys Report. this section compare accurate FPGA Compiler preplace route estimates were actual results. Figure 3-20 shows estimated area results from FPGA Compiler, Figure 3-26 shows actual area results from PPR. following table summarizes area utilization results.
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Table Area Utilization Summary Partitioned Design Utilization Using Part 4005PC84-5 Actual Used Estimated Used
Occupied CLBs Packed CLBs Bonded Pins Function Generators Function Generators Flip-flops Clock Pads
reported number CLBs other cells
actual area utilization accurate because FPGA Compiler mapped design passed this information PPR. Note: Your actual area numbers vary from area utilization reported FPGA Compiler since adds additional CLBs feedthrough split nets. Refer page file, illustrated Figure 3-26, more information split nets count8 design.
Using XDelay
XDelay command allows obtain detailed post-placement post-routing timing information about your design. XDelay results summarize worst paths design, necessarily paths that concern you. XDelay also interactive mode, which enables extract information about specific paths design, example, generate timing report subset design. choose specific paths selecting individual starting ending points indicating specific path type. more information about XDelay options, refer XACT Reference Guide. this section XDelay report worst-case paths maximum clock frequency design. also compare output XDelay estimated timing reported FPGA Compiler.
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Invoking XDelay
Enter following command command line XDelay, which creates short report, count8.dly. xdelay count8 XDelay produces following output shown Figure 3-27.
Figure 3-27 XDelay Short Report
Comparing Actual Versus Estimated Timing Results
often better timing estimates looking number block levels that critical longest path must traverse rather than using estimated delays listed count8.timing report, illustrated Figure 3-21. Block levels number CLBs IOBs. longest path reported FPGA Compiler clock-to-clock delay from
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register through incrementer. This delay reported 26.27 count8.timing report included clock-to-output delay, delay though X-BLOX incrementer, clock-to-setup delay, average wire load, flip-flop setup time. XDelay report, illustrated Figure 3-27, reports longest clock-to-setup delay 24.9 with four block levels. wire-load models mapping X-BLOX modules account difference delay from that timing report. Note: FPGA Compiler does provide estimated block levels X-BLOX components, X-BLOX timing assumes modules single column CLBs.
Verifying Your Design Using XChecker
This section describes function XChecker Download/ Readback cable. actually download count8 design this tutorial. verify that your design works your system, XChecker Download/Readback cable associated software. With XChecker, load configuration bitstream generated MakeBits program. MakeBits file defines internal logic functions interconnections target FPGA. more information XChecker cable MakeBits program, refer XACT Hardware Peripherals Guide XACT Reference Guide, Volume respectively. store file your system memory PROM. Refer section XACT Hardware Peripherals Guide more information about storing files PROMs.
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Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291 Printed U.S.A.
Xilinx Synopsys Interface FPGA User Guide
XACT Development System
Chapter
Design Compiler Tutorial XC3000A Designs
provides interface between Synopsys synthesis tools Xilinx XACT Development System. This interface enables description create your design XACT tools map, place, route design. This tutorial provides step-by-step information Design Compiler XC3000A designs takes approximately hour complete. Note: also perform this tutorial with XC4000 designs, need specify different libraries your .synopsys_dc.setup file. Refer "Using Design Compiler XC4000 Designs" "Getting Started" chapter more information, including access X-BLOX DesignWare library.
Before Begin
Before starting this tutorial, make sure that Xilinx Synopsys Interface (DS-401), XACT Development System (DS-502), Synopsys Design Compiler installed. verify correct installation these tools, refer "Getting Started" section beginning this user guide, which describes modify default Synopsys start-up file include appropriate libraries search path.
Required Files
access files need perform this tutorial, follow these steps. Replace DS401-Directory with directory where software installed.
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291
Xilinx Synopsys Interface FPGA User Guide
files need following directories. VHDL users Verilog users /x3000a/vhd /x3000a/verilog
this tutorial, design called count8, which modulo (8-bit) counter. directory contains VHDL version, count8.vhd, verilog directory contains Verilog version, count8.v. Change your working directory. Create directory called count8 change that directory. mkdir count8 count8 Copy files from either VHDL Verilog tutorial directory into count8 directory. VHDL count8 design, enter following command line. /vhd Verilog count8 design, enter following command line. /verilog Note: backslash continuation character; enter command line. know location DS401-Directory, type following, which displays paths XACT environment variable. path appears first. echo $XACT
Exiting Tutorial
exit stop tutorial time. best results, complete steps section before quitting. must exit Design
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Design Compiler Tutorial XC3000A Designs
Analyzer before completing tutorial, must re-run tutorial from beginning.
Design Flow
This section illustrates Xilinx implementation flow count8 tutorial design. Generally, design process starts with description desired circuit functions ends with file, binary file that contains configuration data your design, file, which back-annotation simulation. Figure illustrates Xilinx XC3000A implementation flow synthesis. checklist proceed with your XC3000A design.
XMake count8 count8.sedif syn2xnf.log Syn2XNF count8.xff xnfprep.log XNFPrep count8.xtf ppr.log count8.lca XDelay count8.lca MakeBits
X4897
count8.xnf Functional Simulation
Timing Simulation
count8.bit
count8.lca
Figure XC3000A Implementation Flow Synthesis Note: design flow, which precedes running XMake, beginning "Using Design Compiler" chapter.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Count8 Design Description
This section describes count8 design used this tutorial. Figure shows VHDL code Figure shows Verilog code count8. count8 design counts 255, then starts again zero. count only when Enable High Clear Low. Clear High, counter resets synchronously. Enable Low, counter disabled. output signal COUT.
Figure VHDL Code Count8
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Figure Verilog Code Count8
Invoking Design Analyzer
this section learn following.
invoke Design Analyzer. verify that Synopsys start-up file (.synopsys_dc.setup) been properly installed modified described release notes "Getting Started" chapter beginning this user guide.
Perform following steps. From count8 directory, Synopsys Design Analyzer background entering following command. design_analyzer .synopsys_dc.setup file generates errors warnings, system displays them onscreen. receive error warning messages, refer "Getting Started" chapter.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Note: command.log file your working directory lists variable settings Design Analyzer, which view verify that Synopsys tools read correct .synopsys_dc.setup file. Verify that your Synopsys options were correctly. Setup Defaults. system displays following dialog box.
Figure Defaults Dialog Verify that your settings match following. search_path /syn SYNOPSYS-Directory/libraries /syn xprim_3020a-6.db xprim_3000a-6.db xgen_3000.db xdc_3000a-6.db xprim_3020a-6.db xprim_3000a-6.db xgen_3000.db xdc_3000a-6.db xc3000.sdb
link_library target_library symbol_library
fields dialog long enough show default information. view hidden information, position your
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Design Compiler Tutorial XC3000A Designs
cursor specific field left arrow enlarge width Defaults window. Note: DS401-Directory directory where Xilinx Synopsys Interface software installed, SYNOPSYS-Directory where Synopsys Design Compiler installed. Select Cancel close window.
Reading Design File
this section learn Design Analyzer analyze create design file.
Analyzing Design File
Analyze command checks syntax logic, converts file intermediate format during simulation. analyze design file, perform following steps. Select File Analyze. from Design Analyzer menu. system displays Analyze File dialog shown Figure 4-5.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Figure Analyze File Dialog left mouse button click once count8.vhd VHDL users, count8.v Verilog users. system displays count8.vhd count8.v File Name(s) field. Click Analyze window displays informational, error, warning messages. system also displays processing messages Command window. display Command window, select Setup Command Window from Design Analyzer menu.)
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Figure illustrates Analyze window output.
Figure Analyze Window Click Cancel close Analyze window.
Creating Design File
create design file, perform following steps. Elaborate command. File Elaborate. Elaborate Design dialog appears follows.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Figure Elaborate Design Dialog Scroll library list click WORK. Click count8(BEHAVIORAL). system displays count8(BEHAVIORAL) Design field. Click system displays informational messages Elaborate window illustrated Figure 4-8.
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Figure Elaborate Window Click Cancel close Elaborate window. symbol that represents count8 design appears Design Analyzer main screen follows.
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Figure Top-Level Symbol Count8 Design
Inserting Buffers
this section define ports top-level design inputs, outputs, clock ports, bidirectional ports. Also, Insert Pads commands necessary buffers top-level design. Defining port causes Insert Pads command attach buffer that port, which Xilinx tools then recognize. Note: Count8 one-level design. Design Compiler optimize registers 3-state functions into IOBs. Refer "Using Design Compiler" chapter this user guide more information. following procedures describe define input ports, CLEAR ENABLE; input clock, CLOCK; output bus, COUT <7:0>. actual buffers added design until pads inserted.
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Note: procedures this section only apply inserting IBUFs, OBUFs, IOBUFs, IFDs, OFDs, ILDs. other configurations, must instantiate buffers into design. "XC3000/A/L XC3100/A Primitives" appendix information other available buffers.
Defining Input Ports Pads
define input ports pads, perform following steps. Click left mouse button count8 icon illustrated Figure 4-9. system changes solid line dotted line indicate icon selected. Click down arrow icon display design Symbol View. system displays count8 design Symbol View illustrated Figure 4-10.
Figure 4-10 Symbol View
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Select CLEAR, CLOCK, ENABLE input ports clicking with left mouse button, other with middle mouse button. middle mouse button extends selection. dotted rectangle indicates that ports selected. Note: deselect input port, click again with middle mouse button. Select Attributes Optimization Directives Input Port. from Design Analyzer menu. Input Port Attributes dialog appears shown Figure 4-11.
Figure 4-11 Input Port Attributes Dialog Click next Port Pad. Select Apply. system sets attributes CLEAR, CLOCK, ENABLE ports. Click Cancel close dialog box.
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Defining Output Port
define output port pad, perform following steps. Select COUT [7:0] clicking with left mouse button. dotted rectangle indicates that output port selected. Select Attributes Optimization Directives Output Port. from Design Analyzer menu. Output Port Attributes window appears first, then Selector dialog appears over illustrated Figure 4-12.
Figure 4-12 Selector Output Port Attributes Dialog Boxes Selector window, select Cancel. Selector dialog disappears. Output Port Attributes dialog box, click labeled Port Pad. Select Apply Cancel. Note: also define inputs, outputs, clock buffers using Port command Synopsys DC-shell prompt Design Analyzer command window follows. This command sets ports pads simple step. set_port_is_pad
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Using Insert Pads Command
After ports defined pads, insert buffers using following procedure. Command window open, select Setup Command Window. from Design Analyzer menu. Command window appears. Design Analyzer prompt Command window, type insert_pads. Command window displays informational messages. want move Command window place your desktop where does obscure Design Analyzer main window. Figure 4-13 illustrates Command window output after running Insert Pads command.
Figure 4-13 Command Window Output Insert Pads Command
Estimating Pre-Layout Timing
libraries contain operating conditions wire-load models that used provide pre-layout timing estimate your design.
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Selecting Operating Condition
offers operating condition parameters called worst-case commercial (WCCOM). operating conditions selected automatically used Synlibs generate link target libraries. more information Synlibs command, refer "Getting Started" chapter beginning this user guide.
Setting Wire-Load Models
libraries offer worst-case average wire-load models. Wire loads estimated delays design that been partitioned into CLBs IOBs. Refer "Using Design Compiler" chapter this user guide more information. Synopsys uses these estimates guidelines optimize your design FPGA. actual wire loads cannot determined until after design been placed routed. models device speed-grade dependent, with average wire-load model (parttype-speedgrade_avg) worst-case wire-load model (parttype-speedgrade_wc) each. average wire-load model mean test suite worst-case average plus standard deviation. Therefore, worst-case model more conservative. average wire-load model selected automatically used Synlibs generate link target libraries.
Optimizing Speed
Before compiling design, area speed constraints improve results. this section timing constraint. most effective results from Design Compiler, constraints must accurate achievable. example, timing goal ports, Design Compiler adds buffers critical paths duplicates logic heavily loaded nets, attempting achieve this goal. unrealistic goal might cause significant unwarranted area increases. Refer Synopsys Design Compiler Reference Manual details optimization techniques. Path timing includes both logic delays. gate timing delays worst-case commercial estimates specified
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nanoseconds. wire-load delays either average estimates worst-case estimates. Actual delays determined only after PPR. Additional timing information about primitives included "XC3000/A/L XC3100/A Primitives" appendix this user guide Programmable Logic Data Book. clock constraint, follow these steps. Select CLOCK placing cursor CLOCK port pressing left mouse button. Select following menu options from Attributes menu. Attributes Clocks Specify. system displays Specify Clock dialog follows. default clock period
Figure 4-14 Specify Clock Dialog
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Select Apply. waveform appears above CLOCK indicate setting timing constraint. Select Cancel close dialog box.
Compiling Design
this section learn compile design with recommended options. optimization process part Compile command. Optimization complex series transformations guided constraints that specify. optimization steps technology mapping, which transforms Boolean logic network representation your design into interconnected gates that selected from target technology library. mapping Low, Medium, High. Refer Synopsys Design Compiler Reference Manual more details about mapping other optimization techniques. compile count8 design, following. Select Tools Design Optimization. from Design Analyzer menu.
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Design Optimization dialog appears follows.
Figure 4-15 Design Optimization Dialog Make sure Design shaded Effort Medium. Click system displays informational messages compilation errors Compile window Command window. Scroll through Compile window view compilation messages. Once design compiled, click Cancel close Compile window.
Evaluating Results
design optimized XC3000A architecture mapped into primitive gates registers. libraries contain both area timing information. this section view area report estimated utilization timing report estimated delays. also learn redirect report output from screen file.
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View schematic design selecting gate picture icon left side Synopsys Design Analyzer window. system displays schematic view count8 design.
Figure 4-16 Schematic View
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When finish viewing schematic, click arrow icon switch Designs View illustrated Figure 4-17.
Figure 4-17 Designs View
Viewing Estimated Area Results
evaluate estimated area results, perform following steps. Click count8 icon. Select following commands from Design Analyzer menu. Analysis Report. Report dialog appears follows.
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Figure 4-18 Report Dialog Analysis Reports section, select next Area. Select Apply. Report Output window appears illustrated Figure 4-19.
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Figure 4-19 Report Output Window (Area) scroll Report Output window view design statistics. Select Cancel close Report Output window. Note: close Report dialog box. Synopsys reports area three parts combinatorial area, noncombinatorial area, total area. area reported terms number Xilinx CLBs used. Each contains 4-input function generators flip-flops. flip-flops 4-input Boolean functions weighted area CLB. 5-input primitives weighted area CLB. your design register-intensive, number CLBs required roughly equal non-combinatorial area reported. design heavily combinatorial, number CLBs required roughly equal
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combinatorial area reported. However, CLBs actually used usually less than what Synopsys reports. rule thumb with Xilinx mapped libraries (Syn2XNF -map option) minimum CLBs required larger combinatorial non-combinatorial areas reported. maximum number CLBs required total number reported both. number CLBs actually required usually less than total area, because function generators flip-flops often share same CLB. rule thumb with Xilinx unmapped libraries (Syn2XNF without options) similar. main difference that minimum number CLBs required could less than combinatorial area reported, depending performs local optimization. Only accurately compute actual number required CLBs.
Viewing Estimated Timing Results
evaluate timing results, perform following steps. Analysis Reports section Report dialog box, click left Timing with left mouse button. Deselect Area box. Select Apply. Report Output window opens. results reported worst-case timing delay estimates. final results cannot determined until after PPR. When finished reviewing Report Output window, select Cancel. Note: close Report dialog box.
Saving Report Results File
save estimated timing results report file, perform following steps. Make sure only Timing selected Analysis Reports section Report dialog box.
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Locate Send Output field bottom Report dialog select File. Place your cursor File field. Double-click highlight default report file name. Type count8.timing Select Apply Cancel. Worst-case delays used Xilinx libraries, which assume that function generators flip-flops same CLB. Synopsys timing delay estimates include wire-load delays addition gate delays. most cases, actual results better than pre-placement routing Synopsys estimates. Figure 4-20 complete timing report count8 design, count8.timing.
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Figure 4-20 Timing Report (count8.timing)
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Saving Design
this section learn save your design (Synopsys Database file) file, design part type speed grade, save design into SEDIF file.
Writing File
save design file, following. Select count8 icon with left mouse button. Select File Save from Design Analyzer menu. system saves file count8.db.
Setting Design Part Type
select particular part count8 design, type following command Design Analyzer prompt Command window. Note: (backslash) line continuation marker. type command line. set_attribute count8 "part" -type string "3020apc84-6"
Saving Design File SEDIF File
Next, save design file SEDIF file follows. Select following menu options. File Save Save File dialog appears follows.
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Figure 4-21 Save File Dialog Click field next File Name. Change extension .sedif. Place your cursor right count8.db, backspace delete then type sedif. Click next File Format. system displays list formats. Select EDIF. Make sure Save Designs Hierarchy shaded. Select
Exiting Design Analyzer
done with Synopsys Design Compiler ready XACT Development System. exit Design Analyzer, following. Select File Quit from Design Analyzer main menu. Quit Design Analyzer? dialog appears.
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Click exit. following section reference section that describes running script that invokes Synopsys tools. continue with tutorial, skip "Placing Routing Your Design Using XMake" section.
Executing Commands from Script File
Warning: execute commands this section. this section reference execute script file. have already executed these commands through Design Analyzer menus. script file compile your design instead using pulldown menus. commands illustrated this tutorial listed script file, count8.script. execute this script either from Design Analyzer Shell. Each command annotated script file. Comments start with Each command corresponds command already executed this tutorial. procedures execute count8.script file from Design Analyzer following. Invoke Synopsys Design Analyzer background. design_analyzer Open Command window view script executes. Setup Command Window. Execute count8.script file. Setup Execute Script. Execute File dialog appears shown Figure 4-22.
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Figure 4-22 Execute File Dialog Select count8.script. system displays count8.script File Name field. Select Exit Design Analyzer. Figure 4-23 Figure 4-24 illustrate actual text count8.script file VHDL Verilog HDL, respectively.
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Figure 4-23 VHDL Script File Count8
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Figure 4-24 Verilog Script File Count8
Placing Routing Your Design Using XMake
XMake automates translation portion Xilinx design flow, which makes processing complex design simple running program. Given name top-level SEDIF file, XMake finds processes lower-level designs. produces file that placed routed, well file ready downloading FPGA. invoke XMake from within XACT Design Manager (XDM) from shell tool window. this section translate count8 design using XMake from shell tool window. Refer XACT Reference Guide details about each program that XMake runs about running XMake from XDM. procedure translating count8 design slightly different installed different platform network than that
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XACT Development System. Follow procedures that apply your specific configuration.
Same Network XACT Software
Follow procedures this section software installed same network platform XACT Development System software. find command-line options that XMake used XMake output file, count8.out. XMake from shell tool window, type following. xmake count8.sxnf Refer Figure flow diagram that illustrates Xilinx XC3000A implementation flow synthesis.
Different Network Than XACT Software
Follow procedures this section software installed different network platform than XACT Development System software. installed machine that does have access both XACT Development System executable files, must Syn2XNF first then copy output files platform where XACT executable files reside. Refer Figure flow diagram that illustrates Xilinx XC3000A implementation flow synthesis. following sections describe Syn2XNF XMake programs.
Running Syn2XNF
Because software installed different platform than XACT software, must first Syn2XNF translate your design into file, follows. Change directory where count8.sedif file located execute following command. syn2xnf count8
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SYN2XNF software might display following message that prompts overwrite existing file that same design name. WARNING: file count8.xff already exists. want overwrite (yes system displays previous message, enter Syn2XNF creates following output files: count8.xff, count8.xnf syn2xnf.log. Copy count8.xff count8.xnf files platform network where XACT software installed. Note: Copy command with option preserve time stamp information.
Running XMake
Perform following steps translate count8 design using XMake. platform where XACT Software installed. Open shell tool window. Enter following command line. xmake count8 option causes XMake start with file skip translation process. XMake program processes necessary design files, displaying progress screen. translation successful, XMake issues this message. `count8.bit' been made, check output `count8.out' sure examine count8.out, count8.prp, count8.rpt files warnings errors, described "Examining XMake Output Files" section this manual.
Examining XMake Output Files
addition routed file bitstream file, XMake generates three very useful output files. this section open each file familiarize yourself with contents.
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file, count8.out, contains output from programs that XMake invokes. This information also displayed onscreen during processing. file, count8.prp, (Design Rules Checker) report file generated XNFPrep. file, count8.rpt, contains placement routing results. This report also contains listing unrouted pins nets.
Reviewing XMake File
When XMake, output XMake program appears screen. file shows every program XMake, command options selected, output each individual program. warnings errors produced programs XMake appear file. should always review file after running XMake, even warnings error messages during design processing. warnings errors occur, save yourself some time catching problem instead later design process. Examine count8.out file count8 design follows. Open shell tool window. Change project directory. text editor view count8.out.
Checking Warnings Errors File
XNFPrep finds errors warnings, file directs examine file. file also contains detailed list logic trimmed XNFPrep unnecessary. This file useful debugging tool. should expect some warning messages count8.prp files errors. Examine count8.prp file count8 design. following headers correspond table contents found count8.prp.
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XNFPrep Errors lists errors found design. Errors problems with design that cause XMake terminate. must reported errors. XNPPrep Warnings lists warnings found design. Warnings notify unusual aspects your design. should correct warnings; however, mandatory. Clock Signals Report contains summary clock signals and/or global buffers assist determining best global buffers. This section also contains list guidelines consider when assigning signals global buffer. Timing Specification Summary contains list XACTPerformance timing specifications used design. Logic Trimming shows logic removed from your design sourceless loadless signals ground connection. should review this section verify that logic required your design been removed design error.
Checking File
After XMake runs PPR, generates report file with .rpt extension. This file contains important information following categories.
Partition, Place, Route Summary includes number occupied CLBs that approximately corresponds total area provided Synopsys Report. Chip Pinout Description contains list pins used design locations specified constraints file. Critical Nets indicates nets that were assigned constraint. Feedthrough Split Nets indicates nets with names that were modified could re-powered. Re-powering signal regeneration accomplished using special function CLB. Deletion Traceback enables check nets cells that were removed that should remain. Synopsys Check Design tool detects unconnected pins unused cells.
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Examine count8.rpt file make sure there unrouted pins nets. text editor view this file, which contains five pages. Figure 4-25 illustrates each page file.
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Figure 4-25 File
Comparing Actual Versus Estimated Area Results
file contains partition, place, route summary that includes number occupied CLBs that approximately corresponds total area number provided Synopsys Report. this section compare accurate Design Compiler preplacement pre-routing estimates were actual results.
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Figure 4-19 shows estimated area results from Design Compiler Figure 4-25 shows actual area results. following table summarizes area utilization results. Table Area Utilization Summary Partitioned Design Utilization Using Part 3020APC84-6 Actual Used Estimated Used
Occupied CLBs Packed CLBs Bonded Pins Function Generators Flip-Flops Clock Pads
actual area utilization timing vary from results reported Design Compiler because performs actual logic mapping. Note: Your actual area numbers also vary from area utilization reported Design Compiler because adds additional CLBs feedthrough split nets. Refer page file, illustrated Figure 4-25, more information split nets count8 design.
Using XDelay
XDelay command allows obtain detailed post-placement post-routing timing information about your design. XDelay results summarize worst paths design, necessarily paths that concern you. XDelay also interactive mode, which enables extract information about specific paths design, example, generate timing report subset design. choose specific paths selecting individual starting ending points indicating specific path type. more information about XDelay options, refer XACT Reference Guide.
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this section XDelay report worst-case paths maximum clock frequency design. also compare output XDelay estimated timing reported Design Compiler.
Invoking XDelay
Enter following command command line XDelay, which creates short report, count8.dly. xdelay count8 XDelay produces following output shown Figure 4-26.
Figure 4-26 XDelay Short Report
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Comparing Actual Versus Estimated Timing Results
often better timing estimates looking number block levels that critical longest path must traverse rather than using estimated delays listed count8.timing report, illustrated Figure 4-20. Block levels number CLBs IOBs. longest path reported Design Compiler clock-to-clock delay from register through incrementer. This delay reported 44.55 count8.timing report included clock-to-output delay, clock-to-setup delay, average wire load. XDelay report, illustrated Figure 4-26, reports longest clock-to-setup delay 30.4 with four block levels. However, short report does include delays from clock clock net. view detailed timing report, refer XDelay chapter XACT Reference Guide, Volume3.
Verifying Your Design Using XChecker
This section describes function XChecker Download/ Readback cable. actually download count8 design this tutorial. verify that your design works your system, XChecker Download/Readback cable associated software. With XChecker, load configuration bitstream generated MakeBits program. MakeBits file defines internal logic functions interconnections target FPGA. more information XChecker cable MakeBits program, refer XACT Hardware Peripherals Guide XACT Reference Guide, Volume respectively. store file your system memory PROM. Refer section XACT Hardware Peripherals Guide more information about storing files PROMs.
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Using FPGA Compiler
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291 Printed U.S.A.
Xilinx Synopsys Interface FPGA User Guide
XACT Development System
Chapter
Using FPGA Compiler
FPGA Compiler enables synthesize implement your design Xilinx FPGA devices. FPGA Compiler offers high-performance features that deliver efficient results accurate timing area reporting, well following features.
Logic optimization XC4000 family configurable logic block (CLB) input/output block (IOB) architectures Timing area constraints evaluations terms actual utilization Area reports that list device usage, example, CLBs, IOBs, 3-state buffers Timing constraints passed XACT-Performance utility (Xilinx Netlist Format) file reader design reuse backannotation post-route results DesignWare library that maps X-BLOX modules, which generate optimized implementations arithmetic functions
addition, FPGA Compiler optimizes flip-flops latches into block, optimizes 3-state buffers into block, encodes one-hot state machines, uses Clock Enable automatically. best results, FPGA Compiler XC4000/A/D/H devices. FPGA Compiler XC3000 XC3100 devices; however, libraries these devices Design Compiler synthesis tools results same.
Xilinx Synopsys Interface FPGA User Guide December, 1994 (0401291
Xilinx Synopsys Interface FPGA User Guide
Before Begin
Before beginning Xilinx design using Synopsys tools, read "Getting Started" chapter beginning this manual, which describes following.
Verify that XACT Development System software installed your system Modify Xilinx-provided default Synopsys startup file, applicable
FPGA Compiler Design Flow
This section describes FPGA Compiler design flow, which varies slightly depending whether installed same platform different platform than XACT Development System software. Proceed following section that applies your system configuration.
Same Platform XACT Software
Figure shows design flow FPGA Compiler based Xilinx XC4000 device FPGA Compiler-specific libraries when software installed same platform network XACT Development System software.
XACT Development System
Using FPGA Compiler
Synlibs*
design.v design.vhd
xblox_4000.sldb xc3000.sdb xc4000.sdb xprim_4000-5.db
.synopsys_dc.setup
design.script
DC-shell Design Analyzer
design.sxnf
XMake File
xprim_3000/*.xnf xprim_4000/*.xnf
X4824
*Append Synlibs output .synopsys_dc.setup file. Refer "Getting Started" chapter more information.
Figure Design Flow with Installed Same Platform
Different Platform than XACT Software
installed machine that does have access both XACT Development System executable files, must copy move Syn2XNF output files, XNF, platform where XACT executable files reside, illustrated Figure 5-2.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Synlibs*
design.v design.vhd
xblox_4000.sldb xc3000.sdb xc4000.sdb xprim_4000-5.db
.synopsys_dc.setup
design.script
DC-shell Design Analyzer xprim_3000/*.xnf xprim_4000/*.xnf
design.sxnf
Syn2XNF
design.xnf
design.xff
Platform Platform
XMake** File *Append Synlibs output .synopsys_dc.setup file. Refer "Getting Started" chapter more information. **Run XMake with option. X4829
Figure Design Flow with Installed Different Platform basic flow different devices same. XMake automatically runs appropriate mapping, placement, routing tools. FPGA Compiler-specific libraries, such xfpga_4000-5.db, allow FPGA Compiler directly CLBs IOBs. This direct mapping allows most compatibility between area timing analysis created within Synopsys environment final implementation FPGA. "Files, Programs, Libraries" chapter additional library information. Note: Although FPGA Compiler XC3000A/L XC3100/A designs, many commands this section specifically XC4000 devices available XC3000A/L XC3100/A devices.
XACT Development System
Using FPGA Compiler
Setting Wire-Load Model
Each primitive library contains estimated pre-layout routing wire-load models that device speed-grade specific. Synopsys tools these estimates when optimizing your design FPGA. provides wire-load models device-speed grade combination average model worst-case model, designated "_avg" "_wc," respectively. default wire load average.
Wire-Load Models Xilinx FPGAs
following tables list wire-load models each Xilinx device. Substitute "_avg" "_wc" a/w, example, 4003-4_wc. Table XC4000/A/D/H Wire-Load Models Speed Grade 4003-4_a/w 4005-4_a/w 4006-4_a/w 4008-4_a/w 4010-4_a/w 4013-4_a/w Speed Grade 4002-5_a/w 4003-5_a/w 4004-5_a/w 4005-5_a/w 4006-5_a/w 4008-5_a/w 4010-5_a/w 4013-5_a/w Speed Grade 4002-6_a/w 4003-6_a/w 4004-6_a/w 4005-6_a/w 4006-6_a/w 4008-6_a/w 4010-6_a/w 4013-6_a/w Speed Grade
4005-10_a/w
4010-10_a/w
Table XC3000 Wire-Load Models Speed Grade 3020-50_a/w 3030-50_a/w 3042-50_a/w 3064-50_a/w 3090-50_a/w Speed Grade 3020-70_a/w 3030-70_a/w 3042-70_a/w 3064-70_a/w 3090-70_a/w -100 Speed Grade 3020-100_a/w 3030-100_a/w 3042-100_a/w 3064-100_a/w 3090-100_a/w -125 Speed Grade 3020-125_a/w 3030-125_a/w 3042-125_a/w 3064-125_a/w 3090-125_a/w
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
Table XC3000A/L Wire-Load Models Speed Grade 3020a-6_a/w 3030a-6_a/w 3042a-6_a/w 3064a-6_a/w 3090a-6_a/w Speed Grade 3020a-7_a/w 3030a-7_a/w 3042a-7_a/w 3064a-7_a/w 3090a-7_a/w Speed Grade 3020l-8_a/w 3030l-8_a/w 3042l-8_a/w 3064l-8_a/w 3090l-8_a/w
Table XC3100/A Wire-Load Models Speed Grade 3120-3_a/w 3120a-3_a/w 3130-3_a/w 3130a-3_a/w 3142-3_a/w 3142a-3_a/w 3164-3_a/w 3164a-3_a/w 3190-3_a/w 3190a-3_a/w 3195-3_a/w 3195a-3_a/w Speed Grade 3120-4_a/w 3120a-4_a/w 3130-4_a/w 3130a-4_a/w 3142-4_a/w 3142a-4_a/w 3164-4_a/w 3164a-4_a/w 3190-4_a/w 3190a-4_a/w 3195-4_a/w 3195a-4_a/w Speed Grade 3120-5_a/w 3120a-5_a/w 3130-5_a/w 3130a-5_a/w 3142-5_a/w 3142a-5_a/w 3164-5_a/w 3164a-5_a/w 3190-5_a/w 3190a-5_a/w 3195-5_a/w 3195a-5_a/w
Changing Wire-Load Model
change wire load from average worst case, Wire Load command follows. set_wire_load "parttype-s_wc" speed grade wire-load model must match speed grade primitive library listed previous wire-load model tables illustrated this example. set_wire_load "4005-5_wc"
XACT Development System
Using FPGA Compiler
want evaluate block delays design without wire load, wire load None using Wire Load command follows. set_wire_load none
Wire-Load Models Determined
Average worst-case models derived from over 6000 designs that were placed routed different Xilinx parts each different speed grades. average wire-load model given part speed grade calculated collecting signal nets given fanout designs using part type speed grade. given fanout, percent nets from test suite slower percent nets faster than delay number average wire-load model. worst-case wire-load models standard deviation each average fanout value. given fanout, percent nets from test suite faster percent slower than delay number worst-case wire-load model; therefore, worst-case wire-load models more conservative than average wire-load models. determine actual wire-load delays after placing routing design. cases, wire-load delays increase size fanout increase. delays decrease with faster device speed grades. Report Timing command combines wire-load delay with block delay. more information Report Timing command, refer "Evaluating Timing Delays" section this chapter.
Operating Conditions
Only operating condition parameters available worstcase commercial (WCCOM) which default Xilinx libraries.
Configuring IOBs
following section describes configure XC4000/A/D/H IOBs. FPGA Compiler performs some optimization
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
automatically; however, must implement some features manually. FPGA Compiler performs following functions automatically.
Inserts input (IBUF) output buffers (OBUF) Inserts input 3-state output buffers bidirectional (IBUF, OBUFT, IOBUF) Optimizes flip-flop (IFD) latch (ILD_1) attached input buffers into Optimizes flip-flop attached output buffers into (OFD) Inserts clock buffer signals driving clock pins (BUFG)
First, must enter these commands either shell Command window prompt ports top-level design pads insert pads. set_port_is_pad insert_pads Insert Pads command adds correct buffers ports declared pads with Port command. following sections provide general description XC4000/A/ devices describes implement additional features manually.
XC4000/A/D IOBs
This section describes configure input output signals, well output slew rate. configure XC4000/A/D IOBs input, output, bidirectional signals with without pull-up pull-down resistor, independent usage.
Inputs
configure buffered input signal that drives data input storage element either flip-flop latch. buffered signal conjunction with input flip-flop latch. delay buffer added signal feeding data input input flip-flop/latch avoids possible hold time violation. Instantiating
XACT Development System
Using FPGA Compiler
flip-flop latch, such IFD_F ILD_1F, removes this delay because these cells include NODELAY attribute. Refer "XC4000/A/H Primitives Hard Macros" appendix complete list primitives that include NODELAY attributes. FPGA Compiler optimizes flip-flops connected input port into flip-flop latch does Clock Enable, Direct Clear, Preset pin.
Outputs
output signals, which drive programmable 3-state output buffer, registered direct. register positive-edge triggered flip-flop, clock polarity inverted inside IOB. (PPR automatically optimizes inverters IOB.) FPGA Compiler ability optimize flip-flops attached output IOB. However, FPGA Compiler cannot optimize flip-flops configured bidirectional pad. XC4000 output buffers sink XC4000A output buffers sink
XC4000/D Slew Rate
XC4000 output buffers have default slow slew rate that alleviates ground-bounce problems option fast slew rate that reduces output delay. SLOW option increases transition time reduces noise level. FAST option decreases transition time increases noise level. Warning: Synopsys Xilinx define slew rate using opposite terms. Synopsys uses slew control, whereas Xilinx uses slew rate. example, Synopsys HIGH slew control equivalent Xilinx SLOW slew rate. There types output buffers libraries. default output buffer FAST attribute assigned that OBUF_F (output buffer) OBUFT_F (3-state output buffer). However, avoid possible ground-bounce problem, Xilinx recommends that select SLOW default slew rate. Assign FAST slew rate only output buffers that require additional speed.
Xilinx Synopsys Interface FPGA User Guide
Xilinx Synopsys Interface FPGA User Guide
FPGA Compiler V3.1 later automatically infers FAST output slew rate. default slew rate SLOW (high control), following command. set_pad_type -slewrate HIGH all_outputs() this command before implementing Insert Pads commands. change output port FAST slew rate after changing default SLOW, following command. Replace port with name output port. set_pad_type -slewrate NONE {port} Table XC4000 Slew Rate Settings Xilinx Slew Rate SLOW FAST Synopsys Slew Control Attribute HIGH NONE FPGA Compiler Command set_pad_type -slewrate HIGH {port} set_pad_type -slewrate NONE {port}
XC4000A Slew Rate
XC4000A family offers more output slew-rate control options each individual output drive: fast, medium fast, medium slow, slow. Slew control alleviate ground-bounce problems when multiple outputs switch simultaneously. also reduce eliminate cross-talk transmission-line effects printed circuit boards. Warning: Synopsys Xilinx define slew rate using opposite terms. Synopsys uses slew control, whereas Xilinx uses slew rate. example, Synopsys HIGH slew con
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