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QUARTERLY JOURNAL XILINX PROGRAMMABLE LOGIC USERS
CELL
Virtex
industry's highest-density, highest performance technology, using 0.25 micron process advanced architecture. pages
Issue First Quarter 1998
PRODUCT INFORMATION
Programmable Logic CompanySM
Inside This Issue:
GENERAL
Record-Breaking Technology Today 1998 Data Book Technical Training Update
FOUR FPGA Families!
Xilinx recently announced four FPGA families, with record-breaking technology innovations:
PRODUCTS
Million-Gate Virtex Family Low-Cost Spartan Family HardWire Architecture 0.25µ XC4000XV Device Family XC4000XV 500K-Gate FPGAs XC5200 Family Faster Customer Success Stories: FPGAs: Matrox Graphics HardWire: Hewlett-Packard Hi-Rel: Ratheon T.I. 13-14 CPLDs: Ericsson Telecom
DEVELOPMENT SYSTEMS
Synplify Synthesis UNISIM Libraries 16-17 Foundation VHDL Verilog Alliance/Foundation Configurations Active-CAD System-Level Design LogiCORE
Spartan
industry's lowest-cost FPGAs, high volume applications, with devices under $2.00 year 2000. page
HINTS ISSUES
Using IBIS Specifications FPGA Self-Reconfiguring XL/XV Chacteristics 22-23 Using XC9500 JTAG UPGs XC9500 CPLDs 200-MHz Pulse Generator Reducing Using Decoupling Capacitors Dangers Plug-In XC4000XL Power Calculation Component Availability Chart 30-31
industry's first FPGA-specific ASIC called "FpgASIC", making ASIC conversions easier than ever before. page
XC4000XV
industry's first 500K gate FPGA family with devices containing over million transistors, industry's largest FPGA. pages
EDITORIAL
Xilinx Record-Breaking Technology Today
CARLIS COLLINS Editor
aggressively expanding limits both device software technology, will from articles this issue XCell. number supplier FPGAs created worldwide because industry's most advanced, highest- spend large portion revperformance, 0.25 micron enues research technology, broadest line development. powerful efficient device result, have created architectures that creating industry's most design opportunities never advanced, highestperformance, 0.25before possible.d micron technology, broadest line powerful efficient device architectures that creating design opportuniXilinx, Inc. 2100 Logic Drive ties never before possible. device Jose, 95124-3450 families include:
have
XCell
Phone: 408-559-7778 FAX: 408-879-4780
©1998 Xilinx Inc. rights reserved.
XCell published quarterly customers Xilinx, Inc. XILINX Xilinx logo registered trademarks Xilinx, Inc. Spartan, Virtex, HardWire, Alliance Series, Foundation Series, AllianceCORE, LogiCORE, WebLINX, SelectRAM, SelectRAM+, Dual Block, FastFLASH, XC-prefix products trademarks, "The Programmable Logic Company" service mark Xilinx, Inc. Other brand product names trademarks registered trademarks their respective owners.
XC4000XV family high-performance FPGAs 500,000 system gates over MHz). Virtexfamily high-performance, very dense, system-level FPGAs 1,000,000 system gates over MHz). Spartanfamily low-cost devices 40,000 system gates over MHz). family HardWireASIC devices that provide unprecedented ease-ofuse, quick turnaround, guaranteed performance high-volume applications.
Powerful Software
have also been working diligently create most powerful efficient
development tools industry. With Alliance Series Foundation Series software, quickly develop debug FPGA CPLD designs devices, using combination design methods, including VHDL schematics. These development tools give most comprehensive powerful solutions available anywhere, constantly refining updating tools with latest software advances, both from in-house development team from Alliance partners. Along with advanced development tools, offer expanding library intellectual property cores that will become increasingly important begin create designs high-density devices. With intellectual property, your next generation designs will faster easier produce. addition, continue develop tools that will automatically create complex, customized functions you. example, using core generator tools, will soon able automatically create massively parallel functions that much faster than commercially available device. doing best anticipate your needs provide with most advanced technology, services, technical support. this magazine, WebLINX site (www.xilinx.com), intend provide with interesting informative articles timely reference information that make your easier more productive. welcome respond your requests your suggestions improvement areas. Please know we're doing writing editor@xilinx.com.
TECHNICAL TRAINING UPDATE
Xilinx Customer Education Group developed courses: one-day Foundation Series schematic entry course one-day synthesis course based Synopsys. Foundation Series schematic-entry course offers combination lecture labs enhance learning experience. course syllabus includes Schematic Editor, Editor, State Machine Bubble Diagrammer, Simulator, Project Manager. reinforce lecture materials, course includes four exercises, plus optional presenting advanced features simulator. one-day Synopsys-based synthesis course focuses implementation FPGA from synthesized design. course
designed experienced Xilinx Synopsys users familiar with Alliance Series software FPGA Compiler. Topics included this course include: Setting Synthesis, Generation Efficient code, Xilinx Synopsys methodologies. Three labs included further enhance synthesis learning experience. offer these courses Xilinx headquarters office Jose, Calif., distributors worldwide will also offering these same courses. find exact dates scheduled distributor courses your area checking with your distributor browsing educational information WebLINX (www.xilinx.com).
1998 Xilinx Data Book Available
1998 Xilinx Data Book available
paper, versions. data sheets have been updated since previous printing, several product introductions included, such Spartan Spartan-XL FPGA Families XC4000XV 2.5V FPGA Series XC4000XLT FPGA Series XC1701/L Serial PROMs book also includes these updated data sheets: XC9500 CPLDs XC4000E/EX/XL Series FPGAs XC5200 Series FPGAs XC3000 Series FPGAs XC1700D Serial PROMs Product overviews provided several products, with additional detail WebLINX: HardWire FpgASICProducts High-Reliability XC4000E/X Series Alliance Foundation Development System Products CORE Solutions Included 700+ pages data book several application notes providing additional technical product information, including Technical Overview first-time user. Complete packaging, programming, quality information also included, everything easy find with tabbed sections complete index.
Electronic Versions
information data book available WebLINX (www.xilinx.com), Xilinx site. latest files also found Rev. AppLINX CD-ROM, which provides quick hyperlinks from table contents, index, bookmarks topic book. WebLINX AppLINX include complete collection Xilinx application notes, well information products that were included general data book (such XC6200 series reconfigurable processing units). Both WebLINX AppLINX allow easy searching data book application notes. order your copy 1998 Data Book latest AppLINX CD-ROM, contact your local Xilinx salesperson, send e-mail literature@xilinx.com.
PRODUCT INFORMATION-COMPONENTS
Virtex
Million-Gate 100-MHz FPGA Technology
Leading process technology, architectural innovation, intellectual property cores, ASIC design methodology combined Xilinx Virtex series.
dards simultaneously, eliminating challenges multiple signal standards system design. Virtex architecture, with 2.5volt supply voltage, offers industry's first devices capable directly interfacing beyond CMOS logic. Virtex series also supports important low-voltage standards such LVTTL, LVCMOS, GTL+, SSTL3.
irtex next generation Xilinx FPGA technology; series high-performance, high-density, system-level devices with revolutionary architecture, built with leading 0.25 micron process technology. These FPGAs meet rapidly growing demand high-speed system-level functions, helping create smaller, lower power, more reliable products with more features. begin Virtex begin designs today, because Xilinx been working Virtex designs today, closely with partners provide immediate because Xilinx been delivery Xilinx working closely with Alliance Series software libraries. This developEDA partners provide ment software solution ASIC designers provides immediate delivery higher performance, faster Xilinx Alliance Series compile times, unique innovations that make software libraries.d much easier develop very high-density, very high-performance FPGA designs. Virtex series, combined with Xilinx software, represents approach system-level design.
SelectRAM+
Virtex SelectRAM+ feature allows distributed RAM, block RAM, high-speed access external RAM. common example system-level designs requiring fast access varied configurations video processing application; where video frame data stored megabytes, line data stored kilobytes, pixel coefficient data stored bytes. megabytes storage, Virtex SelectI/O feature provides external synchronous DRAM access compatible with SSTL3 standard. Kilobytes data stored block SelectRAM memory; Virtex series offers blocks 133-MHz dual-port synchronous SRAM, yielding internal memory bandwidth gigabytes/second. bytes data, Virtex offers distributed SelectRAM memory. Pioneered Xilinx XC4000 family, distributed SelectRAM allows create fast flexible dual-port synchronous SRAMs.
SelectI/O
Virtex SelectI/O interface allows single device interface with multiple stan-
Architecture
Virtex architecture based logic cells, which 4-input look-up tables with register. Each contains four these logic cells. Each also contains special circuitry propagating carry, addition special circuitry implementing efficient multipliers. Combining these features with abundance registers makes very easy create very high speed, pipelined multipliers other applications.
accurately model interconnect delays Virtex Series, without placement information.
Cores
Because would take many designeryears create million-gate system from scratch, Xilinx made Virtex architecture very adaptable cores. optimizing segmented interconnect capability create fundamentally faster architecture, Xilinx reduced need architecture-specific cores. Therefore, easily implement cores with highly predictable performance using high-level languages.
Vector-Based Interconnect
Virtex series uses vector-based, variable-length, segmented routing architecture, optimized allow minimal interconnect delays; this routing faster more predictable than that non-segmented architectures. Vectorbased routing results short, predictable delays that sensitive minor changes placement. This allows synthesis tools
Availability
first Virtex device contains 250,000 system gates user pins. expected sampling second quarter 1998. Virtex devices that offer million system gates expected second half 1998.
Figure Virtex Functional Block Diagram
Xilinx Virtex architecture features Xilinx SelectRAM+ memory with distributed block RAM, plus high-speed access external SSTL3 standard, phase locked loops (PLL), Xilinx SelectI/O pins, Xilinx segmented-routing, vector-based interconnect.
Introducing FPGA Family Cost Applications
Spartan
Under Year 2000
early January, Xilinx announced
Spartan series FPGAs, designed address high-volume FPGA applications. This series incorporates technology with on-chip RAM, easy core implementation, high performance, cost. Initial devices available 5-volt versions, based 0.5-micron technology (see Table 3.3-volt versions based 0.35-micron technology scheduled 3Q98. "It's enough simply offer low-cost replacements traditional ASIC designs. Designers want benefits performance, RAM, intellectual property, lower costs in-system programmability time-to-market advantages, especially fast-paced consumer markets," said Roelandts, Xilinx president chief executive officer. address total cost management, Xilinx reduced cost Spartan devices only reducing size also re-assessing stages manufacturing cycle, including packaging, test, manufacturing overhead costs. third quarter 1998, Xilinx will introduce 3.3-volt version this series. design using 5-volt technology with confidence that 3.3-volt devices will completely footprint compatible. Additionally, 3.3-volt devices will offered even lower price points than their 5-volt predecessors, taking advantage process migration step 0.35 micron.
Software Support
majority Xilinx high-volume customers sensitive time-to-market pressures, preferring complete front-to-back development environment, with minimal learning curves high-quality results. Xilinx Foundation Series software ready-to-use solution that meets this need. Foundation Alliance Series software available Spartan devices, with software pricing starting $495. addition design tools, intellectual property cores will offered, specifically targeting Spartan Series, including interface. Cores available today from several Xilinx AllianceCORE partners, including T7L, Integrated Silicon Systems, Virtual Group (formerly Semiconductor), Memec Design Services (offering RISC processors, microprocessor peripherals, cores). cores Xilinx LogiCORE product series, AllianceCORE products from third-party providers also available.
Process Technology Generates Feature
aggressive process migration, we've realized layout circuit-design techniques through finer geometries technologies that translate directly cost savings customer," continued Roelandts. These leading-edge process technology advances offer smallest possible sizes. Table Further, HIGH first time LOGIC MAX. VOLUME DEVICE CELLS YSTEM GATES I/OS BITS RICE* XCS05 2,000 5,000 3,200 $3.95 industry, lowXCS10 3,000 10,000 6,272 $5.50 cost ASIC XCS20 7,000 20,000 12,800 $6.50 replacement XCS30 1368 10,000 30,000 18,432 $7.95 solutions XCS40 1862 13,000 40,000 25,088 $19.95 incorporate *100,000 unit pricing end-98 on-chip using Xilinx SelectRAMfeature pioneered XC4000 series. Together, robust Spartan series offers total cost management solution while delivering ASIC requirements performance, on-chip SelectRAM, cores, price, with time-to-market advantages FPGAs.
Available From Distributors
first three members Spartan family, XCS20, XCS30, XCS40, available today high-volume quantities. Package offerings will include plastic quad (PQ), thin quad (TQ), very thin quad (VQ) flat packs; plastic leaded chip carrier (PLCC); ball grid array (BGA) options.
Architecture Combines FPGA ASIC Technologies
architecture, Xilinx combined FPGA advantages with eight years HardWire ASIC experience create first FPGA-specific ASIC "FpgASIC." FpgASICs true ASIC devices that designed meet performance feature requirements Xilinx FPGAs. Both conversion method, called DesignLock,and device silicon customized make transition from FPGA ASIC easy possible. family Xilinx-specific FPGA I/Os, JTAG, control logic built into base layers device. They exact, preverified, ASIC versions FPGA features, which often most difficult convert from FPGA ASIC. example, devices have exact Xilinx FPGA built into silicon. More than different models have been verified, allowing perfect timing matches XC4000, XC4000E, XC4000EX, XC5200 device family conversions. HardWire ASICs also support Xilinx LogiCORE functions. macro completely pre-verified transition from FPGA ASIC able encompass tight specifications. HardWire DesignLock methodology begins with your completed FPGA files, including timing, placement routing information. Throughout conversion process, these crucial elements kept intact. ASIC much smaller than FPGA die, because
programmable elements replaced with metal vias. However, relative timing spatial relationships devices preserved. with conversions, ASIC timing usually much faster than that original FPGA. However, Xilinx tools take timing relationships constraints into consideration that each path precisely verified. Even asynchronous paths exactly timed. original functionality FPGA preserved throughout conversion process, eliminating need additional vector development. every step, conversion process verify that original functionality intact. Xilinx full-scan methodology generates complete manufacturing fault coverage vectors, with average fault coverage over 98%. technology unique FPGA/ ASIC industry. HardWire ASIC conversion process gives luxury designing with FPGAs, while taking full advantage ASIC cost reductions.
HardWire Architecture
World's First
0.25-micron FPGA Family
eading logic industry with most advanced semiconductor manufacturing processes, Xilinx, partnership with United Microelectronics Corporation (UMC) developed 0.25-micron FPGA process technology. This leading-edge technology basis new, very-high-density, XC4000XV FPGA family. first device this family, XC40125XV, incorporates million transistors single piece silicon more than three times that today's highest performance microprocessors, such Intel Pentium (with million transistors). Samples XC40125XV industry's largest FPGA device available now, production shipments will begin early first quarter 1998. Xilinx partners DuPont Photomasks Nippon Printing challenge developing photomasks that would unite Xilinx design specifications with UMC's manufacturing process technology. extraordinary density larger Xilinx FPGA required DPI's extensive technical expertise meet demanding 0.25-micron design manufacturing specifications. also drew strengths global network manufacture photomasks, with data collection coordination occurring Santa Clara, Calif., actual production taking place Ichon, Korea, facility. Xilinx partner UMC, based Hsin-Chu City, Taiwan, Taiwan's first private sector manufacturer integrated circuits. operates wafer fabs Science-Based Industrial Park Hsin-Chu City. first dedicated foundry market with 0.25-micron technology, lead industry this next generation processing. 0.25micron CMOS process with dual-gate oxide five-layer metal very demanding rugged technology that will enable products with better integrity, yields, quality, performance," stated Brooks, board member. "Furthermore, offers Xilinx other customers additional advanced technology, including low-voltage mixed signal capability. With progress 0.18-micron technology, will continue leadership process introductions." "Our close partnerships with industryleading manufacturing partners directly aided delivery advanced processes," said Roelandts, Xilinx president chief executive officer. "Furthermore, it's more than just having access industry-leading technology order deliver this process. unique methods rapid deployment architectures processes allows bring better products market faster and, turn, bolster success customers."
Technology Made Possible Through Partnerships
0.25-micron product development, Xilinx partnered with four suppliers Cadence Inc., DuPont Photomasks Inc. (DPI), Nippon Printing (DNP) UMC. Xilinx partner Cadence provided physical verification tools necessary create this technology. "With million transistors FPGA, Xilinx providing dramatic increase capability customers," said Bill Portelli, vice president general manager Cadence Custom Business Unit. "Xilinx turned Vampire, Cadence's state-of-the-art hierarchical physical verification tool, verify correctness world's most complex FPGA device. First-pass working silicon testament excellent design, great tool, impressive teamwork between Xilinx Cadence this project."
XC4000XV:
XC4000XV FPGA family delivers densities 500,000 system gates (20,000 logic cells). This family includes four devices, offering system performance greater than MHz, featuring 2.5-volt internal operation with 3.3-volt I/Os allow optimum performance compatibility with existing voltage standards. announced five-year roadmap last January, which clearly defined plans provide higher-density FPGA families advanced processes. course months, have delivered members XC4000XL family high-density high-performance FPGAs. These widely accepted customers leaders density performance," said Roelandts, Xilinx president chief executive officer. "With migration 0.25-micron process, XC4000XV FPGA family represents next leadership step bring benefits FPGA reconfigurability time-to-market advantages traditional ASIC users demand high-performance high-density logic."
Introducing Industry's First 500K Gate FPGA Family
advanced product, System Explorer. using XC40125XV, highest density programmable logic device available today, able achieve these density levels."
Architectural Advantages XC4000X Series
XC4000XV family more advanced implementation XC4000EX/ architecture, which uses segmented routing distributed RAM. These features make ideal platform implementing cores. example, segmented routing architecture allows predictable performance regardless device size much logic employed. With non-segmented routing used competitors, cores will slow down unpredictably surrounding logic added when designs moved larger devices. performance predictability requirement designs using intellectual property (cores) because want choose cores independently device density, expect core's performance remain same design evolves. addition, footprint-compatibility advantages, current XC4000XL customers easily immediately upgrade higher-density XC4000XV products.
Delivering ASIC Performance Density, Today
Digital designers have traditionally used custom ASIC devices considering time-to-market benefits that Xilinx high-density, high-performance FPGAs offer. According Jordan Selburn, principal analyst Dataquest, Xilinx XC4000XV family, conjunction with Xilinx HardWire ASIC capability, address approximately percent 1997 gatearray design starts, based XC4000XV maximum performance density levels. Vincent Coli, director product marketing Aptix, leader reconfigurable system prototyping solutions, says Xilinx their density because it's here today. customers demanding several million gates programmable logic most
XC4000XV Family
Device Logic Cells System Gates XC40125XV 10,982 80,000 265,000 XC40150XV 12,312 100,000 300,000 XC40200XV 16,758 130,000 400,000 XC40250XV 20,102 180,000 500,000 Available Q198 1H98 1H98
XC5200 Family Faster
XC5200 family percent
faster with introduction XC5200-3 XC5200-4 speed grades. Xilinx introduced XC5200 family 1995 first FPGAs optimized high-volume, low-cost, consumer applications that once required custom gate arrays. Now, wide acceptance, XC5200 industry's fastest growing FPGA family, third-largest unit shipments, with more than three million units shipped. This family offers five devices ranging from 1,936 logic cells, allowing replace gate arrays using 20,000 logic gates. devices come different packages, both commercial industrial grades, including VQ64 package that provides most space-efficient footprint consumer, hand-held, other small form factor applications. And, footprint compatibility allows easily move XC4000 family higher speed, higher density, on-chip RAM, 3-volt operation. XC5200 data sheet, with latest specifications expanded architectural description, available 1998 Data Book WebLINX (www.xilinx.com), Xilinx site World Wide Web. XC5200-3 speed files with percent higher performance available from "file download" area WebLINX. XC5200 devices fully supported Xilinx Foundation Alliance Series software solutions. low-cost base system been extended support XC5206 XC5210 devices, addition XC5202 XC5204 devices. combination powerful, easy-to-use software low-cost programmable architecture, gives shortest time-to-market, eliminating need gate arrays, even high-volume consumer applications.
Using IBIS Specifications
IBIS files, initiated Intel, attempt describe strength CMOS output drivers black boxes, giving only voltage current values without getting into proprietary circuit details. Xilinx IBIS files FPGA families. problem with IBIS large number base; usually just want know strength pull-down transistor (sink capability) pull-up transistor (source capability). Close either rail, outputs resistive, which means voltage proportional current. following table shows condensed IBIS information, expressed output resistance ohms, sink voltage less than volt above ground, source voltage less than volt below Vcc. XC4000 devices, with their n-channel pull-up transistors,
source resistance calculated between three volts. IBIS specifies minimum maximum current values, converted here resistor values.
Sink Resistance (ohms) 13.5 19.2 12.3 16.9 14.4 19.8 22.1 27.7 14.4 18.8 20.5 29.4 14.4 20.5 Source Resistance (ohms) 25.6 40.1 29.7 46.0 25.8 33.1 53.3 60.5 48.1 58.7 32.9 54.0 28.0 41.0
Device Family XC3000A XC3100A XC4000 XC4000E XC4000EX XC5200 XC4000XL
FPGA CUSTOMER SUCCESS STORY
Matrox Graphics
XC5204 Used Rainbow Runner
ntil recently, home computer been tucked away office den, separated from other entertainment media such television VCR. latest developments digital video technology bringing these products together. forefront this convergence Matrox Graphics Rainbow Runner series video upgrades Matrox add-in cards. Together, Rainbow Runner Matrox's graphics accelerators open whole universe video home. They make possible high-quality video editing, frame capture, video conferencing, PC-to-TV output, hardware MPEG playback, Matrox Graphics, Montreal-based company that more than doubled sales graphics add-in cards each last three years, selected Xilinx XC5204 device high-volume Rainbow Runner daughtercard. XC5204 chosen this consumer application because cost, high count, reprogrammability during development. XC5204 able functionality without having redesign custom graphics processor add-in card. "Matrox committed providing innovative, leading-edge technology deliver best performance competitive prices, says Lorne Trottier, president, Matrox Graphics Inc. Rainbow Runner series video companion cards example company's commitment developing breakthrough technology delivering breakthrough pricing. XC5204 device used Rainbow Runner daughtercard Matrox Millenium, providing high-quality video editing, video conferencing, computerbased training, multimedia authoring.
flexibility programmable solution allowed frequent design changes during development, while maintaining required pinouts. Board space critical add-in card, Xilinx XC5200 family enabled solution that would feasible with discrete logic. Plus, large number I/Os were needed interface, points XC5204. Matrox expects sell hundreds thousands daughtercards, sees need fully customized ASIC, even this highvolume consumer application, because Xilinx cost-saving HardWire technology. design created with generic VHDL synthesized Viewlogic's ViewSynthesis product. designer chose VHDL because ability make highlevel design changes. powerful combination ViewSynthesis Xilinx implementation tools allowed designer work independently details target architecture. This Matrox Graphics' first programmable logic device, design completed using Xilinx software with minimal training. Matrox Rainbow Runner example consumer applications that push envelope technology. XC5204 perfect with powerful architecture, fast time-to-market, cost compared other solutions. Matrox Graphics, made possible advanced video companion card cost that average computer user afford.
HARDWIRE CUSTOMER SUCCESS STORY
Hewlett-Packard Companion Scanner
Partnership Success Story
Hewlett-Packard Companion scanner
copier accessory that allows picture document scanned Laserjet printer without first downloading data Facing very tight time constraints, Design Group Printer Division Boise, Idaho realized could rely fully customized ASICs past. According group's leader, Doug Keithly, they decided FPGAs they could meet planned product release date. FPGA vendor decision based three major factors: Level service (the group FPGA design). proven cost-reduction path ASIC device. ability support non-VHDL environment (the designers want spend additional weeks learning rudiments VHDL design). chose Xilinx because offered complete HardWire ASIC cost-reduction plan (including schedule that their target), schematic-based development environment, on-site engineering help. picked full sea-of-gates HardWire approach smallest, most costeffective die, Xilinx provided vector generation guaranteed functionality ASIC. Doug team began slam dunk development project with block diagram system. Within Xilinx. were month, using FPGA, they really pleased.d board with first implementation. second month, they achieved functionality were close final solution. During this phase, system itself still being defined. After design itself finalized, they needed additional months other mechanical design including paper handling, motor control, firmware testing. Because they were constantly making changes during this phase, device programmability key. design team used FPGA enhance system functionality using device functions, processing pixels second. Even on-board microprocessor could handle data speeds required, signal processing done HardWire ASIC, with microprocessor providing set-up coordination between functions. After four months, ready final release. They sent FPGA Xilinx, waited weeks receive design conversion report, which looked clean. Within three weeks, Doug ASIC prototypes hand. first functional test, team discovered potential speed problem. However, with help Kiran Buch, Xilinx HardWire design expert, Doug identified asynchronous path where speed caused race condition. path used design Doug never checked original FPGA design, applied constraints path other asynchronous paths. Kiran sent devices back de-capped. Using focused beam technology, disabled path sent parts back Doug. modified devices worked perfectly. Xilinx made quick change mask fabricated modified ASIC. With HardWire ASIC board, system went final test where remaining system bugs were worked out. scanner full production Doug said, "This slam dunk Xilinx. were really pleased."
This
HI-REL CUSTOMER SUCCESS STORY
Major Program Success
Raytheon T.I.
Made Possible with Xilinx Hi-Rel FPGAs
esigners defense systems have long recognized benefits using FPGAs their system designs. flexibility, reconfigurability, easy access devices used prototyping compelling reasons FPGAs rapidly becoming technology choice defense industry designers. This been dramatically demonstrated with recent design successes team engineers Raytheon T.I. Systems McKinney, Texas, where they have successfully designed Xilinx FPGAs into their Horizontal Technology Integration (HTI) system. system, being developed Raytheon T.I. Hughes, second generation FLIR (forward looking infrared) system that used many different land-based fighting vehicles, well attack aircraft. First generation FLIR fire control systems were used successfully Operation Desert Storm. However, development FLIRs with higher resolution longer identification range critical extending advantage U.S. allies over future adversaries. design team Raytheon T.I. faced with some formidable challenges notably, cost development time. Xilinx high-reliability (Hi-Rel) FPGAs heart system. However, before this decision could reached, careful trade study Hi-Rel FPGAs versus Hi-Rel ASICs performed. Careful consideration HiRel ASIC costs, development time, required design reviews, prototype delivery schedules, inherent risks associated with doing ASIC conclusion that FPGA technology should preferred. Tenhet, Electrical Design Engineer Raytheon T.I. said, "Because ASIC suppliers longer supporting Hi-Rel market, rapidly changing technology evolution
ASICs forcing designers continually redesign make timing specifications smaller process parameters. While FPGAs going through similar evolution, continued support Xilinx Hi-Rel market enables proceed without these continuous redesigns. Additionally, using Xilinx FPGAs, need valuable time engineering resources generating test vectors." Multiple Xilinx FPGAs used system perform numerous control functions. scan control (circuit card assembly), FPGA serves microprocessor interface A/D-D/A converters. It's also serial interface digitizer CCA, transferring data signal controls. FPGA emulates UART RS232 interface between video converter scan control CCAs, generates video timing gates, provides optical position sensor counters. Tenhet design team Raytheon T.I. also deal with highly accelerated development schedule program. flexibility Xilinx FPGAs enabled them meet very aggressive schedule, time. were able layout pick configuration prior completion design," Tenhet said. "With Xilinx FPGAs, could make necessary design changes right production. fact, flexibility FPGAs, were able design sequentially incrementally
Continued following page
Raytheon T.I.
Continued from previous page
real plus given tight schedule were working under." ability make system upgrades field proved important program. need make upgrades system field, reconfiguring serial PROMs' firmware, which very cost-effective," Tenhet said. couldn't this with ASICs." System designers continue face dilemma finding suppliers committed Hi-Rel market. With many others choosing exit this market, become more difficult defense industry designers find reliable long-term sources supply. Xilinx, supplier MIL-PRF-38535,
active program making this search easier. "The commitment Xilinx Hi-Rel/ Military market also played very part decision their FPGAs HTI," Tenhet said. "Because this level commitment, Xilinx provided high levels support during design cycle, helped resolve problems quickly keep schedule. fact, because Xilinx acted part design team, schedule never slipped. program could have succeeded without Xilinx Hi-Rel FPGAs, successes enjoyed engineering team this program directly attributable Xilinx."
CPLD CUSTOMER SUCCESS STORY
Ericsson Telecom
Using XC9500 CPLDs High-Performance Telecommunications Equipment Ericsson Telecom Scandinavia Ericsson engineers also found they
introduced line data communication products used improve quality bandwidth satellite communication systems. designers Ericsson needed benefits in-system programmability (ISP) order designs into smallest possible space (they planned latest surface mount packaging, wanted program chips chose XC95108- circuit board minimize handling problems). This design, which cus7TQ100C because tom, high-performance microprocessor interface, needed fast, dense, extremely flexible. Ericsson chose these stringent XC95108-7TQ100C because these stringent requirements. flexrequirements.d ibility XC9500 CPLDs enabled Ericsson considerably shorten logic design cycle, because design extremely complex parts required several iterations before functioned correctly. could large amounts logic into XC95108, still make substantial logic changes without significant changes device performance pinouts. Ericsson saved substantial amount time money because XC95108 maintained fixed pinouts after design changes; therefore, boards were required. Pin-locking especially critical feature this application because Ericsson estimates there very high possibility that least field upgrade will have performed during each device's lifecycle. features XC9500 family, which also contributed significantly Ericsson's choice, fact that XC9500 products programmed, debugged, tested through industry standard IEEE 1149.1 JTAG Boundary-Scan port. This enables design iterations completed very quickly, greatly simplifies volume production final product.
Ericsson
PRODUCT INFORMATION-DEVELOPMENT SYSTEMS
Synplify
technical development team Synplicity, Inc. been cooperating with Xilinx deliver Synplify, fast, easy-to-use synthesis tool that produces extremely high-quality results. latest version Synplify supports Xilinx XC3X00A/L, XC4000E/X, XC5200, XC9500 families, well XC40125XV device. Synplify accepts timing constraints placed constraint file. this article will learn apply design constraints synthesis optimization.
Optimization Constraints
Synplify provides optimization constraints, which focus synthesis engine critical timing paths within design; these constraints passed place route tools. They control synthesis optimization without over-constraining place route engine. -improve <ns> Using this option forces Synplify restructure your design during optimization meet clock frequency goal. example, input delay input_a "-improve" option forces Synplify harder reduce clock period
define_input_delay input_a -improve
Design Constraints
Synplify supports user-defined timing constraints help improve your synthesis results. Timing constraints, timing-driven synthesis, should specified synthesis timing constraint file, <design_name>.sdc, added into list source files. Synplify encourages constraints closely match your design goal +5%. following design constraints used synthesis passed implementation tools timing-driven place route. Clock Constraint Allows specify specific frequency goal synthesis.
define_clock CLK1 -freq 33.0
Achieving Optimal Synthesis Results
Input Delay Constraint Allows model interface inputs your FPGA with outside environment, such delay before signal arrives input pin.
input delay input port 10.0 define_input_delay 10.0
-route <ns> Using this option forces Synplify additional route delay calculations meet clock frequency goal. example, routing delay reported place route engine input_a more than predicted Synplify. Also, input_a input delay. "-route" option forces Synplify re-run improve results adding additional route delay timing calculations.
define_input_delay input_a -route
Summary
Synplicity focused delivering highest quality results Xilinx FPGAs CPLDs. Synplify 3.0b release introduces Xilinx mapper that shown 5-20 percent performance area improvements. Synplify 3.0c release will support features such Passing timing constraints Alliance Series implementation tools. Speed area improvements Xilinx mapper. Synthesis support Spartan, Virtex, XC4000XV.
Output Delay Constraint Allows model interface outputs your FPGA with outside environment, such delay logic outside your FPGA that driven your outputs.
default output delay outputs 10.0 define_output_delay -default 10.0
UNISIM Libraries Functional VHDL
UNISIM libraries from Xilinx, simulate behavioral code with gate-level instantiations, gate-level descriptions imported from schematics, gate-level VHDL Verilog descriptions exported from synthesis, prior place route. These libraries tailored synthesiscomplement VHDL based design flows Verilog SIMPRIM Libraries currently availinclude special support able timing simulation, available global signals.d Alliance Series Foundation Series software, completing Xilinx HDLbased flow. Figure illustrates simulation flows that possible. libraries tailored synthesisbased design flows include special support global signals. They called UNISIM distinguish them from Unified Library schematic-based libraries, contain Unified Library cells used synthesis, well cells that instantiated limitations inferencing. instantiate cells such I/Os, RAMs, ROMS, oscillators, their Figure
libraries
UNISIM libraries.
code, proceed simulation without converting your synthesized design SIMPRIMS. Furthermore, UNISIM Libraries fully compatible with LogiBloxgenerated behavioral models. Designs have both LogiBlox UNISIM instantiations. Alliance synthesis vendors planning write structural VHDL Verilog that compatible with UNISIM libraries enable post-synthesis simulations that particularly useful verifying high-density synthesis results prior implementation. Because Verilog lacks configuration statement choose between different behavioral models, Verilog library been created each Xilinx technology. VHDL, other hand, does have configuration statement, allowing select between different models same component. Therefore only VHDL library been created Xilinx technologies. Whether pre-route descriptions VHDL Verilog, special attention must paid global signals code. Both VHDL Verilog UNISIM libraries have mechanisms handling GSR, PRLD, signals match pre-route post-route initializations. mechanisms adapted features that best suited each language. Verilog testbench used drive internal signals. Therefore, UNISIM library uses Verilog macros define global signals. variables drive GSR, PRLD, global signals used macros. After variables defined, macros activated reset configuration 3-state conditions enabled. VHDL contrast, requires port every signal stimulated testbench. Furthermore, also does have good mechanism handling global signals that VITAL compliant. Therefore following five unique cells have been developed support VHDL synthesis simulation design flow:
Verilog Simulations
ROC: Emulates chip-generated reset configuration pulse. ROCBUF: Allows testbench drive chip-generated reset configuration without implementing actual input chip. TOC: Emulates chip-generated 3-state configuration pulse. TOCBUF: Allows testbench drive chip-generated 3-state configuration without implementing actual input chip. STARTBUF: technology-independent version STARTUP block supported simulation. These five cells allow control over global reset 3-state signal emulation create pre-route initialization simulations match post-route simulations. cells also drive implementation tools delete pins, select which routed GSR, PRLD, net.
Summary
UNISIM libraries Verilog VHDL give flow with instantiations, imported schematics, postsynthesis functional simulations. libraries completely compatible with synthesisand LogiBlox-oriented flows will help match your pre-route global signal initializations with your post-route simulations.
INNOVATIVE APPLICAT
IONS
FPGA Control Reconfiguration
reconfiguration drivin XC5200 FPGA initiate XC4000 onfiguration sele operation although cess, input Low. This reliab PROGRA Low; reconfiguration tput from driving PROGRAM quence stops allel once triggered, will continue. configurations stored FPGA could have multiple example, ress lines. drives upper PROM code ected binary switch PROM, them against internal these codes input, compar switch, misFPGA could also figuration. When turn iquely determined switch that initiated, according reconfiguration match detected conditions met. delayed until additional reconfiguration could also tion setting. FPGA initiate reconfigura manually operated switch, Even without register used external CMOS latch configurasection parallel PROM selected PROM address throughout significant bit(s) maintain most like tion process. plications that would novel FPGA CPLD have .com. send them editor@xilinx share with other readers,
Xilinx shipping Foundation Series design solutions capable supporting both VHDL Verilog.
Foundation Series Software Delivers VHDL Verilog
Foundation Series software remains simple, continues deliver complete front-to-back development tools supporting Xilinx CPLD FPGA devices. There schematic packages packages. Both Foundation Series packages include VHDL Verilog, design entry, synthesis using Synopsys FPGA Express, implementation tools from Xilinx.
Xilinx offers comprehensive support services providing assistance Xilinx technologies well advanced application assistance.
Powerful Synthesis
This past year, Xilinx added Synopsys Express technology Foundation Series software. With Synopsys' history providing state-of-the-art synthesis solutions highdensity designs, it's surprising that Foundation Express product particularly effective large programmable logic devices. There many advanced synthesis features Foundation Express, including timing optimization, area optimization, graphical constraint entry analysis.
Increased Software Performance
rapidly increasing performance capabilities FPGA CPLD technologies demand increased performance from design solutions. fact, latest architecture from Xilinx delivers 1,000,000 gates speeds greater than 100MHz. meet that challenge, Foundation software solutions continually enhanced provide high-quality results ready-to-use package. software delivers push-button tools without compromising device complexity, functionality, density. Foundation tools have been specifically designed quickly move through learning curve; moment tools taken box, quickly install product implementing designs minutes. have exceptional needs,
Product Configurations
There four Foundation packages: Base, Standard, Base Express, Express. Base Standard packages support XABEL CPLDs support VHDL Verilog. Base Express Express support XABEL, VHDL, Verilog languages. Although there device size limits Base Base Express products, Spartan devices supported Foundation packages. Xilinx Foundation Series packages available today platforms running Windows Windows platforms. Visit Xilinx WebLINX site (www.xilinx.com) contact your local Xilinx representative more information request demonstration.
four Foundation Series packages
Alliance Foundation Series Software Configurations
Last year, released Alliance
Foundation Series software solutions. This innovative software gives best FPGA CPLD development tools industry, range configurations designed meet your needs platform. These configurations cover entire spectrum programmable logic from schematic-based CPLD designs HDL-based high-density FPGA designs using LogiCores. help choose best solution your needs, this article describes available software configurations.
ALLIANCE BASE Workstation ALLIANCE STANDARD Workstation DS-ALI-BAS-PC DS-ALI-BAS-WS DS-ALI-STD-PC DS-ALI-STD-WS
Foundation Series
Choose Foundation Series complete, ready-to-use development system that incorporates design entry, synthesis, simulation, FPGA/CPLD implementation tools into single, fully integrated design environment. Foundation Series also divided into Base (limited FPGA gate count) Standard versions, only available addition, there VHDL options Standard Base versions, system called Foundation Express which incorporates Synopsys FPGA Express technology.
Foundation Foundation Foundation Foundation Base Base w/Express Standard Express DS-FND-BAS-PC DS-FND-BSX-PC DS-FND-STD-PC DS-FND-EXP-PC
Alliance Series
Choose Alliance Series want integrate Xilinx software into your existing tools environment. With this series, choose from widest range design methods industry. This product line works both workstations, comes different versions. Alliance Base limited maximum 10,000 gate FPGAs Alliance Standard supports full range FPGAs. Both Base Standard versions include support CPLD devices, libraries interfaces, LogiBLOX module generator. addition, using Alliance Series Turns Engine, achieve clock performance improvements running unlimited number place-and-route runs multiple workstations.
LogicCORE Development Options
also offer Core solutions available options Alliance Foundation Series: target initiator, target only. site more information cores.
Target Initiator Target only DO-DI-PCIM DO-DI-PCIS
most recent pricing, availability, upgrade options, contact your local Xilinx sales representative.
System-Level Design Capabilities Using Active-CAD From Aldec
complementing Xilinx Foundation Series software with configuration Aldec's Active-CADproduct, system-level design capabilities. "Active-CAD Xilinx" promotion enables Foundation users design simulate multiple Xilinx devices along with CMOS, TTL, memory components; microprocessor simulation models also available additional licensing fee. Because Active-CAD uses same core technology Foundation Series, will immediately productive. environment supports both system-level design. Xilinx Foundation Series software delivers complete design solution Xilinx programmable logic devices. Foundation's standard Windows interface mixed mode (HDL Schematic) design environment ensures that effectively immediately design Xilinx programmable logic devices. While Foundation Series become solution choice many Xilinx customers, application Aldec's system-level design tools techniques employed further improve your overall design process.
previously spent weeks
debugging system-level design that contained multiple Xilinx FPGAs discrete logic devices. Since purchasing Active-CAD, have been able debug same design within days,"
"Aldec's contributions Foundation Series solution product's success. Their extension these technologies Active-CAD Xilinx promotion ensures highly integrated, easy-to-use, system-level design solution Xilinx designers" said Rich Sevcik, executive vice president software development Xilinx. system-level design techniques enabled many Xilinx customers accelerate their design cycle allowing simulation multiple Xilinx devices along with discrete logic components. previously spent weeks debugging system-level design that contained multiple Xilinx FPGAs discrete logic devices. Since purchasing Active-CAD, have been able debug same design within days," says Conemac, vice president hardware development Advanced Laser Technology. addition extending design entry simulation capabilities Xilinx Foundation Series solution, Aldec's ActiveCAD software offers proven integration into industry's most popular layout tools. This tight integration allows complete your programmable logic designs standard Pentium-class Active-CAD Xilinx promotion sold exclusively Aldec authorized worldwide distributors. Registered, in-warranty customers owning Xilinx Foundation Series product eligible take advantage this special offer. order Active-CAD, receive more information capabilities, contact Aldec, Inc. Three Sunset Way, Suite Henderson, 89015 Tel. 800-487-8743 x17, 702-456-1310, info@aldec.com
Industry's Highest Performance Solution FPGAs
achieve highest possible
performance your applications using latest LogiCOREPCI interface XC4000XLT FPGA family. XC4000XLT family includes XC4013XLT, XC4028XLT, XC4062XLT, optimized PCI. biggest device allows integrate interface plus 124K system gates application-specific logic. Some Xilinx customers have achieved Mbyte/ throughput. And, high-volume applications, migrate your design low-cost HardWire FpgASIC. LogiCORE Interface v2.0 supports fully-compliant zero-wait-state bursts, well-defined well-documented backend interface, allowing maximum sustained performance. addition, XC4000XLT family same SelectRAM feature rest XC4000 series. With SelectRAM memory build dual-port, synchronous asynchronous FIFO, sized support your application. have everything need quickly design complete system that supports highest possible bandwidth over bus. XC4000XLT family optimized devices include required upper clamp diodes inputs. This clamp diode mandatory 3.3-volt system ensure data integrity. These diodes connected eight separate pins, which connected volts 3.3-volt system volts 5-volt system. Table lists supported XC4000XLT device/package combinations number system gates that available your specific backend function. Using Xilinx core, quickly complete your design with flexible FPGA, debug verify compliance your board plugging into different vendors' PCs, then convert FPGA HardWire FpgASIC low-cost, high-volume production. During conversion process, Xilinx will review design ensure that HardWire FpgASIC fully compatible with FPGA automatically generate necessary test programs manufacturing. HardWire solution allows complete customized, onechip, interface with your unique backend design, price solution allows that lower than most standard chips currently available complete customized, market. one-chip, interface Xilinx intends provide with solutions that allow with your unique design highest performance backend design, highest density systems. When first LogiCORE price that lower than interface released 1995, most standard Xilinx first FPGA vendor support market. Today, chips.d Xilinx complete engineering applications team dedicated PCI, most robust core market, licensed almost customers. more information Xilinx solution other core products, please visit Xilinx site, WebLINX logicore.htm.
HardWire
Table Supported XC4000XLT devices available user-gates
Device 4013XLT 4028XLT 4062XLT P/HQ208 P/HQ240 BG432 Typical Gate Range available user design2 4,000 6,000 12,000 44,000 34,000 124,000
devices pin-compatible P/HQ240 values Typical Gate Range include 20-30% CLBs used RAM/FIFO
DESIGN HINTS ISSUES
Characteristics XC4000XL/XV Spartan Families
Peter Alfke
article describes electrical input output characteristics 3.3-volt device families. Input thresholds 5-volt tolerance described, output source sink impedances listed, effect additional capacitive loading delays, rise-times, fall-times explained.
Inputs
Input threshold stable over temperature, proportional Vcc: 37-38 percent falling threshold, 39-42 percent rising threshold. And, there 50-150 hysteresis, smallest high Vcc, largest cold Vcc. Many systems will still mixture older 5-volt devices newer 3.3-volt devices. This pose problem when 5-volt logic High drives 3.3-volt input. most CMOS ICs, each signal clamp diode protect circuit against electrostatic discharge (ESD). This diode starts conducting when driven more than 0.7-volt positive with respect Vcc. mixed-voltage systems, this diode presents problem, because might conduct tens milliamps whenever 5-volt logic High connected 3.3-volt input. XC4000XL/XV Spartan devices, Xilinx overcome this difficulty eliminating clamp diode between device pins Vcc. pins thus driven High volts, irrespective
actual supply voltage receiving input. These devices therefore unconditionally 5-volt tolerant; ignore interface precautions, need worry about power sequencing. Excellent protection several thousand volts) achieved means patented diode-transistor structure that connects ground, Vcc. structure behaves like Zener diode; becomes conductive greater than volts diverts charge current directly ground. handle current spikes several hundred milliamps, continuous current must kept below avoid reliability problems caused on-chip metal migration. more information, application note: XAPP080 "Supply-Voltage Migration,
PCI-Compliance
Xilinx structure designed compliant also 5-volt tolerant. compliance requires clamping diode Vcc. other hand, 5-volt tolerance does permit such diode. Therefore, n-well
Excellent
protection several thousand volts) achieved means patented diode-transistor structure that connects ground, Vcc.d
p-channel output transistor must tied 3.3-volt because parasitic diode would prevent from going substantially more positive than volts. satisfy these conflicting requirements, internal diode added each output, with cathode connected internal rail. PCI-compliant XC4000XLT devices, rail internally connected eight device pins which externally must connected appropriate supply (5-volt 3.3-volt). other devices, rail internally left unconnected, thus assuring 5-volt tolerance.
Effect Additional Capacitive Loading Transition Times Delays
Transition Time: specified external load, rise time fall time additional capacitive loads, ps/pF rise time, ps/pF fall time. Delay: ps/pF rising-edge delay volts, ps/pF volts. ps/pF falling-edge delay supply voltage. These values were derived from measurements using fast output option, slew-rate limited output option behaves almost identically.
Output Source Sink Capability:
strength pull-down transistor (sink capability) pull-up transistor (source capability) shown below. Close either rail, outputs resistive, which means voltage proportional current. table below shows condensed IBIS information expressed output resistance ohms, sink voltage less than volt above ground, source voltage less than volt below Vcc. IBIS gives minimum maximum current values, converted here resistor values. This data based SPICE simulation.
These results consistent with IBISderived output impedance, because delay increases with approximately time constant, rise fall times increase with approximately time constants. These guaranteed tested parameters; they were established sampling devices. Therefore, suggest that percent guardband (multiply 1.2) when calculating additional delay capacitive loading above guaranteed test limit same reason, subtract percent (multiply 0.8) when calculating reduced delay capacitive load that less than external. Sink Resistance Source Resistance When comparing Xilinx numto bers those from competitors Device Family (ohms) (ohms) standard load, reduce Xilinx-specified XC4000E 22.1 27.7 53.3 60.5 delay rise time XC4000EX 14.4 18.8 48.1 58.7 fall time XC4000XL/XV 14.4 20.5 28.0 41.0 thus changing both SpartanXL external lumped capacitive load rising-edge delay increases ps/pF over guaranteed data sheet value. rising-edge transition time increases consistent with IBISby ps/pF 10.8 over 50-pF transition time rise time derived output impedance.d thus 13.2
These results
Using XC9500 JTAG Manufacturing
XC9500 CPLD family includes
unique combination JTAG test capability in-system programmability (ISP) that save considerable time money during manufacturing process. Because JTAG functions both controlled through same industry-standard, four-wire JTAG port, automatic test equipment (ATE) perform system test, device test, device programming integrated operation. And, Xilinx supplies tools that make this easy. large number Xilinx customers have successfully integrated XC9500 capability into their manufacturing flows, choosing simply integrate JTAGProgrammer (formerly known EZTag) into their final test process program their XC9500 devices. Because Xilinx devices shipped from factory erased state, "skip erase before programming" option used reduce programming time, maximize product flow through process, reduce costs. Other Xilinx customers have determined that more economical integrate programming step directly into their manufacturing tests. This effectively uses their programming hardware. This method, while conceptually more complicated, make better available hardware resources. also reduce total number steps manufacturprocess, thereby streamlinis only optimizing operations, eliminating fallout CPLD manufacturer increased handling. providing this high level Xilinx supplies free tools facilitate this JTAG integration (available from site, WebLINX, functionality.d www.xilinx.com). These tools retarget standard serial vector format (SVF) Boundary-Scan stimulus description language native stimulus input formats industry's most popular ATEs. Full support available Hewlett Packard HP3070 series, GenRad GR228X series, Teradyne Z1800 series ATE. manufacturing environment, stray electrical noise result incorrect Boundary-Scan test failures. same manner, this noise contribute operation failures. Therefore, XC9500 devices include optional Boundary-Scan HIGHZ instruction which forces device pins into 3-state condition. Xilinx XC9500 CPLDs only type that make this optional instruction available. this instruction make certain that XC9500 devices "quiet" Boundary-Scan neighbor during test operations. forcing XC9500 device outputs into 3-state condition, while other parts being tested programmed, minimize noise generated active system signals effectively "silence" board. Many test engineers have made this functionality improving their overall system test reliability. supporting optional Boundary-Scan IDCODE USERCODE instructions, XC9500 devices fully identifiable their type programmed contents that selectively tests based composition system under test, based contents those devices. Finally, gross functional test 4-pin Boundary-Scan interface supported optional INTEST instruction. This allows application functional test stimuli using low-pin-count testers other BoundaryScan-based tools. Xilinx only CPLD manufacturer providing this high level JTAG functionality, thus continuing make major advancements practical application manufacturing environment.
Xilinx
Designing With XC9500 CPLD Family User-Programmable Grounds
C9500 CPLDs have unique feature that helps create rock-solid designs. UserProgrammable Grounds (UPGs) very easy provide additional noise immunity have very large numbers simultaneously switching outputs (SSOs). UPGs also deliver correct (non-floating) CMOS voltage level floating output pin. This done with special programming cell that connects output external ground internally forces output driver low, while retaining macrocell logic capability behind pin, illustrated Figure
takes approximately three UPGs deliver same grounding capability dedicated ground pin. have large numbers unloaded SSOs total well over acceptable) less than loaded SSOs, UPGs needed.
Software Support
Using Design Manager Xilinx Alliance Series Foundation Series software, easily specify that unconnected output pins must become connected UPG. unsure about what connected these unused pins, best avoid this setting, because could accidentally ground attached external signals. However, have completed your design wish tie-off unused macrocell outputs introduce extra grounding benefit, "UPG ON." reset future needed, taking advantage XC9500 family's in-system programability. general, UPGs convenient terminating unused output signals. rare occasion where additional grounding beneficial, UPGs become even more valuable asset.
Using UPGs
When macrocell outputs change state, they produce current transitions nanoseconds, causing internal device ground voltage rise. have very large number SSOs, this ground rise could possibly cause unwanted state transitions. providing additional grounds, near SSOs, this unwanted ground rise kept well within safe limits providing impedance path dissipate voltage spikes. have more than SSOs, with load capacitance more, UPGs very useful, giving extra noise margin.
Figure XC9500 devices
Peter Alfke
200-MHz Pulse Generator
sing XC4000E XC4000XL devices, reliably clock manipulate data MHz, over full voltage temperature range. design example shown Figure frequency commercially available 100-to-200 Voltage Controlled Oscillator (VCO) divided selected power from 223, generating output frequency that covers range from MHz. output frequency potentiometeradjusted over 2-to-1 range, switchselected over octaves. frequency
Figure pulse generator with frequency ranges.
scaler uses seven CLBs, switch encoder uses CLBs. Thus, design, including switch encoder, uses total CLBs mere smallest XC4000E family device. output clocks CLB. This placed directly adjacent oscillator input output drivers, thus minimizing speed-critical part design.
additional CLBs complete 3-bit ripple counter output signal multiplexer; because this instrument with single output, there reason design these very fast stages synchronous counters. However, remaining binary divider stages implemented synchronous RAM-based state machine, using CLBs counter, adder, 16-bit dual-port RAM. through address synchronous RAM, which effectively acts adjustablelength shift register. Four control inputs determine cycle length address counters create 16-bit shift register. shift register output feeds back input through serial adder, thus implementing serial incrementer counter, which bits long. When read port addresses location zero continuously, sees level change every period variable-length address counter. re-synchronized read output thus divides clock rate determined period Q3-Q6 counter. When counter divides output frequency further reduced advancing read address. Each address increment reduces output frequency factor two. constant read address ones creates lowest output frequency, which equals clock frequency divided frequency divided duty cycle output frequency thus adjusted value from This example shows that FPGAs used clock rates that above limitations conventional synchronous state machine designs. FPGAs continue migrate faster processes, these limits will pushed even farther, there will always opportunity achieve seemingly impossible, through creative understanding device architecture capabilities.
Innovative Reduce Electromagnetic Interference
nwanted (electromagnetic interference) difficult expensive control. Usually, designers simply shield their systems order comply with regulations. However there another, less expensive alternative. Most digital systems clocked stable, duty cycle, crystal-controlled frequency. This simplifies design, debugging, timing margin analysis, also generates high level clock frequency, third harmonic, fifth harmonic. frequency-modulating clock, spread radiated energy over wider
Peter Alfke
band thus reduce energy specific frequency. Spreading clock frequency just ±2.5% (between MHz) reduces amplitude fundamental frequency third harmonic 11.2 fifth harmonic 13.0 would take expensive shielding achieve similar reduction. Many display systems telecom devices cannot tolerate frequency-modulated clock, where applicable, spread-spectrum clock offer inexpensive solution difficult problem.
International Microcircuits offers number low-cost crystal-controlled EMIreducing oscillators. Visit their site (www.imicorp.com) more information.
Using Decoupling Capacitors 3.3-V Systems
power supply decoupling structure
like tree, starting supply ending individual pin. each level, should allow voltage drop (delta more than General Formula: delta following example shows calculate capacitor values typical application. These calculations ignore series inductance each capacitor, make assumptions about power frequency that every application. There decupling capacitor every pin. current reasonable assumption, this current might come 1-Amp spike with duty cycle perhaps MHz: 0.15 This capacitor also must support charging load capacitors. Let's assume eight pins with each total: 0.04 This means that decoupling capacitor marginal supplying internal dynamic current ns), easily supply eight full-swing outputs. There larger capacitor, device, that evens slower current changes. This capacitor might supply Amps microsecond: output switching supply capacitor that supplies Amps whole board, covers period switching supply: 10µs 15,000 decoupling important, becomes more critical chips bigger, clock frequencies supply current increase, supply voltage decreases.
Peter Alfke
Dangers Plug-In
Plugging board device into powVcc net. SRAM-based FPGAs power-up sufficiently close volts start configuration process master mode, still only powered logic signals. result, configuration will usually aborted before finished. These uncontrolled activities uncontrolled electrical overstresses desirable. When signals make contact before ground connected, similar problem occurs. signal output powered-up board acts surrogate ground plug-in device, with current coming through ESD-protection diode from unpowered device. ESD-protection diodes seem main cause plug-in problems, these diodes absolutely necessary protect CMOS inputs against high voltages. Gate oxides thick, volts across gate oxide means field strength 1,000 volts micron megavolt millimeter. Even best silicon dioxide reaches limits under these conditions. Modern CMOS devices usually have strong diodes each input pin, connected ground, connected Vcc, send excessive input charge into supply rails. Xilinx XC4000XL devices have diode Vcc, rather positive discharge structure ground. This eliminates some hotplug-in problems, makes these devices immune power-supply sequencing, which related easier problem.
ered-up system dangerous because pins make contact unpredictable sequence. There many milliseconds from making first contact last one, it's what occurs between that causes problem. best cases, ground mate first before signal ramping pins make contact. There connectors digital system complicated that enforce such mating sequence; their enough. haphazard ground pins plug-in procedure much longer, they always mate first. These worse. should avoid kinds sockets popular telecom plug-in unless equipment applications where plug-in standard specially designed.d practice. With such specialized connectors, there electrical hazards, need only concerned about unpredictable sequence logic connections being made. example, what happens data when drivers connected, perhaps before control signals valid? Without specialized connector, permanent electrical damage possible. Consider case where ground signal pins make contact first, these signals driven High 5-volt CMOS driver with output impedance. Until pins make contact, this High signal will forward-bias electrostatic discharge (ESD) protection diode drive not-as-yet-connected distribution network marginally High level. logic signal acts surrogate supply, none signal traces circuit elements strong enough that job. current value depends number nature devices from unpowered
normal
Summary
normal ramping-up digital system complicated enough, with different devices coming "alive" different voltage levels. haphazard plug-in procedure much worse. should avoid plug-in unless equipment specially designed.
XC4000XL Power Calculation
Almost power consumption Xilinx
FPGAs dynamic, result charging discharging internal external capacitance. small exception static power used internal housekeeping operations, leakage current, driving external resistive loads. total dynamic power XC4000XL devices three major ingredients: Clock distribution power. Output power. Power used internal logic driving interconnections. balance between these depends design implementation, often three ingredients have roughly equal magnitude. clock). reasonable estimate that square root total power consumed global clock thus: example, clock driving flip-flops XC4036XL consumes: 2400
Output Power Charging Capacitive Loads
following estimates assume internal capacitance. output driving external load: mW/MHz million transitions second output driving load: mW/MHz million transitions second.
Note: Clock frequency misleading measure logic activity; counting transitions avoids this ambiguity.
Global Clock Distribution Power
XC4000 Series devices clock distribution network that achieves short clock delay, negligible clock skew, lowest possible power consumption. Each global clock signal routed center chip then drives horizontal "backbone." Each column CLBs several vertical clock distribution "Longlines," each serving upper lower half column. These Longlines only driven when flip-flop placement requires flip-flop clock inputs only connected clock line when needed. Clock power thus minimized. total power each global clock input three ingredients: power drive backbone. discretionary power drive each vertical half-Longline. power clock each individual flip-flop. device-size dependent, while constant. Table lists values expressed µW/MHz, with nominal power supply. power consumption varies with square supply voltage, almost independent temperature device speed grade. calculate total clock power, must know (the number flip-flops driven clock) must estimate (the number vertical half-length Longlines used distribut-
Logic Interconnect Power
internal flip-flop driving nothing neighboring CLB: 0.08 million transitions second. internal flip-flop driving nine loads (very high fan-out): 0.16 million transitions second.
Conclusion
This information allows Table estimate device Clock Power Consumption µW/MHz power consumption. Backper fundamental difficulty Device bone Vertical Flip-Flop finding toggle frequency XC4005XL XC4010XL internal nodes, which XC4013XL requires know XC4020XL statistical behavior XC4028XL system inputs chip, XC4036XL XC4044XL just clock rate. Some XC4052XL estimates assume that 12.5% XC4062XL internal flip-flops XC4085XL toggle clock rate. However, this gross oversimplification, based behavior 16-bit counters. real designs, average activity significantly lower higher than 12.5%.
COMPONENT AVAILABILITY CHART
XC3020A XC3030A XC3042A XC3064A XC3090A XC3020L XC3030L XC3042L XC3064L XC3090L XC3142L XC3190L XC3120A XC3130A XC3142A XC3164A XC3190A XC3195A XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL
CODE
TYPE
PINS
PLASTIC PLASTIC PLASTIC VQFP CERAMIC PLASTIC VQFP PLASTIC CERAMIC PLASTIC CERAMIC CERAMIC PLASTIC PQFP PLASTIC TQFP PLASTIC VQFP BRZ. CQFP CERAMIC PLASTIC CERAMIC PLASTIC TQFP CERAMIC HI-PERF TQFP CERAMIC HI-PERF PLASTIC PQFP BRZ. CQFP PLASTIC CERAMIC PLASTIC TQFP HI-PERF TQFP CERAMIC BRZ. CQFP PLASTIC PQFP HI-PERF CERAMIC PLASTIC BRZ. CQFP PLASTIC PQFP HI-PERF PLASTIC CERAMIC HI-PERF. PLASTIC CERAMIC PLASTIC CERAMIC CERAMIC PLASTIC
PC44 PQ44 VQ44 WC44 VQ64 PC68 WC68 PC84 WC84 PG84 PQ100 TQ100 VQ100 CB100 PG120 PP132 PG132 TQ144 PG144 HT144 PG156 HQ160 PQ160 CB164 PP175 PG175 TQ176 HT176 PG191 CB196 PQ208 HQ208 PG223 BG225 CB228 PQ240 HQ240 BG256 PG299 HQ304 BG352 PG411 BG432 PG475 PG559 BG560
xxxxxxxxxxxxxxxxxxxxxxx xxxxx
xxxxx
xxxx
xxxxx
xxxx
xxxx
JANUARY 1998
XC4052XL XC4062XL XC4085XL XC40125XV XC4005L XC4010L XC4013L XC5202 XC5204 XC5206 XC5210 XC5215 XC6216 XC6236XL XC6264 XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 XCS05 XCS10 XCS20 XCS30 XCS40
CODE
TYPE
PINS
PLASTIC PLASTIC PLASTIC VQFP CERAMIC PLASTIC VQFP PLASTIC CERAMIC PLASTIC CERAMIC CERAMIC PLASTIC PQFP PLASTIC TQFP PLASTIC VQFP BRZ. CQFP CERAMIC PLASTIC CERAMIC PLASTIC TQFP CERAMIC HI-PERF TQFP CERAMIC HI-PERF PLASTIC PQFP BRZ. CQFP PLASTIC CERAMIC PLASTIC TQFP HI-PERF TQFP CERAMIC BRZ. CQFP PLASTIC PQFP HI-PERF CERAMIC PLASTIC BRZ. CQFP PLASTIC PQFP HI-PERF PLASTIC CERAMIC HI-PERF. PLASTIC CERAMIC PLASTIC CERAMIC CERAMIC PLASTIC
PC44 PQ44 VQ44 WC44 VQ64 PC68 WC68 PC84 WC84 PG84 PQ100 TQ100 VQ100 CB100 PG120 PP132 PG132 TQ144 PG144 HT144 PG156 HQ160 PQ160 CB164 PP175 PG175 TQ176 HT176 PG191 CB196 PQ208 HQ208 PG223 BG225 CB228 PQ240 HQ240 BG256 PG299 HQ304 BG352 PG411 BG432 PG475 PG559 BG560
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yyyy
xxxx xxxx
xxxy
xxyx
Product currently shipping planned since last issue XCell
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