implement esigners Supercomputing Systems Switzerland) took novel

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implement esigners Supercomputing Systems Switzerland) took novel

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esigners Supercomputing Systems Switzerland) took novel approach designing GigaBooster parallel computer system combining multiple processing elements built from standard components with fast, lowlatency communication scheme implemented hardware. implement critical communicathe critical communications tions control logic, they chose world's leading control logic, they chose FPGA family world's leading FPGA family XC4000 Series. Based "alpha7," XC4000 Series.d prototype system designed electronics laboratory (the Swiss Federal Institute Technology), GigaBooster parallel computer containing seven
individual processing elements (PEs) single board. Each constructed from DECchip 21066 Alpha processor, Mbyte cache memory, Mbytes DRAM memory (256 Mbytes "root" PE), SCSI controller, special registers that control clock, reset, interrupts similar functions. Each accompanied banks FIFO buffers dedicated interprocessor communication connected common 72-bit bus. special registers FIFO buffers controlled central communications controller realized within three XC4013 FPGAs. Digital UNIX operating system, providing access over 3000 applications. communications protocol called Intelligent Communication developed provide fast communications communication control, enabling system take full advantage processing power each This protocol, implemented directly hardware using FPGAs, allows fast, low-latency data exchange among processors, programming model with simple efficient code. in-system programmable nature XC4013 FPGAs development this protocol; during development, various approaches were tested compared simply reconfiguring FPGA devices. original alpha7 system design, communications controller squeezed into just XC4013 devices.
Supercomputing Processors
GigaBooster system, controller redesigned into three XC4013 FPGAs allow room expansion. FPGA holds several small state machines, abundance control registers, other glue interface logic; this design uses about half available logic blocks, pins. other FPGAs implement logic directly involved gathering redistribution data from processing elements, including 42-bit counter large register/comparator file each first these FPGAs more than utilized, connects five processing elements. About second FPGA contains identical logic remaining PEs. Additional logic dedicated monitoring communications behavior applications running system, remainder this FPGA used support module slot additional processing element interface optical high-speed network. XC4000 architecture's built-in carry logic critical attaining acceptable performance from large counters comparators this implementation. design runs MHz. FPGA designs were developed workstation using Viewlogic's Powerview tools XACT® development system. This combination "forms very comfortable development environment," according Hansruedi Vonder design engineer Swiss Federal Institute Technology responsible original design communications controller. Some floorplanning required, both functional timing simulation were used debug verify system operation. FPGA's readback capability also exploited during system debug, used "dump" state
communications controller event communication failure. Using readback, values internal counters, registers, state machines extracted analyzed. summary, reconfigurable XC4013 FPGAs implementation interprocessor communication protocols directly hardware, opposed more-traditional software approaches. resulting high-performance communications management allows system full processing power each Alpha processors, delivering Gigaflops peak performance affordable compact system.
reconfigurable XC4013 FPGAs
implementation interprocessor communication protocols direclty hardware.d

implement esigners Supercomputing Systems Switzerland) took novel

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