XAPP079 September, 1997 (Version 1.2) Summary This application no

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4Mbit Virtual SPROM
XAPP079 September, 1997 (Version 1.2) Summary
This application note describes design very cost, CPLD-based virtual SPROM downloading programming information Xilinx high density XC4000-Series FPGAs. Xilinx Family XC9500
Introduction
Typically, designers embedded applications serial PROMs (SPROMs) store download configuration data XC4000-Series FPGAs. SPROMs yield faster configuration rates reduce amount circuitry required program FPGAs. FPGA densities continue grow, their configuration memory requirements; SPROM program memory requirements high density XC4000-Series FPGA 512K bits more. virtual serial PROM (VSPROM) solution described this application note uses cost XC9536 CPLD, standard byte-wide EPROM, on-board crystal oscillator support embedded programming high density XC4000Series FPGAs.
EPROM. Data registers data7 through data0 internal nodes used latch shift incoming configuration data from EPROM. data registers broken into busses four bits each: busA busB. State SHIFT_A shifts busA while loading EPROM data into busB. State SHIFT_B shifts busB while loading EPROM data into busA. This provides continual stream data into FPGA with interruption CCLK. state machine enters LASTCLKS state rising edge DONE provide last CCLKs FPGA. This required bring FPGA configuration enable I/O. Finally, state machine enters DONE state complete process. CCLK from XC9536 FPGA output-enabled ensure that FPGA doesn't receive stray clocks while VSPROM state machine DONE state. Since CCLK output goes into high impedance condition while DONE state, resistor tied ground ensure that CCLK always known state.
Design Description
Figure shows schematic circuitry used configure XC4025E FPGA using VSPROM design. XC4025E requires 422,128 configuration bits, which supplied 64Kx8 (512K bits) EPROM. XC9536-15PC44 CPLD, used read data from EPROM download FPGA. on-board crystal oscillator clocks VSPROM design supplies configuration clocks (CCLKs) FPGA. FPGA connected SLAVE SERIAL MODE (see Xilinx Data Book information XC4000-Series configuration modes). this reference design as-is, modify design required. XC9536 acts intelligent state machine monitoring FPGA's INIT DONE pins while pumping serial configuration data into FPGA's pin. Figure shows state diagram. configuration process started falling edge FPGA INIT pin. Data continually read shifted into FPGA until rising edge DONE pin. INIT goes during configuration, XC9536 will pulse FPGA's /PROGRAM low, reset state machine, consequently restart configuration process. Figure shows ABEL code describing VSPROM design. Bits through data interface pins
Design Implementation
This VSPROM design fully verified with both functional timing vectors. Figure shows timing simulation waveforms created with Viewlogic's ViewSimTM. Configuration rates 10MHz were successfully simulated. XC9536 CPLD programmed with Xilinx HW-130 V4.0 programmer, EPROM programmed with generic EPROM programmer. XC9536 IEEE 1149.1 compliant CPLD, therefore could programmed in-system JTAG port, TDI, TCK, TMS, TDO. verify design, XACTstep used implement simple Johnson Counter XC4025E FPGA. design placed routed using default settings. PROM File Formatter utility XACTstep produced byte wide 64Kx8 (512K bits) EPROM file using default settings starting address loading direction. design assembled generic prototyping board configuration rates were verified. XC4025E FPGA used this application note requires 422,128 program bits. Therefore, only address lines through were
XAPP079 September, 1997 (Version 1.2)
4Mbit Virtual SPROM
required. total address lines (4Mbits addressable space) available different configurations. Table shows EPROM address line requirements each XC4000-Series device that requres more than 256Kbits SPROM memory (see Xilinx Data Book, June 1997 more information). Xilinx PROM File Formatter XACTstep determine approximate EPROM size daisy chains. required, connect additional address lines. Finally, XC9536 used
mixed voltage systems 5v/3.3v) connecting it's Vccio appropriate voltage source. XC9500 Data Sheets more information.
Conclusion
This Virtual SPROM application note provides ultra cost solution support embedded programming high density XC4000-Series FPGAs.
!INIT
DONE
INIT !DONEPIN !INIT Counter !INIT
SHIFT_A
Counter
SHIFT_B
DONEPIN DONEPIN
Counter
LASTCLKS
Figure State Diagram
FPGA Target Device XC4010EX/XL XC4013EX/XL XC4020E XC4020EX/XL XC4025E XC4028EX/XL XC4036EX/XL XC4044EX/XL XC4052EX/XL XC4062EX/XL XC4085EX/XL
Req. Program Bits 283,376 393,580 329,264 521,832 422,128 668,132 832,480 1,014,876 1,215,320 1,433,812 1,924,940
Req. EPROM Bits 283,424 393,632 329,312 521,880 422,176 668,184 832,528 1,014,928 1,215,368 1,433,864 1,924,992
CPLD Requirements XC9536 (using design shown) XC9536 (using design shown) XC9536 (using design shown) XC9536 (connect address lines thru standard EPROM) XC9536 (using design shown) XC9536 (connect address lines thru standard EPROM) XC9536 (connect address lines thru standard EPROM) XC9536 (connect address lines thru standard EPROM) XC9536 (connect address lines thru standard EPROM) XC9536 (connect address lines thru standard EPROM) XC9536 (connect address lines thru standard EPROM)
Table EPROM CPLD Requirements XAPP079 September, 1997 (Version 1.2)
ADR[0.15]
ADR10
ADR13 ADR12 ADR11
ADR15 ADR14
CRYSTAL
VCCINT
Figure VSPROM Schematic
ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR0 ADR1 CCLK /PROGRAM
XAPP079 September, 1997 (Version 1.2)
DOUT
VCCINT
VCCIO
5.1K XC9536
ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR13 ADR14 ADR15 27512 UV-EPROM
ADR9
D[0.7]
5.1K
5.1K
XC4025E DONE /INIT DONE /INIT
/PROGRAM CCLK
5.1K
5.1K
5.1K
MODE PINS
XC4025.SCH
4Mbit Virtual SPROM
MODULE VSPROM TITLE Virtual 4Mbit SPROM configure XC4K FPGAs. VERSION: DATE: 9/97' "inputs init, donepin, d7.d0 "outputs adr18.adr0, program cclk dout "nodes data7.data0, count1, count0, node istype `reg'; outen, reset node istype `com, keep'; declarations counter [count1.count0]; address [adr18.adr0]; busA [data3.data0]; busB [data7.data4]; [d3.d0]; [d7.d4]; inAB [d7.d0]; XEPLD PROPERTY `LOGIC_OPT outen, reset'; XEPLD PROPERTY `PWR program'; .Z., .C., .X.; @DCSET; "State values DONE =^b00; SHIFT_A =^b11; SHIFT_B =^b10; LASTCLKS =^b01; VSPROM [s1.s0]; equations VSPROM.clk clk; address.clk clk; counter.clk clk; busA.clk clk; busB.clk clk; program.clk clk; program.ar !init cclk !clk; cclk.oe outen; counter !reset (counter when reset then address else when ((VSPROM SHIFT_A) (counter !reset) then address address else address address; when (VSPROM DONE) then reset else when (((VSPROM SHIFT_A) (VSPROM SHIFT_B)) donepin) then reset else reset when (VSPROM DONE) then {outen busA inA; busB inB; program dout data0;} istype `reg'; 24,25,28; 26,27,40,5,14,13,7,42;
Figure ABEL Code VSPROM
XAPP079 September, 1997 (Version 1.2)
when (VSPROM SHIFT_A) then {outen program busB inB; data0 data1; data1 data2; data2 data3; dout data0;} else when (VSPROM SHIFT_B) then {outen program busA inA; data4 data5; data5 data6; data6 data7; dout data4;} else when ((VSPROM SHIFT_A) (counter then dout data0; else when ((VSPROM SHIFT_B) (counter then dout data4; else when (VSPROM LASTCLKS) then {program outen
state_diagram VSPROM; state DONE: (!init) then DONE; else (!donepin) then SHIFT_A; else DONE; state SHIFT_A: (!init) then DONE; else (donepin) then LASTCLKS; else ((VSPROM SHIFT_A) (counter then SHIFT_B; else SHIFT_A; state SHIFT_B: (!init) then DONE; else (donepin) then LASTCLKS; else ((VSPROM SHIFT_B) (counter then SHIFT_A; else SHIFT_B; state LASTCLKS: ((VSPROM LASTCLKS) (counter then DONE; else LASTCLKS; end;
Figure Continued
XAPP079 September, 1997 (Version 1.2)
4Mbit Virtual SPROM
DONEPIN
INIT
DATAIN
FF\H
VSPROM
CCLK
DOUT
ADDRESS
XXXX\H
0000
0001
0002
0003
0000
0001
0002
0003
0000
OUTEN
PROGRAM
T(DONEPIN)
Time (Seconds)
Figure Simulation Waveforms
XAPP079 September, 1997 (Version 1.2)

XAPP079 September, 1997 (Version 1.2) Summary This application no

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