XC4000XV Family Field Programmable Gate Arrays 1998 (Version 1.1)
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XC4000XV Family Field Programmable Gate Arrays
1998 (Version 1.1)
Advance Product Specification Backward Compatible with XC4000 Devices Development System runs most common computer platforms Interfaces popular design environments Fully automatic mapping, placement routing Interactive design editor design optimization
XC4000XV FPGAs
Note: This data sheet describes XC4000XV devices. This information does necessarily apply other Xilinx families: XC4000, XC4000A, XC4000D, XC4000H, XC4000L, XC4000E, XC4000EX, XC4000XL. information these devices, Xilinx WEBLINX http:// www.xilinx.com. System featured Field-Programmable Gate Arrays Select-RAMmemory: on-chip ultra-fast with synchronous write option dual-port option Abundant flip-flops Flexible function generators Dedicated high-speed carry logic Hierarchy interconnect lines Internal 3-state capability global low-skew clock signal distribution networks Flexible Array Architecture Power Segmented Routing Architecture Systems-Oriented Features IEEE 1149.1-compatible boundary scan Individually programmable output slew rate Programmable input pull-up pull-down resistors Configured Loading Binary File Unlimited reprogrammability Readback Capability Program verification Internal node observability
XC4000XV Electrical Features
Low-Voltage Device Functions Volts compatible LVTTL, LVCMOS compatible 12-mA, 24-mA current sink capability lower power than XC4000XL Devices
Additional XC4000XV Features
Advanced Technology 0.25 SRAM CMOS process Proven Architecture Industry standard XC4000X architecture Highest Performance Internal performance beyond 100MHz Lowest Power technology plus segmented routing architecture Easy Interfaces combination TTL-compatible devices Software Compatibility Supported Alliance/ Foundation Series Software M1.4 Package Compatibility Footprint compatible with XC4000XL devices (except power pins)
Table XC4000XV Field Programmable Gate Array Logic Cells 10,982 12,312 16,758 20,102 Max. Logic Max.RAM Typical Gates Bits Gate Range RAM) Logic) (Logic RAM)* 125,000 147,968 80,000 250,000 150,000 165,888 100,000 300,000 200,000 225,792 130,000 400,000 250,000 270,848 180,000 500,000 Matrix Number Total Max. CLBs Flip-Flops User 4,624 10,336 5,184 11,520 7,056 15,456 8,464 18,400 PROM Size 2,797,040 3,373,448 4,551,056 5,433,888
Device XC40125XV XC40150XV XC40200XV XC40250XV
values Typical Gate Range include 20-30% CLBs used RAM*
1998 (Version 1.1)
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XC4000XV Family Field Programmable Gate Arrays
Introduction
XC4000 Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide benefits custom CMOS VLSI, while avoiding initial cost, long development cycle, inherent risk conventional masked gate array. result thirteen years FPGA design experience feedback from thousands customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered dual-port modes, increased speed, abundant routing resources, new, sophisticated software achieve fully automated implementation complex, high-density, high-performance designs.
Differences between XC4000XV XC4000XL FPGAs
VCCINT (2.5 Volt) Power Supply Pins XC4000XV FPGAs logically identical XC4000EX XC4000XL FPGAs. functionality identical XC4000XL FPGAs. only difference between separate lower core voltage 2.5V which named VCCINT. pins assigned VCCINT supply named pinout guide XC40125XV FPGA Lower Power XC4000XV devices require less power than equivalent devices Increased Drive XC4000XV outputs optionally sink 24-mA each. Increased Routing XC40150XV, XC40200XV, XC40250XV have enhanced routing. Eight routing channels octal length have been added each CLBs.
Power Power Power
Volt Device LVTTL
VCCIO VCCINT XC4000XV LVTTL
(3.3 Volt Device
Ground
X7147
VOUT_max LVTTL LVCMOS
VCCIO
VCCIO
VCCIO
VCCIO
Figure Power supply signaling environment
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XC4000XV Switching Characteristics
Definition Terms
following tables, some specifications designated Advance Preliminary. These terms defined follows: Advance: Initial estimates based simulation and/or extrapolation from other speed grades, devices, families. Values subject change. estimates, production.
Preliminary: Based preliminary characterization. Further changes expected. Unmarked: Specifications identified either Advance Preliminary considered Final.
specifications subject change without notice.
Additional Specifications
Except pin-to-pin input output parameters, a.c. parameter delay specifications included this document derived from measuring internal test patterns.All specifications representative worst- case supply voltage junction temperature conditions. parameters included common popular designs typical applications. design considerations requiring more detailed timing information, appropriate family a.c. supplements available Xilinx WEBLINX http://www.xilinx.com.
Absolute Maximum Ratings
Symbol VCCINT VCCIO TSTG TSOL Supply voltage relative Supply voltage relative Input voltage relative (Note Voltage applied 3-state output (Note Longest Supply Voltage Rise Time from Storage temperature (ambient) Maximum soldering temperature 1/16 Junction temperature Ceramic packages Plastic packages Description -0.5 -0.5 -0.5 -0.5 +150 +260 +150 +125 Units
Notes: Maximum overshoot undershoot above below must limited either whichever easier achieve. During transitions, device pins undershoot -2.0 overshoot provided this over- undershoot lasts less than with forcing current being limited Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those listed under Operating Conditions implied. Exposure Absolute Maximum Ratings conditions extended periods time affect device reliability.
1998 (Version 1.1)
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Recommended Operating Conditions
Symbol VCCINT Description Supply voltage relative GND, +85°C Supply voltage relative GND, -40°C +100°C Supply voltage relative GND, +85°C VCCIO Supply voltage relative GND, -40°C +100°C High-level input voltage Low-level input voltage Input signal transition time Commercial Industrial Commercial Industrial Units
Notes: junction temperatures above those listed Operating Conditions, delay parameters increase 0.35% Input output measurement threshold ~50% VCC.
Characteristics Over Recommended Operating Conditions
Symbol Description High-level output voltage -4.0 (LVTTL) High-level output voltage -500 (LVCMOS) Low-level output voltage 12.0 (LVTTL) (Note Low-level output voltage 1500 (LVCMOS) VDRINT VDRIO ICCO IRPU IRPD IRLL
Note Note
Units
0.02 0.02 0.25 0.15
VCCINT Data Retention Supply Voltage (below which configuration data lost) VCCIO Data Retention Supply Voltage (below which configuration data lost) Quiescent FPGA supply current (Note Input output leakage current Input capacitance (sample tested) BGA, SBGA, packages packages pull-up (when selected) (sample tested) pull-down (when selected) (sample tested) Horizontal Longline pull-up (when selected) logic
With pins simultaneously sinking With output current loads, active input Longline pull-up resistors, pins Tri-stated floating.
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1998 (Version 1.1)
XC4000XV Global Buffer Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values where global clock input drives vertical clock line each accessible column, where accessible flip-flops clocked global clock net. When fewer vertical clock lines connected, clock distribution faster; when multiple clock lines column driven from same global clock, delay longer. more specific, more precise, worst-case guaranteed data, reflecting actual routing structure, values provided static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Speed Grade Description From through Global Skew buffer, clock From through Global Early buffer, clock BUFGEs From through Global Early buffer, clock BUFGEs Symbol TGLS TGE_1256 TGE_3478 Device XC40125XV XC40125XV XC40125XV Units
Advance
1998 (Version 1.1)
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XC4000XV Family Field Programmable Gate Arrays
XC4000XV Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Values expressed nanoseconds unless otherwise noted.
Description Combinatorial Delays inputs outputs inputs outputs inputs transparent latch outputs inputs SR/H0 outputs inputs outputs inputs DIN/H2 outputs inputs DIN/H2 output (bypass) Fast Carry Logic Operand inputs (F1, COUT Add/Subtract input (F3) COUT Initialization inputs (F1, COUT through function generators outputs COUT, bypass function generators Carry Delay, COUT Sequential Delays Clock Flip-Flop outputs Clock Latch outputs Setup Time before Clock inputs inputs inputs through inputs through inputs through inputs inputs inputs S/R, going (inactive) input input Hold Time after Clock inputs inputs inputs SR/H0 through inputs through inputs DIN/H2 through inputs DIN/H2 inputs inputs going (inactive) Clocks Clock High time Clock time Set/Reset Direct Width (High) Delay from inputs S/R, going High Global Set/Reset Speed Grade Symbol TILO TIHO TITO THH0O THH1O THH2O TCBYP TOPCY TASCY TINCY TSUM TBYP TNET TCKO TCKLO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR TRPW TRIO TMRW TMRQ FTOG 17.3 32.9 Advance 15.0 28.6 0.25 Units
Minimum Pulse Width Delay from input
Toggle Frequency (MHz) (for export control purposes)
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XC4000XV Synchronous (Edge-Triggered) Write Operation Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Values apply XC4000XV devices expressed nanoseconds unless otherwise noted.
Single Port
Write Operation Address write cycle time (clock period) Clock pulse width (active edge) Address setup time before clock Address hold time after clock setup time before clock hold time after clock setup time before clock hold time after clock Data valid after clock Read Operation Address read cycle time Data Valid after address change Write Enable) Address setup time before clock
Speed Grade Size Symbol
Units
16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1
TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS
16x2 32x1 16x2 32x1 16x2 32x1
TRCT TILO TIHO TICK TIHCK
Advance
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XC4000XV Family Field Programmable Gate Arrays
XC4000XV Synchronous (Edge-Triggered) Write Operation Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Values apply XC4000XV devices expressed nanoseconds unless otherwise noted.
Dual Port
Speed Grade Size Symbol
Units
Address write cycle time (clock period) Clock pulse width (active edge) Address setup time before clock Address hold time after clock setup time before clock hold time after clock setup time before clock hold time after clock Data valid after clock
Note: Timing option identical to16 RAM.
16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1
TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS
Advance
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XC4000XV Synchronous (Edge-Triggered) Write Timing
TWPS WCLK TWSS TDSS DATA TASS ADDRESS TILO TAHS TDHS TWHS
TILO
TWOS
DATA
X6461
XC4000XV Dual-Port Synchronous (Edge-Triggered) Write Timing
TWPDS WCLK TWSDS TDSDS DATA TASDS ADDRESS TILO TWODS DATA
X6474
TWHDS
TDHDS
TAHDS
TILO
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XC4000XV Family Field Programmable Gate Arrays
Pin-to-Pin Output Parameter Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Pin-to-pin timing parameters derived from measuring external internal test patterns guaranteed over worst-case operating conditions (supply voltage junction temperature). Listed below representative values typical locations normal clock loading. more specific, more precise, worst-case guaranteed data, reflecting actual routing structure, values provided static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report.
XC4000XV Output Flip-Flop, Clock
Speed Grade Description Global Skew Clock Output using Symbol TICKOF Device XC40125XV Units
Global Early Clock Output using BUFGEs TICKEOF_1256 XC40125XV Global Early Clock Output using BUFGEs TICKEOF_3478 XC40125XV output SLOW option Output Flip Flop TSLOW Devices
Advance
Notes: Listed above representative values where global clock input drives vertical clock line each accessible column, where accessible flip-flops clocked global clock net. Output timing measured ~50% threshold with external capacitive load.
Capacitive Load Factor
Delta Delay (ns)
Figure shows relationship between output delay load capacitance. allows user adjust specified output delay load capacitance different than example, actual load capacitance specified delay. load capacitance subtract from specified output delay. Figure usable over specified operating conditions voltage temperature independent output slew rate control.
Capacitance (pF)
X8257
Figure Delay Factor Various Capacitive Loads
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1998 (Version 1.1)
Pin-to-Pin Input Parameter Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Pin-to-pin timing parameters derived from measuring external internal test patterns guaranteed over worst-case operating conditions (supply voltage junction temperature). Listed below representative values typical locations normal clock loading. more specific, more precise, worst-case guaranteed data, reflecting actual routing structure, values provided static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report.
XC4000XV Global Skew Clock, Set-Up Hold
Speed Grade Units Description Symbol Device Input Setup Hold Times Using Global Skew Clock Delay TPSN/TPHN XC40125XV Partial Delay TPSP/TPHP XC40125XV 11.3 Full Delay TPSD/TPHD XC40125XV Input Flip-Flop Latch Advance
Notes: Setup time measured with fastest route lightest load. Hold time measured using furthest distance reference load clock IOBs. static timing analyzer (TRCE) determine setup hold times under given design conditions.
1998 (Version 1.1)
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XC4000XV Family Field Programmable Gate Arrays
XC4000XV BUFGE Global Early Clock, Set-Up Hold
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Pin-to-pin timing parameters derived from measuring external internal test patterns guaranteed over worst-case operating conditions (supply voltage junction temperature). Listed below representative values typical locations normal clock loading. more specific, more precise, worst-case guaranteed data, reflecting actual routing structure, values provided static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. Values expressed nanoseconds unless otherwise noted. Description Input Setup Hold Times Delay, Global Early Clock IFF, Global Early Clock Partial Delay, Global Early Clock IFF, Global Early Clock Full Delay, Global Early Clock
Input Flip-Flop Latch, Fast Capture Latch
Symbol
Speed Grade Device
12.7
11.0
Units
TPSEN/TPHEN XC40125XV TPFSEN/TPFHEN TPSEP/TPHEP XC40125XV TPFSEP/TPFHEP TPSED/TPHED XC40125XV
11.1 Advance
Notes: Setup time measured with fastest route lightest load. Hold time measured using furthest distance reference load clock IOBs. static timing analyzer(TRCE) determine setup hold times under given design conditions.
XC4000XV BUFGE Global Early Clock, Set-Up Hold
Description Input Setup Hold Times Delay,Global Early Clock IFF, Global Early Clock Partial Delay, Global Early Clock IFF, Global Early Clock Full Delay, Global Early Clock
Input Flip-Flop Latch, Fast Capture Latch
Symbol
Speed Grade Device
Units
TPSEN/TPHEN XC40125XV TPFSEN/TPFHEN TPSEP/TPHEP XC40125XV 14.5 12.6 TPFSEP/TPFHEP TPSED/TPHED XC40125XV 12.9 11.2 Advance
Notes: Setup time measured with fastest route lightest load. Hold time measured using furthest distance reference load clock IOBs. static timing analyzer(TRCE) determine setup hold times under given design conditions.
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XC4000XV Input Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Description Speed Grade Symbol TECIK TOKIK Units
Clocks Clock Enable (EC) Clock (IK) Delay from Fast Capture Latch enable (OK) active edge clock (IK) active edge Setup Times Clock (IK), delay Clock (IK), transparent Fast Capture Latch, delay Fast Capture Latch Enable (OK), delay Hold Times Hold Times Global Set/Reset Minimum Pulse Width Delay from input XC40125XV Propagation Delays transparent input latch, delay transparent input latch, delay Clock (IK) (flip-flop) Clock (IK) (latch enable, active Low) Enable (OK) active edge (via transparent standard input latch)
Input Flip-Flop Latch, Fast Capture Latch
TPICK TPICKF TPOCK
15.0 28.6 Advance
TMRW TRRI TPID TPLI TPFLI TIKRI TIKLI TOKLI
17.3 32.9
1998 (Version 1.1)
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XC4000XV Output Switching Characteristic Guidelines
Testing switching parameters modeled after testing methods specified MIL-M-38510/605. devices 100% functionally tested. Internal timing parameters derived from measuring internal test patterns. Listed below representative values. more specific, more precise, worst-case guaranteed data, values reported static timing analyzer (TRCE Xilinx Development System) back-annotated simulation netlist. These path delays, provided guideline, have been extracted from static timing analyzer report. timing parameters assume worst-case operating conditions (supply voltage junction temperature). Propagation Delays, slew-rate fast unless otherwise noted. Values expressed nanoseconds unless otherwise noted. Description Clocks Clock High Clock Propagation Delays (See Note Clock (OK) Output 3-state hi-Z (slew-rate independent) 3-state active valid Output Fast Output Select (OK) Fast Setup Hold Times Output clock (OK) setup time Output clock (OK) hold time Clock Enable (EC) clock (OK) setup time Clock Enable (EC) clock (OK) hold time Global Set/Reset Minimum pulse width Delay from input XC40125XV Slew Rate Adjustment output SLOW option TSLOW Advance TMRW TRPO 17.3 35.5 15.0 30.9 TOOK TOKO TECOK TOKEC TOKPOF TOPF TTSHZ TTSONF TOFPF TOKFPF Symbol Units
Note: Output timing measured ~50% threshold, with external capacitive loads.
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Locations XC40125XV Devices
XC40125XV Name
VCCIO (A8) (A9) (A19) (A18) (A10) (A11) VCCIO VCCIO VCCINT VCCIO (A12) (A13) VCCIO
BG432
VCCIO GND* VCCIO* GND* GND* VCCIO* GND* GND* VCCIO* GND* VCCIO*
BG56VCCIO* GND* VCCIO* GND* GND* VCCIO* GND* GND* VCCIO* GND* VCCIO*
PG559
VCCIO* GND* VCCIO* GND* GND* VCCIO* VCCINT* GND* GND* VCCIO* GND* VCCIO*
XC40125XV Name
(A14) I/O, GCK8 (A15) VCCIO I/O, GCK1 (A16) (A17) VCCINT (TDI) (TCK) VCCIO VCCIO VCCINT (TMS) VCCIO
BG432
GND* VCCIO* GND* GND* VCCIO* GND* VCCIO* GND* GND* VCCIO* GND*
BG56C29 GND* VCCIO* GND* GND* VCCIO* GND* VCCIO* GND* GND* VCCIO* GND*
PG559
GND* VCCIO* GND* VCCINT* GND* VCCIO* GND* VCCIO* GND* GND* VCCINT* VCCIO* GND*
1998 (Version 1.1)
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XC4000XV Family Field Programmable Gate Arrays
XC40125XV Name
VCCIO VCCINT VCCIO VCCIO VCCIO VCCINT
BG432
GND* VCCIO* GND* GND* VCCIO* GND* VCCIO* GND* GND* AA30 VCCIO* AA29 AB31 AB30 AB29 GND* AB28
BG56L33 GND* VCCIO* GND* GND* VCCIO* GND* VCCIO* GND* AA33 AA32 AA31 AA30 AB32 GND* AA29 AB31 AB30 AC33 VCCIO* AC31 AB29 AD32 AC30 GND* AD31
PG559
GND* VCCIO* GND* VCCINT* GND* VCCIO* GND* VCCIO* GND* GND* VCCIO* VCCINT* GND*
XC40125XV Name
VCCIO VCCIO VCCINT I/O, GCK2 (M1) (M0) VCCIO (M2) I/O, GCK3 (HDC) (LDC) VCCIO
BG432
AC30 AC29 AC28 GND* VCCIO* AD31 AD30 AD29 AD28 AE30 AE29 GND* VCCIO* AF31 AE28 AF30 AF29 AG31 AF28 GND* AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCCIO* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 GND* AK27 AJ26 AL27 AH25 AK26 AL26 VCCIO* GND* AH24 AJ25 AK25 AJ24 AH23 AK24
BG56AE33 AC29 AE32 AD30 AE31 AF32 AD29 GND* VCCIO* AF31 AE30 AG33 AH33 AE29 AG31 AF30 AH32 GND* VCCIO* AJ32 AF29 AH31 AG30 AK32 AJ31 GND* AG29 AL33 AH30 AK31 AJ30 AH29 AK30 GND* AJ29 VCCIO* AN32 AJ28 AK29 AL30 AK28 AM31 AJ27 GND* AN31 AL29 AK27 AL28 AJ26 AM30 VCCIO* GND* AM29 AK26 AL27 AJ25 AN29 AN28 AK25 AL26
PG559
GND* VCCIO* GND* VCCIO* GND* VCCINT* GND* VCCIO* GND* VCCIO* GND*
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1998 (Version 1.1)
XC40125XV Name
VCCIO VCCINT VCCIO VCCIO (INIT) VCCIO VCCINT
BG432
VCCIO* GND* AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCCIO* AH20 AK21 GND* AJ20 AH19 AK20 AJ19 AL20 AH18 GND* VCCIO* AK19 AJ18 AL19 AK18 AH17 AJ17 GND* AK17 AL17 AJ16 AK16 VCCIO* GND* AL16 AH15 AL15 AJ15 GND* AK15 AJ14 AH14 AK14 AL13 AK13
BG56VCCIO* GND* AJ24 AM27 AM26 AK24 AL25 AJ23 AN26 AL24 GND* AK23 AN25 AJ22 AL23 VCCIO* AM24 AK22 AM23 AJ21 GND* AL22 AN23 AK21 AM22 AJ20 AL21 AN21 AK20 GND* VCCIO* AL20 AJ19 AM20 AK19 AL19 AN19 GND* AJ18 AK18 AL18 AM18 AK17 AJ17 VCCIO* GND* AL17 AM17 AN17 AK16 AJ16 AL16 GND* AM16 AL15 AK15 AJ15 AN15 AM14
PG559
VCCIO* GND* GND* VCCINT* VCCIO* GND* GND* VCCIO* GND* AA43 AA37 AA39 VCCIO* GND* AA41 AB38 VCCINT* AB42 AB40 AC37 AC39 GND* AD36 AC41 AD38 AC43 AD40 AE39
XC40125XV Name
VCCIO VCCIO VCCINT VCCIO VCCIO VCCINT I/O, GCK4 DONE VCCIO PROGRAM (D7)
BG432
VCCIO* GND* AJ13 AH13 AL12 AK12 AJ12 AK11 GND* AH12 AJ11 VCCIO* AL10 AK10 AJ10 GND* AH10 VCCIO* GND* VCCIO* GND* GND* VCCIO*
BG56VCCIO* GND* AL14 AK14 AJ14 AN13 AM13 AL13 AK13 AJ13 GND* AM12 AL12 AK12 AN11 VCCIO* AJ12 AL11 AK11 AM10 GND* AL10 AJ11 AK10 AJ10 GND* VCCIO* GND* VCCIO* GND* GND* VCCIO*
PG559
VCCIO* GND* AE37 AF40 AD42 AF42 AF38 AG39 AG43 AG37 GND* AH40 AJ41 AG41 AK40 VCCIO* AJ39 AH42 VCCINT* AH36 AL39 GND* AJ37 AJ43 AM40 AK42 AN41 AL41 AR41 AK36 GND* VCCIO* AL37 AN43 AM38 AP42 AN39 AR43 AP40 AT40 GND* VCCIO* AN37 AR39 AT42 BA43 AU43 AU39 GND* AT38 AP36 AR37 AV42 VCCINT* AV40 AW41 GND* AY42 VCCIO* BB42 BC41
1998 (Version 1.1)
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XC4000XV Family Field Programmable Gate Arrays
XC40125XV Name
I/O, GCK5 VCCIO (D6) VCCIO VCCINT VCCIO (D5) (CS0) VCCIO
BG432
GND* VCCIO* GND* VCCIO* GND* GND* VCCIO* GND* GND* VCCIO* GND*
BG56AJ4 GND* VCCIO* GND* VCCIO* GND* GND* VCCIO* GND* GND* VCCIO* GND*
PG559
AV38 BA39 AT36 BB40 AY40 GND* BA41 BB38 AY38 BC37 AW37 AT34 VCCIO* GND* AU35 AV36 BB36 AY36 BC35 AW35 AU33 AT30 VCCIO* GND* AV32 AU31 AW33 BB34 AY34 BC33 AU29 AT28 GND* BA35 BB30 VCCINT* AW31 AY32 VCCIO* BA33 AU27 BC29 AW29 GND* AY30 BA31 BB28 AW27 BC27 AV26 AU25 AY28 GND* VCCIO* BA29 AT24 BB26 AW25 BB24 AY26 GND*
XC40125XV Name
(D4) VCCIO (D3) (RS) VCCINT VCCIO (D2) VCCIO VCCINT VCCIO
BG432
VCCIO* GND* GND* VCCIO* GND* VCCIO* GND* GND* VCCIO*
BG56V4 VCCIO* GND* GND* VCCIO* GND* GND* VCCIO* GND* GND* VCCIO*
PG559
AV24 AU23 BA27 BC23 AY24 AW23 VCCIO* GND* BA23 AV22 VCCINT* AY22 BB22 AU21 AW21 GND* BA21 BC21 AY20 BB20 AT20 AV20 VCCIO* GND* AW19 AY18 BB18 AU19 BC17 BA17 AV18 AW17 GND* AY16 BB16 AU17 BA15 VCCIO* AW15 BC15 VCCINT* AY14 BA13 GND* AT16 BB14 AU15 BC11 AW13 BB10 AY12 BA11 GND* VCCIO* AT14 AU13 AV12 AW11
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1998 (Version 1.1)
XC40125XV Name
VCCIO (D1) (RCLK RDY/BUSY) (D0, DIN) I/O, GCK6 (DOUT) CCLK VCCIO (A0, I/O, GCK7 (A1) VCCINT (CS1, (A3) VCCIO VCCIO
BG432
GND* VCCIO* GND* VCCIO* GND* GND* VCCIO* GND* VCCIO* GND*
BG56H5 GND* VCCIO* GND* VCCIO* GND* GND* VCCIO* GND* VCCIO* GND*
PG559
AU11 GND* VCCIO* AT10 GND* VCCIO* GND* VCCINT* GND* VCCIO* GND* VCCIO* GND*
XC40125XV Name
VCCINT VCCIO VCCIO (A4) (A5) (A21) (A20) VCCINT (A6) (A7)
1/29/98
BG432
GND* VCCIO* GND* GND* VCCIO* GND* GND*
BG56D10 GND* VCCIO* GND* GND* VCCIO* GND* GND*
PG559
GND* VCCINT* VCCIO* GND* GND* VCCIO* GND* VCCINT* GND*
Pads labelled GND*, VCCIO*, VCCINT* internally bonded Ground VCCIO planes within package. They have direct connection specific package pin.
1998 (Version 1.1)
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XC4000XV Family Field Programmable Gate Arrays
Additional XC40125XV Package Pins
BG432 PG559 AE41 AU37 BA37 AT26 AH38 AV16 BB12 7/21/97 BG560 AM15 AN24 AM11 6/4/97 AM21 AN30 AM19 AN10 AK33 AM32 VCCIO Pins AB33 Pins AG32 AJ33 AM25 AM28 AM33 AN14 AN16 AN20 N.C. Pins AN33 AL31 AN12 AC32 AL32 AN22 AF33 AN18 AD33 AN27 AU41 AT32 AV28 BB32 VCCIO Pins AK38 AL43 AV14 AV30 BC13 BC31 BC43 VCCINT Pins** AF36 AM36 Pins AB36 AM42 AP38 AV34 BC19 BC25 BA19 AT12 AE43 AT22 AW39 BC39 BA25 AT18 AV10 AW43 AH11 AH21 AJ29 VCCIO Pins AL11 AL21 AA28 AL31 AA31
AC31 AL14
AK30 AL18
AE31 AK31 AL23
Pins AH16 AL25 N.C. Pins
AL29
AJ31
VCCINT pins must connected package compatible XC4085XL-PG559
4-17
1998 (Version 1.1)
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