Designing Industry's First Million Gate FPGA Drop-In Design

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Designing Industry's First Million Gate FPGA Drop-In Design

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Xilinx Programmable Logic Design Solutions
Designing Industry's First Million Gate FPGA
Drop-In Design
State Programmable Logic Design
Industry's fastest compilation times Industry's highest performance Industry's best support High-Level design flows design Design re-use Cores Robust functional timing verification Internet enabled design Support industry's largest FPGAs Products configured meet your design needs
Density Leadership
Density (system gates)
Gates 2002
Next Generation Virtex
Virtex V1000
million Transiistors
500k
XC40250XV
180k
XC4085XLA
1997
1998
1999
2000 2001 2002
Million System Gates Today!
Software Leadership
Internet Enabled Software v2.1
4Internet Team Design
Ease v1.5
Push Button Design Minimum Delay Reporting Voltage/Temperature Prorating Floorplanning
Million Gate support 4100K Gates minute 4Embedded Core Generator 4Drop-In
1998
1999
Benchmark Results
Virtex 10KE Compilation Time
Timing Driven
Timing Driven
Xilinx 2.1i FASTER
Xilinx 2.1i FASTER
9.3X 4.2X
Benchmarks comparing Virtex with 10KE-1 using Alliance version 2.1i MAX+PLUS2 Design suite consists customer designs ranging from XCV50-XCV600
Benchmark Results
Virtex 10KE Performance
Timing Driven
Timing Driven
Virtex FASTER
Virtex FASTER
Benchmarks comparing Virtex with 10KE-1 using Alliance version 2.1i MAX+PLUS2 Design suite consists customer designs ranging from XCV50-XCV600
Internet Team Design
Solves 21st Century Design Challenges
Problem Variety Flows Remote Location Designers Design Revision Management
Schematic Engineer
Design Team Leader
Solution Communication Coordination Integration
Million+ Gate Designs
VHDL Engineer
Verilog Engineer
Core Engineer
Internet Team Design
Product Description web-based facility coordinate manage team-based design projects
features include: Facilitates project schedule, assignments communication among team members Coordination input source netlist files from multiple designers Provides access implementation reports, timing simulation configuration files
Synopsys
FPGA Express3.2
Push-Button Performance: Advanced synthesis delivers faster clock speeds, more efficient utilization Powerful design: scripting enables ASIC style design flow Advanced Analysis features simplify design debugging: Integrated Schematic Viewing Static Timing Analysis (VISTATM) Consistent signal naming
Real 64/66
Real Flexibility
Uses standard Virtex FPGA Back-end de-coupled from core
Real Compliance
v2.2 Initiator Target Guaranteed timing
FIFO(s)
User Design
DMA(s)
PCI64/66
Zero wait-state
Real Performance
Compliant zero wait-state 66MHz Full 64-bit data path
64-bit, 66MHz
64-bit Interface
Xilinx Alliance Series
Programmable Logic Design Tools Integrated Into Your Environment
Robust support complexities multi-million gate FPGA design High performance synthesis Advanced design analysis through board level verification STAMP models Industry's first Internet Team Design methodology Productivity enhancements speed system level design Dramatic compile time improvements Extensive Design timing layout analysis tools
Xilinx Foundation Series
Complete, Ready Programmable Logic Design Environment
Easy use, mixed-level design environment Industry's fastest compilation times Embedded core generation tool Industry's most comprehensive on-line support Powerful, mixed-language synthesis from SynopsysR Drop-In design Virtex "Real PCI" SpartanXL

Designing Industry's First Million Gate FPGA Drop-In Design

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